CN206040190U - Shift register unit and gate drive circuit, display device - Google Patents
Shift register unit and gate drive circuit, display device Download PDFInfo
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- CN206040190U CN206040190U CN201621080985.4U CN201621080985U CN206040190U CN 206040190 U CN206040190 U CN 206040190U CN 201621080985 U CN201621080985 U CN 201621080985U CN 206040190 U CN206040190 U CN 206040190U
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Abstract
An embodiment of the utility model provides a shift register unit and gate drive circuit, display device relates to and shows technical field, can avoid one -level shift register unit exported the grid line to in the GOA circuit gate driving signal to inputing to the signal waveform's of next stage shift register unit influence. First pull -up module in this shift register unit is used for under the control of pull -up node holding the signal output of first clock signal end to a signal output, the 2nd pull -up module is used for under the control of pull -up node signal output to the 2nd signal output end with the first clock signal end, first drawing die piece is used for under the control of drop -down node, respectively with the drop -down current potential to second voltage end of the current potential of pull -up node and the first signal output, second drawing die piece is used for under the control of drop -down node, with the drop -down current potential to the 2nd voltage end of the 2nd signal output part's current potential.
Description
Technical field
This utility model is related to display technology field, more particularly to a kind of shift register cell and gate driver circuit,
Display device.
Background technology
(Thin Film Transistor Liquid Crystal Display, thin film are brilliant for display, such as TFT-LCD
Body pipe-liquid crystal display) in be provided with array base palte, wherein, array base palte can be divided into viewing area and be located at viewing area
The wiring area of domain periphery.Gate drivers for grid line progressively scanned are provided with neighboring area wherein.It is existing
Gate drivers frequently with GOA (Gate Driver on Array, array base palte row drive) designs by TFT (Thin Film
Transistor, TFT) gate switch circuit is integrated in above-mentioned neighboring area and constitutes GOA circuits, to realize
Narrow frame design.
In prior art, GOA circuits as shown in Figure 1a, shift register cell including multiple cascades (RS1, RS2,
RS3 ...), the outfan OUT of each shift register cell connects a line grid line (G_1, G_2 or G_3 ...), for
Grid line is input into gate drive signal.Wherein, the signal of the outfan OUT of upper level shift register cell RS is moved as next stage
The input signal of bit register unit R S.As every a line grid line is connected with each sub-pix of same a line, set in sub-pix
The elements such as TFT and liquid crystal capacitance and parasitic capacitance are equipped with, therefore said elements can be exported to outfan OUT to next stage and be shifted
The signal of register cell RS inputs causes to postpone.So, as shown in Figure 1 b, the rising edge of gate drive signal is with
The time on drop edge can increase.In the case, during progressive scan, above-mentioned delayed impact can be superimposed grid line line by line, from
And cause the gate drive signal distortion that last column grid line G_n is received more serious, reduce the driving force of GOA circuits.
Utility model content
Embodiment of the present utility model provides a kind of shift register cell and gate driver circuit, display device, can
One-level shift register cell in GOA circuits is avoided to export gate drive signal to grid line to input to next stage shift LD
The impact of the signal waveform of device unit.
For reaching above-mentioned purpose, embodiment of the present utility model is adopted the following technical scheme that：
A kind of one side of this utility model embodiment, there is provided shift register cell, including pull-up control module, first
Pull-up module, the second pull-up module, drop-down control module, the first drop-down module, the second drop-down module, reseting module and replacement
Module；The pull-up control module connection first voltage end, signal input part and pull-up node, in the signal input
Under the control at end, by the voltage output at the first voltage end to pull-up node；The first pull-up module connects the first clock
Signal end, the first signal output part and the pull-up node, during under the control of the pull-up node by described first
The signal output of clock signal end is to first signal output part；The second pull-up module connects first clock signal
End, secondary signal outfan and the pull-up node, for believing first clock under the control of the pull-up node
Number end signal output to the secondary signal outfan；The drop-down control module connection second clock signal end, described the
One clock signal terminal, pull-up node, the pull-down node and second voltage end, for inciting somebody to action under the control of the pull-up node
The current potential of the pull-down node is pulled down to the current potential at the second voltage end, or, under the control for the first clock signal terminal,
By the signal output of first clock signal terminal to the pull-down node, or for the control in second clock signal end
Under, by the signal output of the second clock signal end to the pull-down node；The first drop-down module connection is described drop-down
Node, the pull-up node, first signal output part and the second voltage end, for the control in the pull-down node
Under system, the current potential of the pull-up node and first signal output part is pulled down to the current potential at the second voltage end respectively；
The second drop-down module connects the pull-down node, the secondary signal outfan and the second voltage end, for
Under the control of the pull-down node, the current potential of the secondary signal outfan is pulled down to into the current potential at the second voltage end；Institute
Reseting module connection reset signal end, the pull-up node, tertiary voltage end is stated, for the control at the reset signal end
Under, the current potential of the pull-up node is pulled down to into the current potential at the tertiary voltage end；During replacement module connection described second
Clock signal end, second voltage end, the first signal output part and secondary signal outfan, in the second clock signal end
Control under, the current potential of first signal output part and secondary signal outfan is pulled down to into the second voltage end respectively
Current potential.
Preferably, the pull-up control module includes the first transistor, and the grid of the first transistor connects the letter
Number input, the first pole connect the first voltage end, and the second pole is connected with the pull-up node.
Preferably, the first pull-up module includes transistor seconds and third transistor；The grid of the transistor seconds
Pole connects the pull-up node, and the first pole connects first clock signal terminal, the second pole and the first signal output part phase
Connection.The grid of the third transistor and the second pole connect first signal output part, the second pole and first clock
Signal end is connected.
Preferably, the second pull-up module includes the 4th transistor and storage capacitance；The grid of the 4th transistor
Connect the pull-up node, the first pole connects first clock signal terminal, and the second pole is connected with the secondary signal outfan
Connect；One end of the storage capacitance connects the grid of the 4th transistor, and the other end is connected with the secondary signal outfan
Connect.
Preferably, drop-down control module includes the 5th transistor, the 6th transistor and the 7th transistor；Described 5th is brilliant
The grid of body pipe and the first pole connect the second clock signal end, and the second pole is connected with the pull-down node；Described 6th
The grid of transistor and the first pole connect first clock signal terminal, and the second pole is connected with the pull-down node；Described
The grid of seven transistors connects the pull-up node, and the first pole connects the second voltage end, the first pole and the pull-down node
It is connected.
Preferably, the described first drop-down module includes the 8th transistor and the 9th transistor；The grid of the 8th transistor
Pole connects the pull-down node, and the first pole connects the second voltage end, and the second pole is connected with the pull-up node；Described
The grid of nine transistors connects the pull-down node, and the first pole connects the second voltage end, the second pole and first signal
Outfan is connected.
Preferably, the described second drop-down module includes the tenth transistor, under the grid connection of the tenth transistor is described
Node, the first pole is drawn to connect the second voltage end, the second pole is connected with the secondary signal outfan.
Preferably, the reseting module includes the 11st transistor；The grid connection of the 11st transistor is described multiple
Position signal end, the first pole connect the tertiary voltage end, and the second pole is connected with the pull-up node.
Preferably, the replacement module includes the tenth two-transistor and the 13rd transistor；Tenth two-transistor
Grid connect the second clock signal end, the first pole connects the second voltage end, and the second pole is defeated with the secondary signal
Go out end to be connected；The grid of the 13rd transistor connects the second clock signal end, the first pole connection described the
Two voltage ends, the second pole are connected with first signal output part.
A kind of another aspect of this utility model embodiment, there is provided gate driver circuit, for being input into grid line by line to grid line
Pole drive signal, including upper any one described shift register cell of multi-stage cascade, per one-level shift register cell
The first signal output part for being connected with the grid line；In addition to first order shift register cell, upper level displacement
The secondary signal outfan of register cell is connected with the signal input part of next stage shift register cell；Except last
Beyond level shift register cell, secondary signal outfan and the upper level shift register list of next stage shift register cell
The reset signal end of unit is connected；The signal input part and afterbody shift register cell of the first pole shift register cell
Reset signal end connection initial signal end.
The another aspect of this utility model embodiment, there is provided a kind of display device includes raster data model electricity as above
Road.
This utility model embodiment provides a kind of shift register cell and gate driver circuit, display device, the displacement
Register cell includes pulling up control module, the first pull-up module, the second pull-up module, drop-down control module, first time drawing-die
Block, the second drop-down module, reseting module and replacement module.Control module connection first voltage end, signal input are pulled up wherein
End and pull-up node, under the control of signal input part, by the voltage output at first voltage end to pull-up node.First
Pull-up module connects the first clock signal terminal, the first signal output part and the pull-up node, for the control in pull-up node
By the signal output of the first clock signal terminal to the first signal output part under system.Second pull-up module connects the first clock signal
End, secondary signal outfan and pull-up node, for will be the signal of the first clock signal terminal defeated under the control of pull-up node
Go out to secondary signal outfan.Drop-down control module connection second clock signal end, the first clock signal terminal, pull-up node, under
Node and second voltage end is drawn, for the current potential of pull-down node is pulled down to second voltage end under the control of pull-up node
Current potential, or, under the control for the first clock signal terminal, by the signal output of the first clock signal terminal to pull-down node, or
Person under the control of second clock signal end, by the signal output of second clock signal end to pull-down node.First is drop-down
Module connection pull-down node, pull-up node, the first signal output part and second voltage end, for the control in pull-down node
Under, the current potential of pull-up node and the first signal output part is pulled down to the current potential at second voltage end respectively.Second drop-down module connects
Pull-down node, secondary signal outfan and second voltage end is connect, for, under the control of pull-down node, secondary signal being exported
The current potential at end is pulled down to the current potential at second voltage end.Reseting module connection reset signal end, pull-up node, tertiary voltage end, use
Under the control at reset signal end, the current potential of pull-up node is pulled down to into the current potential at tertiary voltage end.Reset module connection the
Two clock signal terminals, second voltage end, the first signal output part and secondary signal outfan, in second clock signal end
Control under, the current potential of the first signal output part and secondary signal outfan is pulled down to the current potential at second voltage end respectively.
So, when gate driver circuit is constituted using the cascade of above-mentioned shift register cell, the shift register
The first signal output part being connected with the first pull-up module in unit can be connected with grid line, for providing grid to grid line
Scanning signal, and the secondary signal outfan being connected with the second pull-up module can be with the letter of next stage shift register cell
Number input is connected, for providing input signal to the signal input part.Due to above-mentioned first signal output part and the second letter
Number outfan individually can be controlled by the first pull-up module and the second pull-up module respectively, therefore the first signal output part and the
Binary signal outfan is two independent signal output parts, such that it is able to avoid the signal of the first signal output part output to second
The signal of signal output part output is impacted so that the cascade connection between two neighboring shift register cell weakens, and reaches
There is the occurrence probability of delay phenomenon in the signal received to reduction shift register cell signal input part.
Description of the drawings
In order to be illustrated more clearly that this utility model embodiment or technical scheme of the prior art, below will be to embodiment
Or accompanying drawing to be used is briefly described needed for description of the prior art, it should be apparent that, drawings in the following description are only
It is some embodiments of the present utility model, for those of ordinary skill in the art, in the premise for not paying creative work
Under, can be with according to these other accompanying drawings of accompanying drawings acquisition.
Fig. 1 a export the schematic diagram of gated sweep signal for a kind of gate driver circuit that prior art is provided；
Fig. 1 b are the schematic diagram that time delay occurs in the gated sweep signal of the gate driver circuit output shown in Fig. 1 a；
A kind of structural representation of shift register cell that Fig. 2 is provided for this utility model embodiment；
Fig. 3 is a kind of concrete structure schematic diagram of modules in Fig. 2；
Fig. 4 is a kind of signal timing diagram for controlling the shift register cell shown in Fig. 3；
A kind of structural representation of gate driver circuit that Fig. 5 is provided for this utility model embodiment.
Reference：
10- pulls up control module；20- first pulls up module；30- second pulls up module；The drop-down control modules of 40-；50-
Once drawing-die block；The second drop-down modules of 60-；70- reseting modules；80- resets module.
Specific embodiment
Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only this utility model a part of embodiment, rather than whole
Embodiment.Based on the embodiment in this utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment for being obtained, belongs to the scope of this utility model protection.
This utility model embodiment provides a kind of shift register cell, as shown in Fig. 2 include pulling up control module 10,
It is the first pull-up pull-up module 30 of module 20, second, drop-down control module 40, the first drop-down module 50, the second drop-down module 60, multiple
Position module 70 and replacement module 80.
Wherein, the connection first voltage end VDD of control module 10, signal input part INPUT and pull-up node PU is pulled up, is used
Under the control in signal input part INPUT, by the voltage output of first voltage end VDD to pull-up node PU.
First pull-up module 20 connects the first clock signal terminal CLK, the first signal output part OUTPUT1 and pull-up node
PU, under the control of pull-up node PU by the signal output of the first clock signal terminal CLK to the first signal output part
OUTPUT1。
Second pull-up module 30 connects the first clock signal terminal CLKB, secondary signal outfan OUTPUT2 and pull-up section
Point PU, under the control of pull-up node PU by the signal output of the first clock signal terminal CLK to secondary signal outfan
OUTPUT2。
Drop-down control module 40 connection second clock signal end CLKB, the first clock signal terminal CLK, pull-up node PU, under
Node PD and second voltage end VGL is drawn, for the current potential of pull-down node PD is pulled down to the under the control of pull-up node PU
The current potential of two voltage end VGL, or, under the control for the first clock signal terminal CLK, by the letter of the first clock signal terminal CLK
Number export to pull-down node PD, or under the control of second clock signal end CLKB, by second clock signal end CLKB
Signal output to pull-down node PD.
Connection pull-down node PD of first drop-down module 50, pull-up node PU, the first signal output part OUTPUT1 and second
Voltage end VGL, under the control of pull-down node PD, respectively by pull-up node PU and the first signal output part OUTPUT1
Current potential is pulled down to the current potential of second voltage end VGL.
Connection pull-down node PD of second drop-down module 60, secondary signal outfan OUTPUT2 and second voltage end VGL,
For, under the control of pull-down node PD, the current potential of secondary signal outfan OUTPUT2 being pulled down to the electricity of second voltage end VGL
Position.
The connection reset signal end RESET of reseting module 70, pull-up node PU, tertiary voltage end VSS, in reset signal
Under the control of end RESET, the current potential of pull-up node PU is pulled down to into the current potential of tertiary voltage end VSS.
Reset the connection second clock signal end CLKB of module 80, second voltage end VGL, the first signal output part OUTPUT1
And secondary signal outfan OUTPUT2, under the control of second clock signal end CLKB, respectively by the first signal output
The current potential of end OUTPUT1 and secondary signal outfan OUTPUT2 is pulled down to the current potential of second voltage end VGL.So as to first
The current potential of signal output part OUTPUT1 and secondary signal outfan OUTPUT2 is reset.
So, when gate driver circuit is constituted using the cascade of above-mentioned shift register cell, the shift register
The first signal output part being connected with the first pull-up module in unit can be connected with grid line, for providing grid to grid line
Scanning signal, and the secondary signal outfan being connected with the second pull-up module can be with the letter of next stage shift register cell
Number input is connected, for providing input signal to the signal input part.Due to above-mentioned first signal output part and the second letter
Number outfan individually can be controlled by the first pull-up module and the second pull-up module respectively, therefore the first signal output part and the
Binary signal outfan is two independent signal output parts, such that it is able to avoid the signal of the first signal output part output to second
The signal of signal output part output is impacted so that the cascade connection between two neighboring shift register cell weakens, and reaches
There is the occurrence probability of delay phenomenon in the signal received to reduction shift register cell signal input part.
Hereinafter the concrete structure of above-mentioned modules is described in detail.
Specifically, as shown in figure 3, the pull-up control module 10 includes the first transistor M1, the grid of the first transistor M1
Connection signal input part INPUT, the first pole connection first voltage end VDD, the second pole is connected with pull-up node PU.
First pull-up module 20 can include transistor seconds M2 and third transistor M3.Wherein, transistor seconds M2
Grid connects pull-up node PU, and the first pole connects the first clock signal terminal CLK, the second pole and the first signal output part OUTPUT1
It is connected.
The grid of third transistor M3 and the second pole connect the first signal output part OUTPUT1, the second pole and the first clock
Signal end CLK is connected.
It should be noted that when the above-mentioned first pull-up module 20 only includes transistor seconds M2, equally can be in the crystalline substance
In the case that body pipe is turned on, the signal transmission that the first clock signal terminal CLK is exported to the first signal output part OUTPUT1.So
And when the first pull-up module 20 includes transistor seconds M2 and third transistor M3, above-mentioned two transistor can conduct
Driving transistor, to simultaneously turn on to the grid line output gated sweep signal being connected with the first signal output part OUTPUT1, from
And improve the driving force of the gated sweep signal.
Additionally, the second pull-up module 30 includes the 4th transistor M4 and storage capacitance C.
4th transistor M4 grid connection pull-up node PU, the first pole connect the first clock signal terminal CLK, the second pole with
Secondary signal outfan OUTPUT2 is connected.
One end of storage capacitance C connects the grid of the 4th transistor T4, the other end and secondary signal outfan OUTPUT2 phases
Connection.
Drop-down control module 40 includes the 5th transistor M5, the 6th transistor M6 and the 7th transistor M7.
The grid of the 5th transistor M5 and the first pole connection second clock signal end CLKB, the second pole and pull-down node PD phase
Connection.
The grid of the 6th transistor M6 and the first pole connect the first clock signal terminal CLK, the second pole and pull-down node PD phase
Connection.
7th transistor M7 grid connection pull-up node PU, the first pole connection second voltage end VGL, the first pole with it is drop-down
Node PD is connected.
First drop-down module 50 includes the 8th transistor M8 and the 9th transistor M9.
Grid connection pull-down node PD of the 8th transistor M8, the first pole connection second voltage end VGL, the second pole and pull-up
Node PD is connected.
Grid connection pull-down node PD of the 9th transistor M9, the first pole connection second voltage end VGL, the second pole and first
Signal output part OUTPUT1 is connected.
Second drop-down module 60 includes the tenth transistor M10, and the grid of the tenth transistor M10 connects pull-down node PD,
First pole connects second voltage end VGL, and the second pole is connected with secondary signal outfan OUTPUT2.
Reseting module 70 includes the 11st transistor M11.
The grid connection reset signal end RESET of the 11st transistor M11, the first pole connection tertiary voltage end VSS, second
Pole is connected with pull-up node PU.
Resetting module 80 includes the tenth two-transistor M12 and the 13rd transistor M13.
The grid connection second clock signal end CLKB of the tenth two-transistor M12, the first pole connection second voltage end VGL,
Second pole is connected with secondary signal outfan OUTPUT2.
The grid connection second clock signal end CLKB of the 13rd transistor M13, the first pole connection second voltage end VGL,
Second pole is connected with the first signal output part OUTPUT1.
It should be noted that above-mentioned transistor can be N-type transistor, or P-type transistor.Above-mentioned transistor
First can extremely be source electrode, and second can extremely be drain electrode；Or first extremely drain, the second extremely source electrode, this utility model pair
This is not construed as limiting.
Below so that above-mentioned transistor is N-type transistor as an example, and with reference to Fig. 4 to shift register list as shown in Figure 5
Each transistor in unit, carries out detailed illustration in the break-make situation in the different stage (P1～P4) of a picture frame.
Wherein, it is that high level, second voltage end VGL and tertiary voltage are exported with first voltage end VDD in this utility model embodiment
The explanation carried out as a example by the VSS output low levels of end.
In the case, in the first sub-stage P1 of initial phase P1 as shown in Figure 41, CLK=0, CLKB=1,
INPUT=0, RESET=0；Wherein " 0 " represents low level, and " 1 " represents high level.
Now, under the control of second clock signal end CLKB, the tenth two-transistor M12 and the 13rd transistor M13 lead
It is logical, the current potential of secondary signal outfan OUTPUT2 can be pulled down to by second voltage end VGL by the tenth two-transistor M12, led to
Cross 13 transistor M13 and the current potential of the first signal output part OUTPUT1 can be pulled down to second voltage end VGL.So,
Can be in the first sub-stage P1 of above-mentioned initial phase P11, it is defeated to above-mentioned first signal output part OUTPUT1 and secondary signal
Go out to hold the current potential of OUTPUT2 to be reset, shadow is caused to this picture frame output signal with the signal for avoiding upper picture frame residual
Ring.
Additionally, second clock signal end CLKB output high level, such that it is able to by the 5th transistor turns, and during by second
The high level of clock signal end CLKB outputs is transmitted to pull-down node PD, under the control of pull-down node PD, the 8th transistor M8,
Tenth transistor M10 and the 9th transistor M9 are in the conduction state.Now, can be by pull-up node by the 8th transistor M8
The current potential of PU is pulled down to second voltage end VGL, can be by the electricity of secondary signal outfan OUTPUT2 by the tenth transistor M10
Position is pulled down to second voltage end VGL, can be pulled down to the current potential of the first signal output part OUTPUT1 by the 9th transistor M9
Second voltage end VGL.
It should be noted that in this stage in addition to the transistor of above-mentioned conducting, its in this shift register cell
Remaining transistor is in cut-off state.
In the second sub-stage P1 of initial phase P1 as shown in Figure 42, CLK=1, CLKB=0, INPUT=0,
RESET=0.
In the case, under the control of the first clock signal terminal CLK, the 6th transistor M6 conductings, during so as to by first
The high level of clock signal end CLK outputs is transmitted to pull-down node PD.Under the control of pull-down node PD, the 8th transistor M8,
Tenth transistor M10 and the 9th transistor M9 are in the conduction state.Now, can be by pull-up node by the 8th transistor M8
The current potential of PU is pulled down to second voltage end VGL, can be by the electricity of secondary signal outfan OUTPUT2 by the tenth transistor M10
Position is pulled down to second voltage end VGL, can be pulled down to the current potential of the first signal output part OUTPUT1 by the 9th transistor M9
Second voltage end VGL.
It should be noted that in this stage in addition to the transistor of above-mentioned conducting, its in this shift register cell
Remaining transistor is in cut-off state.
In sum, in above-mentioned initial phase P1, the first signal output part OUTPUT1, secondary signal outfan
OUTPUT2 is pulled down to the low level of secondary signal end VGL, such that it is able to avoid the first signal output part OUTPUT1, second
There is the phenomenon of output by mistake in the stage in signal output part OUTPUT2.
In input phase P2 as shown in Figure 4, CLK=0, CLKB=1, INPUT=1, RESET=0.
In the case, signal input part INPUT input high levels, the first transistor M1 conductings, by first voltage end VDD
High level output to pull-up node PU, and the high level is stored by storage capacitance C.In the control of pull-up node PU
Under system, the 4th transistor M4, transistor seconds M2 conducting.Can will be the first clock signal terminal CLK defeated by the 4th transistor M4
The low level for going out is transmitted to secondary signal outfan OUTPUT2.Can be by the first clock signal terminal CLK by transistor seconds M2
The low level of output is transmitted to the first signal output part OUTPUT1, now third transistor M3 cut-off.
Additionally, under the control of pull-up node PU, the 7th transistor M7 conductings, so as to will be the current potential of pull-down node PD drop-down
To the current potential of second voltage end VGL.Now, the 8th transistor M8, the tenth transistor M10, the 9th transistor M9 are in cut-off shape
State.Second clock signal end CLKB exports high level, the 5th transistor M5, the tenth two-transistor M12, the 13rd transistor M13
The current potential of secondary signal outfan OUTPUT2 can be pulled down to second voltage end VGL by the tenth two-transistor M12 by conducting,
The current potential of the first signal output part OUTPUT1 can be pulled down to second voltage end VGL by 13 transistor M13.Although logical
The 5th transistor M5 is crossed, the high level that second clock signal end CLKB is exported can be transmitted to pull-down node PD, but due to
7th transistor M7 is turned on, therefore the current potential of pull-down node PD is pulled down to the current potential of second voltage end VGL again.
Based on this, reset signal end RESET output low levels, the 11st transistor M11 are ended.Additionally, the first clock letter
Number end CLK output low level, therefore the 6th transistor M6 cut-off.
In output stage P3 as shown in Figure 4, CLK=1, CLKB=0, INPUT=0, RESET=0.
In the case, signal input part INPUT input low levels, the first transistor M1 cut-offs.Storage capacitance C from
Under act effect, the current potential of pull-up node PU is further pulled up.Under the control of pull-up node PU, the 4th transistor M4,
Two-transistor M2 is turned on.The high level that first clock signal terminal CLK is exported can be transmitted to second by the 4th transistor M4
Signal output part OUTPUT2, so that secondary signal outfan OUTPUT2 can be to next stage shift register cell
Signal input part INPUT provides input signal.Additionally, the first clock signal terminal CLK can be exported by transistor seconds M2
High level transmit to the first signal output part OUTPUT1, now third transistor M3 conducting, by the first clock signal terminal
The high level of CLK outputs is transmitted to the first signal output part OUTPUT1, such that it is able to increase by the first signal output part OUTPUT1
The driving force of the gated sweep signal of output.
Additionally, under the control of pull-up node PU, the current potential of pull-down node PD is pulled down to the by the 7th transistor M7 conductings
The current potential of two voltage end VGL.Now, the 8th transistor M8, the tenth transistor M10, the 9th transistor M9 are in cut-off state.
First clock signal terminal CLK exports high level, and the first clock signal terminal CLK is exported by the 6th transistor M6 conductings
High level transmit to pull-down node PD, but as the 7th transistor M7 is turned on, therefore the current potential of pull-down node PD is again by under
It is pulled to the current potential of second voltage end VGL.
Based on this, second clock signal end CLKB output low level, the 5th transistor M5, the tenth two-transistor M12, the tenth
Three transistor M13 end.Reset signal end RESET exports low level, the 11st transistor M11 cut-offs.
In sum, gated sweep holding wire, the second letter is provided in this stage the first signal output part OUTPUT1 to grid line
Number outfan OUTPUT2 provides input signal to the signal input part INPUT of next stage shift register cell.
In reseting stage P4 as shown in Figure 4, CLK=0, CLKB=1, INPUT=0, RESET=1.
Reset signal end RESET input high levels, the 11st transistor M11 conductings, will be the current potential of pull-up node PU drop-down
To the current potential of tertiary voltage end VSS, to reset to pull-up node PU.Now, the 4th transistor M4 and transistor seconds M2
Cut-off, third transistor M3 are also at cut-off state.Secondary signal outfan OUTPUT2 and the first signal output part OUTPUT1
No-raster signal output.
Second clock signal end CLKB exports high level, the 5th transistor M5 conductings, and by second clock signal end CLKB
The high level of output is transmitted to pull-down node PD.Under the control of pull-down node PD, the 8th transistor M8, the tenth transistor M10
And the 9th transistor M9 it is in the conduction state.Now, can will be the current potential of pull-up node PU drop-down by the 8th transistor M8
To second voltage end VGL, the current potential of secondary signal outfan OUTPUT2 can be pulled down to second by the tenth transistor M10
The current potential of the first signal output part OUTPUT1 can be pulled down to second voltage end by the 9th transistor M9 by voltage end VGL
VGL。
Additionally, second clock signal end CLKB output high level, the tenth two-transistor M12, the 13rd transistor M13 lead
It is logical, the current potential of secondary signal outfan OUTPUT2 can be pulled down to by second voltage end VGL by the tenth two-transistor M12, led to
Cross 13 transistor M13 and the current potential of the first signal output part OUTPUT1 can be pulled down to second voltage end VGL.
Based on this, signal input part INPUT input low levels, the first transistor M1 end.First clock signal terminal CLK is defeated
Enter low level, the 6th transistor M6 cut-offs.
Next, before next image frame, the above-mentioned initial phase P1 of repetition, so that the first signal output part
The potential duration of OUTPUT1 and secondary signal outfan OUTPUT2 is pulled down to second voltage end VGL.
This utility model embodiment provides a kind of gate driver circuit, for being input into gate drive signal line by line to grid line,
As shown in figure 5, including any one shift register cell as above (RS1, RS2 ... RSn) of multi-stage cascade.
Specifically, per the first signal output part OUTPUT1 of one-level shift register cell RS for being connected with grid line,
To export gated sweep signal to each row grid line.
In addition to first order shift register cell RS1, the secondary signal outfan of upper level shift register cell
OUTPUT2 is connected with the signal input part INPUT of next stage shift register cell.
In addition to afterbody shift register cell RSn, the secondary signal output of next stage shift register cell
End OUTPUT2 is connected with the reset signal end RESET of upper level shift register cell.Afterbody shift register cell
The secondary signal outfan OUTPUT2 of RSn can be with vacant.
The signal input part INPUT's and afterbody shift register cell Gn of the first Ghandler motion bit register unit R S1
Reset signal end RESET connects initial signal end STV.When the initial signal input first order shift LD of initial signal end STV
During the signal input part INPUT of device unit R S1, the reset signal end RESET of afterbody shift register cell RSn can be by
The initial signal of initial signal end STV resets to afterbody shift register cell RSn as reset signal.Or,
The reset signal that the reset signal end RESET of afterbody shift register cell RSn can be separately provided.
It should be noted that in order that the first clock signal input terminal CLK of each shift register cell and
The frequency of the signal waveform as shown in Figure 4 of two clock signal input terminal CLKB outputs, amplitude are identical, opposite in phase.Can be such as Fig. 5
It is shown, the first clock signal input terminal CLK on different shift register cells and second clock signal input part CLKB difference
It is connected with the first system clock signal input terminal CLK1 and second system clock signal input terminal CLK2 alternatings.
For example, the first clock signal input terminal CLK connection the first system clock letters of first order shift register cell RS1
Number input CLK1, second clock signal input part CLKB connection second system clock signal input terminal CLK2；The second level shifts
The first clock signal input terminal CLK connection second system clock signal input terminal CLK2 of register cell RS2, second clock letter
Number input CLKB connection the first system clock signal input terminal CLK3.The connected mode of following shift register cell ibid institute
State.
This utility model embodiment provides a kind of display device, including gate driver circuit as above.With with it is front
The gate driver circuit identical structure and beneficial effect of embodiment offer are provided.As previous embodiment is to raster data model electricity
The structure and beneficial effect on road is described in detail, and here is omitted.
The above, specific embodiment only of the present utility model, but protection domain of the present utility model do not limit to
In this, any those familiar with the art can readily occur in change in the technical scope that this utility model is disclosed
Or replace, should all cover within protection domain of the present utility model.Therefore, protection domain of the present utility model should be with the power
The protection domain that profit is required is defined.
Claims (11)
1. a kind of shift register cell, it is characterised in that including drawing-die on pull-up control module, the first pull-up module, second
Block, drop-down control module, the first drop-down module, the second drop-down module, reseting module and replacement module；
The pull-up control module connection first voltage end, signal input part and pull-up node, in the signal input
Under the control at end, by the voltage output at the first voltage end to pull-up node；
The first pull-up module connects the first clock signal terminal, the first signal output part and the pull-up node, for
By the signal output of first clock signal terminal to first signal output part under the control of the pull-up node；
The second pull-up module connects first clock signal terminal, secondary signal outfan and the pull-up node, uses
By the signal output of first clock signal terminal to the secondary signal outfan under the control in the pull-up node；
The drop-down control module connection second clock signal end, first clock signal terminal, pull-up node, the drop-down section
Point and second voltage end, for being pulled down to described second by the current potential of the pull-down node under the control of the pull-up node
The current potential of voltage end, or, under the control for the first clock signal terminal, by the signal output of first clock signal terminal extremely
The pull-down node, or under the control of second clock signal end, by the signal output of the second clock signal end
To the pull-down node；
The first drop-down module connects the pull-down node, the pull-up node, first signal output part and described
Second voltage end, under the control of the pull-down node, respectively by the pull-up node and first signal output part
Current potential be pulled down to the current potential at the second voltage end；
The second drop-down module connects the pull-down node, the secondary signal outfan and the second voltage end, uses
Under the control in the pull-down node, the current potential of the secondary signal outfan is pulled down to into the electricity at the second voltage end
Position；
The reseting module connection reset signal end, the pull-up node, tertiary voltage end, at the reset signal end
Under control, the current potential of the pull-up node is pulled down to into the current potential at the tertiary voltage end；
The replacement module connects the second clock signal end, second voltage end, the first signal output part and secondary signal
Outfan, under the control of the second clock signal end, respectively by first signal output part and secondary signal
The current potential of outfan is pulled down to the current potential at the second voltage end.
2. shift register cell according to claim 1, it is characterised in that the pull-up control module includes that first is brilliant
Body pipe, the grid of the first transistor connect the signal input part, and the first pole connects the first voltage end, the second pole with
The pull-up node is connected.
3. shift register cell according to claim 1, it is characterised in that the first pull-up module includes that second is brilliant
Body pipe and third transistor；
The grid of the transistor seconds connects the pull-up node, and the first pole connects first clock signal terminal, the second pole
It is connected with first signal output part；
The grid of the third transistor and the second pole connect first signal output part, and the second pole is believed with first clock
Number end is connected.
4. shift register cell according to claim 1, it is characterised in that the second pull-up module includes that the 4th is brilliant
Body pipe and storage capacitance；
The grid of the 4th transistor connects the pull-up node, and the first pole connects first clock signal terminal, the second pole
It is connected with the secondary signal outfan；
One end of the storage capacitance connects the grid of the 4th transistor, and the other end is connected with the secondary signal outfan
Connect.
5. shift register cell according to claim 1, it is characterised in that drop-down control module includes the 5th crystal
Pipe, the 6th transistor and the 7th transistor；
The grid of the 5th transistor and the first pole connect the second clock signal end, the second pole and the pull-down node phase
Connection；
The grid of the 6th transistor and the first pole connect first clock signal terminal, the second pole and the pull-down node phase
Connection；
The grid of the 7th transistor connects the pull-up node, and the first pole connects the second voltage end, the first pole and institute
State pull-down node to be connected.
6. shift register cell according to claim 1, it is characterised in that the first drop-down module includes that the 8th is brilliant
Body pipe and the 9th transistor；
The grid of the 8th transistor connects the pull-down node, and the first pole connects the second voltage end, the second pole and institute
State pull-up node to be connected；
The grid of the 9th transistor connects the pull-down node, and the first pole connects the second voltage end, the second pole and institute
State the first signal output part to be connected.
7. shift register cell according to claim 1, it is characterised in that the second drop-down module includes that the tenth is brilliant
Body pipe, the grid of the tenth transistor connect the pull-down node, and the first pole connects the second voltage end, the second pole and institute
State secondary signal outfan to be connected.
8. shift register cell according to claim 1, it is characterised in that the reseting module includes the 11st crystal
Pipe；
The grid of the 11st transistor connects the reset signal end, and the first pole connects the tertiary voltage end, the second pole
It is connected with the pull-up node.
9. shift register cell according to claim 1, it is characterised in that the replacement module includes the 12nd crystal
Pipe and the 13rd transistor；
The grid of the tenth two-transistor connects the second clock signal end, and the first pole connects the second voltage end, the
Two poles are connected with the secondary signal outfan；
The grid of the 13rd transistor connects the second clock signal end, and first pole connects the second voltage
End, the second pole is connected with first signal output part.
10. a kind of gate driver circuit, for being input into gate drive signal line by line to grid line, wants including multi-stage cascade such as right
Seek the shift register cell described in any one of 1-9, it is characterised in that
The first signal output part per one-level shift register cell is for being connected with the grid line；
In addition to first order shift register cell, the secondary signal outfan of upper level shift register cell and next stage
The signal input part of shift register cell is connected；
In addition to afterbody shift register cell, the secondary signal outfan of next stage shift register cell and upper
The reset signal end of level shift register cell is connected；
The reset signal end connection of the signal input part and afterbody shift register cell of the first pole shift register cell
Initial signal end.
11. a kind of display devices, it is characterised in that including gate driver circuit as claimed in claim 10.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621080985.4U CN206040190U (en) | 2016-09-26 | 2016-09-26 | Shift register unit and gate drive circuit, display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621080985.4U CN206040190U (en) | 2016-09-26 | 2016-09-26 | Shift register unit and gate drive circuit, display device |
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| CN206040190U true CN206040190U (en) | 2017-03-22 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106157923A (en) * | 2016-09-26 | 2016-11-23 | 合肥京东方光电科技有限公司 | Shift register cell and driving method, gate driver circuit, display device |
| CN106847225A (en) * | 2017-04-12 | 2017-06-13 | 京东方科技集团股份有限公司 | Display device and gate driving circuit and driver element |
| CN107622755A (en) * | 2017-10-30 | 2018-01-23 | 北京小米移动软件有限公司 | Gate driving circuit and its driving method, electronic equipment |
| CN109243358A (en) * | 2018-11-22 | 2019-01-18 | 合肥京东方光电科技有限公司 | Shift register cell, gate driving circuit and display device |
| CN114783341A (en) * | 2022-04-14 | 2022-07-22 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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2016
- 2016-09-26 CN CN201621080985.4U patent/CN206040190U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106157923A (en) * | 2016-09-26 | 2016-11-23 | 合肥京东方光电科技有限公司 | Shift register cell and driving method, gate driver circuit, display device |
| CN106157923B (en) * | 2016-09-26 | 2019-10-29 | 合肥京东方光电科技有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN106847225A (en) * | 2017-04-12 | 2017-06-13 | 京东方科技集团股份有限公司 | Display device and gate driving circuit and driver element |
| CN107622755A (en) * | 2017-10-30 | 2018-01-23 | 北京小米移动软件有限公司 | Gate driving circuit and its driving method, electronic equipment |
| CN107622755B (en) * | 2017-10-30 | 2023-09-12 | 北京小米移动软件有限公司 | Gate driving circuit, driving method thereof and electronic equipment |
| CN109243358A (en) * | 2018-11-22 | 2019-01-18 | 合肥京东方光电科技有限公司 | Shift register cell, gate driving circuit and display device |
| CN109243358B (en) * | 2018-11-22 | 2021-11-12 | 合肥京东方光电科技有限公司 | Shifting register unit, grid driving circuit and display device |
| CN114783341A (en) * | 2022-04-14 | 2022-07-22 | Tcl华星光电技术有限公司 | GOA circuit and display panel |
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