CN107622755B - Gate driving circuit, driving method thereof and electronic equipment - Google Patents
Gate driving circuit, driving method thereof and electronic equipment Download PDFInfo
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Abstract
The disclosure relates to a gate driving circuit, a driving method thereof and electronic equipment. The grid driving circuit comprises a plurality of first shift registers and a plurality of second shift registers; the first shift registers are mutually cascaded and used for sequentially controlling the data input of each row of display devices, and the second shift registers are mutually cascaded and used for driving each row of display devices to emit light; for the first shift register and the second shift register in the same row in the first shift registers and the second shift registers, the first shift register is electrically connected with the output end of the second shift register through the first input end EM, and is used for outputting a first level signal when receiving a second level signal indicating line change provided by the second shift register. In the embodiment of the disclosure, the signals between the first mobile register and the second mobile register are matched, so that the number of signal lines in the gate driving circuit can be reduced, and the size of the frame is reduced.
Description
Technical Field
The disclosure relates to the technical field of display, and in particular relates to a gate driving circuit, a driving method thereof and electronic equipment.
Background
Currently, active-matrix organic light emitting diode (AMOLED) pixel circuits are applied to display devices with high contrast, ultra-thin, flexible, etc. due to their self-luminescence characteristics. However, at long-time pressurization and high temperature, a shift in threshold voltage of the thin film transistor TFT in the AMOLED pixel circuit occurs. The difference in display brightness is caused by the difference in threshold shift amounts of TFTs in each portion of the display panel due to the difference in display screen, and the difference is related to the image displayed before, and therefore, it often appears as a afterimage phenomenon, which is called afterimage.
In order to solve the above problems, a shift register for controlling a light emitting stage and a scan shift register for controlling writing of data are provided in the AMOLED circuit in the related art, and the shift registers are designed independently of each other without embedded designs therebetween. Fig. 1 illustrates an AMOLED circuit in the related art that controls writing of data. Referring to fig. 1, the shift register structure is generally a 7-transistor and 2-capacitor (7T 2C for short) structure, and the specific operation process can be seen in the related literature. It can be seen that the shift register has a complicated structure and many connection signals including voltage lines VL and VH, signal lines CK and CKB, and a trigger signal terminal STV.
Disclosure of Invention
The disclosure provides a gate driving circuit, a driving method thereof and an electronic device, which are used for solving the defects in the related art.
According to a first aspect of embodiments of the present disclosure, there is provided a gate driving circuit including a plurality of first shift registers and a plurality of second shift registers; the first shift registers are mutually cascaded and used for sequentially controlling the data input of each row of display devices, and the second shift registers are mutually cascaded and used for driving the display devices of each row to emit light;
for the first shift registers and the second shift registers in the same row, the first shift registers are electrically connected with the output ends of the second shift registers through the first input ends EM, and are used for outputting a first level signal when receiving a second level signal indicating line change provided by the second shift registers.
Optionally, the first shift register further includes a clock signal input terminal CK, a trigger signal terminal STV, and a driving terminal OUT; the trigger signal end STV is connected with the driving end OUT of the first shift register of the upper row;
the first shift register outputs a second level signal when the first input end EM loads the first level signal;
The first shift register outputs a second level signal when the first input end EM loads the second level signal, the trigger signal end STV loads the first level signal and the clock signal input end CK loads the second level signal;
the first shift register outputs a first level signal when the first input terminal EM loads a second level signal, the trigger signal terminal STV loads a second level signal, and the clock signal input terminal CK loads a first level signal.
Optionally, the first shift register includes: the device comprises an input module, a pull-up module, a trigger module and an output module, wherein the second input end VGH, a driving end OUT, a first node A and a second node B;
the input module is respectively and electrically connected with the first input end EM, the first node A and the clock signal input end CK and is used for conducting connection between the first input end EM and the first node A under the control of signals received by the clock signal input end CK;
the pull-up module is electrically connected with the second input end VGH, the driving end OUT and the first node A respectively and is used for conducting connection between the second input end VGH and the driving end OUT according to the potential at the first node A;
The trigger module is respectively and electrically connected with the first node A, the second node B and the trigger signal end STV and is used for conducting connection between the first node A and the second node B under the control of signals received by the trigger signal end STV;
the output module is electrically connected with the clock signal input end CK, the driving end OUT and the second node B respectively and is used for conducting connection between the clock signal input end CK and the driving end OUT according to the electric potential at the second node B.
Optionally, the input module includes a first transistor T1, a first control terminal, a first input terminal, and a first output terminal; the gate of the first transistor T1 is electrically connected to the first control terminal, the first pole of the first transistor T1 is electrically connected to the first input terminal, and the second pole of the first transistor T1 is electrically connected to the first output terminal.
Optionally, the triggering module includes a second transistor T2, a second control terminal, a second input terminal, and a second output terminal;
the gate of the second transistor T2 is electrically connected to the second control terminal, the first pole of the second transistor T2 is electrically connected to the second input terminal, and the second pole of the second transistor T2 is electrically connected to the second output terminal.
Optionally, the output module includes a first capacitor C1 and a third transistor T3, a third control terminal, a third input terminal, and a third output terminal;
a gate of the third transistor T3 is electrically connected to the third control terminal, a first pole of the third transistor T3 is electrically connected to the third input terminal, and a second pole of the third transistor T3 is electrically connected to the third output terminal;
a first end of the first capacitor C1 is electrically connected to the gate of the third transistor T3, and a second end of the first capacitor C1 is electrically connected to the second pole of the third transistor T3.
Optionally, the pull-up module includes a second capacitor C2, a fourth transistor T4, a fourth control terminal, a fourth input terminal, and a fourth output terminal;
the gate of the fourth transistor T4 is electrically connected to the fourth control terminal, the first pole of the fourth transistor T4 is electrically connected to the fourth input terminal, and the second pole of the fourth transistor T4 is electrically connected to the fourth output terminal;
the first end of the second capacitor C2 is electrically connected to the gate of the fourth transistor T4, and the second end of the second capacitor C2 is electrically connected to the first pole of the fourth transistor T4.
According to a second aspect of embodiments of the present disclosure, there is provided a driving method of a gate driving circuit, applicable to the electronic device described in the first aspect, the method including:
Controlling the first shift register to receive a second level signal provided by the second shift register;
the first shift register is controlled to output a first level signal when the second level signal is received.
Optionally, controlling the first shift register to output a first level signal when receiving the second level signal includes:
the clock signal input terminal CK is loaded with a first level signal, and the trigger signal terminal STV is loaded with a second level signal.
Optionally, controlling the first shift register to output a first level signal when receiving the second level signal includes:
when the first input terminal EM loads the second level signal, the trigger signal terminal STV loads the first level signal and the clock signal input terminal CK loads the second level signal, so that the first shift register outputs the second level signal.
Optionally, the method further comprises:
a second level signal is loaded at the first input EM to cause the first shift register to output the second level signal.
Optionally, the method further comprises:
the first shift register comprises a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;
The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are P-type thin film transistors, the first level signal is a low level signal, and the second level signal is a high level signal;
or alternatively, the process may be performed,
the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type thin film transistors, the first level signal is a high level signal, and the second level signal is a low level signal.
According to a third aspect of embodiments of the present disclosure, there is provided an electronic device including the gate driving circuit of the first aspect.
The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects:
as can be seen from the above embodiments, the gate driving circuit in the embodiments of the present disclosure includes a plurality of second shift registers cascaded with each other and a plurality of first shift registers cascaded with each other, and by connecting the output terminal of each of the second shift registers to the first input terminal of the first shift register located in the same row, the first shift register can receive the second level signal provided by the second shift register and indicating the line feed, during which the first shift register outputs the first level signal to realize driving of the pixel units of the corresponding row. Therefore, in the embodiment of the disclosure, the signals between the first mobile register and the second mobile register can be matched for use, so that the number of signal lines in the gate driving circuit can be reduced, and the size of the frame can be reduced. In addition, in the embodiment of the disclosure, the circuit structure of the first mobile register can be simplified, and the size of the frame is further reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic circuit diagram of a shift register for controlling data input of a display device according to the related art;
fig. 2 is a block diagram illustrating a structure of a gate driving circuit according to an exemplary embodiment;
FIG. 3 is a block diagram illustrating a first shift register according to an exemplary embodiment;
fig. 4 is a schematic circuit configuration diagram of a first shift register according to an exemplary embodiment;
FIG. 5 is a schematic diagram of a control timing of the first shift register shown in FIG. 4;
FIG. 6 is a flow chart of a driving method of the gate driving circuit shown in FIG. 2;
fig. 7 is a block diagram of an electronic device, according to an example embodiment.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus consistent with some aspects of the disclosure as detailed in the accompanying claims.
Input-output end definition: the first shift register includes a first input terminal (hereinafter, EM), a second input terminal (hereinafter, VGH), a clock signal input terminal (hereinafter, CK), a trigger signal terminal (hereinafter, STV), and a driving terminal (hereinafter, OUT). The first input end EM is electrically connected to the output end of the second shift register in the same row, the clock signal input end CK is electrically connected to a corresponding clock signal driving circuit (not shown in the drawing), the trigger signal end STV is electrically connected to the driving end OUT of the first shift register in the previous row, and the second input end VGH may be connected to a corresponding control circuit or power supply, and a direct connection power supply is taken as an example.
It should be noted that, since the clock signal input terminals CK of the adjacent two first shift registers are connected to the same clock signal driving circuit, but the timings of the clock signals received by the two first shift registers are different, the corresponding clock signal input terminals CK in the following figures are distinguished by CK1, CK2 and CK 3.
Fig. 2 is a block diagram illustrating a structure of a gate driving circuit according to an exemplary embodiment. As shown in fig. 2, the gate driving circuit includes a plurality of first shift registers and a plurality of second shift registers; the first shift registers are cascaded with each other to sequentially control data input of each row of display devices, and the second shift registers are cascaded with each other (only a partial cascade relationship is shown in fig. 2) to drive each row of display devices (not shown in the figure) to emit light;
For the first shift register and the second shift register located in the same row among the plurality of first shift registers and the plurality of second shift registers, the first shift register is electrically connected to an output terminal of the second shift register through a first input terminal (denoted by reference character EM in fig. 2) for outputting the first level signal when receiving the second level signal indicating the line feed provided by the second shift register.
In this embodiment, the gate driving circuit is exemplified by a part of the first register and a part of the second register. As shown in fig. 2, the gate driving circuit includes a first shift register and a second shift register corresponding to an n-1 th row, and an n+1 th row, respectively. The output end of the second shift register n-1 in the n-1 row is connected with the first input end EM n-1 of the first shift register n-1 in the n-1 row, the output end of the second shift register n in the n-1 row is connected with the first input end EMn of the first shift register n in the n-1 row, and the output end of the second shift register n+1 in the n+1 row is connected with the first input end EMn+1 of the first shift register n+1 in the n+1 row.
For the cascaded second shift register, the second shift register n-1 receives a corresponding control signal (not shown in fig. 2), and outputs a level signal for driving the n-1 th row display device to emit light according to a corresponding timing sequence. Meanwhile, the level signal output by the second shift register n-1 continues to serve as one trigger signal of the second shift register n, so that the second shift register n can continuously output the level signal for driving the n-th row of display devices to emit light by combining the level signal output by the second shift register n-1 and the corresponding control signal. Similarly, the level signal output by the second shift register n continues to be used as one of the trigger signals of the second shift register n+1, so that the second shift register n+1 can combine the level signal output by the second shift register n and the corresponding control signal to continue to output the level signal for driving the n+1th row display device to emit light.
In addition, the level signal output from the second shift register of the next row may be used as a reset signal (the connection relationship is shown by a broken line in fig. 2) of the second shift register of the previous row. For example, the level signal output by the second shift register n continues to be used as one trigger signal of the second shift register n+1, so that the second shift register n+1 can combine the level signal output by the second shift register n and the corresponding control signal to continue to output the level signal for driving the n+1th row display device to emit light, and meanwhile, the second shift register n+1 can feed back the level signal to the second shift register n to be used as a reset signal of the second shift register n, so that the second shift register n can be ensured to output the level signal which cannot trigger the second shift register n+1 to operate when the second shift registers of other rows operate.
For the first shift register in cascade connection, the first shift register n-1 receives corresponding control signals, such as a clock signal received by the clock signal input terminal CK, a level signal outputted from the first shift register n-2 (not shown in the figure) received by the trigger signal terminal STVn-1, and a level signal received by the second input terminal VGH, and outputs a level signal for controlling data inputted to the n-1-th row of display devices according to corresponding timings. Meanwhile, the level signal output by the first shift register n-1 continues to be used as the trigger signal STVn of the first shift register n, so that the first shift register n can continuously output the level signal for controlling the data input to the n-th row of display devices in combination with the level signal output by the first shift register n-1 and the corresponding control signal. Similarly, the level signal output by the first shift register n continues to serve as the trigger signal stvn+1 of the first shift register n+1, so that the first shift register n+1 can continuously output the level signal for controlling the data input to the n+1th row display device in combination with the level signal output by the first shift register n and the corresponding control signal.
In addition, the level signal output from the first shift register of the next row may be used as a reset signal (the connection relationship is shown by a broken line in fig. 2) of the first shift register of the previous row. For example, the level signal output by the second shift register n continues to be used as one trigger signal of the second shift register n+1, so that the second shift register n+1 can combine the level signal output by the second shift register n and the corresponding control signal to continue to output the level signal for driving the n+1th row display device to emit light, and meanwhile, the second shift register n+1 can feed back the level signal to the second shift register n to be used as a reset signal of the second shift register n, so that the second shift register n can be ensured to output the level signal which cannot trigger the second shift register n+1 to operate when the second shift registers of other rows operate.
As can be seen from the above embodiments, in the embodiments of the present disclosure, the output ends of the second shift registers located in the same row are connected to the first input end of the first shift register, so as to realize signal matching of the two shift registers in the same row, thereby reducing the number of signal lines in the gate driving circuit and being beneficial to reducing the size of the frame. In addition, in the embodiment of the disclosure, the circuit structure of the first mobile register can be simplified, and the size of the frame is further reduced.
In order to cooperate with the gate driving circuit, the embodiment of the disclosure further provides a circuit structure of the first shift register. To simplify the circuit structure of the first shift register, it is assumed in the embodiments of the present disclosure that the first shift register includes a plurality of thin film transistors, and that all of the thin film transistors are the same type of thin film transistors, such as P-type thin film transistors and N-type thin film transistors. It is understood that the plurality of thin film transistors may include both P-type thin film transistors and N-type thin film transistors, and the scheme of this embodiment may be implemented in the case of changing the corresponding control signals.
Based on the principle of the first shift register described above, the level signals of the respective input terminals and the respective output terminals thereof are set as the first level signal and the second level signal in the present embodiment. For example, when the first shift register is implemented by using a P-type thin film transistor, the first level signal is a low level signal, and the second level signal is a high level signal, that is, the first level signal is a level signal capable of turning on the P-type thin film transistor, and the second level signal is a level signal capable of turning off the P-type thin film transistor. For example, when the first shift register is implemented by using an N-type thin film transistor, the first level signal is a high level signal, and the second level signal is a low level signal, that is, the first level signal is a level signal capable of turning off the N-type thin film transistor, and the second level signal is a level signal capable of turning on the N-type thin film transistor. Of course, the voltage magnitudes of the first level signal and the second telecommunication signal may be set according to a specific scenario.
In this embodiment, all of the tfts in the first shift register are N-type tfts. On this basis, to achieve cooperation with the second shift register, the first shift register needs to have the following operation modes:
the first shift register outputs a second level signal when the first input end EM loads the first level signal;
the first shift register outputs a second level signal when the first input end EM loads the second level signal, the trigger signal end STV loads the first level signal and the clock signal input end CK loads the second level signal;
the first shift register outputs a first level signal when the first input terminal EM loads a second level signal, the trigger signal terminal STV loads a second level signal, and the clock signal input terminal CK loads a first level signal.
Based on the operation of the first shift register, the embodiment of the disclosure provides a first shift register, and fig. 3 is a block diagram of the structure of the first shift register according to an exemplary embodiment. As shown in fig. 3, the first shift register includes an input module, a pull-up module, a trigger module, and an output module, and a second input terminal VGH, a driving terminal OUT, a first node a, and a second node B. Wherein, the liquid crystal display device comprises a liquid crystal display device,
The input module is respectively and electrically connected with the first input end EM, the first node A and the clock signal input end CK and is used for conducting connection between the first input end EM and the first node A under the control of signals received by the clock signal input end CK;
the pull-up module is respectively and electrically connected with the second input end VGH, the driving end OUT and the first node A and is used for conducting connection between the second input end VGH and the driving end OUT according to the potential of the first node A;
the trigger module is respectively and electrically connected with the first node A, the second node B and the trigger signal end STV and is used for conducting connection between the first node A and the second node B under the control of signals received by the trigger signal end STV;
the output module is respectively and electrically connected with the clock signal input end CK, the driving end OUT and the second node B and is used for conducting connection between the clock signal input end CK and the driving end OUT according to the electric potential of the second node B.
Fig. 4 is a schematic circuit configuration diagram of a first shift register according to an exemplary embodiment. As shown in fig. 4, the input module includes a first transistor T1, a first control terminal, a first input terminal, and a first output terminal. The gate of the first transistor T1 is electrically connected to the first control terminal, the first pole of the first transistor T1 is electrically connected to the first input terminal EM, and the second pole of the first transistor T1 is electrically connected to the first output terminal.
The triggering module comprises a second transistor T2, a second control end, a second input end and a second output end. The gate of the second transistor T2 is electrically connected to the second control terminal, the first pole of the second transistor T2 is electrically connected to the second input terminal, and the second pole of the second transistor T2 is electrically connected to the second output terminal.
The output module comprises a first capacitor C1, a third transistor T3, a third control end, a third input end and a third output end. A gate of the third transistor T3 is electrically connected to the third control terminal, a first pole of the third transistor T3 is electrically connected to the third input terminal, and a second pole of the third transistor T3 is electrically connected to the third output terminal; the first end of the first capacitor C1 is electrically connected to the gate of the third transistor T3, and the second end of the first capacitor C1 is electrically connected to the second pole of the third transistor T3.
The pull-up module includes a second capacitor C2, a fourth transistor T4, a fourth control terminal, a fourth input terminal, and a fourth output terminal. The grid electrode of the fourth transistor T4 is electrically connected with the fourth control end, the first pole of the fourth transistor T4 is electrically connected with the fourth input end, and the second pole of the fourth transistor T4 is electrically connected with the fourth output end; the first end of the second capacitor C2 is electrically connected to the gate of the fourth transistor T4, and the second end of the second capacitor C2 is electrically connected to the first pole of the fourth transistor T4.
Fig. 5 is a schematic diagram of a control timing of the first shift register shown in fig. 4. As shown in fig. 5, the operation of the first shift register includes:
in the first stage of each image frame, a first level signal is loaded at the first input terminal EM, a first level signal is loaded at the clock signal input terminal CK, a second level signal is loaded at the trigger signal terminal STV, and a second level signal is loaded at the second input terminal VGH. When the clock signal input terminal CK is loaded with the first level signal, the first transistor T1 is turned on, thereby turning on the first input terminal EM and the first node a, i.e., the first node a is the first level signal. Since the first node a is the first level signal, the second transistor T2 and the fourth transistor T4 are turned on, the second transistor T2 turns on the trigger signal terminal STV and the second node B, i.e., the second node B is the second level signal, and at this time, the third transistor T3 is turned off. The fourth transistor T4 is turned on to turn on the second input terminal VGH and the driving terminal OUT, i.e., the driving terminal OUT outputs the second level signal.
In the second stage of each image frame, a first level signal is loaded at the first input terminal EM, a second level signal is loaded at the clock signal input terminal CK, a second level signal is loaded at the trigger signal terminal STV, and a second level signal is loaded at the second input terminal VGH. When the clock signal input terminal CK is loaded with the second level signal, the first transistor T1 is turned off, and the first node is still the first level signal due to the holding effect of the second capacitor C2, i.e. the second transistor T2 and the fourth transistor T4 are still turned on. Since the second transistor T2 remains on, the second level signal remains at the second node B, and thus the third transistor T3 remains off. Since the fourth transistor T4 remains turned on, the second input terminal VGH and the driving terminal OUT are continuously turned on, i.e., the driving terminal OUT still outputs the second level signal.
In the third stage of each image frame, the second level signal is loaded at the first input terminal EM, the second level signal is loaded at the clock signal input terminal CK, the first level signal is loaded at the trigger signal terminal STV, and the second level signal is loaded at the second input terminal VGH. When the clock signal input terminal CK is loaded with the second level signal, the first transistor T1 is turned off, and the first node is still the first level signal due to the holding effect of the second capacitor C2, i.e. the second transistor T2 and the fourth transistor T4 are still turned on. When the second transistor T2 is kept turned on, the trigger signal terminal STV loads the first level signal, and the second node B is the second level signal, and the third transistor T3 is turned on, so that the clock signal input terminal CK and the driving terminal OUT are turned on, i.e., the driving terminal OUT outputs the second level signal. While the fourth transistor T4 remains turned on, the second input terminal VGH and the driving terminal OUT are continuously turned on, i.e., the driving terminal OUT still outputs the second level signal. That is, the third transistor T3 and the fourth transistor T4 simultaneously ensure that the driving terminal OUT simultaneously outputs the second level signal in this stage.
In the fourth stage of each image frame, the second level signal is loaded at the first input terminal EM, the first level signal is loaded at the clock signal input terminal CK, the first level signal is loaded at the trigger signal terminal STV, and the second level signal is loaded at the second input terminal VGH. When the clock signal input terminal CK loads the first level signal, the first transistor T1 is turned on again, and turns on the first input terminal EM and the first node a, and the first node a is the second level signal at this time, and the second transistor T2 and the fourth transistor T4 are turned off at the same time, because the first input terminal EM loads the second level signal. Note that since the potential at the first node a and the potential of the second input terminal VGH are the same, resetting of the second capacitor C2 is achieved.
Due to the holding function of the capacitor C1, the third transistor T3 remains in an on state, and still turns on the clock signal input terminal CK and the driving terminal OUT, and the clock signal input terminal CK is loaded with the first level signal so that the driving terminal OUT outputs the first level signal. The potential at the second node B continues to decrease due to the pumping action of the first capacitor C1.
In the fifth stage of each image frame, a first level signal is loaded at the first input terminal EM, a second level signal is loaded at the clock signal input terminal CK, a second level signal is loaded at the trigger signal terminal STV, and a second level signal is loaded at the second input terminal VGH. When the clock signal input terminal CK is loaded with the second level signal, the first transistor T1 is turned off again, and the fourth transistor T4 is turned off at the time when the second capacitor C2 is reset in the fourth stage. Due to the holding function of the first capacitor C1, the potential at the second node B is smaller than the first potential signal, the third transistor T3 is turned on, the clock signal input terminal CK and the driving terminal OUT are turned on, and the driving terminal OUT outputs the second level signal due to the loading of the second level signal by the clock signal input terminal CK. At this time, the potential at the first capacitor C1 is raised (approximately equal to the first level signal).
In the sixth stage of each image frame, the first level signal is loaded at the first input terminal EM, the second level signal is loaded at the clock signal input terminal CK, the second level signal is loaded at the trigger signal terminal STV, and the second level signal is loaded at the second input terminal VGH. When the clock signal input terminal CK is loaded with the second level signal, the first transistor T1 is kept off, and the fourth transistor T4 is turned off at the time of resetting the second capacitor C2 in the fourth stage. Due to the holding function of the first capacitor C1, the potential at the second node B is smaller than the first potential signal, the third transistor T3 is turned on, the clock signal input terminal CK and the driving terminal OUT are turned on, and the driving terminal OUT outputs the second level signal due to the loading of the second level signal by the clock signal input terminal CK.
In the seventh stage of each image frame, the first level signal is loaded at the first input terminal EM, the first level signal is loaded at the clock signal input terminal CK, the second level signal is loaded at the trigger signal terminal STV, and the second level signal is loaded at the second input terminal VGH. When the clock signal input terminal CK loads the first level signal, the first transistor T1 is turned on to turn on the first input terminal EM and the first node a, i.e., the first node a is the first level signal. Since the first level signal is at the first node a, the second transistor T2 and the fourth transistor T4 are turned on. The second transistor T2 turns on the trigger signal terminal STV and the second node B, i.e., the second node B is a second level signal, and at this time, the third transistor T3 is turned off, and the second node B is a second level signal (i.e., resets the second capacitor C1). The fourth transistor T4 is turned on to turn on the second input terminal VGH and the driving terminal OUT, i.e., the driving terminal OUT outputs the second level signal.
According to the above process, the first shift register of each row repeats the first to seventh stages, thereby achieving the purpose of controlling data input of each row of display devices according to the second level signal indicating line feed provided by the second shift register. Therefore, in the embodiment of the disclosure, the signals between the first shift register and the second shift register can be used in cooperation, so that the number of signal lines in the gate driving circuit can be reduced (each first shift register only includes the clock signal input terminal CK, the trigger signal terminal STV and the second input terminal VGH), which is beneficial to reducing the size of the frame. In addition, in the embodiment of the disclosure, the circuit structure of the first mobile register can be simplified, and the size of the frame is further reduced.
Based on the gate driving circuit shown in fig. 2, the embodiment of the disclosure further provides a driving method of the gate driving circuit, as shown in fig. 6, including:
601, controlling the first shift register to receive a second level signal provided by the second shift register;
and 602, controlling the first shift register to output a first level signal when receiving the second level signal.
In an embodiment of the disclosure, controlling the first shift register to output a first level signal when receiving the second level signal includes: the clock signal input terminal CK of the first shift register is loaded with a first level signal, and the trigger signal terminal STV of the first shift register is loaded with a second level signal.
In another embodiment of the present disclosure, controlling the first shift register to output a first level signal when receiving the second level signal includes: when the first input terminal EM loads the second level signal, the trigger signal terminal STV loads the first level signal and the clock signal input terminal CK loads the second level signal, so that the first shift register outputs the second level signal.
In another embodiment of the present disclosure, the driving method includes: the second level signal is loaded at the first input EM to cause the first shift register to output the second level signal.
In yet another embodiment of the present disclosure, the first shift register includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. When the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are P-type thin film transistors, the first level signal is a low level signal, and the second level signal is a high level signal. Alternatively, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type thin film transistors, the first level signal is a high level signal, and the second level signal is a low level signal.
Fig. 7 is a block diagram of an electronic device, according to an example embodiment. For example, the electronic device 700 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.
A display;
a processor;
a memory for storing the processor-executable instructions;
wherein the display includes a gate driving circuit including:
a plurality of first shift registers and a plurality of second shift registers; the first shift registers are mutually cascaded and used for sequentially controlling the data input of each row of display devices, and the second shift registers are mutually cascaded and used for driving the display devices of each row to emit light;
for the first shift registers and the second shift registers in the same row, the first shift registers are electrically connected with the output ends of the second shift registers through the first input ends EM, and are used for outputting a first level signal when receiving a second level signal indicating line change provided by the second shift registers.
Referring to fig. 7, an electronic device 700 may include one or more of the following components: a processing component 702, a memory 704, a power component 706, a multimedia component 708, an audio component 710, an input/output (I/O) interface 712, a sensor component 714, a communication component 716, and a display 722.
The processing component 702 generally controls overall operation of the apparatus 700, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 702 may include one or more processors 720 to execute instructions. Further, the processing component 702 can include one or more modules that facilitate interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate interaction between the multimedia component 708 and the processing component 702.
The memory 704 is configured to store various types of data to support operations at the apparatus 700. Examples of such data include instructions for any application or method operating on the apparatus 700, contact data, phonebook data, messages, pictures, videos, and the like. The memory 704 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.
The power supply component 706 provides power to the various components of the device 700. The power components 706 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the device 700.
The multimedia component 708 includes a screen between the device 700 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 708 includes a front-facing camera and/or a rear-facing camera. The front-facing camera and/or the rear-facing camera may receive external multimedia data when the apparatus 700 is in an operational mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
The audio component 710 is configured to output and/or input audio signals. For example, the audio component 710 includes a Microphone (MIC) configured to receive external audio signals when the device 700 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 704 or transmitted via the communication component 716. In some embodiments, the audio component 710 further includes a speaker for outputting audio signals.
The I/O interface 712 provides an interface between the processing component 702 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.
The sensor assembly 714 includes one or more sensors for providing status assessment of various aspects of the apparatus 700. For example, the sensor assembly 714 may detect an on/off state of the device 700, a relative positioning of the components, such as a display and keypad of the device 700, a change in position of the device 700 or a component of the device 700, the presence or absence of user contact with the device 700, an orientation or acceleration/deceleration of the device 700, and a change in temperature of the device 700. The sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 714 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 716 is configured to facilitate communication between the apparatus 700 and other devices in a wired or wireless manner. The apparatus 700 may access a wireless network based on a communication standard, such as WiFi,2G or 3G, or a combination thereof. In one exemplary embodiment, the communication component 716 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the apparatus 700 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements.
In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided that includes instructions, such as memory 704 that includes instructions that are executable by processor 720 of apparatus 700. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (13)
1. A gate driving circuit is characterized by comprising a plurality of first shift registers and a plurality of second shift registers; the first shift registers are mutually cascaded and used for sequentially controlling the data input of each row of display devices, and the second shift registers are mutually cascaded and used for driving the display devices of each row to emit light;
for a first shift register and a second shift register which are positioned in the same row in the first shift registers and the second shift registers, the first shift register is electrically connected with the output end of the second shift register through a first input end EM and is used for outputting a first level signal when receiving a second level signal which is provided by the second shift register and indicates line feed; the first level signal is used for controlling data input of the display device of the current row and is also used as a trigger signal of the first shift register of the next row and a reset signal of the first shift register of the previous row.
2. The gate driving circuit according to claim 1, wherein the first shift register further comprises a clock signal input terminal CK, a trigger signal terminal STV, and a driving terminal OUT; the trigger signal end STV is connected with the driving end OUT of the first shift register of the upper row;
the first shift register outputs a second level signal when the first input end EM loads the first level signal;
the first shift register outputs a second level signal when the first input end EM loads the second level signal, the trigger signal end STV loads the first level signal and the clock signal input end CK loads the second level signal;
the first shift register outputs a first level signal when the first input terminal EM loads a second level signal, the trigger signal terminal STV loads a second level signal, and the clock signal input terminal CK loads a first level signal.
3. The gate drive circuit of claim 2, wherein the first shift register comprises: the device comprises an input module, a pull-up module, a trigger module and an output module, wherein the second input end VGH, a driving end OUT, a first node A and a second node B;
The input module is respectively and electrically connected with the first input end EM, the first node A and the clock signal input end CK and is used for conducting connection between the first input end EM and the first node A under the control of signals received by the clock signal input end CK;
the pull-up module is electrically connected with the second input end VGH, the driving end OUT and the first node A respectively and is used for conducting connection between the second input end VGH and the driving end OUT according to the potential at the first node A;
the trigger module is respectively and electrically connected with the first node A, the second node B and the trigger signal end STV and is used for conducting connection between the first node A and the second node B under the control of signals received by the trigger signal end STV;
the output module is electrically connected with the clock signal input end CK, the driving end OUT and the second node B respectively and is used for conducting connection between the clock signal input end CK and the driving end OUT according to the electric potential at the second node B.
4. A gate drive circuit as claimed in claim 3, wherein the input module comprises a first transistor T1, a first control terminal, a first input terminal and a first output terminal; the gate of the first transistor T1 is electrically connected to the first control terminal, the first pole of the first transistor T1 is electrically connected to the first input terminal, and the second pole of the first transistor T1 is electrically connected to the first output terminal.
5. A gate drive circuit as claimed in claim 3, wherein the triggering module comprises a second transistor T2, a second control terminal, a second input terminal and a second output terminal;
the gate of the second transistor T2 is electrically connected to the second control terminal, the first pole of the second transistor T2 is electrically connected to the second input terminal, and the second pole of the second transistor T2 is electrically connected to the second output terminal.
6. A gate drive circuit according to claim 3, wherein the output module comprises a first capacitor C1 and a third transistor T3, a third control terminal, a third input terminal and a third output terminal;
a gate of the third transistor T3 is electrically connected to the third control terminal, a first pole of the third transistor T3 is electrically connected to the third input terminal, and a second pole of the third transistor T3 is electrically connected to the third output terminal;
a first end of the first capacitor C1 is electrically connected to the gate of the third transistor T3, and a second end of the first capacitor C1 is electrically connected to the second pole of the third transistor T3.
7. A gate driving circuit according to claim 3, wherein the pull-up module comprises a second capacitor C2, a fourth transistor T4, a fourth control terminal, a fourth input terminal and a fourth output terminal;
The gate of the fourth transistor T4 is electrically connected to the fourth control terminal, the first pole of the fourth transistor T4 is electrically connected to the fourth input terminal, and the second pole of the fourth transistor T4 is electrically connected to the fourth output terminal;
the first end of the second capacitor C2 is electrically connected to the gate of the fourth transistor T4, and the second end of the second capacitor C2 is electrically connected to the first pole of the fourth transistor T4.
8. A driving method of a gate driving circuit, which is applicable to the gate driving circuit of claim 1, the method comprising:
controlling the first shift register to receive a second level signal provided by the second shift register;
controlling the first shift register to output a first level signal when receiving the second level signal; the first level signal is used for controlling data input of the display device of the current row and is also used as a trigger signal of the first shift register of the next row and a reset signal of the first shift register of the previous row.
9. The driving method according to claim 8, wherein controlling the first shift register to output a first level signal when receiving the second level signal comprises:
The clock signal input terminal CK is loaded with a first level signal, and the trigger signal terminal STV is loaded with a second level signal.
10. The driving method according to claim 8, wherein controlling the first shift register to output a first level signal when receiving the second level signal comprises:
when the first input terminal EM loads the second level signal, the trigger signal terminal STV loads the first level signal and the clock signal input terminal CK loads the second level signal, so that the first shift register outputs the second level signal.
11. The driving method according to claim 8, characterized in that the method further comprises:
the second level signal is loaded at the first input EM to cause the first shift register to output the second level signal.
12. The driving method according to claim 8, wherein the first shift register includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4;
the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are P-type thin film transistors, the first level signal is a low level signal, and the second level signal is a high level signal;
Or alternatively, the process may be performed,
the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type thin film transistors, the first level signal is a high level signal, and the second level signal is a low level signal.
13. An electronic device comprising the gate drive circuit according to any one of claims 1 to 7.
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