CN101093647A - Gate driving circuit and display apparatus having the same - Google Patents

Gate driving circuit and display apparatus having the same Download PDF

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Publication number
CN101093647A
CN101093647A CNA2007101114546A CN200710111454A CN101093647A CN 101093647 A CN101093647 A CN 101093647A CN A2007101114546 A CNA2007101114546 A CN A2007101114546A CN 200710111454 A CN200710111454 A CN 200710111454A CN 101093647 A CN101093647 A CN 101093647A
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signal
voltage
transistor
maintaining part
level
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CNA2007101114546A
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CN101093647B (en
Inventor
李旼哲
文胜焕
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Samsung Display Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR20070051904A external-priority patent/KR101512338B1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

In a gate driving circuit and a display apparatus, the gate driving circuit comprises a plurality of stages. At least one of the stages comprises a pull-up section responsive to a first node signal; a pull-down section responsive to a second input signal; a discharging section discharging the first node signal in response to the second input signal; a first holding section responsive to the first clock signal, maintaining the first node signal at the off-voltage; and a second holding section responsive to the second clock signal, maintaining the first node signal at the off-voltage. The second holding section has a greater transistor width-to-length ratio than the first holding section. Therefore, an abnormal gate-on signal is less likely to occur, reducing driving defects of the display apparatus.

Description

Gate driver circuit and have the display device of this gate driver circuit
Technical field
The present invention relates to a kind of gate driver circuit and have the display device of this gate driver circuit.In some embodiments, this gate driver circuit can reduce the driving defective.
Background technology
Usually, liquid crystal display (LCD) device comprises array base palte (array substrate), relative substrate and be arranged on liquid crystal layer between array base palte and the relative substrate.Liquid crystal layer comprises the liquid crystal molecule with anisotropy specific inductive capacity.In the LCD device, electric field puts on liquid crystal molecule, and according to the strength control transmittance of this electric field with display image.
The LCD device comprises the display panel that comprises array base palte and relative substrate, and further comprises gate driver circuit and data drive circuit.Display panel comprises by gate line and a plurality of pixel regions of limiting with the gate line data line crossing.Gate driver circuit outputs to gate line with signal, and data drive circuit outputs to data line with data-signal.Normally, gate driver circuit and data drive circuit form the integrated circuit (IC) chip that is installed on the display panel.
In order to reduce the LCD size and to increase throughput rate, gate driver circuit directly can be integrated on the display base plate.Yet, when at high temperature operating such integrated gate drive circuitry, can produce noise with the unusual gate turn-on signal form that occurs in grid trip time.
Because the stray capacitance (Cgd) between the grid of clock signal and pull up transistor (pull up transistor) produces noise.When the supposition transistor disconnected, this electric capacity was used to increase the transistor gate pole tension.Simultaneously, high temperature makes transistor drain current raise.Therefore, the connection that pulls up transistor.Unusually turn on the intermittence that pulls up transistor and cause display defect on the LCD.
Summary of the invention
Embodiments more of the present invention provide a kind of gate driver circuit that can reduce the driving defective of display device, and the display device with this gate driver circuit.
In embodiments more of the present invention, gate driver circuit comprises shift register, and it has a plurality of levels that are connected in series mutually (stage).This a plurality of level comprises one or more levels, and wherein each discipline comprises: on draw portion, receive first clock signal, and when first input signal is raised to high voltage, transmit first clock signal as signal at the first node signal response; Pull-down section is discharged to cut-off voltage (off voltage) in response to second input signal with signal; Discharge part is discharged to cut-off voltage in response to second input signal with the first node signal; First maintaining part in response to first clock signal, remains on cut-off voltage with the first node signal when signal is discharged to cut-off voltage; And second maintaining part, in response to the second clock signal, when first input signal is in cut-off voltage, the first node signal is remained on cut-off voltage, wherein, second maintaining part has the transistor breadth length ratio bigger than first maintaining part.
In embodiments more of the present invention, display device comprises: display panel, and it comprises external zones around the viewing area of display image and this viewing area, by gate line and a plurality of pixel regions of forming in the viewing area with the gate line data line crossing; Data drive circuit outputs to data line with data-signal; And gate driver circuit, have and be connected in series mutually and directly be integrated in a plurality of level on the external zones, in these grades each outputs to gate line with signal, wherein, described a plurality of level comprises one or more levels, its each discipline comprises: on draw portion, it transmits first clock signal as signal in response to the first node signal, wherein this first node signal response first input signal and be driven to noble potential; Pull-down section is discharged to cut-off voltage in response to second input signal with signal; Discharge part is discharged to cut-off voltage in response to second input signal with the first node signal; First maintaining part remains on the first node signal in response to first clock signal cut-off voltage of signal; And second maintaining part, in response to the second clock signal first node signal is remained on the cut-off voltage of first input signal, wherein, second maintaining part has the transistor breadth length ratio bigger than first maintaining part.
In some embodiments of the present invention, gate driver circuit comprises shift register, it has a plurality of levels that are connected in series mutually, each the level comprise: be connected in first clock terminal on draw portion, it is connected to lead-out terminal with first clock terminal, and signal is provided when first node is driven to noble potential in response to the signal on first input end; Pull-down section is discharged to cut-off voltage in response to the signal on second input terminal with lead-out terminal; Discharge part is discharged to cut-off voltage in response to the signal on second input terminal with first node; First maintaining part in response to the signal on first clock terminal, remains on cut-off voltage with first node when lead-out terminal is discharged to cut-off voltage; And second maintaining part, in response to the signal on the second clock terminal, when first input end is in cut-off voltage, first node is remained on cut-off voltage, wherein, second maintaining part has the transistor breadth length ratio bigger than first maintaining part.
In some embodiments of the present invention, gate driver circuit comprises a plurality of levels that are connected in series mutually.M level (wherein " m " is an integer) comprises draws portion, pull-down section, discharge part, first maintaining part and second maintaining part.On the portion of drawing receive first clock signal, and when the first node signal response is driven to high voltage in first input signal, transmit first clock signal as signal.Pull-down section is discharged to cut-off voltage in response to second input signal with signal.Discharge part is discharged to cut-off voltage in response to second input signal with the first node signal.First maintaining part remains on cut-off voltage with the first node signal in response to first clock signal when signal is discharged to cut-off voltage.Second maintaining part remains on cut-off voltage with the first node signal in response to the second clock signal when first input signal is in cut-off voltage.Second maintaining part comprises nonsymmetrical transistor.
In embodiments more of the present invention, display device comprises display panel, data-driven portion and gate driver circuit.Data drive circuit comprises a plurality of levels that are connected in series mutually.M level (wherein " m " is an integer) comprises draws portion, pull-down section, discharge part, first maintaining part and second maintaining part.On the portion of drawing receive first clock signal, and when the first node signal response is driven to high voltage in first input signal, transmit first clock signal as signal.Pull-down section is discharged to cut-off voltage in response to second input signal with signal.Discharge part is discharged to cut-off voltage in response to second input signal with the first node signal.First maintaining part remains on cut-off voltage with the first node signal in response to first clock signal when signal is discharged to cut-off voltage.Second maintaining part remains on cut-off voltage with the first node signal in response to the second clock signal when first input signal is in cut-off voltage.Second maintaining part comprises nonsymmetrical transistor.
According to embodiments more of the present invention, can be reduced at the last ripple (ripple) that produces in the control electrode of portion that draws, make to prevent unusual gate turn-on signal, drive defective thereby reduce.
Below other features and advantages of the present invention will be discussed.The present invention is defined by the following claims.
Description of drawings
When carrying out graphic extension by following embodiment with reference to the accompanying drawing discussion, above and other feature and advantage of the present invention will become more obvious, in the accompanying drawings:
Fig. 1 is the planimetric map according to the display device of the specific embodiment of the invention;
Fig. 2 shows the structural drawing according to the gate driver circuit of Fig. 1 of first embodiment;
Fig. 3 shows the schematic circuit of the level of Fig. 2;
Fig. 4 is the sequential chart of signal of the level of Fig. 3;
Fig. 5 is the schematic circuit of explaining and reducing at Fig. 3 voltages at nodes ripple;
Fig. 6 shows the sequential chart of the emulation voltage ripple of Fig. 5;
Fig. 7 shows the structural drawing according to the gate driver circuit of Fig. 1 of second embodiment;
Fig. 8 shows the schematic circuit of the level of Fig. 7;
Fig. 9 shows the schematic circuit according to the level of the gate driver circuit of the 3rd embodiment;
Figure 10 A and Figure 10 B show the planimetric map of the 9th transistorized structure among Fig. 9;
Figure 11 shows the curve map of the emulation voltage ripple at first node place in Fig. 9; And
Figure 12 shows the curve map of gate driver circuit according to the frequency characteristic of working time.
Embodiment
Hereinafter with reference to accompanying drawing embodiments more of the present invention are described.Yet the present invention can and should not be construed as limited to these embodiments that this paper proposes with many multi-form imbodies.And, provide these embodiments so that make present disclosure, and scope of the present invention is fully conveyed to those skilled in the art fully with complete.In the accompanying drawings, the size and the relative size in each floor and district are not used for representing actual size.
Be to be understood that, when mention an element or layer another element or layer " on ", during with another element or layer " connection " or " coupling ", its can be directly at this another element or above the layer, directly is connected with this another element or layer or direct the coupling, perhaps replacedly, can there be medium element or layer.On the contrary, when mentioning " directly exist " another element or layer is gone up, " being directly connected in " or " being coupled directly to " another element or layer of an element, then there are not medium element or layer.Same tag refers to similar elements all the time.As used herein, term " and/or " comprise in the relevant listed clauses and subclauses one or more arbitrarily or all combinations.
Although should be appreciated that and can use the term first, second, third, etc. to describe different elements, parts, zone, layer and/or part in this article, these elements, parts, zone, layer and/or part should not be subjected to the restriction of these terms.These terms only are used for distinguishing an element, parts, zone, layer or part and another element, parts, zone, layer or part.Therefore, under the situation that does not deviate from the present invention's instruction, " first " discussed below element, parts, zone, layer or part can replacedly be called " second " element, parts, zone, layer or part.
For ease of describing, in this article can the usage space relational language as " ... under ", " ... following ", D score, " ... top ", " on " wait a feature and the relation of feature in addition described.Should be appreciated that these space correlation terms are not used in the particular space orientation that limits the invention to use or operating device.For example, if with the reversing of the device described among the figure, then be described as other element " below " or the element of " below " will be oriented in " top " of this other element.Therefore, term " ... following " be not used for getting rid of such orientation.This device is directed (revolve and turn 90 degrees or other angle) otherwise.
The purpose that term as used herein only is used to describe embodiment is not limited to the present invention.As used herein, singulative " one " " a kind of " also be used to comprise most forms, is other situation unless clearly indicate in the literary composition.Should further understand, when using in this manual, term " comprises " and/or illustrates " comprising " existence of described feature, integral body, step, operation, element and/or parts, but does not get rid of the existence of other one or more further features, integral body, step, operation, element, parts and/or their group.
This paper describes the specific embodiment of the present invention with reference to cross sectional view, and this diagrammatic sketch schematically shows desirable embodiment of the present invention (and intermediate structure).Like this, can reckon with and exist because for example distortion of the shape shown that causes of manufacturing technology and/or tolerance.Therefore, the specific embodiment of the present invention should not be construed as limited to the illustrated given shape of this paper, and comprises for example according to making the deviation that distortion produces.For example, have circle or bending features usually and/or in the implantation concentration gradient of edge with the injection zone shown in the rectangle, rather than absolute straight flange or on the border of the sudden change (abrupt) at injection/non-injection zone place.Equally, other doped region can inject at the ion between injection zone of estimating and the surface of injecting by it and form.Therefore, the regional essence shown in the figure is schematically, and their shape is not used in the actual shape of expression or limits the scope of the invention.
Describe the present invention in detail now with reference to accompanying drawing.
Fig. 1 shows the planimetric map according to the display device of the specific embodiment of the invention.This display device comprises display panel 100, is used to drive the gate driver circuit 200 and the data drive circuit 130 of display panel 100.
Display panel 100 comprises array base palte, spaced a predetermined distance from array base palte and in the face of the relative substrate (for example, color filter substrate) of array base palte and be arranged on liquid crystal layer between array base palte and the relative substrate.Display panel 100 comprises the external zones PA around viewing area DA and this viewing area DA.Viewing area DA comprises the gate lines G L that extends along first direction, along the data line DL of the second direction extension that intersects with first direction and a plurality of pixel regions that are used for display image that limit by gate lines G L and data line DL.
In each pixel region, form thin film transistor (TFT) (TFT), the liquid crystal capacitance CLC that is electrically connected on TFT and memory capacitance CST as switching device.The gate electrode of TFT is electrically connected on gate lines G L, and the source electrode of TFT is electrically connected on data line DL, and the drain electrode of TFT is electrically connected on liquid crystal capacitance CLC and memory capacitance CST.
External zones PA be included in data line DL an end the first external zones PA1 and at the second external zones PA2 of the end of gate lines G L.
Data drive circuit 130 comprises one or more data driving chip 132, is used for synchronously data-signal being outputed to data line DL with the signal that is applied to gate lines G L.Each data driving chip 132 is installed on the flexible printed circuit board (FPCB) 134.The side attachment of FPCB 134 is in PCB 140, and FPCB 134 is electrically connected on PCB 140.Data driving chip 132 is electrically connected on PCB 140 and display panel 100 by FPCB 134.
Gate driver circuit 200 comprises having a plurality of grades the shift register of being connected in series, and is used for sequentially providing on gate line the gate turn-on signal.Gate driver circuit 200 is integrated on the second external zones PA2 of display panel 100 as integrated circuit.Integrated gate driver circuit 200 can be made by one or more different materials, comprises for example low resistance metal layer, as is used to improve three layers of molybdenum/aluminium/molybdenum (Mo/Al/Mo) of driving margin (driving margin).
Fig. 2 is the structural drawing according to the gate driver circuit of Fig. 1 of first embodiment.This gate driver circuit comprises circuit part CS and circuit pack LS.Circuit part CS comprises the 1st grade of SRC1～(n+1) level SRC (n+1) that is connected in series mutually, is used for signal GOUT is outputed to their lead-out terminal OUT separately, and wherein signal GOUT is urged to the gate-on voltage level subsequently.Circuit pack LS provides control signal for circuit part CS.
The 1st grade of SRC1～n level SRCn is drive(r) stage, and (n+1) level SRCn+1) be diastema level (dummy stage).Each of the 1st grade of SRC1～(n+1) level SRC (n+1) comprises the first clock terminal CK1, second clock terminal CK2, the sub-IN1 of first input end, the second input terminal IN2, voltage terminal V, reseting terminal RE, carry (carry) terminal CR and lead-out terminal OUT.
The anti-phase clock signal of clock signal on the first clock terminal CK1 reception of each among these grades SRC (that is each of level SRC1～SRC (n+1)) and the second clock terminal CK2 of this grade.More specifically, odd level SRC1, SRC3 etc. receive the first clock signal C K at its first clock terminal CK1 place, and receive and the anti-phase second clock signal CKB of the first clock signal C K at its second clock terminal CK2 place.Even level SRC2, SRC4 etc. receive second clock signal CKB at its first clock terminal CK1 place, and receive and the first anti-phase clock signal C K of this second clock signal CKB at its second clock terminal CK2 place.
The sub-IN1 of the first input end of each grade SRC receives the carry signal CR of vertical start signal STV or upper level.For example, the sub-IN1 of the first input end of first order SRC1 receives vertical start signal, and each the carry signal of upper level separately of the sub-IN1 receiver stage of first input end SRC1～SRCn of level SRC2～SRC (n+1).
The second input terminal IN2 of each grade SRC receives the signal GOUT or the vertical start signal STV of next stage.For example, the second input terminal IN2 of the 1st grade of SRC1～n level SRCn receives the signal GOUT of next stage SRC2～SRC (n+1) separately, and the second input terminal IN2 of final stage SRC (n+1) receives vertical start signal STV.
Cut-off voltage is offered the voltage terminal V of each grade in these grades.In some embodiments, this cut-off voltage be pact-5V～-7V.
The carry signal of final stage SRC (n+1) is offered the reseting terminal RE of each grade in these grades.
In each SRC level,, the high potential signal on the first clock terminal CK1 can be offered the lead-out terminal OUT of this SRC level as the first clock terminal CK1 when being high.Particularly, in some embodiments, as the first clock signal C K when being high, with the first clock signal C K of noble potential offer odd level SRC1, SRC3 ... one of lead-out terminal OUT, wherein continuous odd level provides the first clock signal C K of noble potential in the consecutive periods separately of the first clock signal C K.As second clock signal CKB when being high, the second clock signal CKB of this noble potential be provided for even level SRC2, SRC4 ... one of lead-out terminal OUT, wherein continuous even level provides the second clock signal CKB of noble potential in the consecutive periods separately of second clock signal CKB.By this way, the 1st grade of SRC1～(n+1) level SRC (n+1) sequentially is urged to the gate-on voltage current potential with their signal GOUT.
Circuit pack LS is formed on the side of circuit part CS, and comprises a plurality of circuits that are used for signal CK, CKB, STV and cut-off voltage VOFF are offered the 1st grade～(n+1) level.More specifically, circuit pack LS comprises the start signal line SL1 that is used for vertical start signal STV, the first clock line SL2 that is used for the first clock signal C K, the second clock line SL3 that is used for second clock signal CKB, the pressure-wire SL4 that is used for cut-off voltage VOFF and reset line SL5.Vertical start signal STV offers start signal line SL1 from the outside, and start signal line SL1 offers the 1st grade sub-IN1 of first input end and the second input terminal IN2 of final stage with vertical start signal STV.In other words, start signal line SL1 offers the sub-IN1 of first input end of the 1st grade of SRC1 and the second input terminal IN2 of (n+1) level SRC (n+1) with vertical start signal STV.
The first clock signal C K offers the first clock line SL2 from the outside, and the first clock line SL2 with the first clock signal C K offer odd level SRC1, SRC3 ... the first clock terminal CK1 and even level SRC2, SRC4 ... second clock terminal CK2.
The second clock signal CKB anti-phase with the first clock signal C K offers second clock line SL3 from the outside, and second clock line SL3 with second clock signal CKB offer odd level SRC1, SRC3 ... second clock terminal CK2 and even level SRC2, SRC4 ... the first clock terminal CK1.
Cut-off voltage Voff is provided for pressure-wire SL4, and pressure-wire SL4 offers cut-off voltage Voff the voltage terminal V of the 1st grade of SRC1～(n+1) level SRC (n+1).The carry signal of final stage SRC (n+1) is provided for reset line SL5, and reset line SL5 offers carry signal the reseting terminal RE of the 1st grade of SRC1～(n+1) level SRC (n+1).
As mentioned above, the carry signal that each grade SRCm (m＞1) receives (m-1) level SRC (m-1) at the sub-IN1 of first input end is as first input signal, and each grade SRCm (m＜n+1) receive the signal GOUT of (m+1) level SRC (m+1) as second input signal at the second input terminal IN2.Yet, in other embodiment, SRCm is in the sub-IN1 receiver stage of first input end (m-2), (m-3), (m-4) or some other carry signals in prime for level, and/or receiver stage (m+2), (m+3), (m+4) or some other signal GOUT in the back level.
Fig. 3 shows the schematic circuit of the level among Fig. 2, and Fig. 4 is the sequential chart of the signal of the level among Fig. 3.
With reference to Fig. 3 and Fig. 4, in the gate driver circuit 200 according to present embodiment, m level SRCm comprises and draws portion 210 and pull-down section 220.In response to (m-1) level SRC (m-1) carry signal, on draw portion 210 to move the voltage of the first clock terminal CK1 on m the signal GOUT to.After signal GOUT was drawn on like this, in response to the signal GOUT (m+1) of (m+1) level, pull-down section 220 pulled down to cut-off voltage Voff with m level signal GOUTm.
On draw portion 210 to comprise the 5th transistor T 5, it has the gate electrode that is connected in first node N1, the source electrode that is connected in the drain electrode of the first clock terminal CK1 and is connected in lead-out terminal OUT.Therefore, the drain electrode of the 5th transistor T 5 receives the first clock signal C K or second clock signal CKB by the first clock terminal CK1.
Pull-down section 220 comprises the 6th transistor T 6, and it has the gate electrode that is connected in Section Point N2, the source electrode that is connected in the drain electrode of lead-out terminal OUT and is connected in voltage terminal V.Cut-off voltage is provided for the source electrode of the 6th transistor T 6.
The m level further comprises draws driving circuit.On draw driving circuit to draw portion 210 on connecting in response to the carry signal of (m-1) level SRC (m-1), and disconnect in response to the signal GOUT (m+1) of (m+1) level SRC (m+1) and to draw portion 210.On draw driving circuit to comprise buffer part 280, charging part 270 and discharge part 230.
Buffer part 280 comprises the 13 transistor T 13, and it has the gate electrode that is connected in the sub-IN1 of first input end, the source electrode that is connected in the drain electrode of the sub-IN1 of first input end and is connected in first node N1.Charging part 270 comprises the 3rd capacitor C 3, and it has first electrode that is connected in first node N1 and second electrode that is connected in lead-out terminal OUT.Discharge part 230 comprises the 7th transistor T 7, and it has the gate electrode that is connected in the second input terminal IN2, the source electrode that is connected in the drain electrode of first node N1 and is connected in voltage terminal V.Cut-off voltage Voff is provided for the source electrode of the 7th transistor T 7.
On this, draw in the driving circuit, when the 13 transistor T 13 is switched in response to (m-1) level, the carry signal of (m-1) level SRC (m-1) is applied to first node N1 first node N1 being urged to high voltage, and the carry signal of (m-1) level gives the 3rd capacitor C 3 chargings.When the 3rd capacitor C 3 was charged to the threshold voltage of at least the five transistor T 5 and the first clock terminal CK1 and uprises, the 5th transistor T 5 was connected so that the high voltage of the first clock terminal CK1 is transferred to lead-out terminal OUT.
In this embodiment, when the 5th transistor T 5 was connected, the 5th transistor T 5 exported the gate turn-on signal on the lead-out terminal OUT of m level SRCm to.Then, when the 7th transistor T 7 was switched in response to (m+1) individual signal GOUT (m+1), the 3rd capacitor C 3 was discharged to the cut-off voltage of voltage terminal V, makes the 5th transistor T 5 be disconnected.
M level SRCm further comprises first maintaining part 242 and second maintaining part 244 that first node N1 is remained on cut-off voltage Voff.
First maintaining part 242 comprises the 8th transistor T 8, and it has the gate electrode that is connected in the first clock terminal CK1, the source electrode that is connected in the drain electrode of first node N1 and is connected in lead-out terminal OUT.Second maintaining part 244 comprises the 9th transistor T 9, and it has the gate electrode that is connected in second clock terminal CK2, the source electrode that is connected in the drain electrode of the sub-IN1 of first input end and is connected in first node N1.
First maintaining part 242 and second maintaining part 244 remain on cut-off voltage Voff with first node N1 after m signal GOUTm is discharged to cut-off voltage Voff by pull-down section 220.Especially, when m signal GOUTm has been discharged to cut-off voltage Voff and the 8th transistor T 8 and has connected in response to the clock signal on the first clock terminal CK1, the Voff voltage of m signal GOUTm is applied in to first node N1, so that first node N1 is remained on cut-off voltage Voff.In addition, when the 9th transistor T 9 in response to the first clock terminal CK1 on the second clock terminal CK2 of signal inversion on clock signal and when being switched on, first input signal that is in cut-off voltage Voff is applied in to first node N1, so that first node N1 is remained on cut-off voltage Voff.
Therefore, in response to separately the first clock terminal CK1 and the signal on the second clock terminal CK2, each in first maintaining part 242 and second maintaining part 244 sequentially is switched on, so that first node N1 is remained on cut-off voltage Voff.
M level SRCm further comprises the 3rd maintaining part 246, the 4th maintaining part 248 and switching part 250.The 3rd maintaining part 246 and the 4th maintaining part 248 remain on cut-off voltage Voff with m signal GOUTm.The on/off (on/off) of switching part 250 controls the 4th maintaining part 248 is switched.
The 3rd maintaining part 246 comprises the tenth transistor T 10, and it has the gate electrode that is connected in second clock terminal CK2, the source electrode that is connected in the drain electrode of lead-out terminal OUT and is connected in voltage terminal V.The source electrode of the tenth transistor T 10 receives cut-off voltage Voff.The 4th maintaining part 248 comprises the 11 transistor T 11, and it has the gate electrode of the Section Point N2 that is connected in switching part 250, the source electrode that is connected in the drain electrode of lead-out terminal OUT and is connected in voltage terminal V.The source electrode of the 11 transistor T 11 receives cut-off voltage Voff.
Switching part 250 comprises the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4, and first capacitor C 1 and second capacitor C 2.
The first transistor T1 has the gate electrode that is connected in the first clock terminal CK1, the source electrode that is connected in the drain electrode of the first clock terminal CK1 and is connected in the drain electrode of transistor seconds T2.Gate electrode and drain electrode receive the signal on the first clock terminal CK1.Transistor seconds T2 has the gate electrode that is connected in lead-out terminal OUT and is connected in voltage terminal V to receive the source electrode of cut-off voltage Voff.The source electrode that the 3rd transistor T 3 has the drain electrode that is connected in the first clock terminal CK1, is connected in the gate electrode of the first clock terminal CK1 and is connected in Section Point N2 by capacitor C 1.Therefore, the drain electrode of the 3rd transistor T 3 and gate electrode receive the signal on the first clock terminal CK1.Second capacitor C 2 is connected between the gate electrode and source electrode of the 3rd transistor T 3.The 4th transistor T 4 has the gate electrode that is connected in lead-out terminal OUT, is connected in the drain electrode of Section Point N2 and is connected in voltage terminal V to receive the source electrode of cut-off voltage Voff.
When the first transistor T1 and transistor seconds T3 connect by the signal on the first clock terminal CK1 and the first clock terminal CK1 on signal when being passed to lead-out terminal OUT, lead-out terminal OUT is pulled to high voltage.Correspondingly, transistor seconds T2 and the 4th transistor T 4 are switched on, and are discharged by transistor seconds T2 and the 4th transistor T 4 by the electric current that the first transistor T1 and the 3rd transistor T 3 provide.Therefore, Section Point N2 is maintained at low-voltage, makes the 11 transistor T 11 be disconnected.
Then, when m signal GOUTm was discharged to cut-off voltage Voff in response to (m+1) individual signal GOUT (m+1), the voltage on the lead-out terminal OUT was reduced to electronegative potential gradually.Therefore, transistor seconds T2 and the 4th transistor T 4 disconnect, and Section Point N2 is pulled to noble potential by the first transistor T1 and the 3rd transistor T 3.Correspondingly, the 11 transistor T 11 is connected, fast lead-out terminal OUT is discharged to cut-off voltage Voff.
Then, when the first clock terminal CK1 became low-voltage, Section Point N2 also became low-voltage, made the 11 transistor T 11 be switched on.Yet the tenth transistor T 10 is switched on by the voltage on the second clock terminal CK2 (voltage inversion on its voltage and the first clock terminal CK1), makes lead-out terminal OUT be discharged to cut-off voltage Voff.
In response at separately second clock terminal CK2 and the signal on the first clock terminal CK1, each of the 3rd maintaining part 246 and the 4th maintaining part 248 sequentially is discharged to cut-off voltage Voff with lead-out terminal OUT.
The m level of gate driver circuit 200 further comprises reset portion 260 and carry part 290.
Reset portion 260 comprises the tenth two-transistor T12, and it has the gate electrode that is connected in reseting terminal RE, is connected in the drain electrode of first node N1 and is connected in voltage terminal V to receive the source electrode of cut-off voltage Voff.When the carry signal of final stage SRC (n+1) was provided for reseting terminal RE, the tenth two-transistor T12 was switched on, and made first node N1 be discharged to cut-off voltage Voff.Therefore, m level signal GOUTm is discharged to cut-off voltage Voff by the carry signal of (n+1) level SRC (n+1).
Carry part 290 comprises the 14 transistor T 14, and it has the gate electrode that is connected in first node N1, the drain electrode that is connected in the first clock terminal CK1 (for example, to receive the first clock signal C K) and the source electrode that is connected in carry terminal CR.When the voltage on the first node N1 uprised, carry part 290 passed to carry terminal CR with the noble potential of the first clock signal C K.
In the gate driver circuit according to this embodiment, first maintaining part of m level has different electrical characteristics with second maintaining part.For example, in some implementations, the 9th transistorized breadth length ratio (W/L) is greater than the 8th transistorized breadth length ratio (W/L), to reduce the ripple at first node N1 place.
Minimizing now with reference to the ripple at accompanying drawing detailed explanation first node place.
Fig. 5 shows the schematic circuit that the ripple at the first node place of some embodiments according to the present invention improves.
With reference to Fig. 5, on being connected in, draw the first node N1 place of the control electrode of portion 210 ripple to occur, this be since first node N1 by on draw the first stray capacitance Cgd1, the second stray capacitance Cgd2 and the trixenie capacitor C gd3 of portion 210, first maintaining part 242 and carry part 290 to be coupled in the first clock terminal CK1.More specifically, the drain electrode of the 14 transistor T 14 and the first clock terminal CK1 of the trixenie capacitor C gd3 between the gate electrode cause ripple by the drain electrode of the first stray capacitance Cgd1 between drain electrode that is coupled in (a) the 5th transistor T 5 and the gate electrode, (b) the 8th transistor T 8 and the second stray capacitance Cgd2 between the gate electrode and (c).
When supposition the 5th transistor T 5 was disconnected, ripple may be connected this transistor, made to produce unusual gate turn-on signal on lead-out terminal OUT, to cause the driving defective.For example, suppose that the first clock terminal CK1 receives the first clock signal C K, then the rising edge of the first clock signal C K (rising edge) voltage on the first node N1 that can raise to produce unusual gate turn-on signal, makes defective to occur driving.
In addition, the stray capacitance Cgs of second maintaining part 244 can cause ripple on first node N1.This capacitor C gs is coupled in second clock terminal CK2 with first node N1.Stray capacitance Cgs is the electric capacity between the gate electrode of the 9th transistor T 9 and source electrode.In this case, because the signal on the second clock terminal CK2 has anti-phase with respect to the signal on the first clock terminal CK1, so the ripple (" oppositely ripple ") that is caused by the stray capacitance with second clock terminal CK2 coupling has anti-phase with respect to the ripple that is caused by the stray capacitance with first clock terminal CK1 coupling.Therefore, the ripple that the reverse ripple compensation that is caused by the stray capacitance with second clock terminal CK2 coupling is caused by the stray capacitance with first clock terminal CK1 coupling, thus reduced total ripple at first node N1 place.In some embodiments, the size of the difference between the ripple that the degree that total ripple can be reduced is equivalent to be caused by stray capacitance Cgd1, the Cgd2 of the 5th transistor T 5, the 8th transistor T 8 and the 14 transistor T 14 and ripple that Cgd3 causes and stray capacitance Cgs by the 9th transistor T 9, thus minimizing is at total ripple at first node N1 place.
Therefore, if the 9th transistor T 9 has bigger breadth length ratio (W/L) to increase stray capacitance Cgs, then oppositely ripple increases, to reduce the total ripple at first node N1 place.
The oscillogram of the emulation ripple at the first node N1 place that Fig. 6 shows at Fig. 5.
In the embodiment of Fig. 6, suppose that first node N1 is in-cut-off voltage of 7V during " grid disconnection ", that is, and when signal GOUT is in the grid off voltage.Yet because the caused ripple of stray capacitance between first node N1 and the clock terminal, first node N1 can be raised to more high voltage.Yet, wide than the raceway groove of 25 μ m, wide if the 9th transistor T 9 has the raceway groove of 900 μ m, ripple less (the supposition channel length is identical for both of these case).
Table 1 shows the simulation value for the ripple at the first node N1 place of the different breadth length ratios (W/L) of the 9th transistor T 9.These values also are shown among Fig. 6.These values are to obtain under channel length L is the situation of constant and the channel width W numerical value that is assumed to 25 μ m, 354 μ m, 500 μ m and 900 μ m.Before the 9th transistor T 9 is aging and afterwards, the 9th transistor T 9 is carried out hot operation obtain this result.
[table 1]
Von＝23V，Voff＝-7V The ripple at first node N1 place
The width of T9 [μ m] 25 354 500 900
At high temperature drive 2.53 2.21 2.05 1.61
At high temperature drive after aging 2.71 2.6 2.5 2.24
As shown in table 1, in the hot operation before the 9th transistor T 9 for 25 μ m channel widths wears out, ripple is about 2.53V; For 354 μ m channel widths, ripple is about 2.21V; For 500 μ m channel widths, ripple is about 2.05 V; And for 900 μ m channel widths, ripple is about 1.61V.Therefore, the ripple at the first node place can reduce by the channel width that increases by the 9th transistor T 9.
In the hot operation after aging, for 25 μ m channel widths of the 9th transistor T 9, ripple is about 2.71V; For 354 μ m channel widths of the 9th transistor T 9, ripple is about 2.6V; For 500 μ m channel widths, ripple is about 2.5V; And for 900 μ m channel widths, ripple is about 2.24V.Therefore, in this case, perhaps also can reduce ripple by increasing the channel width of the 9th transistor T 9 at the first node place.
When the discharge of the 3rd capacitor C 3, the effect that 9 performances of the 9th transistor T are the same with the 13 transistor T 13.Therefore, if the breadth length ratio of the 9th transistor T 9 (W/L) increases, then current-voltage (I-V) characteristic can improve and the charge rate of the 3rd capacitor C 3 by first input signal can be improved, and makes the low temperature driving margin (margin) of the 5th transistor T 5 to be enhanced.
Table 2 shows the result who is obtained for the low temperature driving margin of the 9th transistor T 9 of different breadth length ratios (W/L) and normal temperature frequency drives tolerance limit.These results remain unchanged and the channel width of the 9th transistor T 9 is assumed under the situation of numerical value of 25 μ m and 936 μ m and obtains in the channel length with the 9th transistor T 9.
[table 2]
Condition The temperature of driving defective [℃] Normal temperature frequency drives tolerance limit [Hz] Voltage [V]
The width of T9 [μ m] Cgs∶Cgd Min. Max. Min. Max. dV Voff
25 10 -33 -18 115 121 38 -7.4
936 11 -50 -24 124 ＞130 34～38 -7.4
As shown in table 2, if the breadth length ratio of the 9th transistor T 9 (W/L) increases, then the 9th transistor T 9 can move down in low-voltage (dV) and low temperature (being lower than-20 ℃), and normal temperature frequency drives tolerance limit increases above 124Hz.
Therefore, in some embodiments of gate driver circuit of the present invention, the 9th transistor T 9 has the breadth length ratio (W/L) greater than the 8th transistor T 8.Therefore, thus oppositely ripple increases the total ripple that reduces first node N1 place.In addition, when the 9th transistor T 9 and the 13 transistor T 13 were all connected, the 3rd capacitor C 3 improved by the charge rate of first input signal, so the low temperature driving margin improves.
Yet, if the breadth length ratio of the 9th transistor T 9 (W/L) is too big, the 9th transistor T 9 will be owing to threshold voltage shift cisco unity malfunction; The 9th transistor T 9 is only brought into play the effect of stray capacitance Cgs thus.This is referred to herein as " transistor ageing ".Then, the 5th transistor T 5 can not be by driven.Therefore, the breadth length ratio of the 9th transistor T 9 (W/L) should be preferably more than the 8th transistor T 8, but less than the summation of the breadth length ratio (W/L) of the 8th transistor T 8 and the 14 transistor T 14.
Fig. 7 shows the detailed structure view according to the gate driver circuit of Fig. 1 of second embodiment.The gate driver circuit of this embodiment is similar to the gate driver circuit of first embodiment.Therefore, will use the same reference surface to refer to the identical or similar portions of first and second embodiment, and avoid the repetition of explanation explanation of these parts.
The gate driver circuit 200 of Fig. 7 comprises circuit part CS and circuit pack LS.Circuit part CS comprises the 1st grade of SRC1～(n+1) the level SRC (n+1) that is connected in series mutually, is used for sequentially exporting gate-on voltage as signal GOUT.Circuit pack LS offers circuit part CS with various control signals.
Each level of the 1st grade of SRC1～(n+1) level SRC (n+1) comprises the first clock terminal CK1, second clock terminal CK2, the sub-IN1 of first input end, the second input terminal IN2, voltage terminal V, reseting terminal RE and lead-out terminal OUT.
First clock terminal CK1 of each grade of the 1st grade of SRC1～(n+1) level SRC (n+1) and second clock terminal CK2 receive anti-phase clock signal.
Vertical start signal STV is provided for the sub-IN1 of first input end of the 1st grade of SRC1.Signal GOUT1～GOUTn of the 1st grade of SRC1～n level SRCn offers the sub-IN1 of first input end of next stage SRC2～SRC (n+1) separately separately.Signal GOUT2～GOUT (n+1) offers the second input terminal IN2 of upper level SRC1～SRCn separately, and vertical start signal STV offers the second input terminal IN2 of (n+1) level SRC (n+1).
The signal GOUT (n+1) of (n+1) level SRC (n+1) offers the reseting terminal RE of the 1st grade of SRC1～(n+1) level SRC (n+1).Cut-off voltage Voff offers the voltage terminal V of the 1st grade of SRC1～(n+1) level SRC (n+1).Each SRC level can be delivered to lead-out terminal OUT with the noble potential clock signal on the first clock terminal CK1.
Circuit pack LS comprises start signal line SL1, the first clock cable SL2, second clock signal wire SL3, pressure-wire SL4 and reset line SL5.
Vertical start signal STV offers start signal line SL1 from the outside, and start signal line SL1 offers the sub-IN1 of first input end of the 1st grade of SRC1 and the second input terminal IN2 of (n+1) level SRC (n+1) with this vertical start signal STV.
The first clock cable SL2 receives the first clock signal C K, and second clock signal wire SL3 receives and the anti-phase second clock signal CKB of the first clock signal C K.The first clock cable SL2 and second clock signal wire SL3 offer the 1st grade of SRC1～(n+1) level SRC (n+1) with the first clock signal C K and second clock signal CKB.
Pressure-wire SL4 receives cut-off voltage Voff, and this cut-off voltage Voff is offered the voltage terminal of the 1st grade of SRC1～(n+1) level SRC (n+1).
Reset line SL5 receives the signal GOUT (n+1) of final stage SRC (n+1), and this signal GOUT (n+1) is offered the reseting terminal RE of the 1st grade of SRC1～(n+1) level SRC (n+1).
According to present embodiment, each of gate driver circuit m level SRCm (m＞1) receives the operation required start signal of the signal GOUT (m-1) of (m-1) level SRC (m-1) as m level SRCm.
Fig. 8 shows the schematic circuit of the single SRC level of Fig. 7.
The SRC level of present embodiment is similar to the SRC level of first embodiment.Therefore, will use same reference numerals to refer to identical or similar portions among first and second embodiment, and avoid the repetition of explanation explanation.
With reference to Fig. 8, (1≤m≤n+1) comprises and draws portion 210 and pull-down section 220 level SRCm.On draw portion 210 m level signal GOUTm to be pulled to the voltage (supposition in order to illustrate that the first clock terminal CK1 receives the first clock signal C K) of the first clock signal C K in response to (m-1) level signal GOUT (m-1) (if m＞1).Pull-down section 220 is in response to (m+1) level signal GOUT (m+1) (if m＜n+1) m level signal GOUTm is pulled down to cut-off voltage Voff.
M level SRCm further comprises and draws driving circuit.Draw driving circuit to draw portion 210 on connecting on being somebody's turn to do, and draw portion 210 on disconnecting in response to (m+1) level signal GOUT (m+1) in response to (m-1) level signal GOUT (m-1).On draw driving circuit to comprise buffer part 280, charging part 270 and discharge part 230.
M level SRCm further comprises first maintaining part 242 and second maintaining part 244.First maintaining part 242 remains on cut-off voltage Voff in response to the first clock signal C K with first node N1, and second maintaining part 244 remains on cut-off voltage Voff in response to second clock signal CKB with first node N1.In addition, m level SRCm comprises the 3rd maintaining part 246 and the 4th maintaining part 248 that m signal GOUTm is remained on cut-off voltage Voff, and the switching part 250 of controlling on/off (on/off) switching of the 4th maintaining part 248.In this embodiment, the 3rd maintaining part 246 is switched in response to second clock signal CKB control on/off (on/off), and the 3rd maintaining part 246 and the 4th maintaining part 248 alternatively are discharged to cut-off voltage Voff with lead-out terminal OUT.
M level SRCm further comprises reset portion 260.The reset portion 260 of the 1st grade of SRC1～(n+1) level SRC (n+1) is discharged to cut-off voltage Voff with first node N1 separately simultaneously in response to (n+1) level signal GOUT (n+1).
In the m level SRCm according to the gate driver circuit of present embodiment, first maintaining part 242 has different electrical characteristics with second maintaining part 244.For example, can so that the 9th transistorized breadth length ratio (W/L) greater than the 8th transistorized breadth length ratio.
Therefore, with respect to by the ripple that causes with first clock signal C K coupling and at first node N1, increased by the reverse ripple of the N1 of first node place that causes with second clock signal CKB coupling, thereby reduced the driving defective.In addition, because the 9th transistor T 9 has been assisted the 13 transistor T 13 when the 9th transistor T 9 chargings the 3rd capacitor C 3, so because the breadth length ratio (W/L) of the 9th transistor T 9 has increased, the charge rate of the 3rd electric capacity improves, and makes the low temperature driving margin be enhanced.
Fig. 9 shows the schematic circuit according to the level of the gate driver circuit of the 3rd embodiment.Present embodiment the level basically with Fig. 2 in identical, difference is the 9th transistor and the 13 transistor.Therefore, will use same reference numerals to refer to identical or similar portions, and omit any repetition of explanation explanation about said elements as describing among Fig. 2.
With reference to Fig. 9, second maintaining part 244 comprises the 9th transistor T 9.The 9th transistor T 9 comprises the gate electrode that is electrically connected on second clock terminal CK2, be electrically connected on the drain electrode of the sub-IN1 of first input end and be electrically connected on the source electrode of first node N1.
The 9th transistor T 9 has dissymmetrical structure.Particularly, gate electrode and the stray capacitance Cgs between the electrode of source at the 9th transistor T 9 is different from the gate electrode of the 9th transistor T 9 and the stray capacitance Cgd between the drain electrode.More specifically, stray capacitance Cgs is greater than stray capacitance Cgd.When second clock signal CKB when high state is reduced to low state, reduced the ripple of the first node N1 of the source electrode that is electrically connected on the 9th transistor T 9 greater than the stray capacitance Cgs of stray capacitance Cgd.Along with stray capacitance Cgs increases, the degree that ripple reduces also increases.Relation between reducing for stray capacitance Cgs and ripple is with reference to Figure 10 A and Figure 10 B detailed explanation.
M level SRCm comprises and draws driving circuit.Draw driving circuit to connect the portion 210 of drawing on being somebody's turn to do, and draw portion 210 on disconnecting in response to the signal Gm+1 of (m+1) level SRCm+1 in response to the carry signal that provides from (m-1) level SRCm-1.On draw driving circuit to comprise buffer part 280, charging part 270 and discharge part 230.
Buffer part 280 comprises the 13 transistor T 13, and it has the gate electrode that is connected in the sub-IN1 of first input end, the source electrode that is connected in the drain electrode of the sub-IN1 of first input end and is connected in first node N1.
When the 13 transistor T 13 was switched in response to the carry signal of (m-1) level SRCm-1, this carry signal was applied to the voltage level of first node N1 with rising first node N1, thereby to 3 chargings of the 3rd capacitor C.When the 3rd capacitor C 3 is fully charged and when to have than the higher voltage of the threshold voltage of the 5th transistor T 5 and the first clock signal C L be high, the 5th transistor T 5 is by bootstrapping (bootstrapped), and the m level signal Gm that makes first clock signal of noble potential be output to lead-out terminal OUT and m level SRCm is output.
The 13 transistor T 13 has enough channel widths, makes when the 13 transistor T 13 is switched on, and the 3rd capacitor C 3 that is electrically connected on the 3rd capacitor C 3 is fully charged and improve drive characteristic.Variable quantity with the channel width of detailed explanation the 13 transistor T 13.
Figure 10 A and Figure 10 B show the planimetric map of the 9th transistorized structure among Fig. 9.
With reference to Figure 10 A, the raceway groove that the 9th transistor T 9 among Fig. 9 has the l-shape.Particularly, the 9th transistor T 9 comprises gate electrode 111, channel pattern 113, multiple source electrode 115 and a plurality of drain electrode 117.Signal pattern 113 is arranged on the gate electrode 111.The source electrode 115 of a part and drain electrode 117 are overlapping with channel pattern 113.
Each of source electrode 115 and drain electrode 117 has l-shape and source electrode 115 and drain electrode 117 mutual arranged alternate.Source electrode 115 and drain electrode 117 separate each other.The raceway groove that is limited by source electrode 115 and drain electrode 117 has the l-shape of channel length L and channel width W.
The 9th transistor T 9 is designed to, and makes the width d of the width s of source electrode 115 greater than drain electrode 117.Therefore, at the stray capacitance Cgs between gate electrode 111 and the source electrode 115 greater than the stray capacitance Cgd between gate electrode 111 and the drain electrode 117.
With reference to Figure 10 B, the raceway groove that the 9th transistor T 9 among Fig. 9 has the U-shape.Particularly, the 9th transistor T 9 comprises gate electrode 131, channel pattern 133, multiple source electrode 135 and a plurality of drain electrode 137.Channel pattern 133 is formed on the gate electrode 131.Source electrode 135 and drain electrode 137 form and make that a part of source electrode 133 and drain electrode 137 and channel pattern 133 are overlapping.
Each source electrode 135 has the U-shape, and each drain electrode 137 is inserted in each source electrode 135.Therefore, the channel layer that is limited by source electrode 135 and drain electrode 137 has the U-shape of channel length L and channel width W.
The 9th transistor T 9 is designed to make the width d of the width s of each source electrode 135 greater than each drain electrode 137.Therefore, the stray capacitance Cgs between gate electrode 131 and each the source electrode 135 becomes greater than the stray capacitance Cgd between gate electrode 131 and each drain electrode 137.
Shown in Figure 10 A and Figure 10 B, when the stray capacitance Cgs between gate electrode and the source electrode became greater than the stray capacitance Cgd between gate electrode and the drain electrode, the ripple that is electrically connected on the first node N1 of the 9th transistorized source electrode was reduced.Stray capacitance Cgs between gate electrode and the source electrode and the ratio of the stray capacitance Cgd between gate electrode and the drain electrode are K: 1 (K＞1) for example is about 2: 1, about 3: 1 or about 4: 1.
Figure 11 shows the curve map of the emulation voltage ripple at the first node place in Fig. 9.
Curve among Figure 11 is that the first node N1 from the following stated level records, described level adopt the channel width W with about 3,500 μ m the 5th transistor T 5, have the channel width W of about 400 μ m the 9th transistor T 9, have the 5th transistor T 5 nine transistor T 9 roughly identical of the channel length L of about 5 μ m～about 6 μ m with the 5th transistor T 5 with having channel length L.
With reference to Figure 11, the first ripple pattern R1 is about 1: 1 corresponding to gate electrode and the gate electrode of stray capacitance Cgs between the electrode of source and the 9th transistor T 9 and the ratio of the stray capacitance Cgd between the drain electrode of the 9th transistor T 9.The second ripple figure R2 is about 2: 1 corresponding to gate electrode and the gate electrode of stray capacitance Cgs between the electrode of source and the 9th transistor T 9 and the ratio of the stray capacitance Cgd between the drain electrode of the 9th transistor T 9.
With reference to the first ripple figure R1, when the ratio of the gate electrode of the gate electrode of the 9th transistor T 9 and stray capacitance Cgs between the electrode of source and the 9th transistor T 9 and the stray capacitance Cgd between the drain electrode was about 1: 1, the gate electrode of the 5th transistor T 3 in Fig. 3 and the voltage difference Vgs between the electrode of source (or voltage of first node N1) were raised to about 1.41V.With reference to the second ripple figure R2, when the ratio of the gate electrode of the gate electrode of the 9th transistor T 9 and stray capacitance Cgs between the electrode of source and the 9th transistor T 9 and the stray capacitance Cgd between the drain electrode was about 2: 1, the gate electrode of the 5th transistor T 3 in Fig. 3 and the voltage difference Vgs between the electrode of source (or voltage of first node N1) were raised to about 1.29V.That is, than the peak value of the first ripple pattern R1, the peak value of the second ripple pattern R2 has reduced about 0.12V.
Therefore, when the ratio of the gate electrode of the gate electrode of the 9th transistor T 9 and stray capacitance Cgs between the electrode of source and the 9th transistor T 9 and the stray capacitance Cgd between the drain electrode was increased to about 2: 1, the ripple peak value that first node N1 place records reduced.
Following table 3 shows the data of the transistor (when this transistor has been driven 3,000 hours) among Fig. 9.
[table 3]
Drain electrode Gate electrode The source electrode Function Vth(ld＞1nA)
T5 CK/CKB VSS VSS Grid output 6
T6 VSS VSS VSS Grid resets 6
T11 VSS INV.OUT VSS Grid keeps 1 7.5
T13 VSS VSS VSS The T5 gate charges 3
T10 VSS CK/CKB VSS Grid keeps 2 21.5
T18 VSS CK/CKB VSS The T5 grid keeps 1 22.5
T9 VSS CK/CKB VSS The T5 grid keeps 2+ carry forward 21
T14 CK/CKB VSS VSS Carry 9
Reference table 3, receive the 9th transistor T 9, the tenth transistor T 10 of the first clock signal C K and second clock signal CKB and the 18 transistor T 18 because grid bias and deterioration, make threshold voltage vt h be offset, have low driving force than other transistor.
That is, when the channel width W of the 9th transistor T 9 increases, the driving force variation of the 5th transistor T 5.
According to the present invention, consider the drive characteristic of the 9th transistor T 9, the ratio of the stray capacitance Cgs of the 9th transistor T 9 and stray capacitance Cgd is increased under the situation of the channel width that does not increase by the 9th transistor T 9, and the channel width of the 13 transistor T 13 (the relative less offset of its threshold voltage vt h) increases, and makes the 5th transistor T 5 to be sufficiently charged.
When the 13 transistor T 13 and the 9th transistor T 9 were switched on, the 13 transistor T 13 was for being electrically connected on the 3rd capacitor C 3 chargings of first node N1.By increasing the channel width of the 13 transistor T 13, the 5th transistor T 5 can be sufficiently charged, thereby even still improves the driving reliability when these grades quilt drives for a long time.
Usually, tradition the 13 transistor T 13 has the channel width of about 1,200 micron (μ m).Therefore, the 13 transistor T 13 according to this embodiment has the channel width that is not less than about 1,200 μ m in the area constraints that allows.
Preferably, as described at second embodiment of first embodiment of Fig. 3 and Fig. 8, the amount size amount of the equaling Δ W that the width of the 13 transistor T 13 increases T9(it is corresponding to the recruitment of the raceway groove of the 9th transistor T 9).
Amount Δ W T9With following formula 1 expression.
Formula 1
ΔW T9＝W T9(1-1/K)，
Wherein, W T9It is the channel width of the 9th transistor T 9 when the ratio of Cgs and Cgd is about 1: 1 (or symmetry).
Under the situation that does not change Cgs, as the Cgd that reduces the 9th transistor T 9 so that the ratio of Cgs and Cgd is about K: during 1 (K＞1), be the width W of about 1: 1 the 9th transistor T 9 than ratio with Cgs and Cgd T, amount Δ W T9Amount corresponding to the channel width minimizing.
For example, when having the channel width W that ratio Cgs: Cgd is about 1: 1 the 9th transistor T 9 TDuring for about 900 μ m, when making ratio Cgs: Cgd be about 3: 1 under the 9th transistor T 9 is designed to not change the situation of the 9th transistor T 9 channel widths, the ripple of first node N1 can be reduced.In this case, the channel width of the 13 transistor T 13 increases by 600 μ m (Δ W T9=900 μ m (1-1/3)=600 μ m).
Amount Δ W T9Scope can be represented as following equation 2, this equation 2 is corresponding to formula W T8＜W T9＜W T8+ W T14, obtained the channel width of the 9th transistor T 9 thus.
Formula 2
W T8x(1-1/K)＜ΔW T9＝W T9x(1-1/K)＜(W T8+W T14)x(1-1/K)
Wherein, W T8Be the width of the 8th transistor T 8, and W T14It is the width of the 14 transistor T 14.
Figure 12 shows the curve map according to the frequency characteristic of the gate driver circuit of working time.
With reference to Figure 12, Comparative examples A adopts the 9th transistor T 9 (ratio of the parasitic electrode Cgd between the stray capacitance Cgs between its gate electrode and the source electrode and gate electrode and the drain electrode is about 1: 2 or about 1: 3) and the 13 transistor T 13, and (it is basically with traditional identical, channel width with about 1,200 μ m).The 13 transistor T 13 that adopts the 9th transistor T 9 (stray capacitance Cgs between its gate electrode and the source electrode and the ratio of the parasitic electrode Cgd between gate electrode and the drain electrode are about 1: 2 or about 1: 3) and have about 1,600 μ m channel width according to embodiments of the invention B.
According to Comparative examples A, driving frequency at first is about 130Hz, but has reduced about 20Hz after being driven about 2,000 hours.Yet according to embodiments of the invention B, driving frequency at first is 130Hz (the same with Comparative examples A), but reduces about 10Hz after being driven about 2,000 hours.Than Comparative examples A, Embodiment B has the frequency that reduces and reduces.
Therefore, when the channel width of the 13 transistor T 13 increases, draw the first node N1 of portion fully charged in the driving, drive reliability thereby improve.
According to the specific embodiment of the present invention, the transistorized breadth length ratio (W/L) in second maintaining part is increased, thereby oppositely the ripple increase makes the total ripple that occurs at last control electrode place of drawing portion to be reduced.Therefore, can prevent the generation of unusual gate turn-on signal, thereby reduce the driving defective of display device.In addition, along with this transistorized breadth length ratio (W/L) in second maintaining part increases, the charge rate of charging part can be enhanced, and makes to improve the low temperature driving margin.
According to another embodiment, the stray capacitance between the 9th transistorized gate electrode and the source electrode is increased, thereby reduces the ripple of the first node that is electrically connected on the 9th transistorized source electrode.
In addition, the 13 transistorized channel width of charging for the electric capacity that is connected in first node is increased, with this electric capacity of abundant charging.Therefore, the reliability of the gate driver circuit of output signal can be enhanced.
Describe embodiments of the invention and advantage thereof, should be understood that under the situation that does not deviate from the spirit and scope of the present invention that are defined by the following claims, can carry out various variations, replacement and change here.

Claims (32)

1. a gate driver circuit comprises shift register, and it has a plurality of level that is connected in series mutually, and described a plurality of levels comprise one or more levels, its each comprise:
On draw portion, receive first clock signal, and when the first node signal response is driven to high voltage in first input signal, transmit described first clock signal as signal;
Pull-down section is discharged to cut-off voltage in response to second input signal with described signal;
Discharge part is discharged to described cut-off voltage in response to described second input signal with described first node signal;
First maintaining part in response to described first clock signal, remains on described cut-off voltage with described first node signal when described signal has been discharged to described cut-off voltage; And
Second maintaining part in response to the second clock signal, remains on described cut-off voltage with described first node signal when described first input signal is in described cut-off voltage,
Wherein, described second maintaining part has the transistor breadth length ratio greater than described first maintaining part.
2. gate driver circuit according to claim 1, further comprise carry part, it transmits described first clock signal as carry signal in response to described first node signal, wherein, described second maintaining part has the crystal breadth length ratio less than the summation of the crystal breadth length ratio of described first maintaining part and described carry part.
3. gate driver circuit according to claim 2 further comprises:
The 3rd maintaining part remains on described cut-off voltage in response to described second clock signal with described signal;
The 4th maintaining part alternately remains on described cut-off voltage with described signal with described the 3rd maintaining part; And
Switching part switches switching on and off of described the 4th maintaining part.
4. gate driver circuit according to claim 3, wherein, described switching part comprises:
The first transistor has drain electrode, gate electrode and source electrode, and described drain electrode and gate electrode receive described first clock signal simultaneously;
Transistor seconds has the drain electrode of the described source electrode that is connected in described the first transistor, and has the gate electrode that receives described signal and have the source electrode that receives described cut-off voltage;
The 3rd transistor has the drain electrode that receives described first clock signal, gate electrode and the source electrode that is connected in the described source electrode of described the first transistor;
The 4th transistor, the source electrode that has the drain electrode that is connected in the described the 3rd transistorized described source electrode at the Section Point place, receives the gate electrode of described signal simultaneously and receive described cut-off voltage with the described gate electrode of described transistor seconds;
First electric capacity connects the described the 3rd transistorized described drain electrode and the described the 3rd transistorized described gate electrode; And
Second electric capacity connects the described the 3rd transistorized described gate electrode and the described the 3rd transistorized described source electrode,
Wherein, described the 4th maintaining part is switched in switching on and off in response to the Section Point signal.
5. gate driver circuit according to claim 4, wherein, described one or more levels comprise the m level;
Described first input signal of described m level is the described carry signal of vertical start signal or (m-1) level, and
Second input signal of described m level is the described signal or the described vertical start signal of (m+1) level.
6. gate driver circuit according to claim 4, wherein, described first clock signal and described second clock signal are anti-phase.
7. gate driver circuit according to claim 1, wherein, described one or more levels comprise the m level;
Described first input signal of described m level is the described signal of vertical start signal or (m-1) level, and
Second input signal of described m level is the described signal or the described vertical start signal of (m+1) level.
8. display device comprises:
Display panel, comprise the viewing area of display image and in described viewing area around external zones, by gate line and a plurality of pixel regions of in described viewing area, forming with described gate line data line crossing;
Data drive circuit outputs to described data line with data-signal; And
Gate driver circuit has and is connected in series mutually and directly is integrated in a plurality of level on the described external zones, and each in described a plurality of levels outputs to described gate line with signal,
Wherein, described a plurality of level comprises one or more levels, its each comprise:
On draw portion, transmit first clock signal as signal in response to the first node signal, wherein said first node signal response is driven to noble potential in first input signal;
Pull-down section is discharged to cut-off voltage in response to second input signal with described signal;
Discharge part is discharged to described cut-off voltage in response to described second input signal with described first node signal;
First maintaining part remains on described first node signal in response to described first clock signal described cut-off voltage of described signal; And
Second maintaining part remains on described first node signal in response to described second clock signal the described cut-off voltage of described first input signal, and wherein, described second maintaining part has the transistor breadth length ratio greater than described first maintaining part.
9. display device according to claim 8, further comprise carry part, it transmits described first clock signal as carry signal in response to described first node signal, wherein, the described transistor breadth length ratio of described second maintaining part is less than the summation of the transistor breadth length ratio of described first maintaining part and described carry part.
10. display device according to claim 9 further comprises:
The 3rd maintaining part remains on described cut-off voltage in response to described second clock signal with described signal;
The 4th maintaining part alternately remains on described cut-off voltage with described signal with described the 3rd maintaining part; And
Switching part switches switching on and off of described the 4th maintaining part.
11. display device according to claim 10, wherein, described switching part comprises:
The first transistor has drain electrode, gate electrode and source electrode, and described drain electrode and gate electrode receive described first clock signal simultaneously;
Transistor seconds, have the described source electrode that is connected in described the first transistor drain electrode, receive the gate electrode of described signal and receive the source electrode of described cut-off voltage;
The 3rd transistor has the drain electrode that receives described first clock signal, gate electrode and the source electrode that is connected in the described source electrode of described the first transistor;
The 4th transistor, the source electrode that has the drain electrode that is connected in the described the 3rd transistorized described source electrode at the Section Point place, receives the gate electrode of described signal simultaneously and receive described cut-off voltage with the described gate electrode of described transistor seconds;
First electric capacity is connected to the described the 3rd transistorized described gate electrode with the described the 3rd transistorized described drain electrode; And
Second electric capacity is connected to the described the 3rd transistorized described source electrode with the described the 3rd transistorized described gate electrode,
Wherein, switch switching on and off of described the 4th maintaining part by the Section Point signal.
12. display device according to claim 11, wherein, described one or more levels comprise the m level;
Wherein, described first input signal of described m level is the described carry signal of vertical start signal or (m-1) level, and
Second input signal of described m level is the described signal or the described vertical start signal of (m+1) level.
13. display device according to claim 12, wherein, described first clock signal and described second clock signal are anti-phase.
14. display device according to claim 8, wherein, described one or more levels comprise the m level;
Wherein, described first input signal of described m level is the described signal of vertical start signal or (m-1) level, and
Second input signal of described m level is the described signal or the described vertical start signal of (m+1) level.
15. a gate driver circuit comprises shift register, it has a plurality of levels that are connected in series mutually, and each level comprises:
Be connected in first clock terminal on draw portion, it is connected to lead-out terminal with described first clock terminal, and signal is provided when first node is driven to high voltage in response to the signal on first input end;
Pull-down section is discharged to cut-off voltage in response to the signal on second input terminal with described lead-out terminal;
Discharge part is discharged to described cut-off voltage in response to the signal on described second input terminal with described first node;
First maintaining part, the signal in response on described first clock terminal remains on described cut-off voltage with described first node when described lead-out terminal has been discharged to described cut-off voltage; And
Second maintaining part in response to the signal on the second clock terminal, remains on described cut-off voltage with described first node when described first input end is in described cut-off voltage,
Wherein, described second maintaining part has the transistor breadth length ratio greater than described first maintaining part.
16. a display device comprises that gate driver circuit according to claim 15 also further comprises:
A plurality of gate lines, its each be connected in the described lead-out terminal of each grade in described one or more level;
The a plurality of data lines that intersect with described gate line; And
Data drive circuit offers described data line with data-signal.
17. a gate driver circuit comprises a plurality of levels that are connected in series mutually, m level (wherein " m " is integer) comprising:
On draw portion, receive first clock signal, and when the first node signal response is driven to high voltage in first input signal, transmit described first clock signal as signal;
Pull-down section is discharged to cut-off voltage in response to second input signal with described signal;
Discharge part is discharged to described cut-off voltage in response to described second input signal with described first node signal;
First maintaining part in response to described first clock signal, remains on described cut-off voltage with described first node signal when described signal has been discharged to described cut-off voltage;
Second maintaining part in response to the second clock signal, remains on described cut-off voltage with described first node signal when described first input signal is in described cut-off voltage, described second maintaining part comprises asymmetric transistor.
18. gate driver circuit according to claim 17, wherein, the described nonsymmetrical transistor of described second maintaining part comprises the gate electrode that receives described second clock signal, receive the drain electrode of described first input signal and be electrically connected on the source electrode of described first node, and
First stray capacitance between the described gate electrode of described nonsymmetrical transistor and the described source electrode is greater than the described gate electrode of described nonsymmetrical transistor and second stray capacitance between the described drain electrode.
19. gate driver circuit according to claim 18 further comprises buffer part, described buffer part comprises the transistor that is electrically connected on described first node, puts on described first node with described first input signal with noble potential.
20. gate driver circuit according to claim 19, wherein, the width Delta W of the described transistorized increase of described buffer part TSatisfy following formula,
W T8x(1-1/K)＜ΔW T
Wherein, W T8Be the channel width of described first maintaining part, the ratio of the transistorized gate electrode of described second maintaining part and the transistorized gate electrode of stray capacitance Cgs between the electrode of source and described second maintaining part and the stray capacitance Cgd between the drain electrode is K: 1 (K＞1).
21. gate driver circuit according to claim 19 further comprises carry part, it exports described first clock signal as carry signal in response to the signal of described first node.
22. gate driver circuit according to claim 21, wherein, the width Delta W of the described transistorized increase of described buffer part TSatisfy following formula,
W T8x(1-1/K)＜ΔW T＜(W T8+W T14)x(1-1/K)
Wherein, W T8Be the channel width of described first maintaining part, W T14Be the channel width of described carry part, and the ratio of the transistorized gate electrode of the transistorized gate electrode of described second maintaining part and stray capacitance Cgs between the electrode of source and described second maintaining part and the stray capacitance Cgd between the drain electrode is K: 1 (K＞1).
23. gate driver circuit according to claim 22, wherein, described first input signal is corresponding to the carry signal of vertical start signal or (m-1) level, and
Described second input signal is corresponding to the signal or the described vertical start signal of (m+1) level.
24. gate driver circuit according to claim 17, wherein, described first input signal is corresponding to the signal of vertical start signal or (m-1) level, and described second input signal is corresponding to the signal or the described vertical start signal of (m+1) level.
25. a display device comprises:
Display panel has pixel region and described pixel region external zones on every side, has a plurality of gate lines and a plurality of data line in described pixel region;
Data-driven portion imposes on described data line with data-signal; And
Gate driver circuit imposes on described gate line with signal, and described gate driver circuit comprises a plurality of levels that are connected in series mutually, and m level (wherein " m " is integer) comprising:
On draw portion, receive first clock signal, and when the first node signal response is driven to high voltage in first input signal, transmit described first clock signal as signal;
Pull-down section is discharged to cut-off voltage in response to second input signal with described signal;
Discharge part is discharged to described cut-off voltage in response to described second input signal with described first node signal;
First maintaining part in response to described first clock signal, remains on described cut-off voltage with described first node signal when described signal has been discharged to described cut-off voltage;
Second maintaining part in response to the second clock signal, remains on described cut-off voltage with described first node signal when described first input signal is in described cut-off voltage, described second maintaining part comprises asymmetric transistor.
26. display device according to claim 25, wherein, the described nonsymmetrical transistor of described second maintaining part comprises the gate electrode that receives described second clock signal, receive the drain electrode of described first input signal and be electrically connected on the source electrode of described first node, and
First stray capacitance between the described gate electrode of described nonsymmetrical transistor and the described source electrode is greater than the described gate electrode of described nonsymmetrical transistor and second stray capacitance between the described drain electrode.
27. display device according to claim 26 further comprises buffer part, described buffer part comprises the transistor that is electrically connected on described first node, puts on described first node with described first input signal with noble potential.
28. display device according to claim 27, wherein, the width Delta W of the described transistorized increase of described buffer part TSatisfy following formula,
W T8x(1-1/K)＜ΔW T
Wherein, W T8Be the channel width of described first maintaining part, the ratio of the transistorized gate electrode of described second maintaining part and the transistorized gate electrode of stray capacitance Cgs between the electrode of source and described second maintaining part and the stray capacitance Cgd between the drain electrode is K: 1 (K＞1).
29. display device according to claim 27 further comprises carry part, it exports described first clock signal as carry signal in response to the signal of described first node.
30. display device according to claim 29, wherein, the width Delta W of the described transistorized increase of described buffer part TSatisfy following formula,
W T8x(1-1/K)＜ΔW T＜(W T8+W T14)x(1-1/K)
Wherein, W T8Be the channel width of described first maintaining part, W T14Be the channel width of described carry part, and the ratio of the transistorized gate electrode of the transistorized gate electrode of described second maintaining part and stray capacitance Cgs between the electrode of source and described second maintaining part and the stray capacitance Cgd between the drain electrode is K: 1 (K＞1).
31. display device according to claim 30, wherein, described first input signal is corresponding to the carry signal of vertical start signal or (m-1) level, and
Described second input signal is corresponding to the signal or the described vertical start signal of (m+1) level.
32. display device according to claim 25, wherein, described first input signal is corresponding to the signal of vertical start signal or (m-1) level, and
Described second input signal is corresponding to the signal or the described vertical start signal of (m+1) level.
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