CN103280196B - A kind of shift register and Thin Film Transistor-LCD - Google Patents
A kind of shift register and Thin Film Transistor-LCD Download PDFInfo
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- CN103280196B CN103280196B CN201210350350.1A CN201210350350A CN103280196B CN 103280196 B CN103280196 B CN 103280196B CN 201210350350 A CN201210350350 A CN 201210350350A CN 103280196 B CN103280196 B CN 103280196B
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Abstract
The invention provides a kind of shift register and Thin Film Transistor-LCD, described shift register comprises the multistage shift register circuit be made up of nine transistors and an electric capacity, described shift register circuit comprises the pulling up transistor of signal output module, the first pull-down transistor, second time crystal pulling, 3rd pull-down transistor, switching transistor, first electric capacity, reset transistor, and the 3rd auxiliary pull-down transistor and the second electric capacity that first of auxiliary drop-down module the auxiliary pull-down transistor, second is assisted pull-down transistor and is connected in parallel.Second electric capacity is as buffering device, burr signal that can be unnecessary in filtered output signal, decrease signal cross-talk, simultaneously due to the first pull-down transistor and each comfortable half drop-down cycling of the second pull-down transistor, also inhibits the drift because of the excessive threshold voltage of transistor breadth length ratio, and then ensure that the stability of circuit.By arranging auxiliary drop-down module, the output waveform of Section Point can be made more stable.
Description
Technical field
The present invention relates to liquid crystal flat-panel display technique, particularly relate to a kind of shift register and Thin Film Transistor-LCD.
Background technology
Start to develop rapidly with FPD (flat-panel display device) technology that TFT-LCD (Thinfilmtransistor-Liquidcrystaldisplay, Thin Film Transistor-LCD) is representative from the nineties in 20th century and progressively move to maturity.Due to TFT-LCD there is high-resolution, low-power consumption, frivolous, the advantage such as be easy to carry, and has been widely used in above-mentioned information display products, make LCD enter the new stage of high image quality, high color display, there are wide market outlook.Tft active matrix is employed all without any exception in the LCD of current nearly all top grade.TFT (Thinfilmtransistor) active matrix mainly comprises A-Si (amorphoussilicon) tft active matrix and P-Si (poly-silicon) tft active matrix two kinds.Compared with P-SiTFT technology, A-SiTFT technical development comparative maturity, homogeneity is good and cost is lower, but its mobility is lower, generally at 0.1 ~ 1.0cm
2the mobility of/Vs, P-SiTFT then can reach 50 ~ 200cm
2/ Vs.Because A-SiTFT mobility ratio is lower, cause its driving circuit speed slower.
Small-medium size LCD is mainly used in portable product, therefore different with large-scale LCD on technical property requirements.Small-medium size product is highlighted light, thin, the integration capability of device, better reliability and low cost of device more.At present, the resolution of market to LCD it is also proposed requirements at the higher level, and in order to make miniaturization LCD have high resolving power, the number reducing TFT-LCD drive IC is very important.Usually, when the resolution of LCD is higher than QVGA (240 × RGB × 320), TFT panel needs more than 1000 outside leads.When product resolution increases further, in limited space, make more outer lead just become very difficult.
Above technical matters can solve by being integrated on thin film transistor，Bao Mojingtiguan substrate by driving circuit (gatedrivercircuits or sourcedrivercircuits).This technology can make that display cost is lower, more compact structure, Mechanical Reliability are higher thus make it have the larger market competitiveness.
And along with the development of technology, sweep circuit trends towards circuit integration, increasing company adopts shift register to instead of turntable driving IC, thus reduce the display bezel size of LCD, simultaneously because circuit is on a display panel integrated, also reduce the usage quantity of IC, thus greatly reduce the cost of manufacture of display panel.
Along with high-end product more and more pursues narrow frame and lightness, therefore the dimensional requirement of shift register circuit constantly reduces, shift register circuit is the display controlling thin film transistor，Bao Mojingtiguan substrate as driving circuit simultaneously, therefore requires the electric current that shift register circuit can provide stable.
Therefore, a kind of number of transistors is provided to make overall dimensions little less and the stable shift register of the signal waveform that provides of working and the Thin Film Transistor-LCD that formed by this kind of shift register cascade become the problem of industry extensive concern.
Summary of the invention
Technical matters to be solved by this invention is to provide the shift register that a kind of number of transistors is few, work wave is stable and the Thin Film Transistor-LCD formed by this kind of shift register cascade.
For solving the problem, the invention provides a kind of shift register, comprising the shift register circuit of multi-stage cascade, each shift register circuit, comprising:
Primary input end and main output terminal;
Signal output module, comprise and be respectively coupled to the pulling up transistor of described main output terminal, the first pull-down transistor, the second pull-down transistor, the described input termination first node pulled up transistor, described pull up transistor in order to open time produce high level output signal to described main output terminal, described first pull-down transistor and the second pull-down transistor low levelly output signal to described main output terminal, the input termination Section Point of described second pull-down transistor in order to alternately to produce when opening;
Switching transistor, is coupled between described primary input end and described first node, in order to the unlatching pulled up transistor according to the input signal control of master clock signal and primary input end;
First electric capacity, is coupled between described first node and described main output terminal, provides burning voltage in order to utilize electric capacity bootstrap effect for described pulling up transistor;
Reset transistor, is coupled to described first node, the replacement of the output signal exported in order to the closedown that pulls up transistor described in controlling and described main output terminal; And
Drop-down supplementary module, be coupled to described main output terminal and described Section Point, in order to realize described first pull-down transistor and the second pull-down transistor alternately produces low level output signal, described drop-down supplementary module comprises: the first auxiliary pull-down transistor, in order to discharge the high level of described Section Point fast according to master clock signal; Second auxiliary pull-down transistor, in order to the level being Section Point described in FEEDBACK CONTROL according to the output signal of described main output terminal, and then stablizes the level of described main output terminal; And the 3rd auxiliary pull-down transistor, in order to according to the described level drawing high described Section Point from clock signal, described from clock signal and described master clock signal anti-phase; Described signal output module also comprises the 3rd pull-down transistor, the input termination first node of described 3rd pull-down transistor, for the level of the drop-down first node of Section Point of the last shift register circuit according to place shift register circuit.
Further, in described shift register, the switching transistor of first order shift register circuit receives initialize signal, and the switching transistor of every grade of shift register circuit is coupled to the main output terminal of its preceding shift register circuit thereafter; The switching transistor of afterbody shift register circuit receives final reset signal, and the reset transistor of other every grade shift register circuit is coupled to the main output terminal of its rear class shift register circuit.
Further, pull up transistor described in, the first pull-down transistor, the second pull-down transistor, the 3rd pull-down transistor, switching transistor, reset transistor, the first auxiliary pull-down transistor, the second auxiliary pull-down transistor and the 3rd auxiliary pull-down transistor be Thin Film Transistor (TFT).
Further, in each shift register circuit: in described signal output module: described in the grid that pulls up transistor connects first node, source electrode connects and describedly connect described main output terminal from clock signal, drain electrode; The grid of described first pull-down transistor connects described master clock signal, source electrode connects described main output terminal, miss and connect low level end; The grid of described second pull-down transistor connects Section Point, source electrode connects described main output terminal, drain electrode connects low level end; The drop-down Section Point of Section Point, the drain electrode of the last shift register circuit that source electrode connects first node, grid connects its place shift register circuit of described 3rd pull-down transistor connect low level end; The grid of described switching transistor connects described master clock signal, source electrode connects described primary input end, drain electrode connects described first node; After the grid of described reset transistor connects a shift register circuit main output terminal, source electrode connects described first node, drain electrode connects low level end; And in described drop-down supplementary module: the described first auxiliary pull-down transistor grid connects described master clock signal, source electrode connects described Section Point, drain electrode connects described low level end; Described second auxiliary pull-down transistor grid connects described main output terminal, source electrode connects described Section Point, drain electrode connects described low level end; Described Section Point is connect from clock signal, source electrode described in the grid of the described 3rd auxiliary pull-down transistor and drain electrode connect.
Further, the breadth length ratio of the described 3rd auxiliary pull-down transistor is greater than the breadth length ratio of the described second auxiliary pull-down transistor.
Further, the breadth length ratio of the described 3rd auxiliary pull-down transistor is greater than ten times of the breadth length ratio of the described second auxiliary pull-down transistor.
Further, described first electric capacity connects between described first node and main output terminal.
Further, the working time of described first pull-down transistor and the second pull-down transistor is respectively the half in drop-down cycle.
Further, in described shift register, shift register circuit is divided into odd level shift register circuit and even level shift register circuit, and the master clock signal that the master clock signal of described odd level shift register circuit reception and described even level shift register circuit receive is anti-phase.
The present invention also provides a kind of Thin Film Transistor-LCD, comprises array of display and gate driver circuit, and described in order to produce multiple signal to control described array of display, described gate driver circuit comprises aforesaid shift register.
In sum, the shift register circuit of shift register of the present invention utilizes output signal to export as the further control signal of feedback is stable, thus reach the object that current stabilization controls actuation voltage, adopt two pull-down transistor to carry out drop-down to output terminal simultaneously, and it is fully drop-down that the drop-down cycle of 100% can be utilized to carry out, avoid floating state, so time circuit stability.
Further, shift register increase of the present invention arranges described 3rd pull-down transistor, described 3rd pull-down transistor can drop-down according to the level of the first node of the Control of Voltage current shift register circuit of the Section Point of the last shift register circuit of place shift register circuit, thus keep the drop-down current potential of first node, and then optimize the overall driving force of shift register.
The present invention also provides a kind of Thin Film Transistor-LCD be made up of aforesaid shift register, described Thin Film Transistor-LCD comprises array of display and gate driver circuit, described shift register is in order to produce multiple signal to control described array of display, and described gate driver circuit comprises the aforesaid shift register of employing.The display of the Thin Film Transistor-LCD adopting shift register of the present invention to form is more stable, and reaction velocity is faster, and reduces panel size, realizes the smooth volume production of high-end light thin product, reduces production cost further.
Accompanying drawing explanation
Fig. 1 is the structural representation of shift register in one embodiment of the invention.
Fig. 2 is the structural representation of shift register circuit in one embodiment of the invention.
Fig. 3 is the signal timing diagram in one embodiment of the invention in the shift register course of work.
Fig. 4 is the signal timing diagram of the course of work of shift register and prior art one shift register circuit in one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Fig. 1 is the structural representation of shift register in one embodiment of the invention, and as shown in Figure 1, the shift register circuit of described shift register produces signal control array of display successively and carries out image display.Wherein, in the present embodiment, in described shift register, shift register circuit is divided into odd level shift register circuit and even level shift register circuit, the master clock signal that the master clock signal of described odd level shift register circuit reception and described even level shift register circuit receive is anti-phase, namely the master clock signal CK1 correspondence that odd level shift register circuit receives receives the first clock signal clk, the master clock signal CK2 correspondence that corresponding described even level shift register circuit receives receives second clock signal CLKB, first clock signal clk and second clock signal CLKB anti-phase.And the switching transistor M1 of first order shift register circuit receives initialize signal STP, thereafter the switching transistor M1 of every grade of shift register circuit is coupled to the main output terminal OUT of its preceding shift register circuit, namely the switching transistor M1 of N+1 level shift register circuit is coupled to the main output terminal OUT of N level shift register circuit, and wherein N is the positive integer being less than shift register circuit sum; The reset transistor M2 of afterbody shift register circuit receives final reset signal, the reset transistor M2 of other every grade shift register circuit is coupled to the main output terminal OUT of its rear class shift register circuit, thus the output signal realizing each shift register circuit controls the unlatching of a shift register circuit thereafter, the output signal of each shift register circuit controls the reset of its last shift register circuit, makes the shift register circuit output signal output successively in shift register.
Fig. 2 is the structural representation of shift register circuit in one embodiment of the invention.Composition graphs 1 and Fig. 2, the invention provides a kind of shift register, comprise the shift register circuit of multi-stage cascade, each shift register circuit, comprising: primary input end IN and main output terminal OUT, signal output module 100, switching transistor M1, the first electric capacity C1, reset transistor M2 and auxiliary drop-down module 200.
Described signal output module 100 comprises the M3 that pulls up transistor, the first pull-down transistor M6 and the second pull-down transistor M8 that are respectively coupled to described main output terminal OUT, the input termination first node of the described M3 that pulls up transistor, the described M3 of pulling up transistor outputs signal to described main output terminal Out in order to the generation high level when opening, described first pull-down transistor M6 and the second pull-down transistor M8 low levelly outputs signal to described main output terminal Out, the input termination Section Point Q of described second pull-down transistor M8 in order to alternately to produce when opening;
Described switching transistor M1 is coupled between described primary input end and described first node P, in order to the unlatching of the M3 that pulls up transistor according to the input signal control of master clock signal CK1 and primary input end IN;
Described first electric capacity C1 is coupled between described first node P and described main output terminal OUT, provides burning voltage in order to utilize electric capacity bootstrap effect for the described M3 of pulling up transistor;
Described reset transistor M2 is coupled to described first node P, the replacement of the output signal that closedown and described main output terminal IN in order to the M3 that pulls up transistor described in controlling export; And
Described auxiliary drop-down module 200 is coupled to described main output terminal IN and described Section Point Q, low level output signal is alternately produced in order to realize described first pull-down transistor M6 and the second pull-down transistor M8, described auxiliary drop-down module comprises: the first auxiliary pull-down transistor M5, in order to discharge the high level of described Section Point Q fast according to master clock signal; Second auxiliary pull-down transistor M7, in order to the level being Section Point Q described in FEEDBACK CONTROL according to the output signal of described main output terminal OUT, and then stablizes the level of described main output terminal OUT; And the 3rd auxiliary pull-down transistor M4, in order to according to the described level drawing high described Section Point from clock signal, wherein said from clock signal and described master clock signal anti-phase.In addition, described signal output module also comprises the 3rd pull-down transistor M9, the input termination first node P of described 3rd pull-down transistor M9, the level of the drop-down first node P of the Section Point for the last shift register circuit according to place shift register circuit.By the level of the first node P of the drop-down shift register circuit at the corresponding levels of the signal of the Section Point Q of previous stage shift register circuit, thus make shift register circuit more stable.
Meanwhile, in described shift register circuit, auxiliary drop-down module 200 is the structure of parallel resistance, and therefore the output waveform of Section Point Q can reach high level sooner, and then makes signal reaction speed faster, makes final output waveform more stable.
Shift register of the present invention has the shift register circuit of multiple cascade, and every one-level shift register circuit comprises nine transistors and an electric capacity, the i.e. circuit structure of 9T1C.Wherein, M1 is switching transistor, and M2 is reset transistor, and M3 pulls up transistor, and M6 is the first pull-down transistor, and M8 is the second pull-down transistor, and M5, M7 and M4 are respectively the first to the 3rd auxiliary pull-down transistor, and M9 is the 3rd pull-down transistor.Transistor size that shift register circuit of the present invention uses is few, can effectively reduce frame size, reduces the size of panel, and effectively reduces the cost of panel; Meanwhile, ensure that shift register circuit normally works, circuit stability, and improve reaction velocity.In the present embodiment, pull up transistor described in M3, the first pull-down transistor M6, the second pull-down transistor M8, the 3rd pull-down transistor M9, switching transistor M1, reset transistor M2, the first auxiliary pull-down transistor M5, the auxiliary pull-down transistor M4 of the second auxiliary pull-down transistor M6 and the 3rd is Thin Film Transistor (TFT).
In each shift register circuit: in described signal output module: described in pull up transistor M3 grid meets first node P, source electrode meets described clock signal C K2, drain electrode meet described main output terminal OUT; The grid of described first pull-down transistor M6 meets described master clock signal CK1, source electrode connects described main output terminal, miss and connect low level end; The grid of described second pull-down transistor M8 meets Section Point Q, source electrode meets described main output terminal OUT, drain electrode meets low level end VGL; The grid of described switching transistor M1 meets described master clock signal CK1, source electrode meets described primary input end IN, drain electrode meets described first node P; After the grid of described reset transistor M2 connects a shift register circuit main output terminal OUT, source electrode meets described first node P, drain electrode meets low level end VGL; And in described auxiliary drop-down module: the described first auxiliary pull-down transistor M5 grid meets described master clock signal CK1, source electrode meets described Section Point Q, drain electrode meets described low level end VGL; Described second auxiliary pull-down transistor M7 grid meets described main output terminal OUT, source electrode meets described Section Point Q, drain electrode meets described low level end VGL; Described Section Point Q is met from clock signal C K2, source electrode described in the grid of the described 3rd auxiliary pull-down transistor M4 and drain electrode connect.In described shift register circuit, auxiliary drop-down module is the structure of parallel resistance, and therefore the output waveform of Q point can reach high level sooner, and then makes signal reaction speed faster, improves reaction velocity and makes final output waveform more stable.
Fig. 3 is the signal timing diagram in one embodiment of the invention in the shift register course of work.Composition graphs 2 and Fig. 3, the effect of the first auxiliary pull-down transistor M5 mainly discharges the high voltage of Section Point Q, in the cycle making the second pull-down transistor M8 to be operated in 50%, add that the level of the first pull-down transistor M6 main output terminal OUT when main clock pulse signal CK1 exports high impulse is drop-down, thus make described shift register circuit reach the drop-down cycle of 100%, thus there is no the floating cycle, avoid floating state, and then make circuit stability.
In preferred embodiment, the breadth length ratio of the described 3rd auxiliary pull-down transistor M4 is greater than the breadth length ratio of the described second auxiliary pull-down transistor M7.In preferred embodiment, the breadth length ratio of the described 3rd auxiliary pull-down transistor M4 is greater than ten times of the breadth length ratio of the described second auxiliary pull-down transistor M7.Described shift register circuit provides output signal by main output terminal OUT, the auxiliary pull-down transistor M7 of this output signal feedback second, because second assists the breadth length ratio of pull-down transistor M7 much larger than the breadth length ratio of the 3rd auxiliary lower trombone slide M4, so the electric current of the electric current of the second auxiliary pull-down transistor M7 auxiliary lower trombone slide M4 than the 3rd is larger, make the electric current of Section Point Q closer to the voltage of the low level VGL of the second auxiliary pull-down transistor M7 conducting, form waveform as shown in Figure 3, thus make to have filtered out a high pulse signal from clock signal C K2.
Further, described first electric capacity C1 connects between described first node P and main output terminal OUT.
Further, the working time of described first pull-down transistor M6 and the second pull-down transistor M8 is respectively the half in drop-down cycle.Due to each comfortable half drop-down cycling of the first pull-down transistor M6 and the second pull-down transistor M8, also inhibits the drift because of the excessive threshold voltage of transistor breadth length ratio, and then ensure that the stability of circuit.By arranging auxiliary drop-down module 200, the output waveform of Section Point can be made more stable.
Fig. 4 is P point signal timing diagram in the course of work of shift register and prior art one shift register circuit in one embodiment of the invention.In Fig. 4, meander line 200 represents the signal timing diagram of first node P in the course of work adopting the shift register circuit shown in Fig. 2, and meander line 100 represents a kind of signal timing diagram not arranging the first node in the course of the work of the shift register circuit of the 3rd pull-down transistor of prior art, as shown in Figure 4, before first node P charging enters noble potential, can be seen by A point, the first node P of shift register circuit of the present invention maintains the low-voltage of-10V, can be seen by B point, and the voltage of the first node P of the shift register circuit of prior art is-8.264V, can be seen by C point, after increasing by the 3rd pull-down transistor, the further drop-down 2.1107V of the electrical potential energy of first node P point before entering noble potential, thus optimization actuation voltage and hold facility are greatly improved.It can thus be appreciated that, increase the pull-down capability that the 3rd pull-down transistor can keep first node P, thus optimize the driving force of shift register circuit, and then optimize the overall driving force of shift register.
In sum, the shift register circuit of shift register of the present invention utilizes output signal to export as the further control signal of feedback is stable, thus reach the object that current stabilization controls actuation voltage, adopt two pull-down transistor to carry out drop-down to output terminal simultaneously, and it is fully drop-down that the drop-down cycle of 100% can be utilized to carry out, avoid floating state, so time circuit stability.
Further, shift register increase of the present invention arranges described 3rd pull-down transistor, described 3rd pull-down transistor can drop-down according to the level of the first node of the Control of Voltage current shift register circuit of the Section Point of the last shift register circuit of place shift register circuit, thus keep the drop-down current potential of first node, and then optimize the overall driving force of shift register.
The present invention also provides a kind of Thin Film Transistor-LCD be made up of aforesaid shift register, described Thin Film Transistor-LCD comprises array of display and gate driver circuit, described shift register is in order to produce multiple signal to control described array of display, and described gate driver circuit comprises the aforesaid shift register of employing.The display of the Thin Film Transistor-LCD adopting shift register of the present invention to form is more stable, and reaction velocity is faster, and reduces panel size, realizes the smooth volume production of high-end light thin product, reduces production cost further.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (10)
1. a shift register, comprises the shift register circuit of multi-stage cascade, and each shift register circuit, comprising:
Primary input end and main output terminal;
Signal output module, comprise and be respectively coupled to the pulling up transistor of described main output terminal, the first pull-down transistor, the second pull-down transistor, the described grid pulled up transistor connects first node, described pull up transistor in order to open time produce high level output signal to described main output terminal, described first pull-down transistor and the second pull-down transistor low levelly output signal to described main output terminal in order to alternately to produce when opening, and the grid of described second pull-down transistor connects Section Point;
Switching transistor, is coupled between described primary input end and described first node, in order to the unlatching pulled up transistor according to the input signal control of master clock signal and primary input end;
First electric capacity, is coupled between described first node and described main output terminal, provides burning voltage in order to utilize electric capacity bootstrap effect for described pulling up transistor;
Reset transistor, is coupled to described first node, the replacement of the output signal exported in order to the closedown that pulls up transistor described in controlling and described main output terminal; And
Drop-down supplementary module, is coupled to described main output terminal and described Section Point, and in order to realize described first pull-down transistor and the second pull-down transistor alternately produces low level output signal, described drop-down supplementary module comprises:
First auxiliary pull-down transistor, in order to discharge the high level of described Section Point fast according to master clock signal;
Second auxiliary pull-down transistor, in order to the level being Section Point described in FEEDBACK CONTROL according to the output signal of described main output terminal, and then stablizes the level of described main output terminal; And
3rd auxiliary pull-down transistor, in order to according to the level drawing high described Section Point from clock signal, described from clock signal and described master clock signal anti-phase;
Described signal output module also comprises the 3rd pull-down transistor, and the source electrode of described 3rd pull-down transistor connects first node, for the level of the drop-down first node of Section Point of the last shift register circuit according to place shift register circuit.
2. shift register as claimed in claim 1, it is characterized in that, in described shift register, the switching transistor of first order shift register circuit receives initialize signal, and the switching transistor of every grade of shift register circuit is coupled to the main output terminal of its preceding shift register circuit thereafter; The reset transistor of afterbody shift register circuit receives final reset signal, and the reset transistor of other every grade shift register circuit is coupled to the main output terminal of its rear class shift register circuit.
3. shift register as claimed in claim 2, it is characterized in that, described in pull up transistor, the first pull-down transistor, the second pull-down transistor, the 3rd pull-down transistor, switching transistor, reset transistor, the first auxiliary pull-down transistor, the second auxiliary pull-down transistor and the 3rd auxiliary pull-down transistor be Thin Film Transistor (TFT).
4. shift register as claimed in claim 3, is characterized in that, in each shift register circuit:
In described signal output module: described in the source electrode that pulls up transistor connect and describedly connect described main output terminal from clock signal, drain electrode; The grid of described first pull-down transistor connects described master clock signal, source electrode connects described main output terminal, miss and connect low level end; The source electrode of described second pull-down transistor connects described main output terminal, drain electrode connects low level end; The grid of described 3rd pull-down transistor connects the drop-down Section Point of Section Point of the last shift register circuit of its place shift register circuit, drain electrode connects low level end;
The grid of described switching transistor connects described master clock signal, source electrode connects described primary input end, drain electrode connects described first node;
After the grid of described reset transistor connects a shift register circuit main output terminal, source electrode connects described first node, drain electrode connects low level end; And in described drop-down supplementary module:
Described first auxiliary pull-down transistor grid connects described master clock signal, source electrode connects described Section Point, drain electrode connects described low level end;
Described second auxiliary pull-down transistor grid connects described main output terminal, source electrode connects described Section Point, drain electrode connects described low level end;
Described Section Point is connect from clock signal, source electrode described in the grid of the described 3rd auxiliary pull-down transistor and drain electrode connect.
5. shift register as claimed in claim 4, is characterized in that, the breadth length ratio of the described 3rd auxiliary pull-down transistor is greater than the breadth length ratio of the described second auxiliary pull-down transistor.
6. shift register as claimed in claim 5, is characterized in that, the breadth length ratio of the described 3rd auxiliary pull-down transistor is greater than ten times of the breadth length ratio of the described second auxiliary pull-down transistor.
7. shift register as claimed in claim 3, it is characterized in that, described first electric capacity connects between described first node and main output terminal.
8. shift register as claimed in any of claims 1 to 7 in one of claims, it is characterized in that, the working time of described first pull-down transistor and the second pull-down transistor is respectively the half in drop-down cycle.
9. shift register as claimed in any of claims 1 to 7 in one of claims, it is characterized in that, in described shift register, shift register circuit is divided into odd level shift register circuit and even level shift register circuit, and the master clock signal that the master clock signal of described odd level shift register circuit reception and described even level shift register circuit receive is anti-phase.
10. a Thin Film Transistor-LCD, it is characterized in that, comprise array of display and gate driver circuit, described gate driver circuit is in order to produce multiple signal to control described array of display, and described gate driver circuit comprises shift register as in one of claimed in any of claims 1 to 9.
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Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295642B (en) * | 2012-09-19 | 2016-02-17 | 上海中航光电子有限公司 | Shift register and panel display apparatus |
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| CN103943057B (en) * | 2014-04-22 | 2016-04-13 | 深圳市华星光电技术有限公司 | The driving circuit of display panel and driving method thereof |
| CN104091572B (en) * | 2014-06-17 | 2016-04-06 | 京东方科技集团股份有限公司 | Two drop-down control module, shifting deposit unit, gate drivers and display panel |
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| CN104952417A (en) * | 2015-07-23 | 2015-09-30 | 合肥京东方光电科技有限公司 | Shift register unit and driving method thereof, grid drive circuit and display device |
| CN105469759B (en) * | 2015-12-15 | 2018-10-19 | 深圳市华星光电技术有限公司 | A kind of shift register |
| CN107068032B (en) * | 2017-01-22 | 2020-06-12 | 上海中航光电子有限公司 | Scanning unit and gate drive circuit |
| CN208938619U (en) * | 2018-11-26 | 2019-06-04 | 北京京东方技术开发有限公司 | Shift register cell, gate driving circuit and display device |
| CN111145678B (en) | 2020-02-19 | 2022-02-25 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, driving circuit and display device |
| CN114067712B (en) * | 2020-07-31 | 2023-09-15 | 京东方科技集团股份有限公司 | Gate driving circuit and display panel |
| WO2023201656A1 (en) * | 2022-04-21 | 2023-10-26 | 京东方科技集团股份有限公司 | Display panel and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093647A (en) * | 2006-06-21 | 2007-12-26 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| CN101533623A (en) * | 2009-02-26 | 2009-09-16 | 深圳华映显示科技有限公司 | Gate drive for inhibiting drift of a critical voltage |
| CN101625841A (en) * | 2009-07-29 | 2010-01-13 | 友达光电股份有限公司 | Liquid crystal display and shift registering device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI401663B (en) * | 2009-03-13 | 2013-07-11 | Au Optronics Corp | Display device with bi-directional voltage stabilizers |
-
2012
- 2012-09-19 CN CN201210350350.1A patent/CN103280196B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093647A (en) * | 2006-06-21 | 2007-12-26 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| CN101533623A (en) * | 2009-02-26 | 2009-09-16 | 深圳华映显示科技有限公司 | Gate drive for inhibiting drift of a critical voltage |
| CN101625841A (en) * | 2009-07-29 | 2010-01-13 | 友达光电股份有限公司 | Liquid crystal display and shift registering device |
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