CN101533623A - Gate drive for inhibiting drift of a critical voltage - Google Patents
Gate drive for inhibiting drift of a critical voltage Download PDFInfo
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- CN101533623A CN101533623A CN200910105817A CN200910105817A CN101533623A CN 101533623 A CN101533623 A CN 101533623A CN 200910105817 A CN200910105817 A CN 200910105817A CN 200910105817 A CN200910105817 A CN 200910105817A CN 101533623 A CN101533623 A CN 101533623A
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Abstract
The invention is appropriate for the field of gate drive technology, which provides a gate drive for inhibiting drift of a critical voltage, so as to provide a multi-gate signal to a multi-gate line, where the gate drive includes multi-level shift register, where each level shift register includes a pull-up unit, an energy storage unit, a buffer unit, a discharge unit, a pull-down unit, a control unit and a signal switch unit, where the pull-up unit pulls a gate signal up according to a drive control voltage and a first frequency; the buffer unit is used for receiving a input signal; the energy storage unit executes a charging procedure according to an input signal so as to supply a drive control voltage; the discharge unit pulls the drive control voltage down according to a control signal; the pull-down unit pulls a gate signal down according to the control signal; the control unit generates the control signal according to the input signal and a second frequency with opposite phase relative to the first frequency; and the signal switch unit switches the control signal according to the first frequency.
Description
Technical field
The invention belongs to the gate drive circuit technical field, outstanding reference and a kind of gate drive circuit that suppresses threshold voltage shift.
Background technology
Liquid crystal indicator (Liquid Crystal Display; LCD) be present widely used a kind of flat-panel screens, it has, and external form is frivolous, power saving and advantage such as radiationless.The principle of work of liquid crystal indicator is the ordered state that the voltage difference that utilize to change the liquid crystal layer two ends changes the liquid crystal molecule in the liquid crystal layer, in order to change the transmittance of liquid crystal layer, to cooperate backlight module again the light source that provided with show image.Generally speaking, liquid crystal indicator includes a plurality of pixel cells, gate drive circuit and source electrode drive circuit.Source electrode drive circuit is in order to provide a plurality of data-signals.Gate drive circuit comprises multi-stage shift register, is used to provide a plurality of gate drive signals and writes to a plurality of pixel cells to control a plurality of data-signals.Therefore, gate drive circuit is the critical components of control data signal write operation.
Fig. 1 is the synoptic diagram of the gate drive circuit that provides of prior art.As shown in Figure 1, for convenience of description, 100 of gate drive circuits show (N-1) level shift register 111, N level shift register 112 and (N+1) level shift register 113, wherein have only N level shift register 112 to show the built-in function unit structure.N level shift register 112 is in order to produce gate signal SGn according to first frequency CK1, second frequency CK2 and gate signal SGn-1.Gate signal SGn is fed into the respective pixel unit of array of pixels 101 via gate line GLn, in order to the write operation of the data-signal of control data line DLi.In addition, gate signal SGn is transferred to (N+1) level shift register 113 in addition, in order to as the required initial pulse signal of energy storage (N+1) level shift register 113.N level shift register 112 comprises pull-up unit 120, energy-storage units 135, buffer cell 140, drop-down unit 150, discharge cell 155 and control module 160.Energy-storage units 135 is used for carrying out charging procedure according to the gate signal SGn-1 that buffer cell 140 is received, and then produces drive control voltage VQn.Promptly the operate a switch gate signal SGn of polar curve GLn of pull-up unit 120 according to drive control voltage VQn and more than the first frequency CK1.Control module 160 comprises a plurality of transistors, in order to produce control signal SCn according to gate signal SGn-1 and anti-phase second frequency CK2 in first frequency CK1.Discharge cell 155 promptly is used for according to control signal SCn, to energy-storage units 135 carry out discharge procedures with drop-down drive control voltage VQn to low supply voltage Vss.150 of drop-down unit according to the utmost point signal SGn that operates a switch below the control signal SCn to low supply voltage Vss.
Yet, in the running of gate drive circuit 100, except N level shift register 112 was triggered with the period of the gate signal SGn that produces the accurate position of high voltage, all the other time control signal SCn all in the accurate position of high voltage with drop-down unit 150 of activation and discharge cell 155.That is the transistor 151,156 of drop-down unit 150 and discharge cell 155 maintains conducting state for a long time, thus cause threshold voltage shift easily, and then reduce the fiduciary level and the serviceable life of gate drive circuit 100.
Summary of the invention
The object of the present invention is to provide a kind of gate drive circuit that suppresses threshold voltage shift, be intended to solve prior art and cause threshold voltage shift easily, and then reduce the fiduciary level of gate drive circuit and the problem in serviceable life.
The present invention realizes like this, a kind of gate drive circuit that suppresses threshold voltage shift, in order to a plurality of gate signals bar gate line at the most to be provided, described gate drive circuit comprises multi-stage shift register, and the N level shift register of described multi-stage shift register comprises:
Pull-up unit is electrically connected on the N gate line, in order to according to drive control voltage and first frequency N gate signal is pulled to the accurate position of high voltage;
Buffer cell is in order to receiving inputted signal;
Energy-storage units is electrically connected on pull-up unit and buffer cell, is used for carrying out charging procedure according to input signal, to provide drive control voltage the supreme unit that draws;
Discharge cell is electrically connected on energy-storage units, in order to according to control signal or (N+1) level (N+1) gate signal that shift register produced drive control voltage is pulled down to low supply voltage;
Drop-down unit is electrically connected on the N gate line, in order to according to control signal N gate signal is pulled down to low supply voltage;
Control module is electrically connected on discharge cell and drop-down unit, in order to produce control signal according to input signal and anti-phase second frequency in first frequency;
Signal switch unit is electrically connected on control module, in order to according to first frequency control signal is switched to low supply voltage.
Another object of the present invention is to provide another kind can suppress the gate drive circuit of threshold voltage shift, in order to a plurality of gate signals bar gate line at the most to be provided, described gate drive circuit comprises multi-stage shift register, and the N level shift register of described multi-stage shift register comprises:
Pull-up unit is electrically connected on the N gate line, in order to according to drive control voltage and first frequency N gate signal is pulled to the accurate position of high voltage;
Buffer cell is in order to receiving inputted signal;
Energy-storage units is electrically connected on pull-up unit and buffer cell, is used for carrying out charging procedure according to input signal, to provide drive control voltage the supreme unit that draws;
Discharge cell is electrically connected on energy-storage units, in order to according to (N+1) level (N+1) gate signal that shift register produced drive control voltage is pulled down to low supply voltage;
Drop-down unit is electrically connected on the N gate line, in order to according to control signal N gate signal is pulled down to low supply voltage;
Control module is electrically connected on drop-down unit, in order to produce control signal according to first frequency and N gate signal;
Signal switch unit is electrically connected on control module, in order to according to anti-phase second frequency in described first frequency control signal is switched to low supply voltage.
In the present invention, the extra signal switch unit of gate drive circuit utilization periodically switches on control signal between accurate position of high voltage and the accurate position of low-voltage, so can significantly reduce the threshold voltage shift of related transistor, and then improve the fiduciary level and the serviceable life of gate drive circuit.
Description of drawings
Fig. 1 is the synoptic diagram of the gate drive circuit that provides of prior art;
Fig. 2 is the synoptic diagram of the gate drive circuit that provides of first embodiment of the invention;
Fig. 3 is the work coherent signal oscillogram of the gate drive circuit that provides of Fig. 2, and wherein transverse axis is a time shaft;
Fig. 4 is the synoptic diagram of the gate drive circuit that provides of second embodiment of the invention;
Fig. 5 is the synoptic diagram of the gate drive circuit that provides of third embodiment of the invention;
Fig. 6 is the synoptic diagram of the gate drive circuit that provides of fourth embodiment of the invention;
Fig. 7 is the synoptic diagram of the gate drive circuit that provides of fifth embodiment of the invention;
Fig. 8 is the work coherent signal oscillogram of the gate drive circuit that provides of Fig. 7, and wherein transverse axis is a time shaft;
Fig. 9 is the synoptic diagram of the gate drive circuit of sixth embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In embodiments of the present invention, the extra signal switch unit of gate drive circuit utilization periodically switches on control signal between accurate position of high voltage and the accurate position of low-voltage, so can significantly reduce the threshold voltage shift of related transistor, and then improve the fiduciary level and the serviceable life of gate drive circuit.
Fig. 2 is the synoptic diagram of the gate drive circuit that provides of first embodiment of the invention.As shown in Figure 2, gate drive circuit 200 comprises multi-stage shift register, for convenience of description, 200 of gate drive circuits show (N-1) level shift register 211, N level shift register 212 and (N+1) level shift register 213, wherein have only N level shift register 212 to show the built-in function unit structure, all the other grades shift register duplicates in N level shift register 212, so do not give unnecessary details in addition.(N-1) level shift register 211 is in order to provide gate signal SGn-1, and N level shift register 212 is in order to provide gate signal SGn, and (N+1) level shift register 213 is in order to provide gate signal SGn+1.Gate signal SGn-1 is fed into the pixel cell 205 of array of pixels 201 via gate line GLn-1, writes to pixel cell 205 in order to the data-signal of control data line DLi.Gate signal SGn is fed into the pixel cell 305 of array of pixels 201 via gate line GLn, writes to pixel cell 305 in order to the data-signal of control data line DLi.Gate signal SGn+1 is fed into the pixel cell 405 of array of pixels 201 via gate line GLn+1, writes to pixel cell 405 in order to the data-signal of control data line DLi.
N level shift register 212 comprises pull-up unit 220, energy-storage units 235, buffer cell 240, discharge cell 250, drop-down unit 255, control module 260, auxiliary drop-down unit 265 and signal switch unit 270.Pull-up unit 220 is electrically connected on gate line GLn, in order to the gate signal SGn of the polar curve GLn that operates a switch according to drive control voltage VQn and more than the first frequency CK1.Buffer cell 240 is electrically connected on (N-1) level shift register 211 with reception gate signal SGn-1, that is N level shift register 212 is as the required initial pulse signal of energy storage with gate signal SGn-1.Energy-storage units 235 is electrically connected on pull-up unit 220 and buffer cell 240, is used for carrying out charging procedure according to gate signal SGn-1, and drive control voltage VQn is provided the supreme unit 220 that draws according to this.Control module 260 is electrically connected on discharge cell 250 and drop-down unit 255, in order to produce control signal SCn according to gate signal SGn-1 and anti-phase second frequency CK2 in first frequency CK1.Discharge cell 250 is electrically connected on energy-storage units 235, be used for according to control signal SCn carry out discharge procedures with drop-down drive control voltage VQn to low supply voltage Vss.Drop-down unit 255 is electrically connected on gate line GLn, is used for according to the utmost point signal SGn that operates a switch below the control signal SCn to low supply voltage Vss.Auxiliary drop-down unit 265 also is electrically connected on gate line GLn, is used for according to the utmost point signal SGn that operates a switch below the gate signal SGn+1 to low supply voltage Vss.Signal switch unit 270 is electrically connected on control module 260, is used for according to first frequency CK1 with switch-over control signal SCn to low supply voltage Vss.
In the embodiment of Fig. 2, buffer cell 240 comprises buffer transistor 242, pull-up unit 220 comprises first switch 221, energy-storage units 235 comprises electric capacity 236, discharge cell 250 comprises second switch 251, and drop-down unit 255 comprises the 3rd switch 256, and auxiliary drop-down unit 265 comprises the 4th switch 266, control module 260 comprises the 5th switch 261 and the 6th switch 262, and signal switch unit 270 comprises minion pass 271.Buffer transistor 242 comprises first end, second end and gate pole end, and wherein first end is electrically connected on (N-1) level shift register 211 to receive gate signal SGn-1, and gate terminal is electrically connected on first end, and second end is electrically connected on electric capacity 236.First switch 221 comprises first end, second end and gate pole end, and wherein first end is in order to receive first frequency CK1, and gate terminal is electrically connected on second end of buffer transistor 242, and second end is electrically connected on gate line GLn.Electric capacity 236 comprises first end and second end, and wherein first end is electrically connected on the gate terminal of first switch 221, and second end is electrically connected on second end of first switch 221.
The work coherent signal oscillogram of the gate drive circuit that Fig. 3 provides for Fig. 2, wherein transverse axis is a time shaft.In Fig. 3, basipetal signal is respectively first frequency CK1, second frequency CK2, gate signal SGn-1, gate signal SGn, gate signal SGn+1, drive control voltage VQn and control signal SCn.
As shown in Figure 3, in period T1, gate signal SGn-1 rises to high levle by low level, and buffer transistor 242 switches to conducting state, makes drive control voltage VQn also and then rise to the first high voltage Vh1 from low-voltage.Simultaneously, but high levle conducting the 6th switch 262 of gate signal SGn-1 with drop-down control signal SCn to low supply voltage Vss.In period T2, SGn-1 reduces to low level by high levle because of the gate signal, buffer transistor 242 switches to cut-off state, making drive control voltage VQn is suspension joint voltage, again because of first frequency CK1 switches to high levle, so can drive control voltage VQn be pulled to the second high voltage Vh2 by the first high voltage Vh1 by the assembly electric capacity coupling of first switch 221, and first switch 221 of conducting according to this, SGn is pulled to high levle by low level with the gate signal.At this moment, first frequency CK1 also the conducting minion close 271 with switch-over control signal SCn to low supply voltage Vss, and then second switch 251 is ended, be used for guaranteeing that the gate terminal of first switch 221 is at floating.
In period T3, second frequency CK2 switches to high levle, so draw control signal SCn to high power supply voltage Vdd more than 261 conductings of the 5th switch, and then conducting second switch 251 with drop-down drive control voltage VQn to low supply voltage Vss, and conducting the 3rd switch is operated a switch utmost point signal SGn to low supply voltage Vss below 256.In addition, because of (N+1) level shift register 213 utilizes gate signal SGn to produce the gate signal SGn+1 of high levle as the required initial pulse signal of energy storage in period T3, utmost point signal SGn is to low supply voltage Vss so the 4th switch 266 is also operated a switch below the conducting.
In period T4, second frequency CK2 switches to low level ends the 5th switch 261.At this moment, first frequency CK1 switches to high levle, thus minion close 271 conductings with switch-over control signal SCn to low supply voltage Vss, and then by second switch 251 and the 3rd switch 256.In period T5, first frequency CK1 switches to low level ends minion pass 271.At this moment, second frequency CK2 switches to high levle, so draw control signal SCn to high power supply voltage Vdd more than 261 conductings of the 5th switch, and then conducting second switch 251 with drop-down drive control voltage VQn to low supply voltage Vss, and conducting the 3rd switch is operated a switch utmost point signal SGn to low supply voltage Vss below 256.Thereafter, continue at gate signal SGn under the state of low level, be set forth in the circuit operation in period T4 and the T5 on periodically carrying out, that is, the 5th switch 261 and minion close 271 mutual conductings with control signal SCn is periodically switched on high power supply voltage Vdd and low supply voltage Vss between.So the mutual conducting mode of operation by the 5th switch 261 and minion pass 271 can significantly reduce threshold voltage shift, and then improve the fiduciary level and the serviceable life of gate drive circuit 200.
The synoptic diagram of the gate drive circuit that Fig. 4 provides for second embodiment of the invention.As shown in Figure 4, gate drive circuit 300 comprises multi-stage shift register, and for convenience of description, gate drive circuit 300 still only shows (N-1) level shift register 311, N level shift register 312 and (N+1) level shift register 313.Compared to gate drive circuit shown in Figure 2 200, (N-1) level shift register 311 is in addition in order to provide initial pulse signal STn-1, in order to initial pulse signal STn to be provided, (N+1) level shift register 313 is in addition in order to provide initial pulse signal STn+1 in addition for N level shift register 312.The waveform of initial pulse signal STn-1 is same as the waveform of gate signal SGn-1 in fact, and the waveform of initial pulse signal STn is same as the waveform of gate signal SGn in fact, and the waveform of initial pulse signal STn+1 is same as the waveform of gate signal SGn+1 in fact.Comprise carry unit 280 and reset cell 295 in addition compared to N level shift register shown in Figure 2 212, the N level shift registers 312.Carry unit 280 comprises octavo pass 281, is used for being fed into (N+1) level shift register 313 according to drive control voltage VQn and first frequency CK1 generation initial pulse signal STn.Octavo is closed 281 and is comprised first end, second end and gate pole end, and wherein first end is in order to receive first frequency CK1, and gate terminal is electrically connected on first end of electric capacity 236, and second end is in order to output initial pulse signal STn to the (N+1) level shift register 313.Reset cell 295 comprises the 9th switch 296, is used for according to reset signal Sre drive control voltage VQn being reset to low supply voltage Vss.The 9th switch 296 comprises first end, second end and gate pole end, and wherein first end is electrically connected on first end of electric capacity 236, and gate terminal is in order to receive reset signal Sre, and second end is in order to receive low supply voltage Vss.It is thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor that octavo is closed the 281 and the 9th switch 296.In addition, first end of buffer transistor 242 then is electrically connected on (N-1) level shift register 311 to receive initial pulse signal STn-1.All the other grades shift register is in like manner analogized.Except above-mentioned points, the internal electrical annexation of each grade shift register all duplicates basically in N level shift register 212 shown in Figure 2, and the work coherent signal waveform of gate drive circuit 300 also is same as signal waveform shown in Figure 3, so repeat no more.
The synoptic diagram of the gate drive circuit that Fig. 5 provides for third embodiment of the invention.As shown in Figure 5, gate drive circuit 400 comprises multi-stage shift register, and for convenience of description, gate drive circuit 400 still only shows (N-1) level shift register 411, N level shift register 412 and (N+1) level shift register 413.Comprise voltage regulation unit 290 in addition compared to N level shift register shown in Figure 4 312, the N level shift registers 412.Voltage regulation unit 290 comprises the tenth switch the 291, the 11 switch 292 and twelvemo pass 293, is used for suppressing the ripple voltage of gate signal SGn.The tenth switch 291 comprises first end, second end and gate pole end, and wherein first end is in order to receive initial pulse signal STn-1, and second end is electrically connected on second end of buffer transistor 242, and gate terminal is in order to receive second frequency CK2.The 11 switch 292 comprises first end, second end and gate pole end, and wherein first end is electrically connected on second end of the tenth switch 291, and second end is electrically connected on second end of first switch 221, and gate terminal is in order to receive first frequency CK1.The 12 closes 293 comprises first end, second end and gate pole end, and wherein first end is electrically connected on second end of the 11 switch 292, and second end is in order to receive low supply voltage Vss, and gate terminal is in order to receive second frequency CK2.It is thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor that the tenth switch the 291, the 11 switch 292 and twelvemo close 293.Basically, voltage regulation unit 290 is a prior art, so no longer carefully state its circuit working principle.All the other grades shift register is in like manner analogized.Except above-mentioned points, the internal electrical annexation of each grade shift register all duplicates basically in N level shift register 312 shown in Figure 4, and the work coherent signal waveform of gate drive circuit 400 also is same as signal waveform shown in Figure 3, so repeat no more.
The synoptic diagram of the gate drive circuit that Fig. 6 provides for fourth embodiment of the invention.As shown in Figure 6, gate drive circuit 500 comprises multi-stage shift register, for convenience of description, gate drive circuit 500 still only shows (N-1) level shift register 511, N level shift register 512 and (N+1) level shift register 513, wherein have only N level shift register 512 to show the built-in function unit structure, all the other grades shift register duplicates in N level shift register 512, so do not give unnecessary details in addition.Compared to N level shift register shown in Figure 5 412, the N level shift registers 512 is that discharge cell 250 is replaced into discharge cell 550, and all the other are constant.Discharge cell 550 comprises second switch 551, be used for according to gate signal SGn+1 carry out discharge procedures with drop-down drive control voltage VQn to low supply voltage Vss.Second switch 551 comprises first end, second end and gate pole end, and wherein first end is electrically connected on first end of electric capacity 236, and second end is in order to receive low supply voltage Vss, and gate terminal is electrically connected on gate line GLn+1 to receive gate signal SGn+1.All the other grades shift register is in like manner analogized.Except above-mentioned points, the internal electrical annexation of each grade shift register all duplicates basically in N level shift register 412 shown in Figure 5, and the work coherent signal waveform of gate drive circuit 500 also is same as signal waveform shown in Figure 3, so repeat no more.
The synoptic diagram of the gate drive circuit that Fig. 7 provides for fifth embodiment of the invention.As shown in Figure 7, gate drive circuit 600 comprises multi-stage shift register, for convenience of description, gate drive circuit 600 still only shows (N-1) level shift register 611, N level shift register 612 and (N+1) level shift register 613, wherein have only N level shift register 612 to show the built-in function unit structure, all the other grades shift register duplicates in N level shift register 612, so do not give unnecessary details in addition.(N-1) level shift register 611 is in order to provide gate signal SGn-1, and N level shift register 612 is in order to provide gate signal SGn, and (N+1) level shift register 613 is in order to provide gate signal SGn+1.
N level shift register 612 comprises pull-up unit 620, energy-storage units 635, buffer cell 640, discharge cell 650, drop-down unit 655, control module 680, auxiliary drop-down unit 665, signal switch unit 670 and voltage regulation unit 690.Pull-up unit 620 is electrically connected on gate line GLn, in order to the gate signal SGn of the polar curve GLn that operates a switch according to drive control voltage VQn and more than the first frequency CK1.Buffer cell 640 is electrically connected on (N-1) level shift register 611 with reception gate signal SGn-1, that is N level shift register 612 is as the required initial pulse signal of energy storage with gate signal SGn-1.Energy-storage units 635 is electrically connected on pull-up unit 620 and buffer cell 640, is used for carrying out charging procedure according to gate signal SGn-1, and drive control voltage VQn is provided the supreme unit 620 that draws according to this.Control module 680 is electrically connected on drop-down unit 655, in order to produce control signal SCn according to first frequency CK1 and gate signal SGn.Drop-down unit 655 is electrically connected on gate line GLn, is used for according to the utmost point signal SGn that operates a switch below the control signal SCn to low supply voltage Vss.Auxiliary drop-down unit 665 also is electrically connected on gate line GLn, is used for according to the utmost point signal SGn that operates a switch below the gate signal SGn+1 to low supply voltage Vss.Signal switch unit 670 is electrically connected on control module 680, is used for according to second frequency CK2 with switch-over control signal SCn to low supply voltage Vss.Discharge cell 650 is electrically connected on energy-storage units 635, be used for according to gate signal SGn+1 carry out discharge procedures with drop-down drive control voltage VQn to low supply voltage Vss.Voltage regulation unit 690 is electrically connected on energy-storage units 635 and gate line GLn, is used for suppressing the ripple voltage of gate signal SGn.
In the embodiment of Fig. 7, buffer cell 640 comprises buffer transistor 642, pull-up unit 620 comprises first switch 621, energy-storage units 635 comprises electric capacity 636, discharge cell 650 comprises second switch 651, drop-down unit 655 comprises the 3rd switch 656, auxiliary drop-down unit 665 comprises the 4th switch 666, signal switch unit 670 comprises the 5th switch 671, voltage regulation unit 690 comprises the 6th switch 691, minion pass 692 and octavo close 693, and control module 680 comprises the 9th switch 681, the tenth switch 682, the 11 switch 683, twelvemo closes 684, first electric capacity 686 and second electric capacity 688.It is thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor that the buffer transistor 642 and first switch 621 to twelvemo closes 684.
Second switch 651 comprises first end, second end and gate pole end, and wherein first end is electrically connected on first end of electric capacity 636, and second end is in order to receive low supply voltage Vss, and gate terminal is electrically connected on gate line GLn+1 to receive gate signal SGn+1.The 3rd switch 656 comprises first end, second end and gate pole end, and wherein first end is electrically connected on second end of first switch 621, and second end is in order to receive low supply voltage Vss, and gate terminal is electrically connected on control module 680 to receive control signal SCn.The 4th switch 666 comprises first end, second end and gate pole end, and wherein first end is electrically connected on second end of first switch 621, and second end is in order to receive low supply voltage Vss, and gate terminal is electrically connected on gate line GLn+1 to receive gate signal SGn+1.The 5th switch 671 comprises first end, second end and gate pole end, and wherein first end is electrically connected on the gate terminal of the 3rd switch 656, and second end is in order to receive low supply voltage Vss, and gate terminal is in order to receive second frequency CK2.The 5th switch 671 in order to according to second frequency CK2 switch-over control signal SCn to low supply voltage Vss.
The 6th switch 691 comprises first end, second end and gate pole end, and wherein first end is in order to receive gate signal SGn-1, and second end is electrically connected on second end of buffer transistor 642, and gate terminal is in order to receive second frequency CK2.Minion is closed 692 and is comprised first end, second end and gate pole end, and wherein first end is electrically connected on second end of the 6th switch 691, and second end is electrically connected on second end of first switch 621, and gate terminal is in order to receive first frequency CK1.Octavo is closed 693 and is comprised first end, second end and gate pole end, and wherein first end is electrically connected on second end of minion pass 692, and second end is in order to receive low supply voltage Vss, and gate terminal is in order to receive second frequency CK2.
The 9th switch 681 comprises first end, second end and gate pole end, and wherein first end is in order to receive first frequency CK1, and gate terminal is electrically connected on first end.The tenth switch 682 comprises first end, second end and gate pole end, and wherein first end is electrically connected on second end of the 9th switch 681, and gate terminal is in order to receive gate signal SGn, and second end is in order to receive low supply voltage Vss.The 11 switch 683 comprises first end, second end and gate pole end, and wherein first end is in order to receive first frequency CK1, and gate terminal is electrically connected on second end of the 9th switch 681, and second end is electrically connected on the gate terminal of the 3rd switch 656.First electric capacity 686 be electrically connected on first end of the 11 switch 683 and gate terminal between.Second electric capacity 688 be electrically connected on the gate terminal of the 11 switch 683 and second end between.Twelvemo is closed 684 and is comprised first end, second end and gate pole end, and wherein first end is electrically connected on second end of the 11 switch 683, and gate terminal is electrically connected on the gate terminal of the tenth switch 682, and second end is in order to receive low supply voltage Vss.
The work coherent signal oscillogram of the gate drive circuit that Fig. 8 provides for Fig. 7, wherein transverse axis is a time shaft.In Fig. 8, basipetal signal is respectively first frequency CK1, second frequency CK2, gate signal SGn-1, gate signal SGn, gate signal SGn+1, drive control voltage VQn, control signal SCn and control signal SCnx.As shown in Figure 8, in period T1, gate signal SGn-1 rises to high levle by low level, and buffer transistor 642 switches to conducting state, makes drive control voltage VQn also and then rise to the first high voltage Vh1 from low-voltage.At this moment, but second frequency CK2 conducting the 5th transistor 671 of tool high levle, in order to switch-over control signal SCn to low supply voltage Vss.
In period T2, SGn-1 reduces to low level by high levle because of the gate signal, buffer transistor 642 switches to cut-off state, making drive control voltage VQn is suspension joint voltage, again because of first frequency CK1 switches to high levle, so can drive control voltage VQn be pulled to the second high voltage Vh2 by the first high voltage Vh1 by the assembly electric capacity coupling of first switch 621, and first switch 621 of conducting according to this, SGn is pulled to high levle by low level with the gate signal.At this moment, but the gate signal SGn conducting twelvemo of tool high levle closes 684, in order to drop-down control signal SCn to low supply voltage Vss, and then by the 3rd switch 656 to keep the gate signal SGn of high levle.In period T3, second frequency CK2 switches to high levle with conducting the 5th transistor 671, in order to retentive control signal SCn in low supply voltage Vss.In addition, because of (N+1) level shift register 613 utilizes gate signal SGn to produce the gate signal SGn+1 of high levle as the required initial pulse signal of energy storage in period T3, thus but conducting the 4th switch is operated a switch below 666 utmost point signal SGn to low supply voltage Vss.
In period T4, second frequency CK2 switches to low level to end the 5th switch 671.At this moment, first frequency CK1 switches to the control signal SCn that high levle makes control module 680 output high levles, is used for conducting the 3rd switch to operate a switch utmost point signal SGn below 656 to low supply voltage Vss.In period T5, second frequency CK2 switches to high levle and makes 671 conductings of the 5th switch,, and then switches the 3rd switch 656 and is cut-off state to low supply voltage Vss in order to switch-over control signal SCn.Thereafter, continue at gate signal SGn under the state of low level, be set forth in the circuit operation in period T4 and the T5 on periodically carrying out, that is, the 5th switch 671 periodically conducting with drop-down control signal SCn periodically to low supply voltage Vss, and then periodically conducting the 3rd switch 656 periodically to switch gate signal SGn to low supply voltage Vss.
Please continue with reference to figure 8, the waveform of control signal SCnx is a gate drive circuit 600 under the circuit running of omitting signal switch unit 670, the signal output waveform of control module 680.As shown in Figure 8, the waveform of control signal SCnx when gate signal SGn continues low level, be the quite unfavorable waveform that discharges and recharges, and if set the appearance value ratio of unsuitable first electric capacity 686 and second electric capacity 688, the waveform of control signal SCnx can be more undesirable.The waveform of unfavorable control signal SCnx can cause the 656 undesired switch runnings of the 3rd switch, causes threshold voltage shift, reduces the fiduciary level and the serviceable life of circuit.Compared to control signal SCnx, the waveform of control signal SCn when gate signal SGn continues low level presents desirable square wave, so can make the normal switch running of the 3rd switch 656 performance period property.In other words, can significantly reduce the threshold voltage shift of the 3rd switch 656, and then improve the fiduciary level and the serviceable life of gate drive circuit 600 by the running of signal switch unit 670.
The synoptic diagram of the gate drive circuit that Fig. 9 provides for sixth embodiment of the invention.As shown in Figure 9, gate drive circuit 700 comprises multi-stage shift register, and for convenience of description, gate drive circuit 700 still only shows (N-1) level shift register 711, N level shift register 712 and (N+1) level shift register 713.Compared to gate drive circuit shown in Figure 7 600, (N-1) level shift register 711 is in addition in order to provide initial pulse signal STn-1, in order to initial pulse signal STn to be provided, (N+1) level shift register 713 is in addition in order to provide initial pulse signal STn+1 in addition for N level shift register 712.The waveform of each initial pulse signal comes down to be same as the waveform of corresponding gate signal.Comprise carry unit 675 and reset cell 695 in addition compared to N level shift register shown in Figure 7 612, the N level shift registers 712.Carry unit 675 comprises the 13 switch 676, is used for being fed into (N+1) level shift register 713 according to drive control voltage VQn and first frequency CK1 generation initial pulse signal STn.The 13 switch 676 comprises first end, second end and gate pole end, and wherein first end is in order to receive first frequency CK1, and gate terminal is electrically connected on first end of electric capacity 636, and second end is in order to output initial pulse signal STn to the (N+1) level shift register 713.Reset cell 695 comprises the 14 switch 696, is used for according to reset signal Sre drive control voltage VQn being reset to low supply voltage Vss.The 14 switch 696 comprises first end, second end and gate pole end, and wherein first end is electrically connected on first end of electric capacity 636, and gate terminal is in order to receive reset signal Sre, and second end is in order to receive low supply voltage Vss.The 13 switch 676 and the 14 switch 696 are thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor.In addition, first end of first end of buffer transistor 642 and the 6th switch 691 is electrically connected on (N-1) level shift register 711 to receive initial pulse signal STn-1.All the other grades shift register is in like manner analogized.Except above-mentioned points, the internal electrical annexation of each grade shift register all duplicates basically in N level shift register 612 shown in Figure 7, and the work coherent signal waveform of gate drive circuit 700 also is same as signal waveform shown in Figure 8, so repeat no more.
In embodiments of the present invention, the extra signal switch unit of gate drive circuit utilization of the present invention periodically switches on control signal between accurate position of high voltage and the accurate position of low-voltage, so can significantly reduce the threshold voltage shift of related transistor, and then improve the fiduciary level and the serviceable life of gate drive circuit.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. gate drive circuit that can suppress threshold voltage shift, in order to a plurality of gate signals bar gate line at the most to be provided, it is characterized in that described gate drive circuit comprises multi-stage shift register, a N level shift register of described multi-stage shift register comprises:
One pull-up unit is electrically connected on a N gate line of described gate line, in order to according to a drive control voltage and a first frequency one N gate signal of described gate signal is pulled to the accurate position of a high voltage;
One buffer cell is in order to receive an input signal;
One energy-storage units is electrically connected on described pull-up unit and described buffer cell, is used for carrying out a charging procedure according to described input signal, and to provide described drive control voltage to described pull-up unit, wherein said energy-storage units comprises an electric capacity;
One discharge cell is electrically connected on described energy-storage units, in order to according to a control signal or one (N+1) level, one (N+1) gate signal that shift register produced described drive control voltage is pulled down to a low supply voltage;
One drop-down unit is electrically connected on described N gate line, in order to according to described control signal described N gate signal is pulled down to described low supply voltage;
One control module is electrically connected on described discharge cell and described drop-down unit, in order to produce described control signal according to described input signal and an anti-phase second frequency in described first frequency; With
One signal switch unit is electrically connected on described control module, in order to according to described first frequency described control signal is switched to described low supply voltage.
2. gate drive circuit as claimed in claim 1 is characterized in that described signal switch unit comprises a transistor, and described transistor comprises:
One first end is electrically connected on described control module;
One gate terminal is in order to receive described first frequency; With
One second end is in order to receive described low supply voltage;
Described pull-up unit comprises a transistor, and described transistor comprises:
One first end is in order to receive described first frequency;
One gate terminal is electrically connected on described energy-storage units to receive described drive control voltage; With
One second end is electrically connected on described N gate line.
3. gate drive circuit as claimed in claim 1 is characterized in that described buffer cell comprises a transistor, and described transistor comprises:
One first end is electrically connected on one (N-1) level shift register to receive one (N-1) gate signal;
One gate terminal is electrically connected on described first end; With
One second end is electrically connected on described energy-storage units;
Wherein said input signal is described (N-1) gate signal;
Described discharge cell comprises a transistor, and described transistor comprises:
One first end is electrically connected on described energy-storage units;
One gate terminal is in order to receive described (N+1) gate signal or to be electrically connected on described control module to receive described control signal; With
One second end is in order to receive described low supply voltage;
Described drop-down unit comprises a transistor, and described transistor comprises:
One first end is electrically connected on described N gate line;
One gate terminal is electrically connected on described control module to receive described control signal; With
One second end is in order to receive described low supply voltage.
4. gate drive circuit as claimed in claim 1 is characterized in that, described control module comprises: a first transistor, and described the first transistor comprises:
One first end is in order to receive a high power supply voltage;
One gate terminal is in order to receive described second frequency; With
One second end is electrically connected on described discharge cell and described drop-down unit; With
One transistor seconds, described transistor seconds comprises:
One first end is electrically connected on second end of described the first transistor;
One gate terminal is in order to receive described input signal; With
One second end is in order to receive described low supply voltage.
5. gate drive circuit as claimed in claim 1 is characterized in that, described N level shift register also comprises:
One carry unit is electrically connected on described energy-storage units, is used for producing a N initial pulse signal according to described drive control voltage and described first frequency, and described N initial pulse signal is sent to a buffer cell of described (N+1) level shift register;
Wherein, described carry unit comprises:
One transistor, described transistor comprises:
One first end is used for receiving described first frequency;
One gate terminal is electrically connected on described energy-storage units to receive described drive control voltage; With
One second end, be electrically connected on described (N+1) level shift register buffer cell;
Wherein, the buffer cell of described N level shift register comprises:
One transistor, described transistor comprises:
One first end is used for receiving one (N-1) initial pulse signal that the carry unit of one (N-1) level shift register is produced;
One gate terminal is electrically connected on described first end; With
One second end is electrically connected on described energy-storage units;
Wherein said input signal is described (N-1) initial pulse signal.
6. gate drive circuit as claimed in claim 1 is characterized in that, described N level shift register also comprises:
One auxiliary drop-down unit is electrically connected on described N gate line, in order to according to described (N+1) gate signal described N gate signal is pulled down to described low supply voltage;
Described auxiliary drop-down unit comprises a transistor, and described transistor comprises:
One first end is electrically connected on described N gate line;
One gate terminal is in order to receive described (N+1) gate signal; With
One second end is in order to receive described low supply voltage;
One voltage regulation unit is electrically connected on described energy-storage units, is used for according to described input signal, described first frequency and described second frequency to suppress the ripple voltage of described N gate signal;
Wherein said voltage regulation unit comprises:
One the first transistor, described the first transistor comprises:
One first end is in order to receive described input signal;
One gate terminal is in order to receive described second frequency; With
One second end is electrically connected on described buffer cell;
One transistor seconds, described transistor seconds comprises:
One first end is electrically connected on second end of described the first transistor;
One gate terminal is in order to receive described first frequency; With
One second end is electrically connected on described N gate line; With
One the 3rd transistor comprises:
One first end is electrically connected on second end of described transistor seconds;
One gate terminal is in order to receive described second frequency; With
One second end is in order to receive described low supply voltage;
One reset cell is electrically connected on described energy-storage units, is used for according to a reset signal described drive control voltage being reset to described low supply voltage;
The reset cell of wherein said N level shift register comprises:
One transistor, described transistor comprises:
One first end is electrically connected on described energy-storage units;
One gate terminal is in order to receive described reset signal; With
One second end is in order to receive described low supply voltage.
7. gate drive circuit that can suppress threshold voltage shift, in order to a plurality of gate signals bar gate line at the most to be provided, it is characterized in that described gate drive circuit comprises multi-stage shift register, a N level shift register of described multi-stage shift register comprises:
One pull-up unit is electrically connected on a N gate line of described gate line, in order to according to a drive control voltage and a first frequency one N gate signal of described gate signal is pulled to the accurate position of a high voltage;
One buffer cell is in order to receive an input signal;
One energy-storage units is electrically connected on described pull-up unit and described buffer cell, is used for carrying out a charging procedure according to described input signal, and to provide described drive control voltage to described pull-up unit, wherein said energy-storage units comprises an electric capacity;
One discharge cell is electrically connected on described energy-storage units, in order to according to one (N+1) level, one (N+1) gate signal that shift register produced described drive control voltage is pulled down to a low supply voltage;
One drop-down unit is electrically connected on described N gate line, in order to according to a control signal described N gate signal is pulled down to described low supply voltage;
One control module is electrically connected on described drop-down unit, in order to produce described control signal according to described first frequency and described N gate signal; With
One signal switch unit is electrically connected on described control module, in order to according to an anti-phase second frequency in described first frequency described control signal is switched to described low supply voltage.
8. gate drive circuit as claimed in claim 7 is characterized in that, described signal switch unit comprises:
One transistor, described transistor comprises:
One first end is electrically connected on described control module;
One gate terminal is in order to receive described second frequency; With
One second end is in order to receive described low supply voltage;
Described pull-up unit comprises:
One transistor, described transistor comprises:
One first end is in order to receive described first frequency;
One gate terminal is electrically connected on described energy-storage units to receive described drive control voltage; With
One second end is electrically connected on described N gate line.
9. gate drive circuit as claimed in claim 7 is characterized in that, described buffer cell comprises:
One transistor, described transistor comprises:
One first end is electrically connected on one (N-1) level shift register to receive one (N-1) gate signal;
One gate terminal is electrically connected on described first end; With
One second end is electrically connected on described energy-storage units;
Wherein said input signal is described (N-1) gate signal;
Described discharge cell comprises:
One transistor, described transistor comprises:
One first end is electrically connected on described energy-storage units;
One gate terminal is in order to receive described (N+1) gate signal; With
One second end is in order to receive described low supply voltage;
Described drop-down unit comprises:
One transistor, described transistor comprises:
One first end is electrically connected on described N gate line;
One gate terminal is electrically connected on described control module to receive described control signal; With
One second end is in order to receive described low supply voltage;
Described control module comprises:
One the first transistor comprises:
One first end is in order to receive described first frequency;
One gate terminal is electrically connected on described first end; With
One second end;
One transistor seconds comprises:
One first end is electrically connected on second end of described the first transistor;
One gate terminal is in order to receive described N gate signal; With
One second end is in order to receive described low supply voltage;
One the 3rd transistor comprises:
One first end is in order to receive described first frequency;
One gate terminal is electrically connected on second end of described the first transistor; With
One second end is electrically connected on described drop-down unit;
One the 4th transistor comprises:
One first end is electrically connected on the described the 3rd transistorized second end;
One gate terminal is electrically connected on the gate terminal of described transistor seconds; With
One second end is in order to receive described low supply voltage;
One first electric capacity, be electrically connected on the described the 3rd transistorized first end and gate terminal between; With
One second electric capacity, be electrically connected on the described the 3rd transistorized gate terminal and second end between.
10. gate drive circuit as claimed in claim 7 is characterized in that, described N level shift register also comprises:
One carry unit is electrically connected on described energy-storage units, is used for producing a N initial pulse signal according to described drive control voltage and described first frequency, and described N initial pulse signal is sent to a buffer cell of described (N+1) level shift register;
The carry unit of described N level shift register comprises:
One transistor, described transistor comprises:
One first end is used for receiving described first frequency;
One gate terminal is electrically connected on described energy-storage units to receive described drive control voltage; With
One second end, be electrically connected on described (N+1) level shift register buffer cell;
The buffer cell of described N level shift register comprises:
One transistor, described transistor comprises:
One first end is used for receiving one (N-1) initial pulse signal that the carry unit of one (N-1) level shift register is produced;
One gate terminal is electrically connected on described first end; With
One second end is electrically connected on described energy-storage units;
Wherein said input signal is described (N-1) initial pulse signal;
One auxiliary drop-down unit is electrically connected on described N gate line, in order to according to described (N+1) gate signal described N gate signal is pulled down to described low supply voltage;
Described auxiliary drop-down unit comprises:
One transistor, described transistor comprises:
One first end is electrically connected on described N gate line;
One gate terminal is in order to receive described (N+1) gate signal; With
One second end is in order to receive described low supply voltage;
One voltage regulation unit is electrically connected on described energy-storage units, is used for according to described input signal, described first frequency and described second frequency to suppress the ripple voltage of described N gate signal;
Described voltage regulation unit comprises:
One the first transistor comprises:
One first end is in order to receive described input signal;
One gate terminal is in order to receive described second frequency; With
One second end is electrically connected on described buffer cell;
One transistor seconds comprises:
One first end is electrically connected on second end of described the first transistor;
One gate terminal is in order to receive described first frequency; With
One second end is electrically connected on described N gate line; With
One the 3rd transistor comprises:
One first end is electrically connected on second end of described transistor seconds;
One gate terminal is in order to receive described second frequency; With
One second end is in order to receive described low supply voltage;
One reset cell is electrically connected on described energy-storage units, is used for according to a reset signal described drive control voltage being reset to described low supply voltage;
The reset cell of described N level shift register comprises:
One transistor, described transistor comprises:
One first end is electrically connected on described energy-storage units;
One gate terminal is in order to receive described reset signal; With
One second end is in order to receive described low supply voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910105817A CN101533623A (en) | 2009-02-26 | 2009-02-26 | Gate drive for inhibiting drift of a critical voltage |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910105817A CN101533623A (en) | 2009-02-26 | 2009-02-26 | Gate drive for inhibiting drift of a critical voltage |
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| CN101533623A true CN101533623A (en) | 2009-09-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200910105817A Pending CN101533623A (en) | 2009-02-26 | 2009-02-26 | Gate drive for inhibiting drift of a critical voltage |
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| CN107507556B (en) * | 2017-09-30 | 2020-06-12 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| WO2020019381A1 (en) * | 2018-07-26 | 2020-01-30 | 武汉华星光电技术有限公司 | Goa circuit, display panel and display device |
| US10714204B1 (en) | 2019-01-31 | 2020-07-14 | Chongqing Boe Optoelectronics Technology Co., Ltd. | Shift register unit, driving method thereof, gate driving circuit and display device |
| CN109616048A (en) * | 2019-01-31 | 2019-04-12 | 重庆京东方光电科技有限公司 | Shift register cell and driving method, gate driving circuit, display device |
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