CN103035218A - Shifting register unit and gate drive circuit and display device - Google Patents
Shifting register unit and gate drive circuit and display device Download PDFInfo
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- CN103035218A CN103035218A CN2012105461838A CN201210546183A CN103035218A CN 103035218 A CN103035218 A CN 103035218A CN 2012105461838 A CN2012105461838 A CN 2012105461838A CN 201210546183 A CN201210546183 A CN 201210546183A CN 103035218 A CN103035218 A CN 103035218A
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Abstract
An embodiment of the invention provides a shifting register unit, a gate drive circuit and a display device, and relates to the technical field of display. The number of signal lines and the number of field effect transistors can be reduced, wherein the signal lines and the field effect transistors are integrated in the shifting register unit. The shifting register unit, the gate drive circuit and the display device comprise a pull-up module, a pull-down module, a control module and a reset module. The shifting register unit, the gate drive circuit and the display device are used for achieving scanning drive.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of shift register cell, gate driver circuit and display device.
Background technology
Along with the development of display technique, people not only have harsh demand to outward appearance and the quality that shows product, and price and the practicality that shows product also had higher concern.For satisfying user's demand, the technology such as integrated scanning driving circuit or bilateral driving circuit are also just arisen at the historic moment on glass substrate, a kind of like this technology not only can make the production yield that shows product greatly improve, significantly reduce simultaneously the price of demonstration product, thereby satisfied the requirement of user to product quality and price.Wherein realization that very important technology is exactly the mass production of GOA (Gate Driveron Array, array base palte is capable to be driven) technology.Utilize the GOA technology with TFT (Thin Film Transistor, Thin Film Transistor (TFT)) the gate switch circuit is integrated on the array base palte of display panel to form the turntable driving to display panel, thereby can save the grid-driving integrated circuit part, it not only can reduce cost of products from material cost and manufacture craft two aspects, and display panel can be accomplished the design for aesthetic of both sides symmetry and narrow frame.Owing to the technique that can save Gate direction Bonding (binding), also more favourable to production capacity and Yield lmproved simultaneously.The gate switch circuit that this GOA of utilization technology is integrated on the array base palte is also referred to as GOA circuit or shift-register circuit.Existing shift register cell structure assembly a large amount of signal wire and Thin Film Transistor (TFT), so not only electric leakage is serious, cause the yield of product to descend, too much electron device also will greatly increase institute and take up space, and this not only affects the production cost that also can improve product attractive in appearance.
Summary of the invention
Embodiments of the invention provide a kind of shift register cell, gate driver circuit and display device, can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT).
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the invention provides a kind of shift register cell, comprising: upper drawing-die piece, drop-down module, control module and reseting module;
Described upper drawing-die piece connects described control module, clock signal and signal output part at the corresponding levels, and the signal that is used under the control of described control module and described clock signal described signal output part at the corresponding levels being exported draws and is high level;
Drop-down module, connect described control module, first signal input end, voltage end and described signal output part at the corresponding levels, be used under the control of described control module or described first signal input end with the signal of described signal output part output at the corresponding levels drop-down be low level;
Control module also connects described clock signal and secondary signal input end, is used for according to the signal of described clock signal and the input of described secondary signal input end described upper drawing-die piece and described drop-down module being controlled;
Reseting module connects reset signal and described voltage end, is used for according to described reset signal shift register cell at the corresponding levels being resetted.
The embodiment of the invention provides a kind of gate driver circuit on the other hand, comprises multistage aforesaid shift register cell;
Except first order shift register cell, the signal output part at the corresponding levels of all the other each shift register cells connects the first signal input end of the upper level shift register cell that is adjacent;
Except the afterbody shift register cell, the signal output part at the corresponding levels of all the other each shift register cells connects the secondary signal input end of the next stage shift register cell that is adjacent.
The embodiment of the invention provides a kind of gate driver circuit on the other hand, comprises multistage aforesaid shift register cell;
Except first order shift register cell, the signal output part at the corresponding levels of all the other each shift register cells connects the first signal input end of the upper level shift register cell adjacent with its interlacing;
Except the afterbody shift register cell, the signal output part at the corresponding levels of all the other each shift register cells connects the secondary signal input end of the next stage shift register cell adjacent with its interlacing.
The another aspect of the embodiment of the invention provides a kind of display device, comprising:
The viewing area has for a plurality of pixels that show image;
Gate driver circuit is used for sweep signal is delivered to described viewing area;
Data drive circuit is used for data-signal is delivered to described viewing area;
Described gate driver circuit is aforesaid gate driver circuit.
The shift register cell that the embodiment of the invention provides, gate driver circuit and display device, can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), thereby avoided because the situation of the undercharge that electric leakage causes, improve the yield of product, reduced the production cost of product.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of a kind of shift register cell that Fig. 1 provides for the embodiment of the invention;
The electrical block diagram of a kind of shift register cell that Fig. 2 provides for the embodiment of the invention;
Signal sequence oscillogram when Fig. 3 is shift register cell shown in Figure 2 work;
The electrical block diagram of another shift register cell that Fig. 4 provides for the embodiment of the invention;
The electrical block diagram of a kind of gate driver circuit that Fig. 5 provides for the embodiment of the invention;
Fig. 6 is the timing waveform of gate driver circuit shown in Figure 5 each signal when scanning from top to bottom;
The electrical block diagram of another gate driver circuit that Fig. 7 provides for the embodiment of the invention;
The structural representation of a kind of display device that Fig. 8 provides for the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The transistor that adopts among all embodiment of the present invention all can be thin film transistor (TFT) or field effect transistor or the identical device of other characteristics, because the transistorized source electrode that adopts here, drain electrode are symmetrical, so its source electrode, drain electrode are as broad as long.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, wherein a utmost point is called source electrode, and another utmost point is called drain electrode.In addition; transistor can be divided into N-type and P type according to transistorized characteristic differentiation; following examples all describe as inner take the N transistor; what can expect is that those skilled in the art can expect easily not making under the creative work prerequisite when adopting the P transistor npn npn to realize, therefore also in the embodiments of the invention protection domain.
The shift register cell that the embodiment of the invention provides as shown in Figure 1, comprising: upper drawing-die piece 11, drop-down module 12, control module 13 and reseting module 14.
Wherein, upper drawing-die piece 11 link control modules 13, clock signal clk and signal output part OUT1 at the corresponding levels, the signal that is used under the control of control module 13 and clock signal clk signal output part OUT1 at the corresponding levels being exported draws and is high level.
Drop-down module 12 link control modules 13, first signal input end FB, voltage end VS S and signal output part OUT1 at the corresponding levels, be used under the control of control module 13 or first signal input end FB with the signal of signal output part OUT1 output at the corresponding levels drop-down be low level.
The shift register cell that the embodiment of the invention provides, can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), thereby avoided because the situation of the undercharge that electric leakage causes, improved the yield of product, reduced the production cost of product.
Wherein, voltage end VSS can be earth terminal or low level end.
Further, as shown in Figure 2, in the shift register cell that the embodiment of the invention provides, upper drawing-die piece 11 can comprise:
The first transistor T1, its source electrode connect signal output part OUT1 at the corresponding levels, grid link control module 13, and drain electrode is connected with clock signal clk.
On draw capacitor C, it is parallel between the source electrode and grid of the first transistor T1.
Like this, when clock signal clk is high level, on draw capacitor C by discharging and recharging conducting the first transistor T1, thereby clock signal clk and signal output part OUT1 at the corresponding levels are communicated with so that the output signal of shift register cell at the corresponding levels is high level.
Drop-down module 12 can comprise:
Transistor seconds T2, its source electrode connect signal output part OUT1 at the corresponding levels, grid link control module 13, and drain electrode is connected with voltage end VSS.
The 3rd transistor T 3, its source electrode connects the source electrode of the first transistor T1, and grid connects first signal input end FB, and drain electrode is connected with voltage end VS S.
Wherein, the signal of first signal input end FB input can be the feedback signal of the signal output part OUT1 output of next stage shift register cell.So, when shift register cell at the corresponding levels is finished output, when the next stage shift register cell begins to scan, the signal of signal output part OUT 1 output of next stage shift register cell is communicated with signal output part OUT1 at the corresponding levels by the 3rd transistor T 3 with voltage VSS, so that no signal at the corresponding levels output, thereby avoided the appearance of data transmission fault.
Further, as shown in Figure 2, shift register cell can also comprise:
The 4th transistor T 4, its source electrode connects the source electrode of the first transistor T1, grid connects the grid of the first transistor T1, drain electrode connects feedback signal output terminal OUT2, and the signal of this feedback signal output terminal OUT2 output is as the signal of the secondary signal input end STV input of next stage shift register cell.
Say that the signal that is noted that shift register cell feedback signal output terminal OUT2 at the corresponding levels output will input the secondary signal input end STV of next stage shift register cell so that the next stage shift register cell begins to scan as start signal.In embodiments of the present invention, can also input the secondary signal input end STV of next stage shift register cell as start signal, with the transistorized quantity of further minimizing by the direct signal that the output terminal OUT1 of shift register cell at the corresponding levels is exported.Compare with the static output feedback signal, adopt the start signal of the structure output next stage of the 4th transistor T 4 can avoid that output exerts an influence to the corresponding levels, improve the quality of output signal; Can also avoid simultaneously shift register cell at the corresponding levels output at a time the state of Floating (floating empty) might occur, affect the start signal of next stage shift register cell, avoid the next stage shift register cell not start working.It namely is the explanation of carrying out as example take the 4th transistor T 4 output feedback signals in shift register cell as shown in Figure 2.
Same, for shift register cell at the corresponding levels, the signal that the signal of secondary signal input end STV input can be exported for the signal output part OUT1 of upper level shift register cell, or the signal that also can export for the feedback signal output terminal OUT2 of upper level shift register cell.
Further, reseting module 14 can comprise:
The 5th transistor T 5, its source electrode connect signal output part OUT at the corresponding levels, and grid connects reset signal RST, and drain electrode is connected with voltage end VSS.
In shift register cell as shown in Figure 2, control module 13 can comprise:
The 6th transistor T 6, its source electrode connects the grid of the first transistor T1, and grid all is connected with secondary signal input end STV with drain electrode.
The 7th transistor T 7, its source electrode connects the grid of the first transistor T1, and drain electrode connects voltage end VSS.
The 8th transistor T 8, its source electrode connects the grid of the 7th transistor T 7, and grid connects the grid of the first transistor T1, and drain electrode is connected with voltage end VSS.
Wherein, control module 13 can also comprise clock control submodule 131, and this clock control submodule 131 connects respectively the grid of at least one clock signal and the 7th transistor T 7.Need to prove, the dutycycle of each clock signal is identical, and when a clock signal was high level, all the other clock signals were low level.In shift register cell as shown in Figure 2, be that to input a clock signal clk be the explanation that example is carried out.
Concrete, with reference to shown in Figure 2, adopt a kind of like this control module 13 of structure, can draw high by the 6th transistor T 6 current potential of the first control node Q, drag down by the level of the 7th transistor T 7 with the first control node Q, this the first control node Q is positioned at the grid of the first transistor T1, is used for the opening and closing of control the first transistor T1; Can realize respectively drawing high and dragging down of the second control node Z current potential by clock control submodule 131 and 8 of the 8th transistor Ts, this the second control node Z connects respectively the grid of transistor seconds T2 and the 7th transistor T 7, is used for the open and close of control transistor seconds T2 and the 7th transistor T 7.
Further, in shift register cell as shown in Figure 2, clock control submodule 131 can comprise:
The 9th transistor T 9 and the tenth transistor T 10, the source electrode of the 9th transistor T 9 is connected with the drain electrode of the tenth transistor T 10, the drain electrode of the 9th transistor T 9 is connected with the source electrode of the tenth transistor T 10, the grid of the 9th transistor T 9 all is connected with the grid of the 7th transistor T 7 with drain electrode, and the grid of the tenth transistor T 10 all is connected with clock signal clk with drain electrode.
Need to prove, in embodiments of the present invention, a kind of like this as structure the 9th transistor T 9 and the tenth transistor T 10 can equivalence be the resistance that resistance is very high.The Z point is dragged down when the Q point is high level, and this moment, this combination by transistor T 9 and T10 can make the electric current that flows through transistor T 9 and T10 very little; When the Q point was electronegative potential, it was noble potential that clock signal clk makes the Z point by transistor T 9 and T10, thereby opens transistor T 2 and T7, makes output signal at the corresponding levels and Q point be electronegative potential.Adopt a kind of like this structure, can avoid when the clock signal be high level, and the 8th transistor T 8 is when opening, clock signal clk is electrically connected with the direct of voltage end VSS, has avoided the data transfer mistake.
In shift register cell as shown in Figure 2, comprise 10 N-type transistors, the external signal that drives a kind of like this shift register cell can be as shown in Figure 3, wherein, CLKn-1 is for driving the clock signal of upper level shift register cell, and CLKn is for driving the clock signal of shift register cell at the corresponding levels, and CLKn+1 is for driving the clock signal of next stage shift register cell, OUTn is output signal at the corresponding levels, and Q, Z then represent respectively the current potential of the corresponding control of shift register cell at the corresponding levels node.When clock signal CLKn-1 is high level, upper level shift register cell output signal is noble potential, be transferred to the drain and gate of the transistor T 6 of shift register cell at the corresponding levels by the transistor T 4 of upper level shift register cell, transistor T 1 is opened, control node Q this moment is noble potential, transistor T 1 is opened, thereby simultaneously transistor T 8 opens that to make control node Z be that electronegative potential is closed transistor T 7; When the noble potential of clock signal CLKn arrived transistor T 1, the signal OUTn of output terminal output was noble potential, and transmit start signal by transistor T 4 to the next stage shift register cell this moment; The signal OUTn of the simultaneously output terminal of this shift register cell output transfers to the transistor T 3 of upper level shift register cell, and T3 is opened, and is electronegative potential (VSS) thereby make an output signal; So repeat to transmit until last shift register cell is waited for the arrival of next start signal.Shift register cell be all electronegative potential up and down the time, if CLKn is noble potential, then can to make control node Z by transistor T 7 and T10 be noble potential to CLKn, thereby open transistor T 2 and transistor T 7, make Q point and output signal OUTn remain on electronegative potential, prevent data transmission fault.
Further, when comprising four clock signals, as shown in Figure 4, clock control submodule 131 also comprises:
The 9th transistor T 9 and the tenth transistor T 10, the source electrode of the 9th transistor T 9 is connected with the drain electrode of the tenth transistor T 10, the drain electrode of the 9th transistor T 9 is connected with the source electrode of the tenth transistor T 10, the grid of the 9th transistor T 9 all is connected with the grid of the 7th transistor T 7 with drain electrode, and the grid of the tenth transistor T 10 all is connected with the first clock signal clk 1 with drain electrode.
The 11 transistor T 11 and the tenth two-transistor T12, the source electrode of the 11 transistor T 11 is connected with the drain electrode of the tenth two-transistor T12, the drain electrode of the 11 transistor T 11 is connected with the source electrode of the tenth two-transistor T12, the grid of the 11 transistor T 11 all is connected with the grid of the 7th transistor T 7 with drain electrode, and the grid of the tenth two-transistor T12 all is connected with second clock signal CLK2 with drain electrode.
The 13 transistor T 13 and the 14 transistor T 14, the source electrode of the 13 transistor T 13 is connected with the drain electrode of the 14 transistor T 14, the drain electrode of the 13 transistor T 13 is connected with the source electrode of the 14 transistor T 14, the grid of the 13 transistor T 13 all is connected with the grid of the 7th transistor T 7 with drain electrode, and the grid of the 14 transistor T 14 all is connected with the 3rd clock signal clk 3 with drain electrode;
The 15 transistor T 15 and the 16 transistor T 16, the source electrode of the 15 transistor T 15 is connected with the drain electrode of the 16 transistor T 16, the drain electrode of the 15 transistor T 15 is connected with the source electrode of the 16 transistor T 16, the grid of the 15 transistor T 15 all is connected with the grid of the 7th transistor T 7 with drain electrode, and the grid of the 16 transistor T 16 all is connected with the 4th clock signal clk 4 with drain electrode.
Need to prove, every group of above-mentioned transistorized unitized construction can equivalence be the resistance that resistance is very high all.Adopt a kind of like this structure, can avoid when the clock signal be high level, and the 8th transistor T 8 is when opening, arbitrary clock signal is electrically connected with the direct of voltage end VSS, has avoided the data transfer mistake.In addition, when comprising a plurality of clock signal, it is the be expert at clock signal of correspondence of shift register cell at the corresponding levels that being used for of input the first transistor T1 drawn the clock signal of output terminal output signal at the corresponding levels, for example, when external timing signal comprises CLK1, CLK2, when CLK3 and CLK4, the clock signal of then inputting the first row shift register cell T1 is CLK1, the clock signal of inputting the second line shift register unit T1 is CLK2, by that analogy, when the clock signal of clock control submodule 131 of each line shift register of input is 4 groups of whole clock signals, a kind of like this driving signal sequence of shift register cell equally can be with reference to shown in Figure 3.Adopt a kind of like this clock control submodule 131, the current potential of control node Z is subjected to respectively the control of many group clock signals, has avoided the appearance of vacant state, has improved the stability of circuit.
Certainly, below also only be to comprise that four clock signals are the explanation that example is carried out, but not the restriction that the present invention is done, clock signal can adopt six clock signals, eight clock signals or more equally according to actual needs, with the toggle frequency of reduction clock signal, thus the power consumption of reduction power supply chip.
The shift register cell that the embodiment of the invention provides, can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), thereby avoided because the situation of the undercharge that electric leakage causes, improved the yield of product, reduced the production cost of product.
A kind of gate driver circuit that the embodiment of the invention provides as shown in Figure 5, comprises multistage aforesaid shift register cell.Wherein, the line scan signals OUT at the corresponding levels of the output terminal of every one-level shift register cell SR output; Each shift register cell has a clock signal clk input, in circuit shown in Figure 5, be the explanation of carrying out as example take four clock signals, the dutycycle of each clock signal is identical, when a clock signal was high level, all the other clock signals were low level.
Except first order shift register cell SR1, the signal output part at the corresponding levels of all the other each shift register cells connects the first signal input end FB of the upper level shift register cell that is adjacent.
Except afterbody shift register cell SRn, the signal output part at the corresponding levels of all the other each shift register cells connects the secondary signal input end STV of the next stage shift register cell that is adjacent.
In embodiments of the present invention, the signal of first signal input end FB input can be the feedback signal FB of the signal output part OUT output of next stage shift register cell, and the signal of shift register cell signal output part OUT output at the corresponding levels will be inputted the secondary signal input end STV of next stage shift register cell so that the next stage shift register cell begins to scan as start signal.The secondary signal input end STV of first order shift register cell SR1 can the incoming frame start signal; The secondary signal input end FB of afterbody shift register cell SRn is without input.
The gate driver circuit that the embodiment of the invention provides, can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), thereby avoided because the situation of the undercharge that electric leakage causes, improved the yield of product, reduced the production cost of product.
Concrete, the external signal timing waveform of gate driver circuit shown in Figure 5 can be as shown in Figure 6.Wherein, gate driver circuit is by a frame start signal STV, four clock signal clks 1, CLK2, CLK3, CLK4, and a reset signal RST and a low voltage signal VSS form.As shown in Figure 6, frame start signal STV begins to provide enabling signal to first order shift register cell SR1 at every frame, when the noble potential of clock signal CKL1 arrived, shift register cell SR1 exported noble potential, provided enabling signal to shift register cell SR2 simultaneously; When clock signal CKL2 noble potential arrived, shift register cell SR2 exported noble potential, enabling signal is provided and provides feedback signal to shift register cell SR1 to shift register cell SR3 simultaneously, made shift register cell SR1 be output as electronegative potential; So repeat until be scanned up to the last item data line.When shift register cell SRn output noble potential, can transmit enabling signal to shift register cell SRn+1, clock signal clk 1 arrives and makes shift register cell SRn+1 output noble potential simultaneously, this moment, shift register cell SRn+1 provided feedback signal to shift register cell SRn, made shift register cell SRn be output as electronegative potential.When white space, reset signal RST is high level, makes the output of all shift register cells be electronegative potential, thereby prevents that erroneous transmissions or crosstalk phenomenon from appearring in data.
The another kind of gate driver circuit that the embodiment of the invention provides as shown in Figure 7, comprises multistage aforesaid shift register cell.Wherein, the line scan signals OUT at the corresponding levels of the output terminal of every one-level shift register cell SR output; Each shift register cell has a clock signal clk input, in circuit shown in Figure 7, be the explanation of carrying out as example take six clock signals, the dutycycle of each clock signal is identical, when a clock signal was high level, all the other clock signals were low level.
Except first order shift register cell SR1, the signal output part at the corresponding levels of all the other each shift register cells connects the first signal input end FB of the upper level shift register cell adjacent with its interlacing.
Except afterbody shift register cell SRn+ 2, the signal output part at the corresponding levels of all the other each shift register cells connects the secondary signal input end STV of the next stage shift register cell adjacent with its interlacing.
Wherein, the output signal of n+1 level shift register cell SRn+1 is used to n-1 level shift register cell SRn-1 that feedback signal is provided, and makes shift register cell SRn-1 be output as electronegative potential; The output signal of n+2 level shift register cell SRn+2 is used to n level shift register cell SRn that feedback signal is provided, and makes shift register cell SRn be output as electronegative potential.
The gate driver circuit that the embodiment of the invention provides, can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), thereby avoided because the situation of the undercharge that electric leakage causes, improved the yield of product, reduced the production cost of product.
Gate driver circuit and previous embodiment that the embodiment of the invention provides are similar, and the external signal sequential of driving circuit equally can be with reference to previous embodiment.Its difference is, the transmission mode that the signal transmission of shift register cell adopts odd-numbered line to transmit to the even number line direction to the transmission of odd-numbered line direction, even number line.Can further improve like this stability of circuit, improve the quality of product.
The embodiment of the invention also provides a kind of display device, as shown in Figure 8, such as being display panel, comprising:
Wherein, display device can also be liquid crystal indicator, el display device, Electronic Paper, mobile phone, TV, digital album (digital photo frame) etc. display device.
The display device that the embodiment of the invention provides, comprise shift register cell, can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), thereby avoided because the situation of the undercharge that electric leakage causes, improve the yield of product, reduced the production cost of product.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (11)
1. a shift register cell is characterized in that, comprising: upper drawing-die piece, drop-down module, control module and reseting module;
Described upper drawing-die piece connects described control module, clock signal and signal output part at the corresponding levels, and the signal that is used under the control of described control module and described clock signal described signal output part at the corresponding levels being exported draws and is high level;
Drop-down module, connect described control module, first signal input end, voltage end and described signal output part at the corresponding levels, be used under the control of described control module or described first signal input end with the signal of described signal output part output at the corresponding levels drop-down be low level;
Control module also connects described clock signal and secondary signal input end, is used for according to the signal of described clock signal and the input of described secondary signal input end described upper drawing-die piece and described drop-down module being controlled;
Reseting module connects reset signal and described voltage end, is used for according to described reset signal shift register cell at the corresponding levels being resetted.
2. shift register cell according to claim 1 is characterized in that, described upper drawing-die piece comprises:
The first transistor, its source electrode connect described signal output part at the corresponding levels, and grid connects described control module, and drain electrode is connected with described clock signal;
On draw electric capacity, it is parallel between the source electrode and grid of described the first transistor;
Described drop-down module comprises:
Transistor seconds, its source electrode connect described signal output part at the corresponding levels, and grid connects described control module, and drain electrode is connected with described voltage end;
The 3rd transistor, its source electrode connects the source electrode of described the first transistor, and grid connects described first signal input end, and drain electrode is connected with described voltage end.
3. shift register cell according to claim 1 is characterized in that, described shift register cell also comprises:
The 4th transistor, its source electrode connects the source electrode of described the first transistor, grid connects the grid of described the first transistor, and drain electrode connects the feedback signal output terminal, and the signal of described feedback signal output terminal output is as the signal of the secondary signal input end input of next stage shift register cell.
4. shift register cell according to claim 3 is characterized in that,
The signal of described first signal input end input is the signal of the signal output part output of next stage shift register cell;
The signal of described secondary signal input end input is the signal of the signal output part output of upper level shift register cell, or is the signal of the feedback signal output terminal output of upper level shift register cell.
5. shift register cell according to claim 1 is characterized in that, described reseting module comprises:
The 5th transistor, its source electrode connect described signal output part at the corresponding levels, and grid connects described reset signal, and drain electrode is connected with described voltage end.
6. according to claim 1 to 5 arbitrary described shift register cells, it is characterized in that, described control module comprises:
The 6th transistor, its source electrode connects the grid of described the first transistor, and grid all is connected with the secondary signal input end with drain electrode;
The 7th transistor, its source electrode connects the grid of described the first transistor, and drain electrode connects described voltage end;
The 8th transistor, its source electrode connect the described the 7th transistorized grid, and grid connects the grid of described the first transistor, and drain electrode is connected with described voltage end;
Described control module also comprises the clock control submodule, and described clock control submodule connects respectively at least one clock signal and the described the 7th transistorized grid;
Wherein, the dutycycle of each described clock signal is identical, and when a clock signal was high level, all the other clock signals were low level.
7. shift register cell according to claim 6 is characterized in that, when only comprising a clock signal, described clock control submodule comprises:
The 9th transistor and the tenth transistor, the described the 9th transistorized source electrode is connected with the described the tenth transistorized drain electrode, the described the 9th transistorized drain electrode is connected with the described the tenth transistorized source electrode, the described the 9th transistorized grid all is connected with the described the 7th transistorized grid with drain electrode, and the described the tenth transistorized grid all is connected with clock signal with drain electrode.
8. shift register cell according to claim 6 is characterized in that, when comprising four clock signals, described clock control submodule also comprises:
The 9th transistor and the tenth transistor, the described the 9th transistorized source electrode is connected with the described the tenth transistorized drain electrode, the described the 9th transistorized drain electrode is connected with the described the tenth transistorized source electrode, the described the 9th transistorized grid all is connected with the described the 7th transistorized grid with drain electrode, and the described the tenth transistorized grid all is connected with the first clock signal with drain electrode;
The 11 transistor and the tenth two-transistor, the described the 11 transistorized source electrode is connected with the drain electrode of described the tenth two-transistor, the described the 11 transistorized drain electrode is connected with the source electrode of described the tenth two-transistor, the described the 11 transistorized grid all is connected with the described the 7th transistorized grid with drain electrode, and the grid of described the tenth two-transistor all is connected with the second clock signal with drain electrode;
The 13 transistor and the 14 transistor, the described the 13 transistorized source electrode is connected with the described the 14 transistorized drain electrode, the described the 13 transistorized drain electrode is connected with the described the 14 transistorized source electrode, the described the 13 transistorized grid all is connected with the described the 7th transistorized grid with drain electrode, and the described the 14 transistorized grid all is connected with the 3rd clock signal with drain electrode;
The 15 transistor and the 16 transistor, the described the 15 transistorized source electrode is connected with the described the 16 transistorized drain electrode, the described the 15 transistorized drain electrode is connected with the described the 16 transistorized source electrode, the described the 15 transistorized grid all is connected with the described the 7th transistorized grid with drain electrode, and the described the 16 transistorized grid all is connected with the 4th clock signal with drain electrode.
9. a gate driver circuit is characterized in that, comprises multistage such as the arbitrary described shift register cell of claim 1 to 8;
Except first order shift register cell, the signal output part at the corresponding levels of all the other each shift register cells or feedback signal output terminal connect the first signal input end of the upper level shift register cell that is adjacent;
Except the afterbody shift register cell, the signal output part at the corresponding levels of all the other each shift register cells or feedback signal output terminal connect the secondary signal input end of the next stage shift register cell that is adjacent.
10. a gate driver circuit is characterized in that, comprises multistage such as the arbitrary described shift register cell of claim 1 to 8;
Except first order shift register cell, the signal output part at the corresponding levels of all the other each shift register cells or feedback signal output terminal connect the first signal input end of the upper level shift register cell adjacent with its interlacing;
Except the afterbody shift register cell, the signal output part at the corresponding levels of all the other each shift register cells or feedback signal output terminal connect the secondary signal input end of the next stage shift register cell adjacent with its interlacing.
11. a display device comprises:
The viewing area has for a plurality of pixels that show image;
Gate driver circuit is used for sweep signal is delivered to described viewing area;
Data drive circuit is used for data-signal is delivered to described viewing area;
It is characterized in that, described gate driver circuit is such as claim 9 or 10 described gate driver circuits.
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