CN102903323B - Shifting register unit, gate drive circuit and display device - Google Patents
Shifting register unit, gate drive circuit and display device Download PDFInfo
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- CN102903323B CN102903323B CN201210383062.6A CN201210383062A CN102903323B CN 102903323 B CN102903323 B CN 102903323B CN 201210383062 A CN201210383062 A CN 201210383062A CN 102903323 B CN102903323 B CN 102903323B
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Abstract
The invention provides a shifting register unit, a gate drive circuit and a display device, and relates to the field of production of displays, so that number of signal lines and film field effect transistors, which are integrated in the shifting register unit, can be reduced, and a space is saved, so that the product cost is reduced. The shifting register unit comprises a pre-charging module, a signal output module, an output level pull-down module, a first knot voltage control module and a second knot voltage control module.
Description
Technical field
The present invention relates to liquid crystal display and manufacture field, particularly relate to shift register cell, gate driver circuit and display device.
Background technology
The development of display in the last few years presents high integration, the development trend of low cost.Wherein very important technology is exactly the realization of the technology mass production of array base palte row cutting (Gate Driver on Array is called for short GOA).GOA technology is utilized to be integrated in by gate switch circuit on the array base palte of display panel to form the turntable driving to display panel, thus grid-driving integrated circuit part can be saved, it not only can reduce cost of products from material cost and manufacture craft two aspect, and display panel can accomplish the design for aesthetic of both sides symmetry and narrow frame.Simultaneously due to the technique in Gate direction Bonding (binding) can be saved, to production capacity and Yield lmproved also more favourable.This gate switch circuit of GOA Integration ofTechnology on array base palte that utilize is also referred to as GOA circuit or shift-register circuit.
Shift-register circuit comprises several shift register cells, the corresponding grid line of each shift register cell, and except first shift register cell and last shift register cell, the output terminal of all the other each shift register cells connects the signal input part of the next shift register cell be adjacent; The a large amount of signal wire of existing shift register cell structure assembly and Thin Film Transistor (TFT) (Thin Film Transistor is called for short TFT), make circuit take up space and considerably increase cost of products.
Summary of the invention
Embodiments of the invention provide a kind of shift register cell, gate driver circuit and display device, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
For achieving the above object, embodiments of the invention adopt following technical scheme:
First aspect, the embodiment of the present invention provides a kind of shift register cell, comprise: the drop-down module of pre-charge module, signal output module, output level, the first node voltage control module and the second node voltage control module, first node is the tie point of described pre-charge module and signal output module, and the second node is the tie point of described first node voltage control module and the second node voltage control module;
Wherein, described pre-charge module, connects the first signal input part and the first node, under the control of described first signal input part to described signal output module precharge;
Described signal output module, connection signal output terminal, described first node and the first clock signal, for connecting described first clock signal and described signal output part under the control of described first node voltage;
The drop-down module of described output level, connects described signal output part, second clock signal and the first voltage end, for connecting described signal output part and described first voltage end under the control of described second clock signal;
Described first node voltage control module, connects second clock signal, described first voltage end, described first node and the second node, for connecting described first node and described first voltage end under the control of described second clock signal;
Described second node voltage control module, connects described first signal input part, described signal output part, described first voltage end and described second node, connects described second node and described first voltage end for controlling.
In the implementation that the first is possible, according to first aspect,
Described pre-charge module comprises:
The first transistor, the grid of described the first transistor is connected described first signal input part with source electrode, the drain electrode of described the first transistor connects described first node;
Described signal output module comprises:
Transistor seconds, the grid of described transistor seconds connects described first node, and the source electrode of described transistor seconds connects described first clock signal, and the drain electrode of described transistor seconds connects described signal output part;
First electric capacity, a pole of described first electric capacity connects the grid of described transistor seconds, and another pole of described first electric capacity connects the drain electrode of described transistor seconds;
The drop-down module of described output level comprises:
Third transistor, the grid of described third transistor connects described second clock signal, and the source electrode of described third transistor connects described signal output part, and the drain electrode of described third transistor connects described first voltage end;
Described first node voltage control module comprises:
4th transistor, the grid of described 4th transistor is connected described second clock signal with source electrode, the drain electrode of described 4th transistor connects described second node;
5th transistor, the grid of described 5th transistor connects described second node, and the source electrode of described 5th transistor connects described first node, and the drain electrode of described 5th transistor connects described first voltage end;
Second node voltage control module comprises:
6th transistor, the grid of described 6th transistor connects described first signal input part, and the source electrode of described 6th transistor connects described second node, and the drain electrode of described 6th transistor connects described first voltage end;
7th transistor, the grid of described 7th transistor connects described signal output part, and the source electrode of described 7th transistor connects described second node, and the drain electrode of described 7th transistor connects described first voltage end.
In the implementation that the second is possible, according to first aspect,
Described pre-charge module also connects secondary signal input end, the second voltage end and tertiary voltage end, when being low level for being high level tertiary voltage end at described second voltage end, to described signal output module precharge under the control of described first signal input part, under the control of described secondary signal input end, connect described first node and described tertiary voltage end;
Or described second voltage end is low level tertiary voltage end when being high level, to described signal output module precharge under the control of described secondary signal input end, under the control of described first signal input part, connect described first node and described second voltage end;
The drop-down module of described output level also connects the 3rd signal input part and the 4th signal input part, for connecting described signal output part and described first voltage end under the control of the 3rd signal input part or the 4th signal input part;
Described second node voltage control module also connects described secondary signal input end, for connecting described second node and described first voltage end under the control of described secondary signal input end.
In the implementation that the third is possible, the implementation possible according to the second,
Described pre-charge module comprises:
The first transistor, the grid of described the first transistor connects described first signal input part, and the source electrode of described the first transistor connects described second voltage end, and the drain electrode of described the first transistor connects described first node;
8th transistor, the grid of described 8th transistor connects described secondary signal input end, and the source electrode of described 8th transistor connects described first node, and the drain electrode of described 8th transistor connects described tertiary voltage end;
Described signal output module comprises:
Transistor seconds, the grid of described transistor seconds connects described first node, and the source electrode of described transistor seconds connects described first clock signal, and the drain electrode of described transistor seconds connects described signal output part;
First electric capacity, a pole of described first electric capacity connects the grid of described transistor seconds, and another pole of described first electric capacity connects the drain electrode of described transistor seconds;
The drop-down module of output level comprises:
Third transistor, the grid of described third transistor connects described second clock signal, and the source electrode of described third transistor connects described signal output part, and the drain electrode of described third transistor connects described first voltage end;
9th transistor, the grid of described 9th transistor connects described 3rd signal input part, and the source electrode of described 9th transistor connects described signal output part, and the drain electrode of described 9th transistor connects described first voltage end;
Tenth transistor, the grid of described tenth transistor connects described 4th signal input part, and the source electrode of described tenth transistor connects described signal output part, and the drain electrode of described tenth transistor connects described first voltage end;
First node voltage control module comprises:
4th transistor, the grid of described 4th transistor is connected described second clock signal with source electrode, the drain electrode of described 4th transistor connects described second node;
5th transistor, the grid of described 5th transistor connects described second node, and the source electrode of described 5th transistor connects described first node, and the drain electrode of described 5th transistor connects described first voltage end;
Second node voltage control module comprises:
6th transistor, the grid of described 6th transistor connects described first signal input part, and the source electrode of described 6th transistor connects described second node, and the drain electrode of described 6th transistor connects described first voltage end;
7th transistor, the grid of described 7th transistor connects described signal output part, and the source electrode of described 7th transistor connects described second node, and the drain electrode of described 7th transistor connects described first voltage end.
11 transistor, the grid of described 11 transistor connects described secondary signal input end, and the source electrode of described 11 transistor connects described second node, and the drain electrode of described 11 transistor connects described first voltage end.
Wherein, above-mentioned first voltage end is earth terminal.
Second aspect, a kind of gate driver circuit is provided, comprise the multiple shift register cell as described in the first possible implementation of first aspect or first aspect of series connection, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input part of the next shift register cell be adjacent.
The third aspect, a kind of gate driver circuit is provided, comprise multiple the first the possible implementation as first aspect of series connection or the possible shift register cell as described in implementation of the second, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input part of the next shift register cell be adjacent, the signal output part of each shift register cell also connects the secondary signal input end of the upper shift register cell be adjacent, except most the first two shift register cell with except latter two shift register cell, the signal output part of all the other each shift register cells also connect with its on the 3rd signal input part of adjacent second shift register cell and the 4th signal input part of second shift register cell of lower neighbour that is adjacent.
Fourth aspect, the embodiment of the present invention provides a kind of display device, comprising:
Viewing area, has the multiple pixels for showing image;
Gate driver circuit, for delivering to described viewing area by sweep signal;
Data drive circuit, for delivering to described viewing area by data-signal;
It is characterized in that, described gate driver circuit is above-mentioned arbitrary gate driver circuit.
The shift register cell that the embodiment of the present invention provides, gate driver circuit and display device, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The simple scanning shift register cell structural representation that Fig. 1 provides for the embodiment of the present invention;
The simple scanning shift register cell electrical block diagram that Fig. 2 provides for the embodiment of the present invention;
The bilateral scanning shift register cell structural representation that Fig. 3 provides for the embodiment of the present invention;
The bilateral scanning shift register cell electrical block diagram that Fig. 4 provides for the embodiment of the present invention;
Simple scanning shift register cell first clock signal that Fig. 5 provides for the embodiment of the present invention, second clock signal, PU voltage node and signal output waveform schematic diagram;
Bilateral scanning shift register cell first clock signal that Fig. 6 provides for the embodiment of the present invention, second clock signal, PU voltage node and signal output waveform schematic diagram;
The grid electrode drive circuit structure formula schematic diagram of the simple scanning that Fig. 7 provides for the embodiment of the present invention;
The grid electrode drive circuit structure formula schematic diagram of the bilateral scanning that Fig. 8 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The transistor adopted in all embodiments of the present invention can be all thin film transistor (TFT) or field effect transistor or the identical device of other characteristics, because the source electrode of the transistor that adopts here, drain electrode are symmetrical, so its source electrode, drain electrode are as broad as long.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, wherein will be called source electrode in a pole, another pole is called drain electrode.Specify that the upside of transistor is source electrode, intermediate ends is grid, lower side is drain electrode by the form in accompanying drawing.In addition; distinguish transistor can be divided into N-type and P type according to the characteristic of transistor; following examples are all inner being described with N transistor; it is conceivable that be that those skilled in the art can expect, therefore also in embodiments of the invention protection domain easily not making under creative work prerequisite when adopting P-type crystal pipe to realize.
The structural representation of the individual event scan shift deposit unit that Fig. 1 provides for the embodiment of the present invention, comprise: pre-charge module 11, signal output module 12, output level drop-down module 13, first node voltage control module 14 and the second node voltage control module 15, first node PU is the tie point of pre-charge module 11 and signal output module 12, and the second node PD is the tie point of the first node voltage control module 14 and the second node voltage control module 15; And the first signal input part of the shift register in Fig. 1 is INPUT1, signal output part is OUTPUT, and the first clock signal is CLK, and second clock signal is CLKB, and the first node is PU point, and the second node is PD point, and the first voltage end is V1;
Specifically describe the relation between its each parts below:
Pre-charge module 11, connects the first signal input part INPUT1 and the first node PU point, under the control of the first signal input part INPUT1 to signal output module 12 precharge;
Signal output module 12, connection signal output terminal OUTPUT, the first node PU point and the first clock signal clk, for connecting the first clock signal clk and signal output part OUTPUT under the control of the first node PU, export high level signal when the first clock signal clk is high level;
The drop-down module 13 of output level, connection signal output terminal OUTPUT, second clock signal CLKB and the first voltage end V1, for connection signal output terminal OUTPUT under the control of second clock signal CLKB and the first voltage end V1;
First node voltage control module 14, connects second clock signal CLKB, the first voltage end V1, described first node PU point and the second node PD point, for connecting first node PU and the first voltage end V1 under the control of second clock signal;
Second node voltage control module 15, connects the first signal input part INPUT1, signal output part OUTPUT, the first voltage end V1 and the second node PD point, for controlling connection second node PD and the first voltage end V1.
The shift register cell that the embodiment of the present invention provides, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduces cost of products.
Optionally, the electrical block diagram of a kind of shifting deposit unit that Fig. 2 provides for the embodiment of the present invention, be applied to individual event scanning, comprise: pre-charge module 11, signal output module 12, the drop-down module 13 of output level, first node voltage control module 14, second node voltage control module 15, following examples are all be described for N-type transistor, namely in following embodiment, the characteristic of each transistor is the conducting when grid input high level, end when grid input low level, because the characteristic first voltage end V1 of N-type pipe is for adopting low level, in Fig. 2, the first voltage end V1 is directly described to connect earth terminal VSS, the annexation of the electricity device comprised in concrete each module is as follows:
Pre-charge module 11 comprises: the first transistor T1, and the grid of this first transistor T1 is connected the first signal input part INPUT1 with source electrode, and the drain electrode of this first transistor T1 connects the first node PU point;
When first signal input part INPUT1 has high level to input, the first transistor T1 is conducting state, carries out precharge to the signal output module precharge be connected with the first node PU point, and the voltage of the first node PU is raised;
Signal output module 12 comprises: transistor seconds T2, and the grid of this transistor seconds T2 connects the first node PU point, and the source electrode of this transistor seconds T2 connects the first clock signal clk, the drain electrode connection signal output terminal OUTPUT of this transistor seconds T2;
One pole of the first electric capacity C1, this first electric capacity C1 connects the grid of transistor seconds T2, and another pole of this first electric capacity C1 connects the drain electrode of transistor seconds T2;
Wherein, after pre-charge module 11, when the first clock signal clk is high level, the first electric capacity C1 electric discharge conducting transistor seconds T2, is communicated with the first clock signal clk with signal output part OUTPUT, makes the output signal of shift register cell be high level;
The drop-down module 13 of output level comprises: the grid of third transistor T3, this third transistor T3 connects second clock signal CLKB, and the drain electrode of the source electrode connection signal output terminal OUTPUT of this third transistor T3, this third transistor T3 connects earth terminal VSS;
Wherein, after shift register cell exports high level signal, first clock signal clk becomes low level, second clock signal CLKB becomes high level, by second clock signal CLKB control T3 conducting, connection signal output terminal OUTPUT and earth terminal VSS, the output signal of drop-down shift register cell at the corresponding levels;
First node voltage control module 14 comprises: the 4th transistor T4, and the grid of the 4th transistor T4 is connected second clock signal CLKB with source electrode, and the drain electrode of the 4th transistor T4 connects the second node PD point;
The grid of the 5th transistor T5, the 5th transistor T5 connects the second node PD point, and the source electrode of the 5th transistor T5 connects the first node PU point, and the drain electrode of the 5th transistor T5 connects earth terminal VSS;
Wherein, after shift register cell exports high level signal, the first clock signal clk becomes low level, when second clock signal CLKB becomes high level, by second clock signal CLKB control T4 and T5 conducting, connect the first node PU and earth terminal VSS, drop-down PU voltage node voltage;
Second node voltage control module 15 comprises: the 6th transistor T6, and the grid of the 6th transistor T6 connects the first signal input part INPUT1, and the source electrode of the 6th transistor T6 connects the second node PD point, and the drain electrode of the 6th transistor T6 connects earth terminal VSS;
The source electrode of the grid connection signal output terminal OUTPUT of the 7th transistor T7, the 7th transistor T7, the 7th transistor T7 connects the second node PD point, and the drain electrode of the 7th transistor T7 connects earth terminal VSS;
Wherein, in order to keep PU voltage node voltage not drop-down at high level, when PU voltage node voltage should be made to be high level, PD voltage node voltage is low level, and the voltage of PU point must keep high level in the output stage of pre-charging stage and shift register cell at the corresponding levels, therefore T6 conducting when the first signal input part input high level, control connection second node PD and earth terminal VSS, holding PD voltage node voltage is low level; T7 conducting when shift register cell signal output part at the corresponding levels exports high level, controls connection second node PD and earth terminal VSS, keeps PD voltage node voltage to be low level.
Be described for N-type transistor in the accompanying drawings in above embodiment, characteristic due to N-type transistor is the conducting of grid high level, grid low level is ended, need the first clock signal clk and second clock signal CLKB to provide corresponding level with this and could realize above-mentioned circuit function, in addition due to the conducting of N-type transistor high level characteristic therefore the first voltage end V1 for adopt low level, directly to connect earth terminal VSS in figure, certainly just adopt during P-type crystal pipe and need the shape of corresponding adjustment first clock signal and second clock signal and the first voltage end V1 is connected to a high level, to ensure the normal work of circuit, concrete principle repeats no more for those skilled in the art are understandable herein.
The shift register cell that the embodiment of the present invention provides, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduces cost of products.
Composition graphs 2 and Fig. 5, time-state method (wherein Fig. 5 is the time-state method of CLK, CLKB, PU point and OUTPUT each signal end signal) the individual event scan shift register unit that the embodiment of the present invention provides of the individual event scan shift register unit that wherein Fig. 2 provides the circuit diagram of individual event scan shift register unit, Fig. 5 provides and the function of shift-register circuit specific implementation as follows:
In the t1 time period, first signal input part INPUT1 is high level, first clock signal clk is low level, second clock signal CLKB is high level, T1 conducting is charged to C1, and conducting T2 makes T2 grid be high level, T6 conducting drags down PD point voltage thus keeps T5 to be cut-off state, thus remains on PU point in cycle t1 and be in high level; The t2 time period after t1, first clock signal clk is high level, second clock signal CLKB is low level, C1 electric discharge keeps T2 to be conducting state, then signal output part OUTPUT is high level, T7 conducting drags down PD point voltage thus keeps T5 to be cut-off state, thus remains on PU point in cycle t2 and be in high level; The t3 time period after t2, the first clock signal clk is low level, and second clock signal CLKB is high level, conducting T3, T4 and T5, and PD point is noble potential, makes signal output part OUTPUT be low level, and PU point is also low level; Within the shift register non-working time, the first clock signal clk is high level, and second clock signal CLKB is low level, and without turn-on transistor, signal output part OUTPUT is low level.
The shift register cell that the embodiment of the present invention provides, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduces cost of products.
Optionally, be illustrated in figure 3 the structural representation of a kind of bilateral scanning shift register cell that embodiments of the invention provide, comprise: pre-charge module 31, signal output module 32, the drop-down module 33 of output level, first node voltage control module 34, second node voltage control module 35 and the first signal input part of shift register in Fig. 3 is INPUT1, secondary signal input end INPUT2, 3rd signal input part INPUT3, 4th signal input part INPUT4, signal output part is OUTPUT, first clock signal is CLK, second clock signal is CLKB, first node is PU point, second node is PD point, first voltage end is V1, second voltage end V2, tertiary voltage end V3, wherein during forward scan, the second voltage end V2 is input high level, tertiary voltage end V3 input low level, or the second voltage end V2 is input low level during reverse scan, tertiary voltage end V3 input high level, here the first voltage end V1 is a low level, in addition concrete restriction is not done to forward scan or reverse scan, direction just in order to distinguish scanning is different, annexation between its concrete each parts is:
Pre-charge module 31, connects the first signal input part INPUT1, the first node PU point, secondary signal input end INPUT2, the second voltage end V2 and tertiary voltage end V3.Wherein, the forward surface sweeping stage, second voltage end V2 is high level tertiary voltage end V3 is low level, pre-charge module 31 for when the first signal input part INPUT1 has high level to input to the first node PU point precharge, connect the first node PU and tertiary voltage end V3 when secondary signal input end INPUT2 has high level to input, drag down the voltage of the first node PU point; The reverse scan stage, second voltage end V2 is low level tertiary voltage end V3 is high level, pre-charge module 31 for when secondary signal input end INPUT2 has high level to input to the first node PU point precharge, connect the first node PU and the second voltage end V2 when the first signal input part INPUT1 has high level to input, drag down the first node PU point voltage.
Signal output module 32, connection signal output terminal OUTPUT, the first node PU point and the first clock signal clk.Signal output module 32, for connecting the first clock signal clk and signal output part OUTPUT under the control of the first node PU, exports high level signal when the first clock signal clk is high level.
The drop-down module 33 of output level, connection signal output terminal OUTPUT, second clock signal CLKB, the first voltage end V1, the 3rd signal input part INPUT3 and the 4th signal input part INPUT4, the drop-down module 33 of output level for connection signal output terminal OUTPUT under the control of second clock signal CLKB and the first voltage end V1, the level of degrade signal output terminal OUTPUT; During this external forward scan, the drop-down module 33 of output level is for connection signal output terminal OUTPUT and the first voltage end V1, the i.e. level of degrade signal output terminal OUTPUT when the voltage of the 3rd signal input part INPUT3 is high level under controlling at the 3rd signal input part INPUT3; Connection signal output terminal OUTPUT and the first voltage end V1 under the 4th signal input part INPUT4 controls is used for when reverse scan, namely at the 3rd signal input part INPUT3, the level of degrade signal output terminal OUTPUT when namely the voltage of the 4th signal input part INPUT4 is high level.
First node voltage control module 34, connects second clock signal CLKB, earth terminal VSS, the first node PU point and the second node PD point.First node voltage control module 34 for connecting the first node PU and the first voltage end V1 under the control of described second clock signal CLKB, namely after shift register cell exports high level signal, first clock signal clk becomes low level, when second clock signal CLKB becomes high level, the voltage of drop-down first node PU point.
Second node voltage control module 35, connects the first signal input part INPUT1, signal output part OUTPUT, the first voltage end V1, the second node PD point and secondary signal input end INPUT2.Second node voltage control module 35 is for controlling to connect described second node PD and described first voltage end V1 at the first signal input part INPUT1, namely the voltage of the second node PD point is dragged down when the first signal input part INPUT1 is high level, for controlling to connect described second node PD and described first voltage end V1 at secondary signal input end INPUT2, when namely secondary signal input end INPUT2 is high level, drag down the voltage of the second node PD point.
The shift register cell that the embodiment of the present invention provides, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduces cost of products.
Optionally, the electrical block diagram of bilateral scanning shift register cell as shown in Figure 4, comprise: pre-charge module 31, signal output module 32, the drop-down module 33 of output level, first node voltage control module 34, second node voltage control module 35, first signal input part of the shift register cell in Fig. 4 is INPUT1, secondary signal input end INPUT2, 3rd signal input part INPUT3, 4th signal input part INPUT4, signal output part is OUTPUT, first clock signal is CLK, second clock signal is CLKB, first node is PU point, PU point is the node of the drain electrode of first crystal T1 pipe and the source electrode of the 5th transistor T5 and the grid of transistor seconds T2, second node is PD point, PD point is the node of the source electrode of the grid of the 5th transistor T5 and the source electrode of the 6th transistor T6 and the 7th transistor T7, second voltage end V2, tertiary voltage end V3, first voltage end V1, in figure, the first voltage end V1 is for earth terminal VSS, the annexation of concrete each electricity device is as follows:
Pre-charge module 31 comprises: the grid of the first transistor T1 connects the first signal input part N-1_OUTPUT, and the source electrode of this first transistor T1 connects the second voltage end V2, and the drain electrode of this first transistor connects the first node PU point;
The grid of the 8th transistor T8, the 8th transistor T8 connects secondary signal input end N+1_OUTPUT, and the source electrode of the 8th transistor T8 connects the first node PU point, and the drain electrode of the 8th transistor T8 connects tertiary voltage end V3;
Wherein, the forward surface sweeping stage, second voltage end V2 is high level tertiary voltage end V3 is low level, when the first signal input part INPUT 1 in pre-charge module 31 is high level, the first transistor T1 is conducting state, and carries out precharge to the first node PU point, when secondary signal input end INPUT2 is high level (when next stage shift register cell exports high level), 8th transistor T8 is conducting state, and carries out drop-down to the first node PU point voltage; The reverse scan stage, second voltage end V2 is low level tertiary voltage end V3 is high level, when secondary signal input end INPUT 2 in pre-charge module 31 is high level, 8th transistor T8 is conducting state, and precharge is carried out to the first node PU point, when the first signal input part INPUT 1 is high level (when upper level shift register cell exports high level), the first transistor T1 is conducting state, and carries out drop-down to the first node PU point voltage.
Signal output module 32 comprises: transistor seconds T2, and the grid of this transistor seconds T2 connects the first node PU point, and the source electrode of this transistor seconds T2 connects the first clock signal clk, the drain electrode connection signal output terminal OUTPUT of this transistor seconds T2;
One pole of the first electric capacity C1, this first electric capacity C1 connects the grid of transistor seconds T2, and another pole of this first electric capacity C1 connects the drain electrode of transistor seconds T2;
Wherein, when the first clock signal clk is high level, transistor seconds T2 is conducting state, makes the output signal of shift register cell be high level.
The drop-down module 33 of output level comprises: the grid of third transistor T3, this third transistor T3 connects second clock signal CLKB, and the drain electrode of the source electrode connection signal output terminal OUTPUT of this third transistor T3, this third transistor T3 connects earth terminal VSS;
The grid of the 9th transistor T9, the 9th transistor T9 connects the source electrode connection signal output terminal OUTPUT of the 3rd signal input part INPUT3, the 9th transistor T9, and the drain electrode of the 9th transistor T9 connects earth terminal VSS;
The grid of the tenth transistor T10, the tenth transistor T10 connects the source electrode connection signal output terminal OUTPUT of the 4th signal input part INPUT the 4, ten transistor T10, and the drain electrode of the tenth transistor T10 connects earth terminal VSS;
Wherein, after shift register cell exports high level signal, first clock signal clk becomes low level, second clock signal CLKB becomes high level, now second clock signal CLKB controls third transistor T3 conducting, plays drop-down, reset response to shift register cell output signal at the corresponding levels; In addition, in the forward scan stage, become high level at next stage first clock signal clk, when second clock signal CLKB is low level, controlled by the 3rd signal input part INPUT3, the 9th transistor T9 plays drop-down, reset response to shift register cell output signal at the corresponding levels; In the reverse scan stage, the tenth transistor T10 plays drop-down, reset response to shift register cell output signal at the corresponding levels.
First node voltage control module 34 comprises: the 4th transistor T4, and the grid of the 4th transistor T4 is connected second clock signal CLKB with source electrode, and the drain electrode of the 4th transistor T4 connects the second node PD point;
The grid of the 5th transistor T5, the 5th transistor T5 connects the second node PD point, and the source electrode of the 5th transistor T5 connects the first node PU point, and the drain electrode of the 5th transistor T5 connects earth terminal VSS;
Wherein, after the output high level signal of shift register cell, first clock signal clk becomes low level, when second clock signal CLKB becomes high level, controlled by second clock signal CLKB, the 4th transistor T4 and the 5th transistor T5 plays drop-down, reset response to PU voltage node voltage;
Second node voltage control module 35 comprises: the 6th transistor T6, and the source electrode that the grid of the 6th transistor T6 connects the first signal input part INPUT the 1, six transistor T6 connects the second node PD point, and the drain electrode of the 6th transistor T6 connects earth terminal VSS;
The source electrode of the grid connection signal output terminal OUTPUT of the 7th transistor T7, the 7th transistor T7, the 7th transistor T7 connects the second node PD point, and the drain electrode of the 7th transistor T7 connects earth terminal VSS.
The source electrode of grid connection secondary signal input end INPUT the 2, the 11 transistor T11 of the 11 transistor T11, the 11 transistor T11 connects the second node PD point, and the drain electrode of the 11 transistor T11 connects earth terminal VSS.
Wherein, be that high level is not drop-down in order to keep PU voltage node voltage, the PD voltage node voltage when PU voltage node voltage is high should be made to be low level, and the voltage of PU point must keep high level in the output stage of pre-charging stage and shift register cell at the corresponding levels, with this in the forward scan stage, T6 conducting when the first signal input part INPUT 1 input high level, keeps PD voltage node voltage to be low level; T7 conducting when shift register cell signal output part at the corresponding levels exports high level, keeps PD voltage node voltage to be low level; In the reverse scan stage, T11 conducting when secondary signal input end INPUT 2 input high level, keeps PD voltage node voltage to be low level; T7 conducting when shift register cell signal output part at the corresponding levels exports high level, keeps PD voltage node voltage to be low level.
The shift register cell that the embodiment of the present invention provides, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduces cost of products.
Composition graphs 4 and Fig. 6, wherein the time-state method time-state method of CLK, CLKB, PU point and OUTPUT each signal end signal (when wherein Fig. 6 is bilateral scanning) two item scan shift register unit that the embodiment of the present invention provides of Fig. 4 two item scan shift register unit of providing the circuit diagram of two item scan shift register circuit and Fig. 6 to provide and the function of shift-register circuit specific implementation as follows:
During forward scan, in the t1 ' time period, second voltage end V2 input high level, tertiary voltage end V3 input low level, by the first signal input part INPUT 1 input high level, conducting T1 carries out precharge to C1, and T6 conducting keeps PD point to be in low level thus makes T5 remain off and then make PU point keep high level; T2 ' the time period after t1 ', first clock signal clk is high level, second clock signal CLKB is low level, then C1 conducting T2 makes signal output part OUTPUT signal be high level, and now T7 conducting keeps PD point to be in low level thus makes T5 remain off and then make PU point keep high level; T3 ' the time period after t2 ', first clock signal clk is low level, second clock signal CLKB is high level, conducting T3, T4 and T5, PD point is high level, makes signal output part OUTPUT be low level, PU point is also low level, and in time period t 3 ', by the 3rd signal input part INPUT 3 input high level, by conducting T9 degrade signal output terminal OUTPUT signal; Within the shift register cell non-working time, the first clock signal clk is high level, and second clock signal CLKB is low level, and without turn-on transistor, signal output part OUTPUT is low level.
During reverse scan, the input voltage of the second voltage end V2 and tertiary voltage end V3 exchanges, in the t1 ' time period by tertiary voltage end V3 input high level, second voltage end V2 input low level, by secondary signal input end INPUT2 input high level, conducting T8 carries out precharge to C1, and T11 conducting keeps PD point to be in low level thus makes T5 remain off and then make PU point keep high level; T2 ' the time period after t1 ', first clock signal clk is high level, second clock signal CLKB is low level, then C1 conducting T2 makes signal output part OUTPUT signal be high level, and now T7 conducting keeps PD point to be in low level thus makes T5 remain off and then make PU point keep high level; T3 ' the time period after t2 ', first clock signal clk is low level, second clock signal CLKB is high level, the signal of conducting T3 degrade signal output terminal OUTPUT, make signal output part OUTPUT signal be low level, conducting T4 and T5 drags down PU voltage node voltage, and in time period t 3 ', by the 4th signal input part INPUT 4 input high level, by conducting T10 degrade signal output terminal OUTPUT signal; Within the shift register non-working time, the first clock signal clk is high level, and second clock signal CLKB is low level, and without turn-on transistor, signal output part OUTPUT is low level.Time-state method when wherein not providing reverse scan specifically can refer to the time-state method of forward scan.
The shift register cell that the embodiment of the present invention provides, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduces cost of products.
The invention provides a kind of gate driver circuit, comprise the multiple shift register cell as shown in Figure 1 or 2 of series connection, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input part of the next shift register cell be adjacent.
Concrete, gate driver circuit is swept in individual event as shown in Figure 7, comprise several shift register cells, wherein the output terminal OUTPUT of shift register cell SR0 connects the first signal input part INPUT 1 of shift register cell SR1 and connects a grid line GL0; The output terminal OUTPUT of shift register cell SR1 connects the first signal input part INPUT 1 of shift register cell SR2 and connects a grid line GL1; The output terminal OUTPUT of shift register cell SR2 connects the first signal input part INPUT 1 of shift register cell SR3 and connects a grid line GL2, except first shift register cell and last shift register cell, other shift register cell links according to the method.First signal input part INPUT 1 of first shift register cell inputs a frame start signal STV at initial time, and each shift register cell has a first clock signal terminal CLK to input and a second clock signal end CLKB inputs; The clock signal of second clock signal end CLKB and the first clock signal terminal CLK has 180 degree of phase differential, and the clock signal of the first clock signal terminal CLK and second clock signal end CLKB is half the time output high level within the respective work period all, second half time output low level; The clock signal of the first clock signal terminal CLK of two adjacent in addition shift register cells has 180 degree of phase differential, and the clock signal of the second clock signal end CLKB of two adjacent shift register cells has 180 degree of phase differential.
The gate driver circuit that the embodiment of the present invention provides, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduces cost of products.
Another kind of gate driver circuit provided by the invention, comprise multiple shift register cells as described in fig 3 of series connection except first shift register cell and last shift register cell, all the other each shift register cell signal output parts also connect the secondary signal input end of the upper shift register cell be adjacent, the signal output part of each shift register cell also connects the secondary signal input end of the upper shift register cell be adjacent, except most the first two shift register cell with except latter two shift register cell, the signal output part of all the other each shift register cells also connect with its on the 3rd signal input part of adjacent second shift register cell and the 4th signal input part of second shift register cell of lower neighbour that is adjacent.
Concrete, bilateral scanning gate driver circuit as shown in Figure 8, comprise several shift register cells, wherein, the signal output part OUTPUT of shift register cell SR0_1 connects the first signal input part INPUT 1 of next shift register cell SR0_2 and the 4th signal input part INPUT4 and the article grid line G0_1 of lower two shift register cells; The signal output part OUTPUT of shift register cell SR0_2 connects the 4th signal input part INPUT 4 and one article of grid line G0_2 of the first signal input part INPUT 1 of next shift register cell SR1, the secondary signal input end INPUT2 of a upper shift register cell and lower two shift register cells; The signal output part OUTPUT of shift register cell SR1 connects the first signal input part INPUT 1 of next shift register cell, the secondary signal input end INPUT 2 of a upper shift register cell SR0_2 and the 4th signal input part INPUT 4 of lower two shift register cells, the 3rd signal input part INPUT 3 of upper two shift register cell SR0_1 and one article of grid line G1; Except the first two shift register cell with except latter two shift register cell, other shift register cell connects according to shift register cell SR1, when forward scan, the signal input part of first shift register cell inputs a frame start signal STV at initial time, and when reverse scan, the signal input part of last shift register cell inputs a frame start signal STV ＇ at initial time; Each shift register cell has a first clock signal terminal CLK to input and a second clock signal end CLKB inputs; The clock signal of second clock signal end CLKB and the first clock signal terminal CLK has 180 degree of phase differential, and the clock signal of the first clock signal terminal CLK and second clock signal end CLKB is half the time output high level within the respective work period all, second half time output low level; The clock signal of the first clock signal terminal CLK of two adjacent in addition shift register cells has 180 degree of phase differential, and the clock signal of the second clock signal end CLKB of two adjacent shift register cells has 180 degree of phase differential.
The gate driver circuit that the embodiment of the present invention provides, can reduce signal wire integrated in shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduces cost of products.
The embodiment of the present invention additionally provides a kind of display device, can be such as display panel, comprise:
Viewing area, has the multiple pixels for showing image; Gate driver circuit, for delivering to viewing area by sweep signal; And data drive circuit, for delivering to viewing area by data-signal.Wherein gate driver circuit is above-mentioned gate driver circuit.In addition, display device can also be Electronic Paper, mobile phone, TV, digital album (digital photo frame) etc. display device.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (8)
1. a shift register cell, it is characterized in that, comprise: the drop-down module of pre-charge module, signal output module, output level, the first node voltage control module and the second node voltage control module, first node is the tie point of described pre-charge module and signal output module, and the second node is the tie point of described first node voltage control module and the second node voltage control module;
Wherein, described pre-charge module, connects the first signal input part and the first node, under the control of described first signal input part to described signal output module precharge;
Described signal output module, connection signal output terminal, described first node and the first clock signal, for connecting described first clock signal and described signal output part under the control of described first node voltage;
The drop-down module of described output level, connects described signal output part, second clock signal and the first voltage end, for connecting described signal output part and described first voltage end under the control of described second clock signal;
Described first node voltage control module, connects second clock signal, described first voltage end, described first node and the second node, for connecting described first node and described first voltage end under the control of described second clock signal;
Described second node voltage control module, connects described first signal input part, described signal output part, described first voltage end and described second node, connects described second node and described first voltage end for controlling.
2. shift register cell according to claim 1, is characterized in that,
Described pre-charge module comprises:
The first transistor, the grid of described the first transistor is connected described first signal input part with source electrode, the drain electrode of described the first transistor connects described first node;
Described signal output module comprises:
Transistor seconds, the grid of described transistor seconds connects described first node, and the source electrode of described transistor seconds connects described first clock signal, and the drain electrode of described transistor seconds connects described signal output part;
First electric capacity, a pole of described first electric capacity connects the grid of described transistor seconds, and another pole of described first electric capacity connects the drain electrode of described transistor seconds;
The drop-down module of described output level comprises:
Third transistor, the grid of described third transistor connects described second clock signal, and the source electrode of described third transistor connects described signal output part, and the drain electrode of described third transistor connects described first voltage end;
Described first node voltage control module comprises:
4th transistor, the grid of described 4th transistor is connected described second clock signal with source electrode, the drain electrode of described 4th transistor connects described second node;
5th transistor, the grid of described 5th transistor connects described second node, and the source electrode of described 5th transistor connects described first node, and the drain electrode of described 5th transistor connects described first voltage end;
Second node voltage control module comprises:
6th transistor, the grid of described 6th transistor connects described first signal input part, and the source electrode of described 6th transistor connects described second node, and the drain electrode of described 6th transistor connects described first voltage end;
7th transistor, the grid of described 7th transistor connects described signal output part, and the source electrode of described 7th transistor connects described second node, and the drain electrode of described 7th transistor connects described first voltage end.
3. shift register cell according to claim 1, is characterized in that,
Described pre-charge module also connects secondary signal input end, the second voltage end and tertiary voltage end, when being low level for being high level tertiary voltage end at described second voltage end, to described signal output module precharge under the control of described first signal input part, under the control of described secondary signal input end, connect described first node and described tertiary voltage end;
Or described second voltage end is low level tertiary voltage end when being high level, to described signal output module precharge under the control of described secondary signal input end, under the control of described first signal input part, connect described first node and described second voltage end;
The drop-down module of described output level also connects the 3rd signal input part and the 4th signal input part, for connecting described signal output part and described first voltage end under the control of the 3rd signal input part or the 4th signal input part;
Described second node voltage control module also connects described secondary signal input end, for connecting described second node and described first voltage end under the control of described secondary signal input end.
4. shift register cell according to claim 3, is characterized in that,
Described pre-charge module comprises:
The first transistor, the grid of described the first transistor connects described first signal input part, and the source electrode of described the first transistor connects described second voltage end, and the drain electrode of described the first transistor connects described first node;
8th transistor, the grid of described 8th transistor connects described secondary signal input end, and the source electrode of described 8th transistor connects described first node, and the drain electrode of described 8th transistor connects described tertiary voltage end;
Described signal output module comprises:
Transistor seconds, the grid of described transistor seconds connects described first node, and the source electrode of described transistor seconds connects described first clock signal, and the drain electrode of described transistor seconds connects described signal output part;
First electric capacity, a pole of described first electric capacity connects the grid of described transistor seconds, and another pole of described first electric capacity connects the drain electrode of described transistor seconds;
The drop-down module of output level comprises:
Third transistor, the grid of described third transistor connects described second clock signal, and the source electrode of described third transistor connects described signal output part, and the drain electrode of described third transistor connects described first voltage end;
9th transistor, the grid of described 9th transistor connects described 3rd signal input part, and the source electrode of described 9th transistor connects described signal output part, and the drain electrode of described 9th transistor connects described first voltage end;
Tenth transistor, the grid of described tenth transistor connects described 4th signal input part, and the source electrode of described tenth transistor connects described signal output part, and the drain electrode of described tenth transistor connects described first voltage end;
First node voltage control module comprises:
4th transistor, the grid of described 4th transistor is connected described second clock signal with source electrode, the drain electrode of described 4th transistor connects described second node;
5th transistor, the grid of described 5th transistor connects described second node, and the source electrode of described 5th transistor connects described first node, and the drain electrode of described 5th transistor connects described first voltage end;
Second node voltage control module comprises:
6th transistor, the grid of described 6th transistor connects described first signal input part, and the source electrode of described 6th transistor connects described second node, and the drain electrode of described 6th transistor connects described first voltage end;
7th transistor, the grid of described 7th transistor connects described signal output part, and the source electrode of described 7th transistor connects described second node, and the drain electrode of described 7th transistor connects described first voltage end;
11 transistor, the grid of described 11 transistor connects described secondary signal input end, and the source electrode of described 11 transistor connects described second node, and the drain electrode of described 11 transistor connects described first voltage end.
5., according to the arbitrary described shift register cell of Claims 1-4, it is characterized in that, described first voltage end is earth terminal.
6. a gate driver circuit, it is characterized in that, comprise the multiple shift register cell as claimed in claim 1 or 2 of series connection, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input part of the next shift register cell be adjacent.
7. a gate driver circuit, it is characterized in that, comprise the multiple shift register cell as described in claim 3 or 4 of series connection, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input part of the next shift register cell be adjacent, the signal output part of each shift register cell also connects the secondary signal input end of the upper shift register cell be adjacent, except most the first two shift register cell with except latter two shift register cell, the signal output part of all the other each shift register cells also connect with its on the 3rd signal input part of adjacent second shift register cell and the 4th signal input part of second shift register cell of lower neighbour that is adjacent.
8. a display device, comprising:
Viewing area, has the multiple pixels for showing image;
Gate driver circuit, for delivering to described viewing area by sweep signal;
Data drive circuit, for delivering to described viewing area by data-signal;
It is characterized in that, described gate driver circuit is the arbitrary gate driver circuit described in claim 6 or 7.
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| CN104332126B (en) * | 2013-11-29 | 2017-08-29 | 北京大学深圳研究生院 | Shift register cell, gate driving circuit and display |
| CN104064153B (en) | 2014-05-19 | 2016-08-31 | 京东方科技集团股份有限公司 | Shift register cell, shift register, gate driver circuit and display device |
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