CN105719599B - Shift-register circuit unit, gate driving circuit and display device - Google Patents
Shift-register circuit unit, gate driving circuit and display device Download PDFInfo
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- CN105719599B CN105719599B CN201610244561.5A CN201610244561A CN105719599B CN 105719599 B CN105719599 B CN 105719599B CN 201610244561 A CN201610244561 A CN 201610244561A CN 105719599 B CN105719599 B CN 105719599B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of shift register cell, gate driving circuit and display devices.Unit includes：Input module is used to that input terminal to be connect signal access first node when the first clock signal is by the first level；It is second electrical level to dispose second node when mutually putting module for being the first level at first node, and it is second electrical level to dispose first node when being the first level at second node；It is second electrical level that output control module, which is used for second node disposition in the case where control terminal connects signal control,；The first clock signal is accessed into the first output terminal when first output module is used at first node as the first level, the first output is set to second electrical level when being the first level at second node；Second output module is used at first node accesses second output terminal when being the first level by second clock signal, by second output terminal disposition is second electrical level when at second node being the first level.The present invention can reduce arrangement space and reduce cost of manufacture.
Description
Technical field
The present invention relates to display technology fields, and in particular to a kind of shift register cell, gate driving circuit and display
Device.
Background technology
Active matrix organic light-emitting diode (Active-Matrix Organic Light Emitting Diode,
AMOLED) as a kind of application in organic light emitting display (Organic Light-Emitting Display, OLED), have
It the advantages that high brightness, wide viewing angle, fast response time, low-power consumption, is widely applied in high-performance display field.Existing skill
In art, most of OLED products use provide gate drive signal of the gate driving circuit for the pixel circuit per a line, and every
Each gate drive signal of a line is generated each by a shift register cell.Although it is capable of providing institute as a result,
The multichannel gate drive signal needed, but there is the superfluous of circuit structure and signal lead for gate driving circuit internal circuit
It is remaining, arrangement space is caused unnecessarily to expand and the increase of cost of manufacture.
Invention content
For the defects in the prior art, the present invention provides a kind of shift register cell, gate driving circuits and aobvious
Showing device, there is circuit structure and the redundancy of signal lead, causes cloth to solve driving circuit internal circuit in the prior art
Office space unnecessarily expands and the technical issues of the increase of cost of manufacture.
In a first aspect, the present invention provides a kind of shift register cell, including input terminal, control terminal, the first output terminal
And second output terminal, it further includes：
The input module of the input terminal and first node is connected respectively, for when the first clock signal is the first level
The signal that the input terminal is connected is accessed into the first node；
The first node is connected respectively and the mutual of second node puts module, for being the first electricity at the first node
It is usually second electrical level by second node disposition, it will be at the first node when being the first level at the second node
It is set to second electrical level；
The output control module of the control terminal and the second node is connected respectively, for being connected in the control terminal
Signal control under by second node disposition for second electrical level；
The first output module of the first node, the second node and first output terminal is connected respectively, is used for
The first clock signal is accessed into first output terminal when being the first level at the first node, is at second node
First output is set to second electrical level during the first level；
The second output module of the first node, the second node and the second output terminal is connected respectively, is used for
Second clock signal is accessed into the second output terminal when being the first level at the first node, is at second node
The second output terminal is disposed as second electrical level during the first level；
Wherein, first clock signal and second clock signal are respectively in non-inverting clock signal and inverting clock signal
One.
Optionally, the input module includes the first transistor；
The grid of the first transistor connects first clock signal, and a connection in source electrode and drain electrode is described defeated
Enter end, another connects the first node.
Optionally, the module of mutually putting includes second transistor and third transistor, wherein：
The grid of the second transistor connects the first node, a connection second electrical level electricity in source electrode and drain electrode
Crimping, another connects the second node；
The grid of the third transistor connects the second node, a connection second electrical level electricity in source electrode and drain electrode
Crimping, another connects the first node.
Optionally, the output control module includes the 4th transistor；
The grid of 4th transistor connects the control terminal, a connection second section in source electrode and drain electrode
Point, another first level voltage line of connection.
Optionally, first output module includes the 5th transistor and the 6th transistor, wherein：
The grid of 5th transistor connects the first node, and the connection described first in source electrode and drain electrode is defeated
Outlet, another connects first clock signal；
The grid of 6th transistor connects the second node, a connection second electrical level electricity in source electrode and drain electrode
Crimping, another connects first output terminal.
Optionally, first output module further includes the first capacitance and the second capacitance, wherein：
The first end of first capacitance connects the first node, and second end connects first output terminal；
The first end of second capacitance connects the second node, second end connection second electrical level pressure-wire.
Optionally, second output module includes the 7th transistor and the 8th transistor, wherein：
The grid of 7th transistor connects the first node, and the connection described second in source electrode and drain electrode is defeated
Outlet, another connects the second clock signal；
The grid of 8th transistor connects the second node, a connection second electrical level electricity in source electrode and drain electrode
Crimping, another connects the second output terminal.
Optionally, second output module further includes third capacitance and the 4th capacitance, wherein：
The first end of the third capacitance connects the first node, and second end connects the second output terminal；
The first end of 4th capacitance connects the second node, second end connection second electrical level pressure-wire.
Second aspect, the present invention also provides a kind of gate driving circuit, including multistage shift register described above
Unit；
In addition to the first order, the of the input terminal of any level shift register cell connection upper level shift register cell
One output terminal；In addition to the first order, the first clock signal and the upper level shift register list of any level shift register cell
First clock signal of member is respectively non-inverting clock signal and one in inverting clock signal.
The third aspect, the present invention also provides a kind of display device, including gate driving circuit described above
As shown from the above technical solution, shift register cell proposed by the present invention be based on input module, mutually put module and
Input terminal and control terminal are connect signal and are converted to a pair of switches at first node and at second node and believed by output control module
Number (at two nodes during difference be the first level).So as to which the first output module can be split at this with the second output module
The first clock signal and second clock the signal shape at the first output terminal and second output terminal are utilized respectively under the control of OFF signal
Into output signal.The present invention can realize the output of two gate drive signals, phase in a shift register cell as a result,
Than circuit structure can be simplified by the way of being exported respectively using two shift register cells, be conducive to the diminution of arrangement space
With the reduction of cost of manufacture.
Description of the drawings
The features and advantages of the present invention can be more clearly understood by reference to attached drawing, attached drawing is schematically without that should manage
It solves to carry out any restrictions to the present invention, in the accompanying drawings：
Fig. 1 is a kind of shift register cell structure diagram provided in an embodiment of the present invention；
Fig. 2 is a kind of part circuit structure figure of shift register cell shown in FIG. 1；
Fig. 3 is a kind of circuit timing diagram of shift register cell shown in Fig. 2；
Fig. 4 is a kind of circuit simulation sequence diagram of shift register cell shown in FIG. 1；
Fig. 5 is a kind of structure diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 6 is the sequence diagram that end signal is controlled in a kind of gate driving circuit provided in an embodiment of the present invention.
Specific embodiment
Purpose, technical scheme and advantage to make the embodiment of the present invention are clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
Member's all other embodiments obtained under the premise of creative work is not made, shall fall within the protection scope of the present invention.
Fig. 1 is a kind of shift register cell structure diagram provided in an embodiment of the present invention, referring to Fig. 1, the shift LD
Device unit, which is characterized in that including input terminal GSTV, control terminal EM, the first output terminal OUT1 and second output terminal OUT2, also wrap
It includes：
The input module 100 of the input terminal GSTV and first node N1 are connected respectively, in the first clock signal
GCK1 by the input terminal GSTV signals connected during the first level by accessing to the first node N1；
Connect the first node N1 and second node N2 respectively mutually puts module 200, in the first node N1
It is second electrical level to dispose the second node N2 when locating as the first level, will when being the first level at the second node N2
The first node N1 disposition is second electrical level；
The output control module 300 of the control terminal EM and the second node N2 are connected respectively, in the control
The second node N2 is disposed as second electrical level under the control of signal that end EM is connected；
The first output mould of the first node N1, the second node N2 and the first output terminal OUT1 are connected respectively
Block 400, at the first node N1 be the first level when by the first clock signal GCK1 access to it is described first output
OUT1 is held, and it is second electrical level the first output terminal OUT1 to be disposed when being the first level at second node N2；
The second output mould of the first node N1, the second node N2 and the second output terminal OUT2 are connected respectively
Block 500, at the first node N1 be the first level when by second clock signal GCK2 access to it is described second output
OUT2 is held, and it is second electrical level the second output terminal OUT2 to be disposed when being the first level at second node N2；
Wherein, when the first clock signal GCK1 and second clock signal GCK2 is respectively non-inverting clock signal and reverse phase
One in clock signal.
It should be understood that described " the first level " and " second electrical level " is in high level and low level respectively herein
One, and second electrical level is low level when the first level is high level, and second electrical level is high electricity when the first level is low level
It is flat.Above-mentioned high level two preset potentials higher and relatively low for referring to relative to each other with low level, people in the art
Member can be configured according to selected device and used circuit structure, and the present invention is without limitation.
It should be understood that described " non-inverting clock signal " and " inverting clock signal " is all a pair of anti-each other herein
The clock signal of phase signals, inverting clock signal is low level when non-inverting clock signal is high level, and non-inverting clock signal is low
Inverting clock signal is high level during level.Those skilled in the art can be according to selected device and used circuit knot
Structure is configured, and the present invention is without limitation.
In order to illustrate more clearly of the structure and function of above-mentioned each module, it is by low level, second electrical level of the first level
For high level, make a summary to the operation principle of the shift register cell below, referring to Fig. 1：
First stage, the first clock signal GCK1 is low level, second clock signal GCK2 is high level, and control terminal EM
Connect signal just switchs to high level by low level, and input terminal GSTV connects signal and just switchs to low level by high level.At this point, due to
Control terminal EM connects signal as high level, therefore output control module 300 does not act second node N2；And at first
Under the low level effect of clock signal GCK1, first node N1 disposition is low level by input module 100；At first node N1
Under low level effect, it is high level on the one hand mutually to put module 200 by second node N2 disposition, on the other hand the first output module
400 will export the first clock signal GCK1 to the first output terminal OUT1, and the second output module 500 will be defeated to second output terminal OU2
Go out second clock signal GCK2；
Second stage, the first clock signal GCK1 is high level, second clock signal GCK2 is low level, input terminal GSTV
Connect signal is high level.At this point, since control terminal EM connects signal as high level, output control module 300 is not to the
Two node N2 are acted；Under the high level effect of the first clock signal GCK1, input module 100 does not produce first node N1
Raw effect；And since the first output module 400 stores current potentials of the first clock signal GCK1 in previous stage, the second output mould
Block 500 stores current potentials of the second clock signal GCK2 in previous stage, therefore, when the first output terminal OUT1 still exports first
Clock signal GCK1, second output terminal OUT2 still export second clock signal GCK2；
Phase III, the first clock signal GCK1 is low level, second clock signal GCK2 is high level, and control terminal EM
Connect signal is low level.At this point, since input terminal GSTV connects signal as high level, input module 100 is not to first
Node N1 is acted；And signal is connect as under the action of low level in control terminal EM, output control module 300 is by second node
N2 disposition is low level；Under the low level effect of second node N2, on the one hand mutually put module 200 is by first node N1 disposition
High level, on the other hand the first output module 400 will be to the first output terminal OUT1 output high level, and the second output module 500 will
High level is exported to second output terminal OUT2.
It is understood that above-mentioned each module can be realized by including the circuit of electric-controlled switch element, it is therein
Electric-controlled switch element can be the electronic device that any one is controlled voltage change between two circuit nodes of realization by electric signal.
As can be seen that the embodiment of the present invention can be based on input module 100, mutually put module 200 and output control module 300,
By input terminal GSTV and control terminal EM connect signal be converted at first node N1 and second node N2 at a pair of switches signal
(being the first level during difference at two nodes).So as to which the first output module 400 and the second output module 500 can be at these
To being utilized respectively the first clock signal GCK1 and second clock signal GCK2 under the control of switching signal in the first output terminal OUT1
Output signal is formed at second output terminal OUT2.The embodiment of the present invention can be real in a shift register cell as a result,
The output of existing two gate drive signals, compared to electricity can be simplified by the way of being exported respectively using two shift register cells
Line structure is conducive to the diminution of arrangement space and the reduction of cost of manufacture.
As a kind of specific example, Fig. 2 shows a kind of electricity of shift register cell provided in an embodiment of the present invention
Line structure schematic diagram.As shown in Figure 2：
As a kind of specific example of input module internal structure, first is equipped in the output module in the embodiment of the present invention
Transistor T1.Wherein：
The grid of the first transistor T1 connects the first clock signal GCK1, a connection input in source electrode and drain electrode
GSTV is held, another connects the first node N1.
It should be noted that the transistor used in the embodiment of the present invention all can be thin film transistor (TFT) or field effect transistor
Pipe or the identical device of other characteristics, when source electrode, drain electrode in the transistor of use have symmetrical structure, source electrode and drain electrode can be with
It does not distinguish especially.As a kind of example, the transistor is opened during each transistor gate connection low level in the embodiment of the present invention
It opens, and does not differentiate between source electrode and the drain electrode of each transistor.Those skilled in the art can be according to corresponding function in concrete application
Source electrode and the drain electrode of each transistor are determined in circuit, details are not described herein.
It will be appreciated that since transistor is using low level unlatching in the embodiment of the present invention, the first level is low electricity
It is flat, the first level voltage line VGL can be originated from；Second electrical level is high level, can be originated from second electrical level pressure-wire VGH.As a result,
When the first clock signal GCK1 and input terminal GSTV connect signal and are low level, the first transistor T1 open, with formed by
First level voltage line VGL flows to the electric current of first node N1, realizes that input module 100 disposes first node N1 for low level
Function.
The specific example of inside modules structure is mutually put as a kind of, is mutually put in the embodiment of the present invention and the is equipped in module 200
Two-transistor T2 and third transistor T3, wherein：
The grid of the second transistor T2 connects the first node N1, the second electricity of a connection in source electrode and drain electrode
Ordinary telegram crimping VGH, another connects the second node N2
The grid of the third transistor T3 connects the second node N2, the second electricity of a connection in source electrode and drain electrode
Ordinary telegram crimping VGH, another connects the first node N1.
Thus, it is possible to when first node N1 is low level, second transistor T2 is opened, to be formed by second electrical level voltage
Line VGH flows to the electric current of second node N2, realizes and mutually puts module 200 by function of the second node N2 disposition for high level；It can be with
When second node N2 is low level, third transistor T3 is opened, and first node is flowed to by second electrical level pressure-wire VGH to be formed
The electric current of N1 is realized and mutually puts module 200 by function of the first node N1 disposition for high level.
As a kind of specific example of output control module internal structure, output control module 300 in the embodiment of the present invention
Inside it is equipped with the 4th transistor T4.The grid of 4th transistor T4 connects the control terminal EM, a company in source electrode and drain electrode
The second node N2 is met, the first level voltage line VGL of another connection.
As a result, when control terminal EM connects signal as low level, the 4th transistor T4 is opened, to be formed by the first level electricity
Crimping VGL flows to the electric current of first node N1, realizes that output control module 300 disposes first node N1 for low level work(
Energy.
As a kind of specific example of first output module internal structure, the first output module 400 in the embodiment of the present invention
Inside it is equipped with the 5th transistor T5 and the 6th transistor T6.The grid of 5th transistor T5 connects the first node N1, source electrode
With connection the first output terminal OUT1 in drain electrode, another connects the first clock signal GCK1；
The grid of the 6th transistor T6 connects the second node N2, the second electricity of a connection in source electrode and drain electrode
Ordinary telegram crimping VGH, another connects the first output terminal OUT1.
When N1 is low level at first node as a result, the 5th transistor T5 is opened, so that the first clock signal GCK1 connects
Enter to the first output terminal OUT1；When second electrical level is low level, the 6th transistor T6 is opened, to be formed by second electrical level voltage
Line VGH flows to the electric current of the first output terminal OUT1, realizes that the first output module 400 disposes the first output terminal OUT1 for high level
Function.
As the specific example of another first output module internal structure, the first output module in the embodiment of the present invention
The 5th transistor T5, the 6th transistor T6, the first capacitance C1 and the second capacitance C2 are equipped in 400；
The grid of 5th transistor T5 connects the first node N1, a connection described first in source electrode and drain electrode
Output terminal OUT1, another connects the first clock signal GCK1；
The first end of the first capacitance C1 connects the first node N1, and second end connects first output terminal
OUT1；
The grid of the 6th transistor T6 connects the second node N2, the second electricity of a connection in source electrode and drain electrode
Ordinary telegram crimping VGH, another connects the first output terminal OUT1；
The first end of the second capacitance C2 connects the second node N2, second end connection second electrical level pressure-wire VGH.
As a kind of specific example of second output module internal structure, the second output module 500 in the embodiment of the present invention
Inside it is equipped with the 7th transistor T7 and the 8th transistor T8.
The grid of 7th transistor T7 connects the first node N1, a connection described second in source electrode and drain electrode
Output terminal OUT2, another connects the second clock signal GCK2；
The grid of the 8th transistor T8 connects the second node N2, the second electricity of a connection in source electrode and drain electrode
Ordinary telegram crimping VGH, another connects the second output terminal OUT2.
When being as a result, low level at first node N1, the 7th transistor T7 is opened, so that second clock signal GCK1 connects
Enter to second output terminal OUT2；When second electrical level is low level, the 8th transistor T8 is opened, to be formed by second electrical level voltage
Line VGH flows to the electric current of second output terminal OUT2, realizes that the second output module 500 disposes second output terminal OUT2 for high level
Function.
As the specific example of 500 internal structure of another second output module, second exports mould in the embodiment of the present invention
The 7th transistor T7, the 8th transistor T8, third capacitance C3 and the 4th capacitance C4 are equipped in block 500.
The grid of 7th transistor T7 connects the first node N1, a connection described second in source electrode and drain electrode
Output terminal OUT2, another connects the second clock signal GCK2；
The first end of the third capacitance C3 connects the first node N1, and second end connects the second output terminal
OUT2；
The grid of the 8th transistor T8 connects the second node N2, the second electricity of a connection in source electrode and drain electrode
Ordinary telegram crimping VGH, another connects the second output terminal OUT2.
The first end of the 4th capacitance C4 connects the second node N2, second end connection second electrical level pressure-wire VGH.
Fig. 3 is a kind of circuit timing diagram of shift register cell shown in Fig. 2.As shown in figure 3, the embodiment of the present invention carries
A kind of course of work of the shift register cell supplied, including：
Stage i：Control terminal EM connects signal as high potential, and the 4th transistor T4 is closed, therefore exports control
Molding block 300 does not act second node N2；The first clock signal GCK1 at this time is low level, and the first transistor T1 is opened
It opens, current potential connects low level write-in by input module 100 and is set to low level at first node N1, on the one hand, the second crystal
Pipe T2 is opened, and second node N2 locates current potential, and since second electrical level pressure-wire VGH connects the write-in of high level voltage, to be set to height electric
Flat, the 6th transistor T6 and the 8th transistor T8 are closed；On the other hand, the 5th transistor T5 and the 7th transistor T7
It opens, the first output terminal OUT1 signals exported are remained low level by the first clock signal GCK1 by the 5th transistor T5；
The second output terminal OUT2 signals exported are remained high level by second clock signal GCK2 by the 7th transistor T7；In addition,
Between the two poles of the earth of first capacitance C1 and third capacitance C3 there is voltage difference to charge to the first capacitance C1 and third capacitance C3.
Phase il：First clock signal GCK1 and control terminal EM connects signal as equal high level, the first transistor T1 and
4th transistor T4 is in closed state, therefore output control module 300 does not act second node N2, input module
100 do not act first node N1；But due to charged in stage i the first capacitance C1 and third capacitance C3, can make
First node N1 remains low-potential state, and the 5th transistor T5 and the 7th transistor T7 are opened, and the first output terminal OUT1 is still
The first clock signal GCK1 is exported, second output terminal OUT2 still exports second clock signal GCK2；
The Section III stage：First clock signal GCK1 is low potential, and input terminal GSTV connects GSTV signals as high potential, the
One transistor T1 is opened, and first node N1 locates current potential since the write-in of GSTV signals is set to high level, the 6th transistor T6 with
8th transistor T8 is closed；Control terminal EM connects signal as low potential, and the 4th transistor T4 is opened, second node N2
Place's current potential is since the first level voltage line VGL write-ins for connecing low level voltage are set to low level, the 6th transistor T6 and the
Eight transistor T8 are opened, and the first output terminal OUT1 and second output terminal OUT2 export second electrical level pressure-wire VGH and connect high electricity
It is flat.
The embodiment of the present invention additionally provides circuit simulation sequence diagram shown in Fig. 4.As shown in Figure 4, it can be seen that in Fig. 4
The oscillogram of each signal is consistent with the oscillogram of signal each in Fig. 3, so as to illustrate that a kind of displacement provided in an embodiment of the present invention is posted
Storage unit can it is anticipated that sequential normal work, reach expected technique effect.
A kind of shift register cell circuit provided in an embodiment of the present invention uses 8 transistors and 4 capacitances
It realizes.
Wherein the 5th transistor T5, the 6th transistor T6, the 7th transistor T7 and the 8th transistor T8 are as output crystal
Pipe is from the first output terminal OUT1 and second output terminal OUT2 output signals.That is, the embodiment of the present invention can be in a shifting
Bit register element circuit exports two gate drive signals.With exported respectively using two shift register cells by the way of phase
Compare, the embodiment of the present invention can simplify circuit structure, be conducive to reduce arrangement space and reduce cost of manufacture.In addition, first
The signal of output terminal EM inputs can be associated again as the input of rear stage so as to fulfill two gate drive signals, ensure
The reliability of output signal.
Fig. 5 is a kind of structure diagram of gate driving circuit provided in an embodiment of the present invention.As shown in figure 5, the grid drives
Dynamic circuit include it is multistage as described above any one shift register cell (input terminal be denoted as GSTV_1 ..., GSTV_n-1,
GSTV_n、…；First output terminal be denoted as OUT_1, OUT_2 ..., OUT_n-1, OUT_n, OUT_n+1 ...).Except the first order it
Outside, the first output terminal OUT_ of the input terminal GSTV_n connection upper level shift register cells of any level shift register cell
n-1；And in order to ensure that sequential is consistent between multi-stage shift register unit, in addition to the first order, any level shift register
First clock signal of unit and the first clock signal of upper level shift register cell be respectively non-inverting clock signal with it is anti-
(in i.e. adjacent two-stage shift register cell, the first clock signal is set one in clock signal with second clock signal
The mode of putting is opposite).Wherein, n is the positive integer more than 1.
The work schedule of shown shift register cell according to fig. 3, it is to be understood that per level-one shift register
The control terminal EM of unit is required for the signal for being connected to stage i and phase il is high level；However, it is posted for the displacement per level-one
The control terminal EM of storage unit, which is configured, to be needed to occupy a large amount of circuit layout space just like signal shown in Fig. 3.As a result, in order to
The wiring space that control terminal EM connects signal is saved, signal is connect as a kind of control terminal EM of shift register cells at different levels
Specific example, Fig. 6 are the sequence diagrams of EM signals in a kind of gate driving circuit provided in an embodiment of the present invention.Referring to Fig. 6：
In the embodiment of the present invention, be gate driving circuit set first control signal EM1, second control signal EM2,
Third controls the control signals of signal EM3 and the 4th EM4.As can be seen that EM1 to EM4 lags a quarter period successively for phase
Periodic signal, in each period high level and low level time respectively account for half.
So as to for any positive integer n, the control terminal EM connection first control signals of 4n grades of shift register cell
Control terminal EM connection second control signals EM2,4n+2 grades of the shift LD of EM1,4n+1 grades of shift register cell
The control terminal EM connections of the control terminal EM connections third control signal EM3,4n+3 grades of shift register cell of device unit the
Three control signal EM4.
It is understood that remain low level period in input terminal GSTV, the height variation of level at control terminal EM
It can't influence the level of output；So in the case where not influencing the normal work of other shift register cells, it can
Periodic signal is set as so that control terminal EM is connect signal, is per level-one shift register by the EM1 that high level is staggered to EM4
Unit provides required control terminal EM inputs, so as to realize all displacements by the control signal wire of four or four or more
The input and output sequential as shown in Figure 3 of register cell.
Based on same inventive concept, the embodiment of the present invention provides a kind of including any one above-mentioned gate driving circuit
Display device.
The display device can be：Display panel, tablet computer, television set, laptop, Digital Frame, is led at mobile phone
Navigate any products or component with display function such as instrument.The display device is due to including above-mentioned any one gate driving electricity
Road, thus the technical issues of similary can be solved, and obtain identical technique effect, this is no longer going to repeat them.
In the specification of the present invention, numerous specific details are set forth.It is to be appreciated, however, that the embodiment of the present invention can be with
It puts into practice without these specific details.In some instances, well known method, structure and skill is not been shown in detail
Art, so as not to obscure the understanding of this description.
Similarly, it should be understood that disclose to simplify the present invention and help to understand one or more in each inventive aspect
It is a, above in the description of exemplary embodiment of the present invention, each feature of the invention is grouped together into single sometimes
In embodiment, figure or descriptions thereof.It is intended to however, should not explain the method for the disclosure in reflection is following：Want
Ask protection the present invention claims the more features of feature than being expressly recited in each claim.More precisely, such as
As claims reflect, inventive aspect is all features less than single embodiment disclosed above.Therefore, it abides by
Thus the claims for following specific embodiment are expressly incorporated in the specific embodiment, wherein each claim is in itself
Separate embodiments as the present invention.
The orientation of the instructions such as " on ", " under " or position relationship are base it should be noted that term in the description of the present invention
In orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description rather than instruction or imply
Signified device or element must have specific orientation, with specific azimuth configuration and operation, therefore it is not intended that this
The restriction of invention.Unless otherwise clearly defined and limited, term " installation ", " connected ", " connection " should broadly understood, example
Such as, it may be fixed connection or may be dismantle connection, or integral connection；Can be mechanically connected or be electrically connected
It connects；It can be directly connected, can also be indirectly connected by intermediary, can be the connection inside two elements.For this
For the those of ordinary skill in field, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, term " comprising ", "comprising" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those
Element, but also including other elements that are not explicitly listed or further include as this process, method, article or equipment
Intrinsic element.It is more limit in the case of, the element that is limited by sentence "including a ...", it is not excluded that
Also there are other identical elements in process, method, article or equipment including the element.
The above embodiments are merely illustrative of the technical solutions of the present invention rather than it is limited；Although with reference to the foregoing embodiments
The present invention is described in detail, it will be understood by those of ordinary skill in the art that：It still can be to aforementioned each implementation
Technical solution recorded in example modifies or carries out equivalent replacement to which part technical characteristic；And these modification or
It replaces, the spirit and scope for various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution.
Claims (10)
1. a kind of shift register cell, which is characterized in that including input terminal, control terminal, the first output terminal and second output terminal,
It further includes：
Connect the input module of the input terminal and first node respectively, for when the first clock signal is the first level by institute
It states the signal that input terminal is connected and accesses to the first node；
Connect the first node and second node respectively mutually puts module, during for being the first level at the first node
By second node disposition for second electrical level, it is by the first node disposition when at the second node being the first level
Second electrical level；
The output control module of the control terminal and the second node is connected respectively, for the letter connected in the control terminal
Number control under by second node disposition for second electrical level；
The first output module of the first node, the second node and first output terminal is connected respectively, in institute
The first clock signal is accessed into first output terminal when stating at first node as the first level, is first at second node
First output is set to second electrical level during level；
The second output module of the first node, the second node and the second output terminal is connected respectively, in institute
Second clock signal is accessed into the second output terminal when stating at first node as the first level, is first at second node
The second output terminal is disposed as second electrical level during level；
Wherein, first clock signal and second clock signal are respectively non-inverting clock signal and one in inverting clock signal
It is a.
2. shift register cell according to claim 1, which is characterized in that the input module includes first crystal
Pipe；
The grid of the first transistor connects first clock signal, a connection input in source electrode and drain electrode
End, another connects the first node.
3. shift register cell according to claim 1, which is characterized in that the module of mutually putting includes second transistor
And third transistor, wherein：
The grid of the second transistor connects the first node, a connection second electrical level voltage in source electrode and drain electrode
Line, another connects the second node；
The grid of the third transistor connects the second node, a connection second electrical level voltage in source electrode and drain electrode
Line, another connects the first node.
4. shift register cell according to claim 1, which is characterized in that it is brilliant that the output control module includes the 4th
Body pipe；
The grid of 4th transistor connects the control terminal, a connection second node in source electrode and drain electrode, separately
One the first level voltage line of connection.
5. shift register cell according to claim 1, which is characterized in that it is brilliant that first output module includes the 5th
Body pipe and the 6th transistor, wherein：
The grid of 5th transistor connects the first node, a connection first output in source electrode and drain electrode
End, another connects first clock signal；
The grid of 6th transistor connects the second node, a connection second electrical level voltage in source electrode and drain electrode
Line, another connects first output terminal.
6. shift register cell according to claim 5, which is characterized in that first output module further includes first
Capacitance and the second capacitance, wherein：
The first end of first capacitance connects the first node, and second end connects first output terminal；
The first end of second capacitance connects the second node, second end connection second electrical level pressure-wire.
7. shift register cell according to claim 1, which is characterized in that it is brilliant that second output module includes the 7th
Body pipe and the 8th transistor, wherein：
The grid of 7th transistor connects the first node, a connection second output in source electrode and drain electrode
End, another connects the second clock signal；
The grid of 8th transistor connects the second node, a connection second electrical level voltage in source electrode and drain electrode
Line, another connects the second output terminal.
8. shift register cell according to claim 7, which is characterized in that second output module further includes third
Capacitance and the 4th capacitance, wherein：
The first end of the third capacitance connects the first node, and second end connects the second output terminal；
The first end of 4th capacitance connects the second node, second end connection second electrical level pressure-wire.
9. a kind of gate driving circuit, which is characterized in that including multistage as displacement described in any item of the claim 1 to 8 is posted
Storage unit；
In addition to the first order, the first of the input terminal connection upper level shift register cell of any level shift register cell is defeated
Outlet；In addition to the first order, the first clock signal and the upper level shift register cell of any level shift register cell
First clock signal is respectively non-inverting clock signal and one in inverting clock signal.
10. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 9.
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| CN105976749A (en) * | 2016-07-12 | 2016-09-28 | 京东方科技集团股份有限公司 | Shift register, grid driving circuit and display panel |
| CN106782338B (en) * | 2017-02-24 | 2018-11-23 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN107123390A (en) * | 2017-07-04 | 2017-09-01 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| CN108735151B (en) * | 2018-05-07 | 2020-04-21 | 上海天马微电子有限公司 | Light emission control signal generation circuit, display panel, and display device |
| CN111243516B (en) | 2020-03-19 | 2021-11-05 | 京东方科技集团股份有限公司 | Drive circuit, display panel, display device and circuit drive method |
| CN111564132A (en) * | 2020-05-29 | 2020-08-21 | 厦门天马微电子有限公司 | Shift register, display panel and display device |
| CN112071273A (en) * | 2020-09-28 | 2020-12-11 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, gate drive circuit and display device |
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| CN102903323A (en) * | 2012-10-10 | 2013-01-30 | 京东方科技集团股份有限公司 | Shifting register unit, gate drive circuit and display device |
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| JP3734664B2 (en) * | 2000-02-24 | 2006-01-11 | 株式会社日立製作所 | Display device |
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| CN101527129A (en) * | 2008-03-04 | 2009-09-09 | 株式会社日立显示器 | A display device |
| CN102903323A (en) * | 2012-10-10 | 2013-01-30 | 京东方科技集团股份有限公司 | Shifting register unit, gate drive circuit and display device |
| CN104299590A (en) * | 2014-10-30 | 2015-01-21 | 京东方科技集团股份有限公司 | Shifting register, drive method thereof, gate drive circuit and display device |
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