KR101308440B1 - A shift register - Google Patents

Abstract

The present invention relates to a shift register that can reduce the area of the stage by reducing the number of switching elements and to reduce the cost. Wherein each stage is connected to each of the disable nodes by a pull-up switching element that outputs the scan pulse according to a logic state of the enable node. According to the logic state of the disable node, at least two pull-down switching elements outputting an off voltage source, the logic state of the enable node and the disable node, and the logic state of the disable node of another stage It is configured to include a node control unit for controlling.

LCD, Shift Register, Node, Degradation

Description

A shift register

1 is a block diagram of one stage in a conventional shift register

2 illustrates a shift register according to a first embodiment of the present invention.

3 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 2 and an output signal output from each stage;

4 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth stages of FIG. 2.

FIG. 5 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 2.

FIG. 6 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 2.

FIG. 7 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 2.

8 illustrates a shift register according to a second embodiment of the present invention.

9 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 8 and an output signal output from each stage;

FIG. 10 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth stages of FIG. 8.

FIG. 11 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 8.

FIG. 12 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 8.

FIG. 13 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 8.

14 illustrates a shift register according to a third embodiment of the present invention.

FIG. 15 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 14 and an output signal output from each stage.

FIG. 16 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth stages of FIG. 14.

FIG. 17 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 14.

FIG. 18 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 14.

FIG. 19 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 14.

20 illustrates a shift register according to a fourth embodiment of the present invention.

FIG. 21 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 20 and an output signal output from each stage.

FIG. 22 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth stages of FIG. 20.

FIG. 23 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 20.

24 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 20.

FIG. 25 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 20.

26 illustrates a shift register according to a fifth embodiment of the present invention.

27 is a view showing a shift register according to a sixth embodiment of the present invention.

28A and 28B illustrate waveforms of an input signal supplied to each stage of FIG. 27 and an output signal output from each stage.

29A and 29B are diagrams illustrating a circuit configuration of the node controller provided in the first to fourth stages of FIG. 27.

30 is a diagram illustrating another circuit configuration of the node controller provided in the third stage of FIG. 27.

FIG. 31 illustrates another circuit configuration of the node controller provided in the third stage of FIG. 27.

32 illustrates a shift register according to the seventh embodiment of the present invention.

33A and 33B illustrate waveforms of an input signal supplied to each stage of FIG. 32 and an output signal output from each stage.

34A and 34B illustrate a circuit configuration of the node controller provided in the first to fourth stages of FIG. 32.

35 illustrates a shift register according to an eighth embodiment of the present invention.

FIG. 36A illustrates waveforms of an input signal supplied to each stage of FIG. 35 and an output signal output from each stage.

FIG. 36B illustrates another waveform of an input signal supplied to each stage of FIG. 35 and an output signal output from each stage;

FIG. 37 is a diagram illustrating a circuit configuration included in third and fourth stages of FIG. 35.

38 is a view showing a shift register according to a ninth embodiment of the present invention;

FIG. 39A illustrates waveforms of an input signal supplied to each stage of FIG. 38 and an output signal output from each stage.

FIG. 39B illustrates another waveform of an input signal supplied to each stage of FIG. 38 and an output signal output from each stage; FIG.

39C is a view illustrating another waveform of an input signal supplied to each stage of FIG. 38 and an output signal output from each stage;

40 is a diagram illustrating the circuit configuration of the fourth stage of FIG. 38.

FIG. 41 is a diagram illustrating a circuit configuration of the fifth and sixth stages of FIG. 38.

FIG. 42 illustrates another circuit configuration of the fourth stage of FIG. 38.

43 illustrates a shift register according to a tenth embodiment of the present invention.

FIG. 44 is a view showing waveforms of an input signal supplied to each stage of FIG. 43 and an output signal output from each stage;

45 shows another circuit configuration of the first switching device.

* Explanation of symbols on the main parts of the drawings

205: node controller Tru: pull-up switching element

Trd: Pull-down switching element Vac: AC voltage source

Vdc: DC voltage source ST: Stage

Vout: Scan pulse Q: Enable node

QB: Node for disable

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of reducing the area of a stage by reducing the number of switching elements and reducing costs.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

A plurality of gate lines and a plurality of data lines are alternately arranged in the liquid crystal panel, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) as a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line so that a data signal of the data line is charged to the pixel voltage.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying various driving voltages used in the plasma display apparatus.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register to sequentially output the scan pulses as described above. Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

The shift register has a plurality of stages arranged in a line. Each stage is connected to gate lines, respectively, to supply a scan pulse to each gate line.

Each stage is then enabled in response to the scan pulse from the preceding stage and disabled in response to the scan pulse from the next stage.

In general, each stage includes a node controller for controlling the charging and discharging states of the enable node and the disable node, a pull-up switching device that outputs a scan pulse according to the state of the enable node, and the disable And a pull-down switching device for outputting an off voltage according to the state of the node.

On the other hand, since each stage outputs an off voltage for the remaining period except one horizontal period (1H) of one frame, the time for which the disable node is kept in the charged state is maintained in the charged state. It will be much longer than it will be. Accordingly, the pull-down switching device connected to the disable node remains turned on for much longer than the pull-up switching device. This causes a problem that the pull-down switching device is easily degraded.

In order to solve this problem, a shift register having a stage having two or more disable nodes has been developed. Such a shift register may alternately charge the disable nodes on a frame-by-frame basis to prevent deterioration of a pull-down switching device connected to each disable node.

Hereinafter, a configuration of a conventional stage will be described in detail with reference to the accompanying drawings.

1 is a block diagram of one stage in a conventional shift register.

In the conventional stage, as shown in FIG. 1, the charge / discharge state of the enable node Q, the charge / discharge state of the first disable node QB1, and the second disable node ( The node control unit 201 for controlling the charge / discharge state of the QB2, the pull-up switching device Tru which outputs a scan pulse Vout according to the state of the enable node Q, and the first disable. A first pull-down switching device Trd1 outputting the off voltage source Vdc2 according to the state of the node QB1, and a second outputting off voltage source Vdc2 according to the state of the second disable node QB2. And a pull-down switching device Trd2.

Here, one of the first and second disable nodes QB2 is charged while the stage is disabled, and the other is discharged. For example, when the first disable node QB1 is charged and the second disable node QB2 is discharged, a first pull-down in which a gate terminal is connected to the first disable node QB1 is discharged. The switching element Trd1 operates, and the second pull-down switching element Trd2 having the gate terminal connected to the second disable node QB2 does not operate. That is, the second pull-down switching device Trd2 has a rest period.

As described above, since the first pull-down switching device Trd1 and the second pull-down switching device Trd2 are alternately driven, deterioration of each pull-down switching device can be prevented.

However, due to this structure, the node control unit 201 of the conventional stage is provided with a large number of switching elements. That is, the node controller 201 may have a large number of switching elements for controlling one enable node Q and two disable nodes QB1 and QB2. This increases the size of the stage and increases the cost associated with a large number of switching elements.

The present invention has been made to solve the above problems, by reducing the number of switching elements by allowing the node control unit of each stage to control the disable node and the disable node of the other stage together The purpose is to provide a shift register that can reduce the size of the stage.

A shift register according to the present invention for achieving the above object is a shift register having a plurality of stages for sequentially outputting a scan pulse for driving a plurality of conductive lines, wherein each stage is the node for enable A pull-up switching element for outputting the scan pulse according to a logic state of an enable node at least two disable nodes are connected to each of the disable nodes to output an off voltage source according to the logic state of each disable node At least two pull-down switching elements, and a node controller for controlling the logic states of the enable node and the disable nodes, and the logic states of the disable nodes of other stages. .

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to a first exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 2 and an output signal output from each stage.

Hereinafter, all the switching elements, the pull-up switching element, and the pull-down switching element are one of an N-type metal oxide semiconductor (MOS) transistor and a P-type MOS transistor, and the present invention will be described using an N-type MOS transistor.

The shift register according to the first embodiment of the present invention has a plurality of stages ST201, ST202, ST203, ... for driving the plurality of gate lines, as shown in FIG.

Here, each stage ST201, ST202, ST203, ... includes an enable node Q, a pull-up switching element Tru connected to the enable node Q, and a first disable node QB1. ), A first pull-down switching device Trd1 connected to the first disable node QB1, a second disable node QB2, and a second connect node connected to the second disable node QB2. 2 pull-down switching device (Trd2).

The node control unit 205 provided in the 2n-3 (n is a natural number of 2 or more) stages is used to charge / enable the enable node Q and the first disable node QB1 provided in the 2n-3 stage. In addition to controlling the discharge state, the charge / discharge state of the first disable node QB1 provided in the 2n-2 stage is controlled.

The node control unit 205 provided in the second n-2 stage controls the charging / discharging states of the enable node Q and the second disable node QB2 provided in the second n-2 stage. In addition, the charge / discharge state of the second disable node QB2 included in the second n-3 stage is controlled.

To this end, the first disable node QB1 of the 2n-3 stage and the first disable node QB1 of the 2n-2 stage are connected to each other, and the second The disable node QB2 and the second disable node QB2 of the 2n-2 stage are electrically connected to each other.

For example, the node controller 205 of the third stage ST203 may charge / discharge the enable node Q and the first disable node QB1 included in the third stage ST203. In addition to controlling the state, the charge / discharge state of the first disable node QB1 included in the fourth stage ST204 is controlled.

The node control unit 205 provided in the fourth stage ST204 may be configured to charge / discharge states of the enable node Q and the second disable node QB2 provided in the fourth stage ST204. And control the charge / discharge state of the second disable node QB2 included in the third stage ST203.

To this end, the first disable node QB1 of the third stage ST203 and the first disable node QB1 of the fourth stage ST204 are connected to each other, and the fourth stage ST204 is connected to each other. The second disable node QB2 of FIG. 3) and the second disable node QB2 of the third stage ST203 are electrically connected to each other.

In particular, the node control unit 205 provided in the second n-3 stage includes the charge / discharge state of the first disable node QB1 provided in the second n-3 stage and the second nn stage. The charge / discharge state of the first disable node QB1 is controlled by the first AC voltage source.

The node control unit 205 provided in the 2n-2th stage is configured for the second disable node QB2 provided in the 2n-2 stage and the second disable unit provided in the 2n-3 stage. The charging / discharging state of the node QB2 is controlled by the second AC voltage source.

That is, each node control unit 205 provided in the odd stages ST201, ST203, ST205,..., Among the stages ST201, ST202, ST203,..., Is configured as the first AC voltage source Vac1. The node control unit 205 provided in the even-numbered stages ST202, ST204, ST206, ... receives the second AC voltage source Vac2.

Here, the first AC voltage source Vac1 and the second AC voltage source Vac2 are AC voltage sources whose voltage changes in units of frames, and the first AC voltage source Vac1 is 180 degrees with respect to the second AC voltage source Vac2. It has a phase inverted form.

Meanwhile, each of the stages ST201, ST202, ST203, ... receives a first DC voltage source Vdc1 to charge its enable node Q, and receives a second DC voltage source Vdc2. This is output as an off voltage source.

In addition, each stage ST201, ST202, ST203, ... may receive the scan pulse from the front stage instead of the first DC voltage source Vdc1 to charge its enable node Q.

Here, the first DC voltage source Vdc1 means a positive voltage source, and the second DC voltage source Vdc2 means a negative voltage source.

Each of the stages ST201, ST202, ST203, ... configured as described above receives one of the first to fifth clock pulses CLK1 to CLK5 and outputs the supplied clock pulse as a scan pulse. .

As shown in Fig. 3, the first to fifth clock pulses CLK1 to CLK1 to CLK5 are delayed and output by one pulse width from each other. Phase delayed by one pulse width than one clock pulse (CLK1) and output, the third clock pulse (CLK3) is delayed by one pulse width than the second clock pulse (CLK2) output, the fourth clock pulse CLK4 is delayed in phase by one pulse width than the third clock pulse CLK3, and the fifth clock pulse CLK5 is delayed in phase by one pulse width than the fourth clock pulse CLK4. The first clock pulse CLK1 is delayed in phase by one pulse width than the fifth clock pulse CLK5 and output.

In this case, the first to fifth clock pulses CLK1 to CLK5 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the fifth clock pulse CLK5 are sequentially output, the first clock pulse CLK1 to the fifth clock pulse CLK5 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fifth clock pulse CLK5 and the second clock pulse CLK2.

Each of the first to fifth clock pulses CLK1 to CLK5 is continuously output at regular intervals. Therefore, when five clock pulses are used as described above, the first to fifth stages ST201 to ST205 output the first to fifth clock pulses CLK1 to CLK5 as scan pulses.

At this time, since the first to fifth clock pulses CLK1 to CLK5 are phase-delayed by one clock pulse as described above, each of the scan pulses output from the first to fifth stages ST201 to ST205. (Von1 to Von5) are also phase-delayed by one pulse width and outputted.

That is, each of the scan pulses Von1 to Von5 is sequentially output. The sixth stage ST206 again outputs the first clock pulse CLK1 as a sixth scan pulse Vout6. At this time, the first clock pulse CLK1 output by the sixth stage ST206 is a pulse delayed by one period from the first clock pulse CLK1 output from the first stage ST201.

On the other hand, in order for each stage ST201, ST202, ST203, ... to output the scan pulse as described above, each stage ST201, ST202, ST203, ... must be enabled and Each stage ST201, ST202, ST203, ... must be disabled in order to output an off voltage source.

For this purpose, each stage ST201, ST202, ST203, ... is enabled in response to the scan pulse from the front stage, and disabled in response to the scan pulse from the rear stage.

Specifically, the 2n-1 and 2n stages are simultaneously enabled in response to the 2n-3 scan pulses from the 2n-3 stages and in response to the 2n + 2 scan pulses from the 2n + 2 stages. It is disabled at the same time.

The enabled 2n-1 stage outputs a 2n-1 scan pulse, and supplies the 2n-1 scan pulse to the 2n + 1 and 2n + 2 stages to supply the 2n + 1 and 2nd stages. Enable 2n + 2 stages simultaneously.

The enabled 2n stage outputs a 2n scan pulse and supplies the 2n scan pulse to the 2n-3 and 2n-2 stages to supply the 2n-3 and 2n-2 stages. Disable at the same time.

For example, the third stage ST203 and the fourth stage ST204 are simultaneously enabled in response to the first scan pulse Vout1 from the first stage ST201 and also from the sixth stage ST206. It is disabled at the same time in response to the sixth scan pulse Vout6.

The enabled third stage ST203 outputs a third scan pulse Vout3, and supplies the third scan pulse Vout3 to the fifth and sixth stages ST205 and ST206. And the sixth stages ST205 and ST206 at the same time.

The enabled fourth stage ST204 outputs the fourth scan pulse Vout4, and supplies the fourth scan pulse Vout4 to the first and second stages ST201 and ST202. And the second stages ST201 and ST202 are simultaneously disabled.

On the other hand, since there are no stages in the first front end of the first stage ST201 and the second front end of the second stage ST202, the first and second stages ST201 and ST202 start pulses from the timing controller. Enabled in response to (Vst). Also, for this reason, the second scan pulse Vout2 from the second stage ST202 is supplied only to the second gate line.

On the other hand, the start pulse Vst is output before the first clock pulse CLK1. That is, the start pulse Vst is output two clock pulses ahead of the first clock pulse CLK1. In addition, the start pulse Vst is output only once in one frame. That is, the start pulse Vst is first outputted every frame, and then the first to fifth clock pulses CLK1 to CLK5 are sequentially output.

The reason why the time difference between the start pulse Vst and the first clock pulse CLK1 is set by two pulse widths is to equalize the output characteristics of all the stages.

That is, the odd stages ST201, ST203, ST205, ... are enabled by the scan pulses from the stage located at the second front end from themselves and the even stages ST202, ST204, ST206, ... Enabled by the scan pulse from the stage located at the third front end from the first stage ST201 by adjusting the start pulse Vst and the first clock pulse CLK1 to be output with a time difference of two pulse widths. ) May be operated as if it is enabled by the scan pulse from the stage located at the second front end, and the second stage (ST202) may be operated as if it is enabled by the scan pulse from the stage located at the third front end. have.

Of course, although not shown in the drawing, the start pulse Vst and the first clock pulse CLK1 may be adjusted to be output with a time difference of one pulse width.

Here, the configuration of each node control unit 205 provided in the stages ST201, ST202, ST203, ... will be described in more detail as follows.

4 is a diagram illustrating a circuit configuration of the node controller provided in the third and fourth stages of FIG. 2.

Here, the odd-numbered stages (2n-1 stages ST201, ST203, ST205, ...) and the even-numbered stages (2n stages) ST202, ST204, ST206, ... have different configurations.

First, the node control unit 205 provided in the odd stages ST201, ST203, ST205, ... has first to ninth switching elements Tr1 to Tr9, as shown in FIG.

That is, the first switching device Tr1 provided in the 2n-1 stage transmits the enable node Q of the 2n-1 stage to the first DC voltage source in response to the scan pulse from the 2n-3 stage. Charge to Vdc1).

For example, the first switching device Tr1 included in the third stage ST203 of FIG. 4 may be configured to respond to the first scan pulse Vout1 from the first stage ST201 of the third stage ST203. The enable node Q is charged with the first DC voltage source Vdc1.

To this end, a gate terminal of the first switching device Tr1 provided in the third stage ST203 is connected to the first stage ST201, and a drain terminal is a power source for transmitting the first DC voltage source Vdc1. The source terminal is connected to the enable node Q of the third stage ST203.

The second switching device Tr2 provided in the 2n-1 stage is in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the 2n-1 stage. The enable node Q of the stage is discharged to the second DC voltage source Vdc2.

For example, the second switching device Tr2 provided in the third stage ST203 of FIG. 4 is the first AC voltage source Vac1 supplied to the first disable node QB1 of the third stage ST203. In response to), the enabling node Q of the third stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the second switching device Tr2 provided in the third stage ST203 is connected to the first disable node QB1 of the third stage ST203, and the drain terminal thereof is connected to the third disable node QB1. It is connected to the enable node Q of the stage ST203, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The third switching device Tr3 provided in the 2n-1 stage responds to the second AC voltage source Vac2 supplied to the second disable node QB2 of the 2n-1 stage through the 2nn stage. Thus, the enable node Q of the 2n-1 stage is discharged to the second DC voltage source Vdc2.

That is, the third switching device Tr3 provided in the 2n-1 stage is configured to respond to the second AC voltage source Vac2 supplied to the second disable node QB2 of the 2n-1 stage. The enable node Q of the 2n-1 stage is discharged to the second DC voltage source Vdc2, where the state of the second disable node QB2 provided in the 2n-1 stage is the second n stage. Is controlled by the node control unit 205.

For example, the third switching device Tr3 included in the third stage ST203 of FIG. 4 is connected to the second disable node QB2 of the third stage ST203 through the fourth stage ST204. In response to the supplied second AC voltage source Vac2, the enable node Q of the third stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the third switching device Tr3 provided in the third stage ST203 is connected to the second disable node QB2 of the third stage ST203, and the drain terminal of the third stage ST203 is connected to the second disable node QB2. It is connected to the enable node Q of the three stages ST203, and the source terminal is connected to a power supply line for transmitting the second DC voltage source Vdc2.

The fourth switching device Tr4 provided in the 2n-1 stage transmits the enable node Q of the 2n-1 stage to the second DC voltage source Vdc2 in response to the scan pulse from the 2n + 2th stage. To discharge).

For example, the fourth switching device Tr4 included in the third stage ST203 of FIG. 4 may be configured to respond to the sixth scan pulse Vout6 from the sixth stage ST206 of the third stage ST203. The enable node Q is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the fourth switching device Tr4 provided in the third stage ST203 is connected to the sixth stage ST206, and the drain terminal is for enabling the third stage ST203. It is connected to the node Q, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The fifth switching device Tr5 provided in the 2n-1 stage is turned on or turned off in response to the first AC voltage source Vac1 and, when turned on, the common node N of the 2n-1 stage. ) Is charged to the first AC voltage source Vac1.

For example, the fifth switching device Tr5 provided in the third stage ST203 of FIG. 4 is turned on or turned off in response to a first AC voltage source Vac1, and when turned on, the third stage The common node N of ST203 is charged with the first AC voltage source Vac1.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the third stage ST203 are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal is connected to the third terminal ST203. It is connected to the common node N of the stage ST203.

The sixth switching device Tr6 provided in the 2n-1 stage is the second n-1 stage in response to the first DC voltage source Vdc1 charged in the enabling node Q of the 2n-1 stage. Common node N is discharged to second DC voltage source Vdc2.

For example, the sixth switching device Tr6 provided in the third stage ST203 of FIG. 4 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the third stage ST203. In response, the common node N of the third stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the sixth switching device Tr6 provided in the third stage ST203 is connected to the enable node Q of the third stage ST203, and the drain terminal is connected to the third stage. It is connected to the common node N of ST203, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The seventh switching device Tr7 provided in the 2n-1 stage is formed in response to the first AC voltage source Vac1 supplied to the common node N of the 2n-1 stage. The first disable node QB1 and the first disable node QB1 of the second nn stage are charged with the first AC voltage source Vac1.

That is, the seventh switching device Tr7 included in the 2n-1 stage is for the state of the first disable node QB1 provided in the 2n-1 stage and for the first disable provided in the 2n stage. The state of node QB1 is controlled together.

For example, the seventh switching device Tr7 included in the third stage ST203 of FIG. 4 may respond to the first AC voltage source Vac1 supplied to the common node N of the third stage ST203. The first disable node QB1 of the third stage ST203 and the first disable node QB1 of the fourth stage ST204 are charged with the first AC voltage source Vac1.

To this end, the gate terminal of the seventh switching element Tr7 provided in the third stage ST203 is connected to the common node N of the third stage ST203, and the drain terminal thereof is the first AC voltage source. Vac1) is connected to the power supply line, and a source terminal is connected to the first disable node QB1 of the third stage ST203.

The eighth switching device Tr8 provided in the 2n-1 stage includes the first disable node QB1 and the 2n stage of the 2n-1 stage in response to the scan pulse from the 2n-3 stage. The first disable node QB1 is discharged to the second DC voltage source Vdc2.

That is, the eighth switching device Tr8 provided in the 2n-1 stage is for the first disable node QB1 provided in the 2n-1 stage and the first disable device provided in the 2nn stage. The state of node QB1 is controlled together.

For example, the eighth switching device Tr8 of the third stage ST203 of FIG. 4 may be configured to respond to the first scan pulse Vout1 from the first stage ST201 of the third stage ST203. The first disable node QB1 of the first disable node QB1 and the fourth stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the eighth switching element Tr8 provided in the third stage ST203 is connected to the first stage ST201, and the drain terminal of the first stage ST203 is disabled. It is connected to the node QB1, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The ninth switching device Tr9 of the 2n-1 stage is provided in response to the first DC voltage source Vdc1 charged in the enabling node Q of the 2n-1 stage. The first disable node QB1 and the first disable node QB1 of the second nn stage are discharged to the second DC voltage source Vdc2.

That is, the ninth switching device Tr9 provided in the second n-1 stage is in a state of the first disable node QB1 provided in the second n-1 stage and the first disable provided in the second nn stage. The state of the node QB1 is controlled together.

For example, the ninth switching device Tr9 of the third stage ST203 of FIG. 4 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the third stage ST203. In response, the first disable node QB1 of the third stage ST203 and the first disable node QB1 of the fourth stage ST204 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the ninth switching device Tr9 provided in the third stage ST203 is connected to the enable node Q of the third stage ST203, and the drain terminal of the third stage ST203 is provided. It is connected to the first disable node QB1 of ST203, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

Meanwhile, the pull-up switching device Tru provided in the 2n-1 stage transmits the corresponding clock pulse to the 2n-1 stage in response to the first DC voltage source Vdc1 charged in the enable node Q of the 2n-1 stage. -1 Output as scan pulse. The 2n-1 scan pulse is supplied to the 2n-1 gate line, the 2n + 1, and the 2n + 2 stages.

Here, the 2n-1 scan pulse output from the 2n-1 stage drives the 2n-1 gate line and simultaneously enables the 2n + 1 and 2n + 2 stages.

For example, the pull-up switching device Tru provided in the third stage ST203 of FIG. 4 responds to the first DC voltage source Vdc1 charged in the enabling node Q of the third stage ST203. The third clock pulse CLK3 is output as the third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line, the fifth stage ST205, and the sixth stage ST206.

To this end, a gate terminal of the pull-up switching device Tru provided in the third stage ST203 is connected to an enable node Q of the third stage ST203, and a drain terminal thereof is connected to the third clock pulse. It is connected to a clock transmission line for transmitting CLK3, and a source terminal is connected to the third gate line, the fifth stage ST205, and the sixth stage ST206.

The first pull-down switching device Trd1 included in the 2n-1 stage has a second direct current in response to the first AC voltage source Vac1 charged in the first disable node QB1 of the 2n-1 stage. The voltage source Vdc2 is output as an off voltage source. The off voltage source is then supplied to the 2n-1 gate lines, the 2n + 1, and the 2n + 2 stages.

For example, the first pull-down switching device Trd1 included in the third stage ST203 of FIG. 4 may include the first AC voltage source Vac1 charged in the first disable node QB1 of the third stage ST203. The second DC voltage source Vdc2 is output as an off voltage source, and the off voltage source is supplied to the third gate line, the fifth stage ST205, and the sixth stage ST206.

To this end, the gate terminal of the first pull-down switching device Trd1 provided in the third stage ST203 is connected to the first disable node QB1 of the third stage ST203, and the source terminal is It is connected to a power supply line for transmitting the second DC voltage source Vdc2, and a drain terminal is connected to the third gate line, the fifth stage ST205, and the sixth stage ST206.

The second pull-down switching device Trd2 provided in the 2n-1 stage responds to the second AC voltage source Vac2 charged in the second disable node QB2 of the 2n-1 stage through the 2n stage. To output the second DC voltage source Vdc2 as an off voltage source. The off voltage source is then supplied to the 2n-1 gate lines, the 2n + 1, and the 2n + 2 stages.

That is, the second pull-down switching device Trd2 provided in the 2n-1 stage is configured in response to the second AC voltage source Vac2 supplied to the second disable node QB2 of the 2n-1 stage. The state of the second disable node QB2 included in the 2n-1 stage is controlled by the node controller 205 of the 2n stage.

For example, the second pull-down switching device Trd2 included in the third stage ST203 of FIG. 4 is the second AC voltage source Vac2 charged in the second disable node QB2 of the third stage ST203. The second DC voltage source Vdc2 is output as an off voltage source, and the off voltage source is supplied to the third gate line, the fifth stage ST205, and the sixth stage ST206.

To this end, the gate terminal of the second pull-down switching device Trd2 provided in the third stage ST203 is connected to the second disable node QB2 of the third stage ST203, and the source terminal is It is connected to a power supply line for transmitting the second DC voltage source Vdc2, and a drain terminal is connected to the third gate line, the fifth stage ST205, and the sixth stage ST206.

However, since the stage does not exist in the first front end of the first stage ST201, the first and eighth switching elements Tr1 and Tr8 included in the first stage ST201 may have a start pulse (T1) from the timing controller. Operate in response to Vst).

On the other hand, the node control unit 205 provided in even-numbered stages ST202, ST204, ST206, ... also has first to ninth switching elements Tr1 to Tr9, as shown in FIG.

That is, the first switching device Tr1 provided in the second nn stage charges the enabling node Q of the second nn stage to the first DC voltage source Vdc1 in response to the scan pulse from the second nn-3 stage. Let's do it.

For example, the first switching device Tr1 included in the fourth stage ST204 of FIG. 4 may be configured to respond to the first scan pulse Vout1 from the first stage ST201 of the fourth stage ST204. The enable node Q is charged with the first DC voltage source Vdc1.

To this end, the gate terminal of the first switching device Tr1 provided in the fourth stage ST204 is connected to the first stage ST201, and the drain terminal is a power line for transmitting the first DC voltage source Vdc1. The source terminal is connected to the enabling node Q of the fourth stage ST204.

The second switching device Tr2 provided in the second nn stage is provided in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the second nn stage through the second n-1 stage. The enable node Q of the stage is discharged to the second DC voltage source Vdc2.

That is, the second switching device Tr2 provided in the second n-stage is in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the second n-th stage. The enable node Q is discharged to the second DC voltage source Vdc2, wherein the state of the first disable node QB1 provided in the second n-stage is determined by the node controller 205 of the second n-1 stage. Controlled by

For example, the second switching device Tr2 included in the fourth stage ST204 of FIG. 4 is connected to the first disable node QB1 of the fourth stage ST204 through the third stage ST203. The enable node Q of the fourth stage ST204 is discharged to the second DC voltage source Vdc2 in response to the supplied first AC voltage source Vac1.

To this end, the gate terminal of the second switching element Tr2 provided in the fourth stage ST204 is connected to the first disable node QB1 of the fourth stage ST204, and the drain terminal of the second switching element Tr2 is connected to the first disable node QB1. It is connected to the enable node Q of the 4th stage ST204, and a source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The third switching device Tr3 provided in the second n stage is configured to enable the second n stage in response to a second AC voltage source Vac2 supplied to the second disable node QB2 of the second n stage. The node Q is discharged to the second DC voltage source Vdc2.

For example, the third switching device Tr3 included in the fourth stage ST204 of FIG. 4 is the second AC voltage source Vac2 supplied to the second disable node QB2 of the fourth stage ST204. In response to), the enable node Q of the fourth stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the third switching device Tr3 provided in the fourth stage ST204 is connected to the second disable node QB2 of the fourth stage ST204, and the drain terminal of the third switching element Tr3 is connected to the fourth terminal ST204. It is connected to the enable node Q of the 4th stage ST204, and a source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The fourth switching device Tr4 provided in the second nn stage discharges the enable node Q to the second DC voltage source Vdc2 in response to the scan pulse from the second n + 2th stage.

For example, the fourth switching device Tr4 included in the fourth stage ST204 of FIG. 4 may be configured to respond to the sixth scan pulse Vout6 from the sixth stage ST206 of the fourth stage ST204. The enable node Q is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the fourth switching device Tr4 provided in the fourth stage ST204 is connected to the sixth stage ST206, and the drain terminal is a node for enabling the fourth stage ST204. It is connected to (Q), the source terminal is connected to the power supply line for transmitting the second DC voltage source (Vdc2).

The fifth switching device Tr5 provided in the second n-th stage is turned on or off in response to a second AC voltage source Vac2, and when turned on, the fifth switching element Tr5 turns off the common node N of the second n-th stage. 2 Charge with AC voltage source (Vac2).

For example, the fifth switching device Tr5 provided in the fourth stage ST204 of FIG. 4 is turned on or turned off in response to a second AC voltage source Vac2, and when turned on, the fourth stage ST204 is turned on. The common node N of ST204 is charged with the second AC voltage source Vac2.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the fourth stage ST204 are connected to a power line for transmitting the second AC voltage source Vac2, and the source terminal is connected to the fourth terminal ST204. It is connected to the common node N of the stage ST204.

The sixth switching device Tr6 included in the second n-th stage is the common node N of the second n-th stage in response to the first DC voltage source Vdc1 charged in the enabling node Q of the second n-th stage. Is discharged to the second DC voltage source Vdc2.

For example, the sixth switching device Tr6 included in the fourth stage ST204 of FIG. 4 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST204. In response, the common node N of the fourth stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the sixth switching element Tr6 provided in the fourth stage ST204 is connected to the enable node Q of the fourth stage ST204, and the drain terminal of the fourth stage ST204 is connected to the enable node Q. It is connected to the common node N of ST204, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The seventh switching element Tr7 included in the second n-th stage is configured as a second disable node of the second n-th stage in response to the second AC voltage source Vac2 supplied to the common node N of the second n-th stage. QB2) and the second disable node QB2 of the 2n-1 stage are charged with the second AC voltage source Vac2.

That is, the seventh switching element Tr7 included in the second n-stage is for the state of the second disable node QB2 included in the second n-stage and for the second disable provided in the 2n-1th stage. The state of node QB2 is controlled together.

For example, the seventh switching device Tr7 provided in the fourth stage ST204 of FIG. 4 may respond to the second AC voltage source Vac2 supplied to the common node N of the fourth stage ST204. The second disable node QB2 of the fourth stage ST204 and the second disable node QB2 of the third stage ST203 are charged with the second AC voltage source Vac2.

To this end, the gate terminal of the seventh switching element Tr7 provided in the fourth stage ST204 is connected to the common node N of the fourth stage ST204, and the drain terminal of the second AC voltage source ( Vac2) is connected to the power supply line, and the source terminal is connected to the second disable node QB2 of the fourth stage ST204.

The eighth switching device Tr8 included in the second n-th stage includes the second disable node QB2 of the second n-th stage and the second n-th stage of the second n-1 stage in response to a scan pulse from the second n-3 stage. The disable node QB2 is discharged to the second DC voltage source Vdc2.

That is, the eighth switching device Tr8 provided in the second n-stage includes the state of the second disable node QB2 provided in the second n-n stage and the second disable node provided in the 2n-1th stage. The state of (QB2) is controlled together.

For example, the eighth switching device Tr8 included in the fourth stage ST204 of FIG. 4 may respond to the fourth stage ST204 in response to the first scan pulse Vout1 from the first stage ST201. The second disable node QB2 and the second disable node QB2 of the third stage ST203 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the eighth switching device Tr8 provided in the fourth stage ST204 is connected to the first stage ST201, and the drain terminal of the second stage ST203 is disabled. It is connected to the node QB2, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The ninth switching device Tr9 provided in the second n stage is configured to disable the second disable of the second n stage in response to the first DC voltage source Vdc1 charged in the enabling node Q of the second n stage. The node QB2 and the second disable node QB2 of the 2n-1 stage are discharged to the second DC voltage source Vdc2.

That is, the ninth switching device Tr9 provided in the second n-stage is for the state of the second disable node QB2 provided in the second n-n stage and for the second disable provided in the 2n-1th stage. The state of node QB2 is controlled together.

For example, the ninth switching device Tr9 of the fourth stage ST204 of FIG. 4 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST204. In response, the second disable node QB2 of the fourth stage ST204 and the second disable node QB2 of the third stage ST203 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the ninth switching element Tr9 provided in the fourth stage ST204 is connected to the enable node Q of the fourth stage ST204, and the drain terminal is connected to the fourth stage ST204. It is connected to the second disable node QB2 of ST204, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

Meanwhile, the pull-up switching device Tru provided in the 2n stage outputs the corresponding clock pulse as the 2n scan pulse in response to the first DC voltage source Vdc1 charged in the enabling node Q of the 2n stage. do. The 2nn scan pulse is then supplied to the 2nn gate lines, 2n-3, and 2n-2 stages.

Here, the 2n scan pulse output from the 2n stage drives the 2n gate line and simultaneously disables the 2n-3 and 2n-2 stages.

For example, the pull-up switching device Tru provided in the fourth stage ST204 of FIG. 4 responds to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST204. The fourth clock pulse CLK4 is output as the fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line, the first stage ST201, and the second stage ST202.

To this end, a gate terminal of the pull-up switching device Tru provided in the fourth stage ST204 is connected to an enable node Q of the fourth stage ST204, and a drain terminal of the fourth clock pulse is connected to the enable node Q. A source terminal is connected to the fourth gate line, the first stage ST201, and the second stage ST202.

In response to the first AC voltage source Vac1 charged in the first disable node QB1 of the second n-th stage, the first pull-down switching device Trd1 included in the second n-th stage is provided. The second DC voltage source Vdc2 is output as an off voltage source. The off voltage source is then supplied to the 2n gate lines, 2n-3, and 2n-2 stages.

That is, the first pull-down switching device Trd1 included in the second nn stage may respond to a second DC voltage source Vc1 in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the second nn stage. Vdc2) is output to an off voltage source, wherein the state of the first disable node QB1 provided in the second nn stage is controlled by the node controller 205 of the second nn stage.

For example, the first pull-down switching device Trd1 included in the fourth stage ST204 of FIG. 4 is the first AC voltage source Vac1 charged in the first disable node QB1 of the fourth stage ST204. The second direct current voltage source Vdc2 is output as an off voltage source, and the off voltage source is supplied to the fourth gate line, the first stage ST201, and the second stage ST202.

To this end, the gate terminal of the first pull-down switching device Trd1 provided in the fourth stage ST204 is connected to the first disable node QB1 of the fourth stage ST204, and the source terminal is It is connected to a power supply line for transmitting a second DC voltage source Vdc2, and a drain terminal is connected to the fourth gate line, the first stage ST201, and the second stage ST202.

The second pull-down switching device Trd2 included in the second n-th stage is a second DC voltage source Vdc2 in response to the second AC voltage source Vac2 charged in the second disable node QB2 of the second n-th stage. Is output as an off voltage source. The off voltage source is then supplied to the 2n gate lines, 2n-3, and 2n-2 stages.

For example, the second pull-down switching device Trd2 included in the fourth stage ST204 of FIG. 4 is the second AC voltage source Vac2 charged in the second disable node QB2 of the fourth stage ST204. The second direct current voltage source Vdc2 is output as an off voltage source, and the off voltage source is supplied to the fourth gate line, the first stage ST201, and the second stage ST202.

To this end, the gate terminal of the second pull-down switching device Trd2 provided in the fourth stage ST204 is connected to the second disable node QB2 of the fourth stage ST204, and the source terminal of the fourth terminal ST204. It is connected to a power supply line for transmitting a second DC voltage source Vdc2, and a drain terminal is connected to the fourth gate line, the first stage ST201, and the second stage ST202.

However, since the stage does not exist in the second front end of the second stage ST202, the first and eighth switching elements Tr and Tr8 included in the second stage ST202 may have the start pulse (Tr) from the timing controller. Operate in response to Vst).

In addition, each stage ST201, ST202, ST203, ... may have the following circuit structures.

FIG. 5 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 2.

The third and fourth stages ST203 and ST204 illustrated in FIG. 5 further include tenth and eleventh switching elements Tr10 and Tr11 in addition to the first to ninth switching elements Tr1 to Tr9 described above.

The tenth switching element Tr10 provided in each stage ST201, ST202, ST203, ... is in response to the start pulse Vst from the timing controller. Common node N is discharged to second DC voltage source Vdc2.

For example, the tenth switching element Tr10 included in the third stage ST203 of FIG. 5 controls the common node N of the third stage ST203 in response to the start pulse Vst from the timing controller. Discharge to the second DC voltage source Vdc2.

To this end, the gate terminal of the tenth switching element Tr10 provided in the third stage ST203 is connected to the timing controller, and the drain terminal is connected to the common node N of the third stage ST203. The source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The tenth switching device Tr10 discharges (initializes) the common node N included in the stage to which the stage belongs to it in response to the start pulse Vst outputted once every frame.

The eleventh switching element Tr11 provided in the 2n-1 stage (including the first stage ST201) is turned on or turned off in response to the first AC voltage source Vac1 and is turned on. The second disable node QB2 of the 2n-1 stage is discharged to the second DC voltage source Vdc2.

That is, the eleventh switching device Tr11 provided in the 2n-1 stage directly discharges the second disable node QB2 of the 2n-1 stage. In other words, the 2n-1 stage controls the state of the second disable node QB2 provided therein by the eleventh switching element Tr11 and the node controller 205 of the 2n stage.

For example, the eleventh switching element Tr11 included in the third stage ST203 of FIG. 5 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the third switching element Tr11 is turned on. The second disable node QB2 of the stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, a gate terminal of the eleventh switching element Tr11 is connected to a power line for transmitting the first AC voltage source Vac1, and a drain terminal of the second disable node of the third stage ST203 QB2), the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The eleventh switching element Tr11 included in the second n stage (including the second stage ST202) is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the second n The first disable node QB1 of the stage is discharged to the second DC voltage source Vdc2.

That is, the eleventh switching device Tr11 provided in the second n stage directly discharges the second disable node QB2 of the second nn stage. In other words, the second n-1 stage controls the state of the first disable node QB1 provided therein by the eleventh switching element Tr11 and the node controller 205 of the second nn stage.

For example, the eleventh switching element Tr11 provided in the fourth stage ST204 of FIG. 5 is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the fourth switching element Tr11 is turned on. The first disable node QB1 of the stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, a gate terminal of the eleventh switching element Tr11 provided in the fourth stage ST204 is connected to a power line for transmitting the second AC voltage source Vac2, and a drain terminal thereof is connected to the fourth stage ST204. Is connected to a first disable node QB1, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

In addition, each stage ST201, ST202, ST203, ... may have the following circuit structures.

FIG. 6 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 2.

First, the node controller 205 provided in the odd stages ST201, ST203, ST205, ... has first to seventh switching elements Tr1 to Tr7, as shown in FIG.

That is, the first switching device Tr1 provided in the 2n-1 stage transmits the enable node Q of the 2n-1 stage to the first DC voltage source in response to the scan pulse from the 2n-3 stage. Charge to Vdc1).

For example, the first switching device Tr1 included in the third stage ST203 of FIG. 6 may be configured to respond to the first scan pulse Vout1 from the first stage ST201 of the third stage ST203. The enable node Q is charged with the first DC voltage source Vdc1.

To this end, a gate terminal of the first switching device Tr1 provided in the third stage ST203 is connected to the first stage ST201, and a drain terminal of the power supply line for transmitting the first DC voltage source Vdc1. The source terminal is connected to the enabling node Q of the third stage ST203.

The second switching device Tr2 provided in the 2n-1 stage is in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the 2n-1 stage. The enable node Q of the stage is discharged to the second DC voltage source Vdc2.

For example, the second switching device Tr2 provided in the third stage ST203 of FIG. 6 is the first AC voltage source Vac1 supplied to the first disable node QB1 of the third stage ST203. In response to), the enabling node Q of the third stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the second switching device Tr2 provided in the third stage ST203 is connected to the first disable node QB1 of the third stage ST203, and the drain terminal thereof is connected to the third disable node QB1. It is connected to the enable node Q of the stage ST203, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The third switching device Tr3 provided in the 2n-1 stage responds to the second AC voltage source Vac2 supplied to the second disable node QB2 of the 2n-1 stage through the 2nn stage. Thus, the enable node Q of the 2n-1 stage is discharged to the second DC voltage source Vdc2.

That is, the third switching device Tr3 provided in the 2n-1 stage is configured to respond to the second AC voltage source Vac2 supplied to the second disable node QB2 of the 2n-1 stage. The enable node Q of the 2n-1 stage is discharged to the second DC voltage source Vdc2, where the state of the second disable node QB2 provided in the 2n-1 stage is the second n stage. Is controlled by the node control unit 205.

For example, the third switching device Tr3 included in the third stage ST203 of FIG. 6 is connected to the second disable node QB2 of the third stage ST203 through the fourth stage ST204. In response to the supplied second AC voltage source Vac2, the enable node Q of the third stage ST203 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the third switching device Tr3 provided in the third stage ST203 is connected to the second disable node QB2 of the third stage ST203, and the drain terminal of the third stage ST203 is connected to the second disable node QB2. It is connected to the enable node Q of the three stages ST203, and the source terminal is connected to a power supply line for transmitting the second DC voltage source Vdc2.

The fourth switching device Tr4 provided in the 2n-1 stage transmits the enable node Q of the 2n-1 stage to the second DC voltage source Vdc2 in response to the scan pulse from the 2n + 2th stage. To discharge).

For example, the fourth switching device Tr4 included in the third stage ST203 of FIG. 6 may be configured to respond to the sixth scan pulse Vout6 from the sixth stage ST206 of the third stage ST203. The enable node Q is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the fourth switching device Tr4 provided in the third stage ST203 is connected to the sixth stage ST206, and the drain terminal is a node for enabling the third stage ST203. It is connected to (Q), the source terminal is connected to the power supply line for transmitting the second DC voltage source (Vdc2).

The fifth switching device Tr5 provided in the 2n-1 stage is turned on or off in response to a first AC voltage source Vac1, and when turned on, the first disable of the 2n-1 stage is disabled. The first node QB1 for the second node nB and the second node QB1 are charged with the first AC voltage source Vac1.

That is, the fifth switching device Tr5 provided in the second n-1 stage is in a state of the first disable node QB1 provided in the second n-1 stage and the first disable provided in the second nn stage. The state of the node QB1 is controlled together.

For example, the fifth switching device Tr5 of the third stage ST203 of FIG. 6 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the third stage ST203 is turned on. The first disable node QB1 of ST203 and the first disable node QB1 of the fourth stage ST204 are charged with the first AC voltage source Vac1.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the third stage ST203 are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal is connected to the third terminal ST203. It is connected to the first disable node QB1 of the stage ST203.

The sixth switching device Tr6 included in the second n-1 stage includes the first disable node QB1 and the second nth stage of the second n-1 stage in response to a scan pulse from the second n-3 stage. 1 Disabling node QB1 is discharged to second DC voltage source Vdc2.

That is, the sixth switching device Tr6 provided in the 2n-1 stage is in a state of the first disable node QB1 provided in the 2n-1 stage and the first disc provided in the second nn stage. The state of the enable node QB1 is controlled together.

For example, the sixth switching device Tr6 included in the third stage ST203 of FIG. 6 may be configured to respond to the first scan pulse Vout1 from the first stage ST201 of the third stage ST203. The first disable node QB1 of the first disable node QB1 and the fourth stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, a gate terminal of the sixth switching device Tr6 provided in the third stage ST203 is connected to the first stage ST201, and a drain terminal of the first stage ST203 is disabled. It is connected to the node QB1, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The seventh switching device Tr7 provided in the 2n-1 stage is in response to the first DC voltage source Vdc1 charged in the enabling node Q of the 2n-1 stage. The first disable node QB1 and the first disable node QB1 of the second nn stage are discharged to the second DC voltage source Vdc2.

That is, the seventh switching device Tr7 provided in the 2n-1 stage is in a state of the first disable node QB1 provided in the 2n-1 stage and the first disc provided in the second nn stage. The state of the enable node QB1 is controlled together.

For example, the seventh switching device Tr7 included in the third stage ST203 of FIG. 6 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the third stage ST203. In response, the first disable node QB1 of the third stage ST203 and the first disable node QB1 of the fourth stage ST204 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the seventh switching element Tr7 provided in the third stage ST203 is connected to the enable node Q of the third stage ST203, and the drain terminal of the third stage ST203. It is connected to the first disable node QB1 of ST203, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

Meanwhile, the node controller 205 provided in even-numbered stages ST202, ST204, ST206, ... also has first to seventh switching elements Tr1 to Tr7, as shown in FIG.

That is, the first switching device Tr1 provided in the second nn stage charges the enabling node Q of the second nn stage to the first DC voltage source Vdc1 in response to the scan pulse from the second nn-3 stage. Let's do it.

For example, the first switching element Tr1 included in the fourth stage ST204 of FIG. 6 may respond to the fourth stage ST204 in response to the first scan pulse Vout1 from the first stage ST201. Enable node Q is charged with a first DC voltage source Vdc1.

To this end, the gate terminal of the first switching device Tr1 provided in the fourth stage ST204 is connected to the first stage ST201, and the drain terminal is a power line for transmitting the first DC voltage source Vdc1. The source terminal is connected to the enabling node Q of the fourth stage ST204.

The second switching device Tr2 provided in the second nn stage is provided in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the second nn stage through the second n-1 stage. The enable node Q of the stage is discharged to the second DC voltage source Vdc2.

That is, the second switching device Tr2 provided in the second n-stage is in response to the first AC voltage source Vac1 supplied to the first disable node QB1 of the second n-th stage. The enable node Q is discharged to the second DC voltage source Vdc2, wherein the state of the first disable node QB1 provided in the second n-stage is determined by the node controller 205 of the second n-1 stage. Controlled by

For example, the second switching device Tr2 included in the fourth stage ST204 of FIG. 6 is connected to the first disable node QB1 of the fourth stage ST204 through the third stage ST203. The enable node Q of the fourth stage ST204 is discharged to the second DC voltage source Vdc2 in response to the supplied first AC voltage source Vac1.

To this end, the gate terminal of the second switching device Tr2 provided in the fourth stage ST204 is connected to the first disable node QB1 of the fourth stage ST204, and the drain terminal is It is connected to the enabling node Q of the fourth stage ST204, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The third switching device Tr3 provided in the second n stage is configured to enable the second n stage in response to a second AC voltage source Vac2 supplied to the second disable node QB2 of the second n stage. The node Q is discharged to the second DC voltage source Vdc2.

For example, the third switching device Tr3 included in the fourth stage ST204 of FIG. 6 is the second AC voltage source Vac2 supplied to the second disable node QB2 of the fourth stage ST204. In response to), the enable node Q of the fourth stage ST204 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the third switching device Tr3 provided in the fourth stage ST204 is connected to the second disable node QB2 of the fourth stage ST204, and the drain terminal of the third switching element Tr3 is connected to the fourth terminal ST204. It is connected to the enable node Q of the 4th stage ST204, and a source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The fourth switching device Tr4 provided in the second nn stage discharges the enabling node Q of the second nn stage to the second DC voltage source Vdc2 in response to a scan pulse from the second nn + 2 stage. .

For example, the fourth switching device Tr4 of the fourth stage ST204 of FIG. 6 may be configured to respond to the sixth scan pulse Vout6 from the sixth stage ST206 of the fourth stage ST204. The enable node Q is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the fourth switching device Tr4 provided in the fourth stage ST204 is connected to the sixth stage ST206, and the drain terminal is a node for enabling the fourth stage ST204. It is connected to (Q), the source terminal is connected to the power supply line for transmitting the second DC voltage source (Vdc2).

The fifth switching device Tr5 provided in the second n-th stage is turned on or off in response to the second AC voltage source Vac2, and when turned on, the second QB2 node of the second n-th stage is turned off. ) And the second disable node QB2 of the 2n-1 stage with the second AC voltage source Vac2.

That is, the fifth switching device Tr5 provided in the second n-stage is for the state of the second disable node QB2 included in the second n-stage and for the second disable provided in the 2n-1th stage. The state of node QB2 is controlled together.

For example, the fifth switching device Tr5 included in the fourth stage ST204 of FIG. 6 is turned on or turned off in response to a second AC voltage source Vac2, and when turned on, the fourth stage ST204 is turned on. The second disable node QB2 of ST204 and the second disable node QB2 of the third stage ST203 are charged with a second AC voltage source Vac2.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the fourth stage ST204 are connected to a power line for transmitting the second AC voltage source Vac2, and the source terminal is connected to the fourth terminal ST204. It is connected to the second disable node QB2 of the stage ST204.

The sixth switching device Tr6 included in the second n-th stage includes the second disable node QB2 of the second n-th stage and the second n-th stage of the second n-1 stage in response to a scan pulse from the second n-3 stage. 2 The discharge node QB2 is discharged to the second DC voltage source Vdc2.

That is, the sixth switching device Tr6 included in the second n-stage is for the state of the second disable node QB2 included in the second n-n stage and for the second disable provided in the 2n-1th stage. The state of node QB2 is controlled together.

For example, the sixth switching device Tr6 included in the fourth stage ST204 of FIG. 6 may be configured to respond to the first scan pulse Vout1 from the first stage ST201 of the fourth stage ST204. The second disable node QB2 of the second disable node QB2 and the third stage ST203 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the sixth switching device Tr6 provided in the fourth stage ST204 is connected to the first stage ST201, and the drain terminal of the fourth stage ST204 is disabled. It is connected to the node QB2, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The seventh switching device Tr7 provided in the second n stage is configured to disable the second disable of the second n stage in response to the first DC voltage source Vdc1 charged in the enabling node Q of the second n stage. The node QB2 and the second disable node QB2 of the 2n-1 stage are discharged to the second DC voltage source Vdc2.

That is, the seventh switching device Tr7 included in the second n-stage is for the state of the second disable node QB2 included in the second n-n stage and for the second disable provided in the 2n-1 stage. The state of node QB2 is controlled together.

For example, the seventh switching device Tr7 included in the fourth stage ST204 of FIG. 6 is connected to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST204. In response, the second disable node QB2 of the fourth stage ST204 and the second disable node QB2 of the third stage ST203 are discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the seventh switching element Tr7 provided in the fourth stage ST204 is connected to the enable node Q of the fourth stage ST204, and the drain terminal of the fourth stage ST204. It is connected to the second disable node QB2 of ST204, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

Of course, the first and eighth switching elements Tr1 and Tr8 included in the first and second stages ST201 and ST202 operate in response to the start pulse Vst from the timing controller.

In addition, since the pull-up switching device Tru, the first pull-down switching device Trd1, and the second pull-down switching device Trd2 are the same as those described with reference to FIG. 4, description thereof will be omitted.

In addition, each stage ST201, ST202, ST203, ... may have the following circuit structures.

FIG. 7 is a diagram illustrating another circuit configuration of the node controller 205 provided in the third and fourth stages of FIG. 2.

The third and fourth stages ST203 and ST204 shown in FIG. 7 further include eighth and ninth switching elements Tr8 and Tr9 in addition to the first to seventh switching elements Tr1 to Tr7 of FIG. 6 described above. do.

The tenth switching element Tr10 provided in each stage ST201, ST202, ST203, ... is in response to the start pulse Vst from the timing controller. Common node N is discharged to second DC voltage source Vdc2.

The eighth switching device Tr8 of the 2n-1 stage is configured to include the first disable node QB1 of the 2n-1 stage and the 2nd nth stage in response to the scan pulse from the 2n + 2 stage. 1 The disable node QB1 is charged or discharged with the first AC voltage source Vac1.

That is, the eighth switching device Tr8 provided in the 2n-1 stage is in a state of the first disable node QB1 provided in the 2n-1 stage and the first disc provided in the second nn stage. The state of the enable node QB1 is controlled together.

For example, the eighth switching device Tr8 included in the third stage ST203 of FIG. 7 may be configured to respond to the sixth scan pulse Vout6 from the sixth stage ST206 of the third stage ST203. The first disable node QB1 of the first disable node QB1 and the fourth stage ST204 are charged or discharged by the first AC voltage source Vac1.

To this end, a gate terminal of the eighth switching device Tr8 of the third stage ST203 is connected to the sixth stage ST206, and a drain terminal of the power source for transmitting the first AC voltage source Vac1. The source terminal is connected to the first disable node QB1 of the third stage ST203.

The ninth switching device Tr9 provided in the 2n-1 stage is turned on or off in response to a first AC voltage source Vac1, and when turned on, the second disable of the 2n-1 stage is disabled. The dragon node QB2 is discharged to the second DC voltage source Vdc2.

For example, the ninth switching device Tr9 provided in the third stage of FIG. 7 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the third stage ST203 is turned on. Discharges the second disable node (QB2) to a second DC voltage source (Vdc2).

To this end, the gate terminal of the ninth switching element Tr9 provided in the third stage ST203 is connected to a power line for transmitting the first AC voltage source Vac1, and the drain terminal of the third stage ST203 Is connected to a second disable node QB2, and a source terminal thereof is connected to a power line for transmitting the second DC voltage source Vdc2.

That is, the ninth switching device Tr9 of the third stage ST203 of FIG. 7 plays the same role as the eleventh switching device Tr11 of the third stage ST203 of FIG. 5.

On the other hand, the eighth switching device Tr8 included in the second n-th stage includes the second disable node QB2 of the second n-th stage and the second n-1-th stage in response to the scan pulse from the second n + 2 stage. The second disable node QB2 is charged or discharged by the second AC voltage source Vac2.

That is, the eighth switching device Tr8 provided in the second n-stage is for the state of the second disable node QB2 provided in the second n-n stage and for the second disable provided in the 2n-1th stage. The state of node QB2 is controlled together.

For example, the eighth switching device Tr8 of the fourth stage ST204 of FIG. 7 may be configured to respond to the sixth scan pulse Vout6 from the sixth stage ST206 of the fourth stage ST204. The second disable node QB2 and the second disable node QB2 of the third stage ST203 are charged or discharged by the second AC voltage source Vac2.

To this end, the gate terminal of the eighth switching device Tr8 provided in the fourth stage ST204 is connected to the sixth stage ST206, and the drain terminal of the power source for transmitting the second AC voltage source Vac2. The source terminal is connected to the second disable node QB2 of the fourth stage ST204.

The ninth switching device Tr9 provided in the 2n stage is turned on or off in response to the second AC voltage source Vac2, and when turned on, the node QB1 for the first disable of the 2n stage is turned on. ) Is discharged to the second DC voltage source Vdc2.

For example, the ninth switching device Tr9 included in the fourth stage ST204 of FIG. 7 is turned on or turned off in response to a second AC voltage source Vac2, and when turned on, the fourth stage ST204 is turned on. The first disable node QB1 of ST204 is discharged to the second DC voltage source Vdc2.

To this end, the gate terminal of the ninth switching device Tr9 provided in the fourth stage ST204 is connected to a power line for transmitting the second AC voltage source Vac2, and the drain terminal of the fourth stage ST204 Is connected to a first disable node QB1, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

That is, the ninth switching device Tr9 of the fourth stage ST204 of FIG. 7 plays the same role as the eleventh switching device Tr11 of the fourth stage ST204 of FIG. 5.

The operation of the shift register according to the first embodiment of the present invention configured as described above is as follows.

This will be described with reference to FIGS. 3 and 4.

First, the operation of the first initial period T0A in the first frame is as follows.

During the first frame, the first AC voltage source Vac1 shows positive polarity and the second AC voltage source Vac2 shows negative polarity.

During the first initial period T0A, as shown in FIG. 3, only the start pulse Vst output from the timing controller is kept high and the remaining clock pulses are kept low.

The start pulse Vst output from the timing controller is input to the first and second stages ST201 and ST202.

That is, the start pulse Vst is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the eighth switching element Tr8 provided in the first stage ST201.

Then, the first and eighth switching devices Tr1 and Tr8 are turned on, and at this time, the first DC voltage source Vdc1 is enabled through the turned-on first switching device Tr1. Is applied. Accordingly, the enable node Q is charged, and the pull-up switching device Tru, the sixth switching element Tr6, and the ninth, to which the gate terminal is connected to the charged enable node Q, is connected. The switching element Tr9 is turned on.

Here, the second DC voltage source Vdc2 is supplied to the first disable node QB1 through the turned-on eighth and ninth switching elements Tr8 and Tr9. Accordingly, the first switching node QB1 is discharged by the second DC voltage source Vdc2, and the second switching device Tr2 having a gate terminal connected to the first disable node QB1 and The first pull-down switching device Trd1 is turned off.

On the other hand, since the first AC voltage source Vac1 remains positive during the first frame, the fifth switching device Tr5 of the first stage ST201 supplied with the first AC voltage source Vac1 may be a first one. It stays on during the frame. The first AC voltage source Vac1 is supplied to the common node N of the first stage ST201 through the turned-on fifth switching device Tr5. In addition, a second DC voltage source Vdc2 output through the turned-on sixth switching device Tr6 is also supplied to the common node N of the first stage ST201. That is, the first AC voltage source Vac1 having the positive polarity and the second DC voltage source Vdc2 having the negative polarity are simultaneously supplied to the common node N of the first stage ST201.

However, the channel width of the sixth switching device Tr6 for supplying the second DC voltage source Vdc2 is set larger than the channel width of the fifth switching device Tr5 for supplying the first AC voltage source Vac1. The common node N of the first stage ST201 is maintained as the second DC voltage source Vdc2. Therefore, the common node N is discharged, and the seventh switching element Tr7 of the first stage ST201 to which the gate terminal is connected to the discharged common node N is turned off.

As described above, the first stage ST201 charges its enable node Q and discharges its first disable node QB1 in response to the start pulse Vst. That is, the first stage ST201 is enabled.

Meanwhile, in the first initial period T0A, the second stage ST202 is also enabled by receiving the start pulse Vst. If this is explained in more detail as follows.

That is, the start pulse Vst is supplied to the gate terminal of the first switching device Tr1 and the gate terminal of the eighth switching device Tr8 provided in the second stage ST202.

Then, the first and eighth switching devices Tr1 and Tr8 are turned on, and the first DC voltage source Vdc1 is turned on through the turned-on first switching device Tr1 to the second stage ST202. Is applied to the enabling node Q of. Accordingly, the enable node Q is charged, and the pull-up switching device Tru, the sixth switching device Tr6, and the ninth switching device having a gate terminal connected to the charged enable node Q. Element Tr9 is turned on.

Here, the second DC voltage source Vdc2 is supplied to the second disable node QB2 of the second stage ST202 through the turned-on eighth and ninth switching elements Tr8 and Tr9. Accordingly, the second switching node QB2 is discharged by the second DC voltage source Vdc2, and the third switching device Tr3 having a gate terminal connected to the second disable node QB2, and The second pull-down switching device Trd2 is turned off.

On the other hand, since the second AC voltage source Vac2 remains negative during the first frame, the fifth switching device Tr5 of the second stage ST202 supplied with the second AC voltage source Vac2 may be a first one. It remains turned off during the frame.

The second DC voltage source Vdc2 output through the turned-on sixth switching device Tr6 is supplied to the common node N of the second stage ST202. Accordingly, the common node N of the second stage ST202 is discharged by the second DC voltage source Vdc2. Therefore, the seventh switching element Tr7 of the second stage ST202 having the gate terminal connected to the discharged common node N is turned off.

As described above, in the first initial period T0A, the second stage ST202 charges its enable node Q in response to the start pulse Vst, and has its own second disable node. (QB2) is discharged.

At this time, the first and second disable nodes QB1 and QB2 of the first stage ST201 and the first and second disable nodes QB1 and QB2 of the second stage ST202 are electrically connected to each other. Since the second node QB2 of the first stage ST201 has the same state as the second node QB2 of the second stage ST202, the second stage node QB2 has the same state as that of the second stage ST201. The first disable node QB1 of the stage ST202 represents the same state as the first disable node QB1 of the first stage ST201.

That is, the second disable node QB2 of the first stage ST201 is discharged by the second DC voltage source Vdc2 supplied to the second disable node QB2 of the second stage ST202. Indicates the state. In addition, the first disable node QB1 of the second stage ST202 is discharged by the second DC voltage source Vdc2 supplied to the first disable node QB1 of the first stage ST201. Indicates the state.

In other words, in the first initial period T0A, the first stage ST201 charges its enable node Q, and its own first disable node QB1 and the second stage ST202. The first disable node (QB1) is discharged. In the first initial period T0A, the second stage ST202 charges its enable node Q, and has its own second disable node QB2 and the first stage ST201. The second disable node QB2 is discharged.

Next, the operation during the second initial period T0B will be described.

In the second initial period T0B, the start pulse Vst and all clock pulses remain low.

Therefore, the first and second stages ST202 maintain the enabled state for the second initial period T0B. Meanwhile, since the start pulse Vst is turned low in the second initial period T0B, the first and eighth switching elements Tr1 and Tr8 of the first and second stages ST202 are turned on. A change-off state occurs, whereby each enable node Q of the first and second stages ST202 is maintained in a floating state. Accordingly, the first DC voltage source Vdc1 supplied to each of the enable nodes Q of the first and second stages ST201 and ST202 in the first initial period T0A is the node Q for each enable. Stays on).

The operation during the first period T1 will now be described.

In the first period T1, only the first clock pulse CLK1 indicates a high state, and the remaining clock pulses maintain a low state.

Here, as the enabling node Q of the first stage ST201 is continuously charged by the first DC voltage source Vdc1 applied during the first initial period T0A, the first stage ( The pull-up switching device Tru of ST201 is kept on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Tru, a first DC charged in the enable node Q of the first stage ST201. The voltage source Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Tru of the first stage ST201 is stably output through the source terminal of the pull-up switching device Tru. In this case, the output first clock pulse CLK1 functions as a first scan pulse Vout1 applied to the first gate line to drive the first gate line.

The first scan pulse Vout1 output from the first stage ST201 in the first period T1 is also input to the third and fourth stages ST203 and ST204. In detail, as illustrated in FIG. 4, the first scan pulse Vout1 may include gate terminals of the first and eighth switching elements Tr1 and Tr8 and the fourth stage of the third stage ST203. It is input to the gate terminals of the first and eighth switching elements Tr1 and Tr8 provided at ST204.

Accordingly, the third and fourth stages ST203 and ST204 are simultaneously enabled in the first period T1. In this case, the third stage ST203 operates in the same manner as the first stage ST201 during the first initial period T0A described above, and the fourth stage ST204 operates in the first initial period T0A described above. The same operation as in the second stage ST202 during

That is, the third stage ST203 charges its enable node Q, and has its first disable node QB1 and the first disable node QB1 of the fourth stage ST204. ) Is discharged. Then, the fourth stage ST204 charges its enable node Q, and its own second disable node QB2 and the second disable node QB2 of the third stage ST203. ) Is discharged.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

The second clock pulse CLK2 is supplied to the enabled second stage ST202. Specifically, the second clock pulse CLK2 is supplied to the drain terminal of the pull-up switching device Tru provided in the second stage ST202. Accordingly, the pull-up switching device Tru provided in the second stage ST202 outputs the second clock pulse CLK2 as the second scan pulse Vout2. The second scan pulse Vout2 is supplied to the second gate line to drive the second gate line.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in FIG. 3, only the third clock pulse CLK3 remains high and the remaining clock pulses remain low.

The third clock pulse CLK3 is supplied to the enabled third stage ST203. In detail, the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching device Tru provided in the third stage ST203. Therefore, the pull-up switching device Tru provided in the third stage ST203 outputs the third clock pulse CLK3 as a third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line, the fifth stage ST205, and the sixth stage ST206.

That is, the third scan pulse Vout3 drives the third gate line and simultaneously enables the fifth and sixth stages ST206.

Next, the operation during the fourth period T4 will be described.

During the fourth period T4, as shown in FIG. 4, only the fourth clock pulse CLK4 remains high and the remaining clock pulses remain low.

The fourth clock pulse CLK4 is supplied to the enabled fourth stage ST204. In detail, the fourth clock pulse CLK4 is supplied to the drain terminal of the pull-up switching device Tru provided in the fourth stage ST204. Accordingly, the pull-up switching device Tru provided in the fourth stage ST204 outputs the fourth clock pulse CLK4 as a fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line, the first stage ST201, and the second stage ST202.

That is, the fourth scan pulse Vout4 drives the fourth gate line and simultaneously disables the first and second stages ST202. This disable operation will be described in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth stage ST204 in the fourth period T4 is supplied to the first stage ST201. In detail, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the first stage ST201. Then, the fourth switching device Tr4 is turned on, and the second DC voltage source Vdc2 is enabled for the first stage ST201 through the turned-on fourth switching device Tr4. Q) is supplied.

Accordingly, the enable node Q is discharged, and the pull-up switching device Tru and the sixth switching device Tr6 of the first stage ST201 having a gate terminal connected to the discharged enabling node Q are discharged. And the ninth switching element Tr9 are all turned off.

As the sixth switching device Tr6 is turned off, the first AC voltage source Vac1 output through the fifth switching device Tr5 is supplied to the common node N of the first stage ST201. . Accordingly, the common node N of the first stage ST201 is charged, and the seventh switching element Tr7 of the first stage ST201 having the gate terminal connected to the charged common node N is Is turned on.

The first AC voltage source Vac1 is supplied to the first disable node QB1 of the first stage ST201 through the turned-on seventh switching device Tr7. Then, the first disable node QB1 of the first stage ST201 is charged and the first stage ST201 of which the gate terminal is connected to the charged first disable node QB1. The pull-down switching device Trd1 and the second switching device Tr2 are turned on. The second switching device Tr2 further accelerates the discharge of the enable node Q by supplying a second DC voltage source Vdc2 to the enable node Q of the first stage ST201. .

As such, the pull-up switching device Tru of the first stage ST201 is turned off and the first pull-down switching device Trd1 is turned on for the fourth period T4, thereby the first stage ST201. Outputs a second DC voltage source Vdc2 through the turned-on first pull-down switching device Trd1. This second DC voltage source Vdc2 serves as an off voltage source that is supplied to the first gate line to deactivate the first gate line.

In summary, the first stage ST201 discharges its enable node Q in response to the fourth scan pulse Vout4 and charges its first disable node QB1. That is, the first stage ST201 is disabled. At this time, the second disable node QB2 of the first stage ST201 maintains the discharge state in the first initial period T0A.

Meanwhile, the second stage ST202 is also supplied with the fourth scan pulse Vout4 in the fourth period T4 and is disabled. If this is explained in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth stage ST204 in the fourth period T4 is supplied to the second stage ST202. Specifically, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the second stage ST202. Then, the fourth switching device Tr4 is turned on, and the second DC voltage source Vdc2 is enabled for the second stage ST202 through the turned-on fourth switching device Tr4. Q) is supplied.

Accordingly, the enable node Q is discharged, and the pull-up switching device Tru and the sixth switching device Tr6 of the second stage ST202 having a gate terminal connected to the discharged enabling node Q are discharged. And the ninth switching element Tr9 are all turned off.

In addition, the fifth switching device Tr5 of the second stage ST202 supplied with the second AC voltage source Vac2 maintains a turn-off state.

On the other hand, since the state of the first disable node QB1 provided in the second stage ST202 is controlled by the node controller 205 provided in the first stage ST201, the second stage ST202 ), The state of the first disable node QB1 is the same as the state of the first disable node QB1 of the first stage ST201.

That is, as described above, since the first disable node QB1 of the first stage ST201 is charged in the fourth period T4, the node for the first disable of the second stage ST202 is charged. QB1 is also charged.

In addition, since the state of the second disable node QB2 included in the first stage ST201 is controlled by the node controller 205 included in the second stage ST202, the first stage ST201 ) Is the same as the state of the second disable node QB2 provided in the second stage ST202.

That is, since the second disable node QB2 of the second stage ST202 still exhibits a discharge state in the fourth period T4, the first stage ST201 in the fourth period T4. The second disable node QB2 also represents a discharge state.

Therefore, in the fourth period T4, the enabling node Q of the first and second stages ST201 and ST202 indicates a discharge state, and the first and second stages ST201 and ST202 The first disable node QB1 represents a charging state, and the second disable node QB2 of the first and second stages ST201 and ST202 represents a discharge state.

As a result, in the fourth period T4, each pull-up switching device Tru of the first and second stages ST201 and ST202 is turned off, and the first and second stages ST201 and ST202 are turned off. Each first pull-down switching device Trd1 is first turned on, and each second pull-down switching device Trd2 of the first and second stages ST201 and ST202 is turned off.

Accordingly, in the fourth period T4, the first stage ST201 supplies the second DC voltage source Vdc2 to the first gate line as the off voltage source, and the second stage ST202 supplies the second gate line. The second DC voltage source Vdc2 is supplied as an off voltage source.

Thereafter, in the fifth period T5, the enabled fifth stage ST205 outputs the fifth clock pulse CLK5 as the fifth scan pulse Vout5, and outputs the fifth scan pulse Vout5 to the fifth gate. To the line, the seventh stage, and the eighth stage.

Next, in the sixth period T6, the enabled sixth stage ST206 outputs the sixth clock pulse as the sixth scan pulse Vout6, and outputs the sixth scan pulse Vout6 to the sixth gate line, It supplies to 3rd stage ST203 and 4th stage ST204.

In this way the remaining stages operate.

After that, since the first AC voltage source Vac1 is kept negative and the second AC voltage source Vac2 is positive in the second frame, the stages ST201, ST202, ST203, ... are disabled during the disabled period. ), The first disable node QB1 is discharged, and the second disable node QB2 is charged. That is, in the second frame, the first pull-down switching device Trd1 of each stage ST201, ST202, ST203, ... is turned off and the second pull-down switching device Trd2 is turned on.

Another operation of the shift register according to the first embodiment of the present invention configured as described above is as follows.

This will be described with reference to FIGS. 3 and 6.

First, the operation of the first initial period T0A in the first frame is as follows.

During the first frame, the first AC voltage source Vac1 shows positive polarity and the second AC voltage source Vac2 shows negative polarity.

During the first initial period T0A, as shown in FIG. 3, only the start pulse Vst output from the timing controller is kept high and the remaining clock pulses are kept low.

The start pulse Vst output from the timing controller is input to the first and second stages ST201 and ST202.

That is, the start pulse Vst is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the sixth switching element Tr6 provided in the first stage ST201.

Then, the first and sixth switching elements Tr1 and Tr6 are turned on, and at this time, the first DC voltage source Vdc1 is enabled through the turned-on first switching element Tr1. Is applied. Accordingly, the enable node Q is charged, and the pull-up switching device Tru and the seventh switching device Tr7 having a gate terminal connected to the charged enable node Q are turned on. .

Here, the second DC voltage source Vdc2 is supplied to the first disable node QB1 through the turned-on sixth and seventh switching elements Tr6 and Tr7. Accordingly, the first switching node QB1 is discharged by the second DC voltage source Vdc2, and the second switching device Tr2 having a gate terminal connected to the first disable node QB1 and The first pull-down switching device Trd1 is turned off. The turned-on second switching device Tr2 further accelerates the discharge of the enable node Q by supplying a second DC voltage source Vdc2 to the enable node Q.

On the other hand, since the first AC voltage source Vac1 remains positive during the first frame, the fifth switching device Tr5 of the first stage ST201 supplied with the first AC voltage source Vac1 may be a first one. It stays on during the frame. The first AC voltage source Vac1 is supplied to the first disable node QB1 of the first stage ST201 through the turned-on fifth switching device Tr5.

Here, as described above, the second DC voltage source Vdc2 output to the first disable node QB1 of the first stage ST201 through the turned-on sixth and seventh switching elements Tr7. Is also supplied. That is, the first AC voltage source Vac1 having the positive polarity and the second DC voltage source Vdc2 having the negative polarity are simultaneously supplied to the first disable node QB1 of the first stage ST201.

However, since the number of switching elements Tr6 and Tr7 for supplying the second DC voltage source Vdc2 is greater than the number of switching elements Tr5 for supplying the first AC voltage source Vac1, the first stage The first disable node QB1 of ST201 is maintained as the second DC voltage source Vdc2. Therefore, the first disable node QB1 is discharged.

As described above, the first stage ST201 charges its enable node Q and discharges its first disable node QB1 in response to the start pulse Vst. That is, the first stage ST201 is enabled.

Meanwhile, in the first initial period T0A, the second stage ST202 is also enabled by receiving the start pulse Vst. If this is explained in more detail as follows.

That is, the start pulse Vst is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the sixth switching element Tr6 provided in the second stage ST202.

Then, the first and sixth switching devices Tr1 and Tr6 are turned on, and the first DC voltage source Vdc1 is turned on through the turned-on first switching device Tr1 to the second stage ST202. Is applied to the enabling node Q of. Accordingly, the enable node Q is charged, and the pull-up switching device Tru and the seventh switching device Tr7 having a gate terminal connected to the charged enable node Q are turned on. .

Here, the second DC voltage source Vdc2 is supplied to the second disable node QB2 of the second stage ST202 through the turned-on sixth and seventh switching elements Tr6 and Tr7. Accordingly, the second switching node QB2 is discharged by the second DC voltage source Vdc2, and the third switching device Tr3 having a gate terminal connected to the second disable node QB2, and The second pull-down switching device Trd2 is turned off.

On the other hand, since the second AC voltage source Vac2 remains negative during the first frame, the fifth switching device Tr5 of the second stage ST202 supplied with the second AC voltage source Vac2 may be a first one. It remains turned off during the frame.

As described above, in the first initial period T0A, the second stage ST202 charges its enable node Q in response to the start pulse Vst, and has its own second disable node. (QB2) is discharged.

At this time, the first and second disable nodes QB1 and QB2 of the first stage ST201 and the first and second disable nodes QB1 and QB2 of the second stage ST202 are electrically connected to each other. Since the second node QB2 of the first stage ST201 has the same state as the second node QB2 of the second stage ST202, the second stage node QB2 has the same state as that of the second stage ST201. The first disable node QB1 of the stage ST202 represents the same state as the first disable node QB1 of the first stage ST201.

That is, the second disable node QB2 of the first stage ST201 is discharged by the second DC voltage source Vdc2 supplied to the second disable node QB2 of the second stage ST202. Indicates the state. In addition, the first disable node QB1 of the second stage ST202 is provided by a second DC voltage source Vdc2 supplied to the first disable node QB1 of the first stage ST201. Indicates a discharge state.

In other words, in the first initial period T0A, the first stage ST201 charges its enable node Q, and its own first disable node QB1 and the second stage ST202. The first disable node (QB1) is discharged. In the first initial period T0A, the second stage ST202 charges its enable node Q, and has its own second disable node QB2 and the second stage ST202. The second disable node QB2 is discharged.

Next, the operation during the second initial period T0B will be described.

In the second initial period T0B, the start pulse Vst and all clock pulses remain low.

Therefore, the first and second stages ST202 maintain the enabled state for the second initial period T0B. On the other hand, since the start pulse Vst is turned low in the second initial period T0B, the first and sixth switching elements Tr1 and Tr6 of the first and second stages ST202 are turned on. A change-off state occurs, whereby each enable node Q of the first and second stages ST202 is maintained in a floating state. Accordingly, the first DC voltage source Vdc1 supplied to each of the enable nodes Q of the first and second stages ST201 and ST202 in the first initial period T0A is the node Q for each enable. Stays on).

The operation during the first period T1 will now be described.

In the first period T1, only the first clock pulse CLK1 indicates a high state, and the remaining clock pulses maintain a low state.

Here, as the enabling node Q of the first stage ST201 is continuously charged by the first DC voltage source Vdc1 applied during the first initial period T0A, the first stage ( The pull-up switching device Tru of ST201 is kept on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Tru, a first DC charged in the enable node Q of the first stage ST201. The voltage source Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Tru of the first stage ST201 is stably output through the source terminal of the pull-up switching device Tru. In this case, the output first clock pulse CLK1 functions as a first scan pulse Vout1 applied to the first gate line to drive the first gate line.

The first scan pulse Vout1 output from the first stage ST201 in the first period T1 is also input to the third and fourth stages ST203 and ST204. In detail, as illustrated in FIG. 6, the first scan pulse Vout1 may include gate terminals of the first and sixth switching elements Tr1 and Tr6 and the fourth stage provided in the third stage ST203. It is input to the gate terminals of the first and sixth switching elements Tr1 and Tr6 provided at ST204.

Accordingly, the third and fourth stages ST203 and ST204 are simultaneously enabled in the first period T1. In this case, the third stage ST203 operates in the same manner as the first stage ST201 during the above-described first initial period T0A, and the fourth stage ST204 operates in the first initial period T0A. The same operation as in the second stage ST202 during

That is, the third stage ST203 charges its enable node Q, and has its first disable node QB1 and the first disable node QB1 of the fourth stage ST204. ) Is discharged. Then, the fourth stage ST204 charges its enable node Q, and its own second disable node QB2 and the second disable node QB2 of the third stage ST203. ) Is discharged.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

The second clock pulse CLK2 is supplied to the enabled second stage ST202. Specifically, the second clock pulse CLK2 is supplied to the drain terminal of the pull-up switching device Tru provided in the second stage ST202. Accordingly, the pull-up switching device Tru provided in the second stage ST202 outputs the second clock pulse CLK2 as the second scan pulse Vout2. The second scan pulse Vout2 is supplied to the second gate line to drive the second gate line.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in FIG. 3, only the third clock pulse CLK3 remains high and the remaining clock pulses remain low.

The third clock pulse CLK3 is supplied to the enabled third stage ST203. In detail, the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching device Tru provided in the third stage ST203. Therefore, the pull-up switching device Tru provided in the third stage ST203 outputs the third clock pulse CLK3 as a third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line, the fifth stage ST205, and the sixth stage ST206.

That is, the third scan pulse Vout3 drives the third gate line and enables the fifth and sixth stages ST205 and ST206 simultaneously.

Next, the operation during the fourth period T4 will be described.

During the fourth period T4, as shown in FIG. 3, only the fourth clock pulse CLK4 remains high and the remaining clock pulses remain low.

The fourth clock pulse CLK4 is supplied to the enabled fourth stage ST204. In detail, the fourth clock pulse CLK4 is supplied to the drain terminal of the pull-up switching device Tru provided in the fourth stage ST204. Accordingly, the pull-up switching device Tru provided in the fourth stage ST204 outputs the fourth clock pulse CLK4 as a fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line, the first stage ST201, and the second stage ST202.

That is, the fourth scan pulse Vout4 drives the fourth gate line and simultaneously disables the first and second stages ST201 and ST202. This disable operation will be described in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth stage ST204 in the fourth period T4 is supplied to the first stage ST201. In detail, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the first stage ST201. Then, the fourth switching device Tr4 is turned on, and the second DC voltage source Vdc2 is enabled for the first stage ST201 through the turned-on fourth switching device Tr4. Q) is supplied.

Accordingly, the enable node Q is discharged, and the pull-up switching device Tru and the seventh switching device Tr7 of the first stage ST201 having a gate terminal connected to the discharged enabling node Q are discharged. ) Are all turned off.

Meanwhile, since the fifth switching device Tr5 of the first stage ST201 is turned on for one frame by the first AC voltage source Vac1, the turned-on fifth switching device Tr5 is turned on. The first AC voltage source Vac1 is supplied to the first disable node QB1 of the first stage ST201 through the first AC voltage source Vac1. Accordingly, the first pull-down switching device of the first stage ST201 charged with the first disable node QB1 of the first stage ST201 and connected to the charged first disable node QB1. Trd1 and the second switching device Tr2 are turned on. The second switching device Tr2 accelerates the discharge of the enable node Q by supplying a second DC voltage source Vdc2 to the enable node Q of the first stage ST201.

As such, the pull-up switching device Tru of the first stage ST201 is turned off and the first pull-down switching device Trd1 is turned on for the fourth period T4, thereby the first stage ST201. Outputs a second DC voltage source Vdc2 through the turned-on first pull-down switching device Trd1. This second DC voltage source Vdc2 serves as an off voltage source that is supplied to the first gate line to deactivate the first gate line.

In other words, the first stage ST201 discharges its enable node Q in response to the fourth scan pulse Vout4 and charges its first disable node QB1. That is, the first stage ST201 is disabled. At this time, the second disable node QB2 of the first stage ST201 maintains the discharge state in the first initial period T0A.

Meanwhile, the second stage ST202 is also supplied with the fourth scan pulse Vout4 in the fourth period T4 and is disabled. If this is explained in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth stage ST204 in the fourth period T4 is supplied to the second stage ST202. Specifically, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the second stage ST202. Then, the fourth switching device Tr4 is turned on, and the second DC voltage source Vdc2 is enabled for the second stage ST202 through the turned-on fourth switching device Tr4. Q) is supplied.

Accordingly, the enable node Q is discharged, and the pull-up switching device Tru and the seventh switching device Tr7 of the second stage ST202 having a gate terminal connected to the discharged enabling node Q are discharged. ) Are all turned off.

In addition, the fifth switching device Tr5 of the second stage ST202 supplied with the second AC voltage source Vac2 maintains a turn-off state.

On the other hand, since the state of the first disable node QB1 provided in the second stage ST202 is controlled by the node controller 205 provided in the first stage ST201, the second stage ST202 ), The state of the first disable node QB1 is the same as the state of the first disable node QB1 of the first stage ST201.

That is, as described above, since the first disable node QB1 of the first stage ST201 is charged in the fourth period T4, the node for the first disable of the second stage ST202 is charged. QB1 is also charged.

In addition, since the state of the second disable node QB2 included in the first stage ST201 is controlled by the node controller 205 included in the second stage ST202, the first stage ST201 ) Is the same as the state of the second disable node QB2 provided in the second stage ST202.

That is, since the second disable node QB2 of the second stage ST202 still exhibits a discharge state in the fourth period T4, the first stage ST201 in the fourth period T4. The second disable node QB2 also represents a discharge state.

Therefore, in the fourth period T4, the enabling node Q of the first and second stages ST202 indicates a discharge state and is the first of the first and second stages ST201 and ST202. The disable node QB1 represents a charging state, and the second disable node QB2 of the first and second stages ST201 and ST202 represents a discharge state.

As a result, in the fourth period T4, each pull-up switching device Tru of the first and second stages ST201 and ST202 is turned off, and the first and second stages ST201 and ST202 are turned off. Each first pull-down switching device Trd1 is first turned on, and each second pull-down switching device Trd2 of the first and second stages ST201 and ST202 is turned off.

Accordingly, in the fourth period T4, the first stage ST201 supplies the second DC voltage source Vdc2 to the first gate line as the off voltage source, and the second stage ST202 supplies the second gate line. The second DC voltage source Vdc2 is supplied as an off voltage source.

Thereafter, in the fifth period T5, the enabled fifth stage ST205 outputs the fifth clock pulse CLK5 as the fifth scan pulse Vout5, and outputs the fifth scan pulse Vout5 to the fifth gate. To the line, the seventh stage, and the eighth stage.

Next, in the sixth period T6, the enabled sixth stage ST206 outputs the sixth clock pulse as the sixth scan pulse Vout6, and outputs the sixth scan pulse Vout6 to the sixth gate line, It supplies to 3rd stage ST203 and 4th stage ST204.

In this way the remaining stages operate.

After that, since the first AC voltage source Vac1 is kept negative and the second AC voltage source Vac2 is positive in the second frame, the stages ST201, ST202, ST203, ... are disabled during the disabled period. ), The first disable node QB1 is discharged, and the second disable node QB2 is charged. That is, in the second frame, the first pull-down switching device Trd1 of each stage ST201, ST202, ST203, ... is turned off and the second pull-down switching device Trd2 is turned on.

Hereinafter, the shift register according to the second embodiment of the present invention will be described.

8 is a diagram illustrating a shift register according to a second exemplary embodiment of the present invention, and FIG. 9 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 8 and an output signal output from each stage.

The shift register according to the second embodiment of the present invention has a plurality of stages ST801, ST802, ST803, ... as shown in FIG.

Here, the configuration of each stage ST801, ST802, ST803, ... is the same as that of the first embodiment, and only the connection relation between the stages ST801, ST802, ST803, ... is different. This will be described. In addition, the shift register according to the second embodiment of the present invention receives the first to fourth clock pulses CLK1 to CLK4. Of course, the shift register according to the second embodiment of the present invention may be supplied with five or more clock pulses.

The 2n-1 and 2n stages are simultaneously enabled in response to the 2n-2 scan pulses from the 2n-2 stages and simultaneously disabled in response to the 2n + 2 scan pulses from the 2n + 2 stages. do.

The enabled 2n stage outputs a 2n scan pulse, and supplies the 2n scan pulse to the 2n + 1 and 2n + 2 stages, thereby providing the 2n + 1 and 2n + 2 stages. Enable at the same time. In addition, the second n stage simultaneously disables the second n-3 and second n-2 stages by supplying the second n scan pulses to the second n-3 and second n-2 stages.

For example, the third stage ST803 and the fourth stage ST804 of FIG. 8 are simultaneously enabled in response to the second scan pulse Vout2 from the second stage ST802, and the sixth stage ST806. Are simultaneously disabled in response to the sixth scan pulse Vout6 from

The enabled fourth stage ST804 outputs the fourth scan pulse Vout4, and supplies the fourth scan pulse Vout4 to the fifth and sixth stages ST205 and ST806. And the sixth stages ST205 and ST806 at the same time. In addition, the fourth stage ST804 simultaneously disables the first and second stages ST802 by supplying the fourth scan pulses Vout4 to the first and second stages ST201 and ST802.

Meanwhile, the first and second stages ST201 and ST802 are enabled in response to the start pulse Vst from the timing controller.

Here, the configuration of each node control unit 805 provided in each of the stages ST801, ST802, ST803, ... will be described in more detail as follows.

FIG. 10 is a diagram illustrating a circuit configuration of the node controller provided in the third and fourth stages of FIG. 8.

The first to ninth switching elements Tr1 to Tr9, the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 shown in FIG. 10 are shown in FIG. 4. Same as those made.

However, the first and eighth switching elements Tr1 and Tr8 provided in the 2n-1 stage and the first and eighth switching elements Tr1 and Tr8 provided in the second nn stage are scanned from the 2n-2 stage. It operates in response to a pulse.

For example, the first and eighth switching elements Tr1 and Tr8 provided in the third stage ST803 of FIG. 10 and the first and eighth switching elements Tr1 and Tr8 provided in the fourth stage ST804. Operates in response to the second scan pulse Vout2 from the second stage ST802.

The scan pulse output from the pull-up switching device Tru provided in the 2n-1 stage and the off voltage source output from the first and second pull-down switching devices Trd1 and Trd2 provided in the 2n-1 stage. Is supplied only to the 2n-1 gate line.

For example, the third scan pulse Vout3 output from the pull-up switching device Tru provided in the third stage ST803 may include first and second pull-down switching devices provided in the third stage ST803. The off voltage source output from (Trd1, Trd2) is supplied only to the third gate line.

The scan pulse output from the pull-up switching device Tru provided in the 2n stage, and the off voltage sources output from the first and second pull-down switching devices Trd1 and Trd2 provided in the second n stage may include a second gate. It is supplied to a line, a 2n + 1 stage, a 2n + 2 stage, a 2n-3 stage, and a 2n-2 stage.

For example, the fourth scan pulse Vout4 output from the pull-up switching device Tru provided in the fourth stage ST804, and the first and second pull-down switching devices provided in the fourth stage ST804 (for example). The off voltage sources output from Trd1 and Trd2 are supplied to the fourth gate line, the fifth stage ST805, the sixth stage ST806, the first stage ST801, and the second stage ST802.

In addition, each stage ST801, ST802, ST803, ... provided in the shift register according to the second embodiment of the present invention may have the following circuit configuration.

FIG. 11 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 8.

The first to ninth switching elements Tr1 to Tr9 and the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 shown in FIG. 11 are those of FIG. 10. Is the same as The tenth and eleventh switching elements Tr11 shown in FIG. 11 are the same as those of FIG. 5.

In addition, each stage ST801, ST802, ST803, ... provided in the shift register according to the second embodiment of the present invention may have the following circuit configuration.

FIG. 12 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 8.

The first to seventh switching elements Tr1 to Tr7 shown in FIG. 12, the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 are shown in FIG. 6. Same as those.

However, the first and sixth switching elements Tr1 and Tr6 provided in the 2n-1 stage and the first and sixth switching elements Tr1 and Tr6 provided in the 2n n stage are scanned from the 2n-2 stage. It operates in response to a pulse.

For example, the first and sixth switching elements Tr1 and Tr6 provided in the third stage ST803 and the first and sixth switching elements Tr1 and Tr6 provided in the fourth stage ST804 are second to each other. It operates in response to the second scan pulse Vout2 from the stage ST802.

The scan pulse output from the pull-up switching device Tru provided in the 2n-1 stage and the off voltage source output from the first and second pull-down switching devices Trd1 and Trd2 provided in the 2n-1 stage. Is supplied only to the 2n-1 gate line.

For example, the third scan pulse Vout3 output from the pull-up switching device Tru provided in the third stage ST803 may include first and second pull-down switching devices provided in the third stage ST803. The off voltage source output from (Trd1, Trd2) is supplied only to the third gate line.

The scan pulse output from the pull-up switching device Tru provided in the 2n stage, and the off voltage sources output from the first and second pull-down switching devices Trd1 and Trd2 provided in the second n stage may include a second gate. It is supplied to a line, a 2n + 1 stage, a 2n + 2 stage, a 2n-3 stage, and a 2n-2 stage.

For example, a fourth scan pulse Vout4 output from the pull-up switching device Tru provided in the fourth stage ST804, and first and second pull-down switching devices provided in the fourth stage ST804. The off voltage sources output from Trd1 and Trd2 are supplied to the fourth gate line, the fifth stage ST805, the sixth stage ST806, the first stage ST801, and the second stage ST802.

In addition, each stage ST801, ST802, ST803, ... provided in the shift register according to the second embodiment of the present invention may have the following circuit configuration.

FIG. 13 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 8.

The first to seventh switching elements Tr1 to Tr7 and the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 shown in FIG. 13 are those of FIG. 12. Is the same as The eighth and ninth switching elements Tr8 and Tr9 shown in FIG. 13 are the same as those in FIG.

On the other hand, each scan pulse Vout1, Vout3, Vout5, ... output from the odd stages ST801, ST803, ST805, ... is supplied only to the corresponding gate line (oddth gate line). In contrast, the scan pulses Vout2, Vout4, Vout6, ... outputted from the even-numbered stages ST802, ST804, ST806, ... are not only corresponding gate lines (excellent gate lines), but also front stages. And the next stage.

To this end, the output terminal (source terminal) of the pull-up switching device Tru provided in the odd stages ST801, ST803, ST805, ... is connected only to the odd gate line. The output terminal (source terminal) of the pull-up switching device Tru provided in the even-numbered stages ST802, ST804, ST806, ... is connected not only to the even-numbered gate line but also to the preceding stage and the next stage. .

Accordingly, the load applied to the output terminal of the pull-up switching device Tru provided in the even-numbered stages ST802, ST804, ST806,... Is the odd-numbered stages ST801, ST803, ST805, ...) is greater than the load on the output terminal of the pull-up switching device (Tru) provided in.

Then, the distortion degree of the scan pulses Vout2, Vout4, Vout6, ... outputted from the even-numbered stages ST802, ST804, ST806, ... is the odd-numbered stages ST801, ST803, ST805, .. It becomes larger than the distortion degree of the scan pulses (Vout1, Vout3, Vout5, ...) output from.

As a result, a deviation occurs between the magnitudes of the scan pulses Vout1, Vout3, Vout5, ... supplied to the odd-numbered gate line and the scan pulses Vout2, Vout4, Vout6, ... supplied to the even-numbered gate line. Thus, the quality of the image may be degraded.

In order to prevent this, the size of the pull-up switching device Tru provided in the even-numbered stages ST802, ST804, ST806,..., Having a larger load is determined by the odd-numbered stages ST801, ST803, ST805 It is preferable to design larger than the size of the pull-up switching device (Tru) provided in ...).

That is, the width of the channel width of the pull-up switching device Tru provided in the even-numbered stages ST802, ST804, ST806, ... is determined by the odd-numbered stages ST801, ST803, ST805, .. It is preferable to design wider than the channel width of the pull-up switching device (Tru) provided in the.

In this way, the scan pulses Vout2, Vout4, Vout6, ... outputted from the pull-up switching device Tru provided in the even-numbered stages ST802, ST804, ST806, ..., and the odd stage ( The deviation between the scan pulses Vout1, Vout3, Vout5, ... output from the pull-up switching device Tru provided in the ST801, ST803, ST805, ... can be minimized.

The channel width of the pull-up switching device Tru provided in the even-numbered stages ST802, ST804, ST806,... Is the pull-up switching device provided in the odd-numbered stages ST801, ST803, ST805,... Is wider by α than the channel width of Tru).

In this case, α has the following value.

0.1 * {(channel width of first switching element Tr1) * 2 + (channel width of fourth switching element Tr4) * 2} ≤ α ≤ {(channel width of first switching element Tr1) * 2+ (channel width of fourth switching element Tr4) * 2}

Hereinafter, the shift register according to the third embodiment of the present invention will be described in detail.

14 is a diagram illustrating a shift register according to a third exemplary embodiment of the present invention, and FIG. 15 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 14 and an output signal output from each stage.

The shift register according to the third embodiment of the present invention has a plurality of stages ST1401, ST1402, ST1403, ... as shown in FIG.

Here, the configuration of each stage ST1401, ST1402, ST1403, ... is the same as that of the first embodiment, and only this connection relationship is different between the stages ST1401, ST1402, ST1403, .... This will be described. In addition, the shift register according to the third embodiment of the present invention receives the first to fourth clock pulses CLK1 to CLK4. Of course, the shift register according to the second embodiment of the present invention may be supplied with five or more clock pulses.

On the other hand, the start pulse and the first clock pulse CLK1 supplied to the shift register according to the third embodiment of the present invention are output to have a difference of two pulse widths as shown in FIG. 15.

The 2n-1 and 2n stages are simultaneously enabled in response to the 2n-3 scan pulses from the 2n-3 stages and simultaneously disabled in response to the 2n + 1 scan pulses from the 2n + 1 stages. do.

The enabled 2n-1 stage outputs a 2n-1 scan pulse, and supplies the 2n-1 scan pulse to the 2n + 1 and 2n + 2 stages, thereby providing the 2n + 1 and Enable the 2n + 2 stage simultaneously. In addition, the 2n-1 stage simultaneously disables the 2n-3 and 2n-2 stages by supplying the 2n-1 scan pulses to the 2n-3 and 2n-2 stages.

For example, the third stage ST1403 and the fourth stage ST1404 of FIG. 14 are simultaneously enabled in response to the first scan pulse Vout1 from the first stage ST1401, and the fifth stage ST1405. Are simultaneously disabled in response to the fifth scan pulse Vout5 from < RTI ID = 0.0 >

The enabled third stage ST1403 outputs a third scan pulse Vout3, and supplies the third scan pulse Vout3 to the fifth and sixth stages ST1405 and ST1406. And the sixth stages ST1405 and ST1406 at the same time. In addition, the third stage ST1403 simultaneously disables the first and second stages ST1401 and ST1402 by supplying the third scan pulse Vout3 to the first and second stages ST1401 and ST1402. .

On the other hand, the first and second stages ST1401 and ST1402 are enabled in response to the start pulse Vst from the timing controller.

Herein, the configuration of each node controller 1405 provided in each of the stages ST1401, ST1402, ST1403,...

FIG. 16 is a diagram illustrating a circuit configuration of the node controller provided in the third and fourth stages of FIG. 14.

The first to ninth switching elements Tr1 to Tr9 shown in FIG. 16, the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 are shown in FIG. 4. Same as those.

However, the fourth switching device Tr4 provided in the 2n-1 stage and the fourth switching device Tr4 provided in the second nn stage operate in response to the scan pulse from the second n + 1 stage.

For example, the fourth switching device Tr4 provided in the third stage ST1403 of FIG. 16 and the fourth switching device Tr4 provided in the fourth stage ST1404 are formed from the fifth stage ST1405. It operates in response to 5 scan pulses Vout5.

The scan pulse output from the pull-up switching device Tru provided in the 2n-1 stage and the off voltage source output from the first and second pull-down switching devices Trd1 and Trd2 provided in the 2n-1 stage. Is supplied to the 2n-1 gate line, the 2n + 1 stage, the 2n + 2 stage, the 2n-3 stage, and the 2n-2 stage.

For example, the third scan pulse Vout3 output from the pull-up switching device Tru provided in the third stage ST1403 of FIG. 16, and the first and second pulldowns provided in the third stage ST1403. The off voltage sources output from the switching elements Trd1 and Trd2 are supplied to the third gate line, the fifth stage ST1405, the sixth stage ST1406, the first stage ST1401, and the second stage ST1402.

The scan pulse output from the pull-up switching device Tru provided in the 2n stage, and the off voltage sources output from the first and second pull-down switching devices Trd1 and Trd2 provided in the second n stage may include a second gate. Supplied only on the line.

For example, the fourth scan pulse Vout4 output from the pull-up switching device Tru provided in the fourth stage ST1404 of FIG. 16 is, and the first and second scan pulses Vout4 provided in the fourth stage ST1404. The off voltage source output from the pull-down switching devices Trd1 and Trd2 is supplied only to the fourth gate line.

In addition, each stage ST1401, ST1402, ST1403, ... provided in the shift register according to the third embodiment of the present invention may have the following circuit configuration.

FIG. 17 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 14.

The first to ninth switching elements Tr1 to Tr9 and the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 shown in FIG. 17 are those of FIG. 16. Is the same as The tenth and eleventh switching elements Tr10 and Tr11 shown in FIG. 17 are the same as those of FIG. 5.

In addition, each stage ST1401, ST1402, ST1403, ... provided in the shift register according to the third embodiment of the present invention may have the following circuit configuration.

FIG. 18 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 14.

The first to seventh switching elements Tr1 to Tr7 shown in FIG. 18, the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 are shown in FIG. 6. Same as those.

However, the fourth switching device Tr4 provided in the 2n-1 stage and the fourth switching device Tr4 provided in the second nn stage operate in response to the scan pulse from the second n + 1 stage.

For example, the fourth switching device Tr4 provided in the third stage ST1403 of FIG. 18 and the fourth switching device Tr4 provided in the fourth stage ST1404 are formed from the fifth stage ST1405. It operates in response to 5 scan pulses Vout5.

The scan pulse output from the pull-up switching device Tru provided in the 2n-1 stage and the off voltage source output from the first and second pull-down switching devices Trd1 and Trd2 provided in the 2n-1 stage. Is supplied to the 2n-1 gate line, the 2n + 1 stage, the 2n + 2 stage, the 2n-3 stage, and the 2n-2 stage.

For example, the third scan pulse Vout3 output from the pull-up switching device Tru provided in the third stage ST1403 of FIG. 18, and the first and second pulldowns provided in the third stage ST1403. The off voltage sources output from the switching elements Trd1 and Trd2 are supplied to the third gate line, the fifth stage ST1405, the sixth stage ST1406, the first stage ST1401, and the second stage ST1402.

The scan pulse output from the pull-up switching device Tru provided in the 2n stage, and the off voltage sources output from the first and second pull-down switching devices Trd1 and Trd2 provided in the second n stage may include a second gate. Supplied only on the line.

For example, the fourth scan pulse Vout4 output from the pull-up switching device Tru provided in the fourth stage ST1404 of FIG. 18 is, and the first and second provided in the fourth stage ST1404. The off voltage source output from the pull-down switching devices Trd1 and Trd2 is supplied only to the fourth gate line.

In addition, each stage ST1401, ST1402, ST1403, ... provided in the shift register according to the third embodiment of the present invention may have the following circuit configuration.

FIG. 19 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 14.

The first to seventh switching elements Tr1 to Tr7 and the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 shown in FIG. 19 are those of FIG. 18. Is the same as The eighth and ninth switching elements Tr8 and Tr9 shown in FIG. 19 are the same as those in FIG.

However, the eighth switching device Tr8 of the 2n-1 and 2n stages operates in response to the 2n + 1 scan pulse from the 2n + 1 stage.

For example, the eighth switching device Tr8 provided in the third and fourth stages ST1403 and ST1404 of FIG. 19 operates in response to the fifth scan pulse Vout5 from the fifth stage ST1405.

Here, each scan pulse Vout2, Vout4, Vout6, ... output from the even-numbered stages ST1402, ST1404, ST1406, ... is supplied only to the corresponding gate line (odd gate line). On the other hand, the scan pulses Vout1, Vout3, Vout5, ... outputted from the odd stages ST1401, ST1403, ST1405, ... are not only the corresponding gate lines (excellent gate lines), but also the preceding stages. And the next stage.

To this end, the output terminal (source terminal) of the pull-up switching device Tru provided in the even-numbered stages ST1402, ST1404, ST1406, ... is connected only to the even-numbered gate line. The output terminal (source terminal) of the pull-up switching device Tru provided in the odd stages ST1401, ST1403, ST1405, ... is connected not only to the odd gate line but also to the front stage and the next stage. .

Accordingly, the load applied to the output terminal of the pull-up switching device Tru provided in the odd stages ST1401, ST1403, ST1405, ... is the even-numbered stages ST1402, ST1404, ST1406,. The load on the output terminal of the pull-up switching element Tru provided in.

Then, the distortion degree of the scan pulses Vout1, Vout3, Vout5, ... output from the odd stages ST1401, ST1403, ST1405, ... is the even-numbered stages ST1402, ST1404, ST1406, .. It is larger than the distortion degree of the scan pulses (Vout2, Vout4, Vout6, ...) output from.

As a result, a deviation occurs between the magnitudes of the scan pulses Vout2, Vout4, Vout6, ... supplied to the even-numbered gate line and the scan pulses Vout1, Vout3, Vout5, ... supplied to the odd-numbered gate line. Thus, the quality of the image may be degraded.

In order to prevent this, the size of the pull-up switching device Tru provided in the odd stages ST1401, ST1403, ST1405,..., Having a larger load is determined by the even-numbered stages ST1402, ST1404, ST1406, It is preferable to design larger than the size of the pull-up switching device (Tru) provided in ...).

That is, the channel width of the pull-up switching device Tru provided in the odd stages ST1401, ST1403, ST1405,... It is desirable to design wider than the channel width of the element Tru.

In this way, the scan pulses Vout1, Vout3, Vout5, ... outputted from the pull-up switching device Tru provided in the odd stages ST1401, ST1403, ST1405, ..., and the even-numbered stage ( The deviation between the scan pulses Vout2, Vout4, Vout6, ... outputted from the pull-up switching device Tru provided in the ST1402, ST1404, ST1406, ... can be minimized.

The channel width of the pull-up switching device Tru provided in the odd stages ST1401, ST1403, ST1405, ... is the pull-up switching device provided in the even-numbered stages ST1402, ST1404, ST1406, ... Wider by α than the channel width of (Tru).

In this case, α has the following value.

{0.1 * (channel width of the first switching element Tr1) * 2 + (channel width of the fourth switching element Tr4) * 2} ≤ α ≤ {(channel width of the first switching element Tr1) * 2+ (channel width of fourth switching element Tr4) * 2}

Hereinafter, the shift register according to the fourth embodiment of the present invention will be described in detail.

20 is a diagram illustrating a shift register according to a fourth exemplary embodiment of the present invention, and FIG. 21 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 20 and an output signal output from each stage.

The shift register according to the fourth embodiment of the present invention has a plurality of stages (ST2001, ST2002, ST2003, ...) as shown in FIG.

Here, the configuration of each stage ST2001, ST2002, ST2003, ... is the same as that of the first embodiment, and only this connection relationship is different between the stages ST2001, ST2002, ST2003, .... This will be described. In addition, the shift register according to the fourth embodiment of the present invention receives the first to fourth clock pulses CLK1 to CLK4. Of course, the shift register according to the second embodiment of the present invention may be supplied with five or more clock pulses.

The 2n-1 and 2n stages are simultaneously enabled in response to the 2n-2 scan pulses from the 2n-2 stages and simultaneously disabled in response to the 2n + 1 scan pulses from the 2n + 1 stages. do.

The enabled 2n-1 stage outputs a 2n-1 scan pulse, and supplies the 2n-1 scan pulse to the 2n-3 and 2n-2 stages, thereby providing the 2n-3 and Disable the 2n-2 stage simultaneously.

The enabled 2n stage outputs a 2n scan pulse and simultaneously supplies the 2n + 1 and 2n + 2 stages by supplying the 2n scan pulses to the 2n + 1 and 2n + 2 stages. Enable.

For example, the third stage ST2003 and the fourth stage ST2004 of FIG. 20 are simultaneously enabled in response to the second scan pulse Vout2 from the second stage ST2002, and the fifth stage ST2005. Are simultaneously disabled in response to the fifth scan pulse Vout5 from < RTI ID = 0.0 >

The enabled third stage ST2003 outputs a third scan pulse Vout3, and supplies the third scan pulse Vout3 to the first and second stages ST2001 and ST2002. The first and second stages ST2002 are simultaneously disabled.

The enabled fourth stage ST2004 outputs the fourth scan pulse Vout4, and supplies the fourth scan pulse Vout4 to the fifth and sixth stages ST2005 and ST2006 to provide the fifth scan pulse Vout4. And the sixth stages ST2005 and ST2006 at the same time.

Meanwhile, the first and second stages ST2001 and ST2002 are enabled in response to the start pulse Vst from the timing controller.

Here, the configuration of each node control unit 2005 provided in each of the stages ST2001, ST2002, ST2003, ... will be described in more detail as follows.

FIG. 22 is a diagram illustrating a circuit configuration of the node controller provided in the third and fourth stages of FIG. 20.

The first to ninth switching elements Tr1 to Tr9 shown in FIG. 22, the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 are shown in FIG. 4. Same as those.

However, the first and eighth switching elements Tr1 and Tr8 provided in the 2n-1 stage and the first and eighth switching elements Tr1 and Tr8 provided in the second nn stage are scanned from the 2n-2 stage. It operates in response to a pulse.

For example, the first and eighth switching elements Tr1 and Tr8 provided in the third stage ST2003 of FIG. 22 and the first and eighth switching elements Tr1 and Tr8 provided in the fourth stage ST2004. X is operated in response to the second scan pulse Vout2 from the second stage ST2002.

The fourth switching device Tr4 provided in the 2n-1 stage and the fourth switching device Tr4 provided in the second nn stage operate in response to the scan pulse from the second n + 1 stage.

For example, the fourth switching device Tr4 provided in the third stage ST2003 of FIG. 22 and the fourth switching device Tr4 provided in the fourth stage ST2004 may include the fourth switching device Tr4 from the fifth stage ST2005. It operates in response to 5 scan pulses Vout5.

The scan pulse output from the pull-up switching device Tru provided in the 2n-1 stage and the off voltage source output from the first and second pull-down switching devices Trd1 and Trd2 provided in the 2n-1 stage. Is supplied to the 2n-1 gate line, the 2n-3 stage, and the 2n-2 stage.

For example, the third scan pulse Vout3 output from the pull-up switching device Tru provided in the third stage ST2003 of FIG. 22, and the first and second pulldowns provided in the third stage ST2003. The off voltage sources output from the switching elements Trd1 and Trd2 are supplied to the third gate line, the first stage ST2001, and the second stage ST2002.

The scan pulse output from the pull-up switching device Tru provided in the 2n stage, and the off voltage sources output from the first and second pull-down switching devices Trd1 and Trd2 provided in the second n stage may include a second gate. A line, a second n + 1 stage, and a second n + 2 stage.

For example, the fourth scan pulse Vout4 output from the pull-up switching device Tru provided in the fourth stage ST2004 of FIG. 22, and the first and second pulldowns provided in the fourth stage ST2004. The off voltage sources output from the switching elements Trd1 and Trd2 are supplied to the fourth gate line, the fifth stage ST2005, and the sixth stage ST2006.

In addition, each stage (ST2001, ST2002, ST2003, ...) provided in the shift register according to the fourth embodiment of the present invention may have the following circuit configuration.

FIG. 23 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 20.

The first to ninth switching elements Tr1 to Tr9 and the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 shown in FIG. 23 are those of FIG. 22. Is the same as The tenth and eleventh switching elements Tr10 and Tr11 shown in FIG. 23 are the same as those of FIG. 5.

In addition, each stage (ST2001, ST2002, ST2003, ...) provided in the shift register according to the fourth embodiment of the present invention may have the following circuit configuration.

FIG. 24 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 20.

The first to seventh switching elements Tr1 to Tr7, and the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 shown in FIG. 24 are shown in FIG. 6. Same as those.

However, the first and sixth switching elements Tr1 and Tr6 provided in the 2n-1 stage and the first and sixth switching elements Tr1 and Tr6 provided in the 2n n stage are scanned from the 2n-2 stage. It operates in response to a pulse.

For example, the first and sixth switching elements Tr1 and Tr6 provided in the third stage ST2003 of FIG. 24 and the first and sixth switching elements Tr1 and Tr6 provided in the fourth stage ST2004. X is operated in response to the second scan pulse Vout2 from the second stage ST2002.

The fourth switching device Tr4 provided in the 2n-1 stage and the fourth switching device Tr4 provided in the second nn stage operate in response to the scan pulse from the second n + 1 stage.

For example, the fourth switching device Tr4 provided in the third stage ST2003 of FIG. 24 and the fourth switching device Tr4 provided in the fourth stage ST2004 may include the fourth switching device Tr4 provided from the fifth stage ST2005. It operates in response to 5 scan pulses Vout5.

The scan pulse output from the pull-up switching device Tru provided in the 2n-1 stage and the off voltage source output from the first and second pull-down switching devices Trd1 and Trd2 provided in the 2n-1 stage. Is supplied to the 2n-1 gate line, the 2n-3 stage, and the 2n-2 stage.

For example, the third scan pulse Vout3 output from the pull-up switching device Tru provided in the third stage ST2003 of FIG. 24, and the first and second pulldowns provided in the third stage ST2003. The off voltage sources output from the switching elements Trd1 and Trd2 are supplied to the third gate line, the first stage ST2001, and the second stage ST2002.

The scan pulse output from the pull-up switching device Tru provided in the 2n stage, and the off voltage sources output from the first and second pull-down switching devices Trd1 and Trd2 provided in the second n stage may include a second gate. A line, a second n + 1 stage, and a second n + 2 stage.

For example, the fourth scan pulse Vout4 output from the pull-up switching device Tru provided in the fourth stage ST2004 of FIG. 24, and the first and second pulldowns provided in the fourth stage ST2004. The off voltage sources output from the switching elements Trd1 and Trd2 are supplied to the fourth gate line, the fifth stage ST2005, and the sixth stage ST2006.

In addition, each stage (ST2001, ST2002, ST2003, ...) provided in the shift register according to the fourth embodiment of the present invention may have the following circuit configuration.

FIG. 25 is a diagram illustrating another circuit configuration of the node controller provided in the third and fourth stages of FIG. 20.

The first to seventh switching elements Tr1 to Tr7 and the pull-up switching element Tru, the first pull-down switching element Trd1, and the second pull-down switching element Trd2 shown in FIG. 25 are those of FIG. 24. Is the same as The eighth and ninth switching elements Tr8 and Tr9 shown in FIG. 25 are the same as those in FIG.

However, the eighth switching device Tr8 provided in the 2n-1 stage and the eighth switching device Tr8 provided in the 2nn stage operate in response to the 2n + 1 scan pulses from the 2n + 1 stage. .

For example, the eighth switching device Tr8 provided in the third stage ST2003 of FIG. 25 and the eighth switching device Tr8 provided in the fourth stage ST2004 may be separated from the fifth stage ST2005. It operates in response to the fifth scan pulse Vout5.

Hereinafter, the shift register according to the fifth embodiment of the present invention will be described.

26 is a diagram illustrating a shift register according to a fifth embodiment of the present invention.

The shift register according to the fifth embodiment of the present invention has a plurality of stages (ST2601, ST2602, ST2603, ...), Figure 26 shows the first to third of the stage (ST2601 to ST2603) Drawing.

As illustrated in FIG. 26, each stage ST2601, ST2602, ST2603,..., Each of the enable node Q, a pull-up switching device Tru connected to the enable node Q, and a first node are provided. Disable node QB1, a first pull-down switching device Trd1 connected to the first disable node QB1, a second disable node QB2, and a second disable node QB2. A second pull-down switching device Trd2 connected to the third node, the third disable node QB3, and a third pull-down switching device Trd3 connected to the third disable node QB3.

Here, the node controller 2605 provided in the 2n-3 stage controls the charge / discharge states of the enable node Q and the first disable node QB1 provided in the 2n-3 stage. And controls the charge / discharge state of the first disable node QB1 provided in the 2n-2 stage, and controls the charge / discharge state of the first disable node QB1 provided in the 2n-1 stage. To control.

The node control unit 2605 provided in the second n-2 stage controls the charging / discharging states of the enable node Q and the second disable node QB2 provided in the second n-2 stage. And control a charge / discharge state of the second disable node QB2 provided in the 2n-3 stage, and charge / discharge the second disable node QB2 provided in the 2n-1 stage. Control the state.

The node control unit 2605 provided in the 2n-1 stage controls the charge / discharge states of the enable node Q and the third disable node Q provided in the 2n-1 stage. And control the charge / discharge state of the third disable node Q provided in the second n-2 stage, and charge / discharge the third disable node Q provided in the second n-3 stage. Control the discharge state.

For example, the first stage ST2601 of FIG. 26 controls the charge / discharge states of the enable node Q and the first disable node QB1 included in the first stage ST2601. The charge / discharge state of the first disable node QB1 provided in the second stage ST2602 is controlled, and the charge / discharge state of the third disable node Q provided in the third stage ST2603 is controlled. To control.

In addition, the node controller 2605 of the second stage ST2602 may determine the charge / discharge states of the enable node Q and the second disable node QB2 included in the second stage ST2602. Control the charge / discharge state of the second disable node QB2 provided in the first stage ST2601, and control the second disable node QB2 provided in the third stage ST2603. To control the charging / discharging status.

In addition, the node controller 2605 of the third stage ST2603 may determine the charge / discharge states of the enable node Q and the third disable node Q provided in the third stage ST2603. And control the charge / discharge state of the third disable node Q provided in the first stage ST2601, and control the third disable node Q provided in the second stage ST2602. To control the charging / discharging status.

Thus, three stages form one block, and each stage (ST2601, ST2602, ST2603, ...) in this block is supplied with an AC voltage source of three phases.

That is, the node control unit 2605 provided in the 2n-3 stage receives the first AC voltage source Vac1 in the 2n-3 frame, and each node control unit provided in the remaining 2n-2 and 2n-1 stages is provided. 2605 is supplied with a second AC voltage source Vac2.

In addition, the node controller 2605 provided in the 2n-2 stage receives the first AC voltage source Vac1 in the 2n-2 frame, and the remaining 2n-3 and 2n-1 stages receive the second AC voltage source ( Supplied with Vac2).

In addition, the node controller 2605 provided in the 2n-1 stage receives the first AC voltage source Vac1 in the 2n-1 frame, and the remaining 2n-3 and 2n-2 stages receive the second AC voltage source ( Supplied with Vac2).

In the shift register according to the fifth embodiment of the present invention configured as described above, each stage ST2601, ST2602, ST2603, ... may have any one of the circuit configurations of the first embodiment described above.

Hereinafter, the shift register according to the sixth embodiment of the present invention will be described.

27 is a diagram illustrating a shift register according to a sixth embodiment of the present invention, and FIG. 28 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 27 and an output signal output from each stage.

The shift register according to the sixth embodiment of the present invention has a plurality of stages ST2701, ST2702, ST2703, ... as shown in FIG.

Here, the configuration of each stage ST2701, ST2702, ST2703, ... is the same as that of the first embodiment, and only this connection relationship is different between the stages ST2701, ST2702, ST2703, .... This will be described.

In addition, the shift register according to the sixth embodiment of the present invention receives the first to fourth clock pulses CLK1 to CLK4. Of course, the shift register according to the sixth embodiment of the present invention may be supplied with five or more clock pulses.

The node controller 2705 provided in the nth stage controls the logic states of the enable node Q, the first disable node QB1, and the second disable node QB2 of the nth stage. do.

In addition, the node controller 2705 provided in the nth stage controls the logic state of the second disable node QB2 of the nth-1th stage.

In addition, the node controller 2705 provided in the nth stage controls the logic state of the first disable node QB1 of the n + 1th stage.

To this end, the first disabling node QB and the second disabling node QB2 of adjacent stages are electrically connected to each other.

That is, the first disable node QB1 of the nth stage and the second disable node QB2 of the n-1th stage are electrically connected to each other, and the second disable node of the nth stage ( QB2) and the node QB1 for the first disable of the n + 1th stage are electrically connected to each other.

On the other hand, the stage does not exist in front of the first stage ST2701. Accordingly, the node controller 2705 of the first stage ST2701 may include the enable node Q, the first disable node QB1, and the second disable provided in the first stage ST2701. In addition to controlling the node QB2, the logic state of the first disable node QB1 of the second stage ST2702 is controlled.

Each stage charges its enabling node Q to the first DC voltage source Vdc1 in response to the scan pulse from the preceding stage, and for its first disable node QB1 and second disable. The node QB2 is discharged to the second DC voltage source Vdc2.

That is, the nth stage charges the enabling node Q of the nth stage to the first DC voltage source Vdc1 in response to the n-1th scan pulse from the n-1th stage, and the nth stage The first disable node QB1 and the second disable node QB2 are discharged to the second DC voltage source Vdc2.

Each stage discharges its enable node Q to the second DC voltage source Vdc2 in response to the scan pulse from the next stage, and the first disable node QB1 and the second disable node Qdc. One of the disable nodes QB2 is charged or discharged.

That is, the nth stage discharges the enable node Q of the nth stage to the second DC voltage source Vdc2 in response to the n + 1 scan pulse from the n + 1th stage, and the nth stage One of the first disable node QB1 and the second disable node QB2 is charged.

At this time, when the stages are disabled, the odd-numbered stages ST2701, ST2703, ST2705,..., Charge or discharge their first disable node QB1 by using a first AC voltage source Vac1. The even-numbered stages ST2702, ST2704, ST2706,... Charge or discharge their first disable node QB1 using the second AC voltage source Vac2.

The operation of the shift register having the stage configured as described above is as follows.

First, the operation during the first frame period will be described with reference to FIG. 28A. During the first frame period, the first AC voltage source Vac1 is kept high (positive polarity) and the second AC voltage source Vac2 is kept low (negative polarity).

In the initial period T0, the first stage ST2701 is enabled by the start pulse Vst from the timing controller. That is, in the initial period T0, the enabling node Q of the first stage ST2701 is charged with the first DC voltage source Vdc1 and the first and second disable nodes QB1 and QB2. Is discharged to the second DC voltage source Vdc2.

Accordingly, in the initial period T0, the pull-up switching device Tru included in the first stage ST2701 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned off. do.

Meanwhile, since the second disable node QB2 of the first stage ST2701 and the first disable node QB1 of the second stage ST2702 are electrically connected to each other, the first stage ST2701 The second disable node QB2 and the first disable node QB1 of the second stage ST2702 are discharged to the same voltage. That is, in the initial period T0, the first disable node QB1 of the second stage ST2702 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the first stage ST2701 is charged in the initial period T0. The first and second disable nodes QB1 and QB2 of the first stage ST2701 and the first disable node QB1 of the second stage ST2702 are discharged.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Tru provided in the first stage ST2701 in the first period T1. Then, the pull-up switching device Tru outputs the first scan pulse Vout1 and supplies it to the first gate line and the second stage ST2702.

Accordingly, the first gate line is driven in the first period T1, and the second stage ST2702 is enabled.

That is, the enable node Q of the second stage ST2702 is charged with the first DC voltage source Vdc1, and the first and second disable nodes QB1 and QB2 of the second stage ST2702 are charged. ) Is discharged to the second DC voltage source Vdc2.

Accordingly, in the first period T1, the pull-up switching device Tru included in the first stage ST2701 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. Is off.

On the other hand, since the second disable node QB2 of the second stage ST2702 and the first disable node QB1 of the third stage ST2703 are electrically connected to each other, the second stage ST2702 The second disable node QB2 and the first disable node QB1 of the third stage ST2703 are discharged to the same voltage. That is, in the first period T1, the first disable node QB1 of the third stage ST2703 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the second stage ST2702 is charged in the first period T1. The first and second disable nodes QB1 and QB2 of the second stage ST2702 and the first disable node QB1 of the third stage ST2703 are discharged.

Thereafter, in the second period T2, the second clock pulse CLK2 is supplied to the pull-up switching device Tru provided in the second stage ST2702. Then, the pull-up switching device Tru outputs the second scan pulse Vout2 and supplies it to the second gate line, the third stage ST2703, and the first stage ST2701.

Accordingly, the second gate line is driven in the second period T2, and the third stage ST2703 is enabled. In addition, the first stage ST2701 is disabled. That is, the enable node Q and the second disable node QB2 of the first stage ST2701 are discharged to the second DC voltage source Vdc2, and the first disc of the first stage ST2701 is discharged. The enable node QB1 is charged with the first AC voltage source Vac1. In other words, the first AC voltage source Vac1 is supplied to the first stage ST2701 which is the odd stage ST2701, ST2703, ST2705, ..., which is used during the first frame period. Since it is a high state, when the first stage ST2701 is disabled, only the first disable node QB1 of the first stage ST2701 remains in a charged state.

In summary, the enable node Q of the third stage ST2703 is charged in the second period T2. The first and second disable nodes QB1 and QB2 of the third stage ST2703 and the first disable node QB1 of the fourth stage ST2704 are discharged. In addition, the enable node Q and the second disable node QB2 of the first stage ST2701 are discharged, and the first disable node QB1 is charged.

Thereafter, the third clock pulse CLK3 is supplied to the pull-up switching device Tru provided in the third stage ST2703 in the third period T3. Then, the pull-up switching device Tru outputs the third scan pulse Vout3 and supplies it to the third gate line, the fourth stage ST2704, and the second stage ST2702.

Accordingly, the third gate line is driven in the third period T3 and the fourth stage ST2704 is enabled. In addition, the second stage ST2702 is disabled. That is, all of the enable node Q, the first disable node QB1, and the second disable node QB2 of the second stage ST2702 are discharged. In other words, the second AC voltage source Vac2 is supplied to the second stage ST2702 which is the even-numbered stages ST2702, ST2704, ST2706,..., Which is supplied during the first frame period. Since the state is low, all the nodes Q, QB1, and QB2 of the second stage ST2702 are discharged when the second stage ST2702 is disabled.

In summary, the enable node Q of the fourth stage ST2704 is charged in the third period T3. The first and second disable nodes QB1 and QB2 of the fourth stage ST2704 and the first disable node QB1 of the fifth stage ST2705 are discharged. In addition, all the nodes Q, QB1, and QB2 of the second stage ST2702 are discharged.

Thereafter, the fourth clock pulse CLK4 is supplied to the pull-up switching device Tru provided in the fourth stage ST2704 in the fourth period T4. Then, the pull-up switching device Tru outputs the fourth scan pulse Vout4 and supplies it to the fourth gate line, the fifth stage ST2705, and the third stage ST2703.

Accordingly, the fourth gate line is driven in the fourth period T4 and the fifth stage ST2705 is enabled. In addition, the third stage ST2703 is disabled. That is, the enable node Q and the second disable node QB2 of the third stage ST2703 are discharged, and the second disable node QB2 is charged. In other words, the first AC voltage source Vac1 is supplied to the third stage ST2703 which is the odd-numbered stages ST2701, ST2703, ST2705, ..., during the first frame period. Since the state is high, when the third stage ST2703 is disabled, only the first disable node QB1 of the third stage ST2703 is maintained in the charged state.

In this case, as the first disable node QB1 of the third stage ST2703 is changed to a charged state in the fourth period T4, the first disable node of the third stage ST2703 ( The second disable node QB2 of the second stage ST2702 connected to QB1 is also changed from a discharge state to a charged state.

In summary, the enable node Q of the fifth stage ST2705 is charged in the fourth period T4. The first and second disable nodes QB1 and QB2 of the fifth stage ST2705 and the first disable node QB1 of the sixth stage ST2706 are discharged. Further, the first disable node QB1 of the third stage ST2703 and the second disable node QB2 of the second stage ST2702 are charged.

In this manner, the odd stages ST2701, ST2703, ST2705, ... in the first frame period perform the disable operation by charging their first disable node QB1.

In the first frame period, even-numbered stages ST2702, ST2704, ST2706, ... discharge all their nodes Q, QB1, and QB2 to perform the disable operation. At this time, the second disable node QB2 of the even-numbered stages ST2702, ST2704, ST2706,..., The discs of the odd-numbered stages ST2701, ST2703, ST2705,... The change from the discharge state to the charge state is made by the enable operation.

 Next, an operation during the second frame period will be described with reference to FIG. 28B. During the second frame period, the first AC voltage source Vac1 is kept low (negative polarity) and the second AC voltage source Vac2 is kept high (positive polarity).

In the initial period T0, the first stage ST2701 is enabled by the start pulse Vst from the timing controller. That is, in the initial period T0, the enabling node Q of the first stage ST2701 is charged with the first DC voltage source Vdc1 and the first and second disable nodes QB1 and QB2. Is discharged to the second DC voltage source Vdc2.

Accordingly, in the initial period T0, the pull-up switching device Tru included in the first stage ST2701 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned off. do.

Meanwhile, since the second disable node QB2 of the first stage ST2701 and the first disable node QB1 of the second stage ST2702 are electrically connected to each other, the first stage ST2701 The second disable node QB2 and the first disable node QB1 of the second stage ST2702 are discharged to the same voltage. That is, in the initial period T0, the first disable node QB1 of the second stage ST2702 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the first stage ST2701 is charged in the initial period T0. The first and second disable nodes QB1 and QB2 of the first stage ST2701 and the first disable node QB1 of the second stage ST2702 are discharged.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Tru provided in the first stage ST2701 in the first period T1. Then, the pull-up switching device Tru outputs the first scan pulse Vout1 and supplies it to the first gate line and the second stage ST2702.

Accordingly, the first gate line is driven in the first period T1, and the second stage ST2702 is enabled.

That is, the enable node Q of the second stage ST2702 is charged with the first DC voltage source Vdc1, and the first and second disable nodes QB1 and QB2 of the second stage ST2702 are charged. ) Is discharged to the second DC voltage source Vdc2.

Accordingly, in the first period T1, the pull-up switching device Tru included in the first stage ST2701 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. Is off.

On the other hand, since the second disable node QB2 of the second stage ST2702 and the first disable node QB1 of the third stage ST2703 are electrically connected to each other, the second stage ST2702 The second disable node QB2 and the first disable node QB1 of the third stage ST2703 are discharged to the same voltage. That is, in the first period T1, the first disable node QB1 of the third stage ST2703 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the second stage ST2702 is charged in the first period T1. The first and second disable nodes QB1 and QB2 of the second stage ST2702 and the first disable node QB1 of the third stage ST2703 are discharged.

Thereafter, in the second period T2, the second clock pulse CLK2 is supplied to the pull-up switching device Tru provided in the second stage ST2702. Then, the pull-up switching device Tru outputs the second scan pulse Vout2 and supplies it to the second gate line, the third stage ST2703, and the first stage ST2701.

Accordingly, the second gate line is driven in the second period T2, and the third stage ST2703 is enabled. In addition, the first stage ST2701 is disabled. That is, all the nodes Q, QB1, and QB2 of the first stage ST2701 are discharged. In other words, the first AC voltage source Vac1 is supplied to the first stage ST2701 which is the odd stage ST2701, ST2703, ST2705, ..., during the second frame period. Since the state is low, all nodes Q, QB1, and QB2 of the first stage ST2701 are discharged when the first stage ST2701 is disabled.

In summary, the enable node Q of the third stage ST2703 is charged in the second period T2. The first and second disable nodes QB1 and QB2 of the third stage ST2703 and the first disable node QB1 of the fourth stage ST2704 are discharged. In addition, all the nodes Q, QB1, and QB2 of the first stage ST2701 are charged.

Thereafter, the third clock pulse CLK3 is supplied to the pull-up switching device Tru provided in the third stage ST2703 in the third period T3. Then, the pull-up switching device Tru outputs the third scan pulse Vout3 and supplies it to the third gate line, the fourth stage ST2704, and the second stage ST2702.

Accordingly, the third gate line is driven in the third period T3 and the fourth stage ST2704 is enabled. In addition, the second stage ST2702 is disabled. That is, the enable node Q and the second disable node QB2 of the second stage ST2702 are discharged, and the first disable node QB1 is charged. In other words, a second AC voltage source Vac2 is supplied to the second stage ST2702 which is the even-numbered stages ST2702, ST2704, ST2706,... Which is supplied during the second frame period. Since it is a high state, when the second stage ST2702 is disabled, only the first disable node QB1 of the second stage ST2702 is charged.

At this time, as the first disable node QB1 of the second stage ST2702 is changed to a charged state in the third period T3, the first disable node of the second stage ST2702 ( The second disable node QB2 of the first stage ST2701 connected to QB1 is also changed from a discharge state to a charged state.

In summary, the enable node Q of the fourth stage ST2704 is charged in the third period T3. The first and second disable nodes QB1 and QB2 of the fourth stage ST2704 and the first disable node QB1 of the fifth stage ST2705 are discharged. Further, the first disable node QB1 of the second stage ST2702 and the second disable node QB2 of the first stage ST2701 are charged.

Thereafter, the fourth clock pulse CLK4 is supplied to the pull-up switching device Tru provided in the fourth stage ST2704 in the fourth period T4. Then, the pull-up switching device Tru outputs the fourth scan pulse Vout4 and supplies it to the fourth gate line, the fifth stage ST2705, and the third stage ST2703.

Accordingly, the fourth gate line is driven in the fourth period T4 and the fifth stage ST2705 is enabled. In addition, the third stage ST2703 is disabled. That is, all of the enable node Q, the first disable node QB1, and the second disable node QB2 of the third stage ST2703 are discharged. In other words, the first AC voltage source Vac1 is supplied to the third stage ST2703 which is the odd-numbered stages ST2701, ST2703, ST2705, ..., during the second frame period. Since the state is low, all the nodes Q, QB1, and QB2 of the third stage ST2703 are discharged when the third stage ST2703 is disabled.

In summary, the enable node Q of the fifth stage ST2705 is charged in the fourth period T4. The first and second disable nodes QB1 and QB2 of the fifth stage ST2705 and the first disable node QB1 of the sixth stage ST2706 are discharged. In addition, all the nodes Q, QB1, QB2 of the third stage ST2703 are discharged.

In this manner, the even-numbered stages ST2702, ST2704, ST2706, ... in the second frame period perform the disable operation by charging their first disable node QB1.

In the second frame period, the odd-numbered stages ST2701, ST2703, ST2705, ... discharge all their nodes Q, QB1, and QB2 to perform the disable operation. At this time, the second disable node QB2 of the odd stages ST2701, ST2703, ST2705, ... is the disc of the even-numbered stages ST2702, ST2704, ST2706,. The change from the discharge state to the charge state is made by the enable operation.

Here, the configuration of each node control unit 2705 provided in each stage will be described in more detail as follows.

29A and 29B are diagrams illustrating a circuit configuration of the node controller provided in the first to fourth stages of FIG. 27.

First, the node controller 2705 provided in each stage has first to ninth switching elements Tr1 to Tr9, as illustrated in FIGS. 29A and 29B.

That is, the first switching device Tr1 provided in the n-th stage is turned on or off according to the logic state of the scan pulse from the n-th stage, and when turned on, the first switching element Tr1 is turned on. The first DC voltage source Vdc1 is supplied to the node Q for the enable.

For example, the first switching device Tr1 included in the third stage ST2703 of FIG. 29B is turned on or turned on depending on the logic state of the second scan pulse Vout2 from the second stage ST2702. When turned off, the first DC voltage source Vdc1 is supplied to the enabling node Q of the third stage ST2703 at turn-on.

To this end, the gate terminal of the first switching device Tr1 provided in the third stage ST2703 is connected to the output terminal of the first stage ST2701, and the drain terminal transmits the first DC voltage source Vdc1. The source terminal is connected to the enable node Q of the third stage ST2703.

The second switching device Tr2 provided in the nth stage is turned on or turned off according to the logic state of the signal supplied to the first disable node QB1 of the nth stage. The second DC voltage source Vdc2 is supplied to the enabling node Q of the n stage.

For example, the second switching device Tr2 included in the third stage ST2703 of FIG. 29B may be based on a logic state of a signal supplied to the first disable node QB1 of the third stage ST2703. It is turned on or turned off, and when turned on, the second DC voltage source Vdc2 is supplied to the enabling node Q of the third stage ST2703.

For this purpose, the gate terminal of the second switching element Tr2 provided in the third stage ST2703 is connected to the first disable node QB1 of the third stage ST2703, and the drain terminal of the third stage ST2703 It is connected to the enable node Q of the stage ST2703, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The third switching device Tr3 provided in the nth stage is turned on or turned off according to the logic state of the signal supplied to the second disable node QB2 of the nth stage. The second DC voltage source Vdc2 is supplied to the enabling node Q of the nth stage.

For example, the third switching device Tr3 included in the third stage ST2703 of FIG. 29B may be based on a logic state of a signal supplied to the second disable node QB2 of the third stage ST2703. It is turned on or turned off, and when turned on, the second DC voltage source Vdc2 is supplied to the enabling node Q of the third stage ST2703.

To this end, the gate terminal of the third switching element Tr3 provided in the third stage ST2703 is connected to the second disable node QB2 of the third stage ST2703, and the drain terminal of the third stage ST2703 is connected to the second disable node QB2. It is connected to the enabling node Q of the three stages ST2703, and the source terminal is connected to a power supply line for transmitting the second DC voltage source Vdc2.

The fourth switching device Tr4 provided in the nth stage is turned on or turned off according to the logic state of the scan pulse from the n + 1th stage, and is enabled for the nth stage. The second DC voltage source Vdc2 is supplied to the node Q.

For example, the fourth switching device Tr4 included in the third stage ST2703 of FIG. 29B is turned on or turned on according to the logic state of the fourth scan pulse Vout4 from the fourth stage ST2704. When turned off, the second DC voltage source Vdc2 is supplied to the enabling node Q of the third stage ST2703 at turn-on.

To this end, the gate terminal of the fourth switching device Tr4 provided in the third stage ST2703 is connected to the output terminal of the fourth stage ST2704, and the drain terminal of the third stage ST2703 is It is connected to the enable node Q, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The fifth switching device Tr5 provided in the n-th stage is turned on or turned off according to the logic state of the first AC voltage source Vac1 (or the second AC voltage source Vac2), and is common during turn-on. The first AC voltage source Vac1 (or the second AC voltage source Vac2) is supplied to the node N.

For example, the fifth switching device Tr5 provided in the third stage ST2703 of FIG. 29B is turned on or turned off according to the logic state of the first AC voltage source Vac1, and when turned on, the third switching device Tr5 is turned on. The first AC voltage source Vac1 is supplied to the common node N of the stage ST2703.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the third stage ST2703 are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal of the third stage ST2703 is connected to the power supply line. It is connected to the common node N of the stage ST2703.

The sixth switching device Tr6 provided in the nth stage is turned on or turned off according to a logic state of a signal supplied to the enabling node Q of the nth stage, The second DC voltage source Vdc2 is supplied to the common node N.

For example, the sixth switching device Tr6 included in the third stage ST2703 of FIG. 29B is turned in accordance with the logic state of the signal supplied to the enabling node Q of the third stage ST2703. It is turned on or turned off, and supplies a second DC voltage source Vdc2 to the common node N at turn-on.

To this end, the gate terminal of the sixth switching device Tr6 provided in the third stage ST2703 is connected to the enable node Q of the third stage ST2703, and the drain terminal of the third stage ST2703 is connected to the enable node Q. It is connected to the common node N of ST2703, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The seventh switching device Tr7 provided in the nth stage is turned on or off according to a logic state of a signal supplied to the common node N of the nth stage, and when turned on, the nth stage The first AC voltage source Vac1 (or the second AC voltage source Vac2) is supplied to the first disable node QB1.

For example, the seventh switching device Tr7 included in the third stage ST2703 of FIG. 29B may be turned on or turned on according to a logic state of a signal supplied to the common node N of the third stage ST2703. It is turned off and supplies a first AC voltage source Vac1 to the first disable node QB1 of the third stage ST2703 when it is turned on.

To this end, the gate terminal of the seventh switching element Tr7 provided in the third stage ST2703 is connected to the common node N of the third stage ST2703, and the drain terminal thereof is the first AC voltage source. Vac1) is connected to the power supply line, and the source terminal is connected to the first disable node QB1 of the third stage ST2703.

The eighth switching device Tr8 provided in the nth stage is turned on or off according to the logic state of the scan pulse from the n-1th stage, and when turned on, the second disable of the nth stage is disabled. The second DC voltage source Vdc2 is supplied to the dragon node QB2.

For example, the eighth switching device Tr8 included in the third stage ST2703 of FIG. 29B is turned on or turned on depending on the logic state of the second scan pulse Vout2 from the second stage ST2702. When turned off, the second DC voltage source Vdc2 is supplied to the second disable node QB2 of the third stage ST2703.

To this end, the gate terminal of the eighth switching device Tr8 of the third stage ST2703 is connected to the output terminal of the first stage ST2701, and the drain terminal of the eighth switching element T270 is connected to the output terminal of the third stage ST2703. 1 is connected to the disable node (QB1), the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The ninth switching device Tr9 provided in the nth stage is turned on or turned off according to the logic state of the signal supplied to the enable node Q of the nth stage, The second DC voltage source Vdc2 is supplied to the first disable node QB1 of the n stage.

For example, the ninth switching device Tr9 of the third stage ST2703 of FIG. 29B is turned on in accordance with the logic state of the signal supplied to the enabling node Q of the third stage ST2703. On or off, the second DC voltage source Vdc2 is supplied to the first disable node QB1 of the third stage ST2703 during turn-on.

To this end, the gate terminal of the ninth switching element Tr9 provided in the third stage ST2703 is connected to the enable node Q of the third stage ST2703, and the drain terminal of the third stage ST2703 It is connected to the first disable node QB1 of ST2703, and a source terminal is connected to a power supply line for transmitting the second DC voltage source Vdc2.

On the other hand, since the stage does not exist in front of the first stage ST2701, the first and eighth switching elements Tr1 and Tr8 included in the first stage ST2701 receive the start pulse Vst from the timing controller. Supply is turned on or off.

The first AC voltage source Vac1 is supplied to the fifth switching device Tr5 provided in the odd stages ST2701, ST2703, ST2705, ... among the stages, and the even-numbered stages ST2702, ST2704, The second AC voltage source Vac2 is supplied to the fifth switching device Tr5 provided in ST2706, ...).

The operation of the shift register having stages to which such a circuit configuration is applied is as follows.

First, the operation during the first frame period will be described with reference to FIGS. 28A, 29A, and 29B. During the first frame period, the first AC voltage source Vac1 is kept high and the second AC voltage source Vac2 is kept low.

On the other hand, the clock pulses, the start pulses Vst, and the scan pulses show high states unless otherwise stated in the following description.

During the initial period T0, as shown in FIG. 28A, only the start pulse Vst output from the timing controller is kept high and the remaining clock pulses are kept low.

The start pulse Vst output from the timing controller is input to the first stage ST2701.

That is, the start pulse Vst is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the eighth switching element Tr8 provided in the first stage ST2701.

Then, the first and eighth switching devices Tr1 and Tr8 are turned on, and at this time, the first DC voltage source Vdc1 is enabled through the turned-on first switching device Tr1. Is applied. Accordingly, the enable node Q is charged, and the pull-up switching device Tru, the sixth switching device Tr6, and the ninth switching device having a gate terminal connected to the charged enable node Q. Element Tr9 is turned on.

Here, the second DC voltage source Vdc2 is supplied to the first disable node QB1 through the turned-on ninth switching element Tr9, and the switch is turned on through the turned-on eighth switching element Tr8. 2 DC voltage source Vdc2 is supplied to the second disable node QB2.

Therefore, the first and second disable nodes QB1 and QB2 of the first stage ST2701 are discharged by the second DC voltage source Vdc2.

Accordingly, the second switching device Tr2 and the first pull-down switching device Trd1 having the gate terminal connected to the first disable node QB1 are turned off, and the second disable node QB2 is turned off. ), The third switching device Tr3 and the second pull-down switching device Trd2 having the gate terminal connected thereto are turned off.

On the other hand, since the first AC voltage source Vac1 is kept high for the first frame period, the fifth switching device Tr5 of the first stage ST2701 supplied with the first AC voltage source Vac1 is formed in the fifth state. It remains turned on for one frame period. The first AC voltage source Vac1 is supplied to the common node N of the first stage ST2701 through the turned-on fifth switching device Tr5.

In addition, a second DC voltage source Vdc2 output through the turned-on sixth switching device Tr6 is also supplied to the common node N of the first stage ST2701. That is, the first AC voltage source Vac1 in the high state and the second DC voltage source Vdc2 in the low state are simultaneously supplied to the common node N of the first stage ST2701.

However, the channel width of the sixth switching device Tr6 for supplying the second DC voltage source Vdc2 is set larger than the channel width of the fifth switching device Tr5 for supplying the first AC voltage source Vac1. The common node N of the first stage ST2701 is maintained as the second DC voltage source Vdc2. Accordingly, the common node N is discharged, and the seventh switching element Tr7 of the first stage ST2701 having the gate terminal connected to the discharged common node N is turned off.

As described above, the first stage ST2701 charges its enable node Q in response to the start pulse Vst, and charges its own first and second disable nodes QB1 and QB2. Discharge. That is, the first stage ST2701 is enabled.

Here, since the second disable node QB2 of the first stage ST2701 and the first disable node QB1 of the second stage ST2702 are connected to each other, the second disable node QB2 is connected to the initial period T0. The first disable node QB1 of the second stage ST2702 is also discharged to the second DC voltage source Vdc2.

The operation during the first period T1 will now be described.

In the first period T1, as shown in FIG. 28A, only the first clock pulse CLK1 represents a high state, and the start pulse Vst and the remaining clock pulses represent a low state.

Here, as the enabling node Q of the first stage ST2701 is kept charged by the first DC voltage source Vdc1 applied during the first initial period T0A, the first stage The pull-up switching device Tru of ST2701 maintains a turn-on state.

In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Tru, a first DC charged in the enable node Q of the first stage ST2701. The voltage source Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Tru of the first stage ST2701 is stably output through the source terminal of the pull-up switching device Tru. In this case, the output first clock pulse CLK1 functions as a first scan pulse Vout1 applied to the first gate line to drive the first gate line.

The first scan pulse Vout1 output from the first stage ST2701 in the first period T1 is also input to the second stage ST2702. Specifically, as shown in FIG. 29A, the first scan pulse Vout1 is input to the gate terminals of the first and eighth switching elements Tr1 and Tr8 provided in the third stage ST2703.

Then, the first and eighth switching devices Tr1 and Tr8 are turned on, and the first DC voltage source Vdc1 is turned on through the turned-on first switching device Tr1 to the second stage ST2702. Is applied to the enabling node Q of. Accordingly, the enable node Q is charged, and the pull-up switching device Tru, the sixth switching device Tr6, and the ninth switching device having a gate terminal connected to the charged enable node Q. Element Tr9 is turned on.

Here, the second DC voltage source Vdc2 is supplied to the first disable node QB1 through the turned-on ninth switching element Tr9, and the switch is turned on through the turned-on eighth switching element Tr8. 2 DC voltage source Vdc2 is supplied to the second disable node QB2.

Therefore, the first and second disable nodes QB1 and QB2 of the second stage ST2702 are discharged by the second DC voltage source Vdc2.

Accordingly, the second switching device Tr2 and the first pull-down switching device Trd1 having the gate terminal connected to the first disable node QB1 are turned off, and the second disable node QB2 is turned off. ), The third switching device Tr3 and the second pull-down switching device Trd2 having the gate terminal connected thereto are turned off.

Meanwhile, since the second AC voltage source Vac2 is kept low for the first frame period, the fifth switching device Tr5 of the second stage ST2702 supplied with the second AC voltage source Vac2 is formed in the second state. The turn-off state is maintained for one frame period.

In addition, the second DC voltage source Vdc2 output through the turned-on sixth switching device Tr6 is supplied to the common node N of the second stage ST2702. Accordingly, the common node N of the second stage ST2702 is discharged by the second DC voltage source Vdc2. Therefore, the seventh switching element Tr7 of the second stage ST2702 having the gate terminal connected to the discharged common node N is turned off.

As such, in the first period T1, the second stage ST2702 charges its enable node Q in response to the start pulse Vst, and disables its first and second disables. The discharge nodes QB1 and QB2 are discharged.

Here, the second disable node QB2 of the second stage ST2702 and the first disable node QB1 of the third stage ST2703 are connected to each other, and thus, in the first period T1. The first disable node QB1 of the third stage ST2703 is also discharged to the second DC voltage source Vdc2.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in Fig. 28A, only the second clock pulse CLK2 remains high. The start pulse Vst, the first scan pulse Vout1, and the remaining clock pulses remain low.

The second clock pulse CLK2 is supplied to the second stage ST2702. In detail, the second clock pulse CLK2 is supplied to the drain terminal of the pull-up switching device Tru provided in the second stage ST2702. Therefore, the pull-up switching device Tru provided in the second stage ST2702 outputs the second clock pulse CLK2 as the second scan pulse Vout2. The second scan pulse Vout2 is supplied to the second gate line to drive the second gate line.

In addition, the second scan pulse Vout2 output from the second stage ST2702 in the second period T2 is also supplied to the third stage ST2703 and the first stage ST2701.

The second scan pulse Vout2 supplied to the third stage ST2703 enables the third stage ST2703 in the manner described above. That is, the enable node Q of the third stage ST2703 is charged, and the first and second disable nodes QB1 and QB2 are discharged. At this time, as the second disable node QB2 of the third stage ST2703 is discharged, the fourth stage ST2704 connected to the second disable node QB2 of the third stage ST2703. The first disable node QB1 of is also discharged.

In addition, the second scan pulse Vout2 supplied to the first stage ST2701 disables the first stage ST2701. The disable operation of the first stage ST2701 which is the odd stage ST2701, ST2703, ST2705, ... will be described in detail as follows.

That is, the second scan pulse Vout2 output from the second stage ST2702 in the second period T2 is supplied to the first stage ST2701. Specifically, the second scan pulse Vout2 is supplied to the gate terminal of the fourth switching device Tr4 provided in the first stage ST2701. Then, the fourth switching device Tr4 is turned on, and the second DC voltage source Vdc2 is enabled for the node of the first stage ST2701 through the turned-on fourth switching device Tr4. It is supplied to (Q).

Accordingly, the enable node Q is discharged and the pull-up switching device Tru and the sixth switching device Tr6 of the first stage ST2701 having a gate terminal connected to the discharged enabling node Q. And the ninth switching element Tr9 are all turned off.

As the sixth switching device Tr6 is turned off, the first AC voltage source Vac1 output through the fifth switching device Tr5 is supplied to the common node N of the first stage ST2701. . Accordingly, the common node N of the first stage ST2701 is charged, and the seventh switching element Tr7 of the first stage ST2701 having the gate terminal connected to the charged common node N is Is turned on.

The first AC voltage source Vac1 is supplied to the first disable node QB1 of the first stage ST2701 through the turned-on seventh switching device Tr7. Then, the first disable node QB1 of the first stage ST2701 is charged, and the first stage ST2701 of the first stage ST2701 having a gate terminal connected to the charged first disable node QB1. The pull-down switching device Trd1 and the second switching device Tr2 are turned on. The second switching device Tr2 further accelerates the discharge of the enable node Q by supplying a second DC voltage source Vdc2 to the enable node Q of the first stage ST2701. .

As such, the pull-up switching device Tru of the first stage ST2701 is turned off and the first pull-down switching device Trd1 is turned on during the second period T2, thereby the first stage ST2701. Outputs a second DC voltage source Vdc2 through the turned-on first pull-down switching device Trd1. This second DC voltage source Vdc2 serves as an off voltage source that is supplied to the first gate line to deactivate the first gate line.

In summary, the first stage ST2701 discharges its enable node Q in response to the second scan pulses Vout2 and Vout4, and decodes its first disable node QB1. Charge it. That is, the first stage ST2701 is disabled. At this time, the second disable node QB2 of the first stage ST2701 maintains a discharge state.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in FIG. 28A, only the third clock pulse CLK3 remains high. The start pulse Vst, the first scan pulse Vout1, the second scan pulse Vout2, and the remaining clock pulses remain low.

The third clock pulse CLK3 is supplied to the enabled third stage ST2703. Specifically, the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching device Tru provided in the third stage ST2703. Therefore, the pull-up switching device Tru provided in the third stage ST2703 outputs the third clock pulse CLK3 as a third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line, the fourth stage ST2704, and the second stage ST2702.

That is, the third scan pulse Vout3 drives the third gate line, enables the fourth stage ST2704, and disables the second stage ST2702.

Here, the second disable node QB2 of the fourth stage ST2704 and the first disable node QB1 of the fifth stage ST2705 are connected to each other, and thus, in the third period T3. The first disable node QB1 of the fifth stage ST2705 is also discharged to the second DC voltage source Vdc2.

Here, the disable operation of the second stage ST2702 which is the even-numbered stages ST2702, ST2704, ST2706, ... will be described in detail.

That is, the third scan pulse Vout3 output from the third stage ST2703 in the third period T3 is supplied to the second stage ST2702. In detail, the third scan pulse Vout3 is supplied to the gate terminal of the fourth switching device Tr4 provided in the third stage ST2703. Then, the fourth switching device Tr4 is turned on, and the second DC voltage source Vdc2 is enabled through the turned-on fourth switching device Tr4 to enable the node of the third stage ST2703. Q) is supplied.

Accordingly, the enable node Q is discharged and the pull-up switching device Tru and the sixth switching device Tr6 of the third stage ST2703 having a gate terminal connected to the discharged enabling node Q. And the ninth switching element Tr9 are all turned off.

On the other hand, as described above, since the fifth switching device Tr5 provided in the second stay supplied with the second AC voltage source Vac2 is turned off during the first frame period, the second stage ST2702 The common node N is still in a discharged state. Accordingly, the seventh switching device Tr7 having the gate terminal connected to the common node N also maintains the turn-off state. Therefore, the first disable node QB1 of the second stage ST2702 still maintains a discharge state.

As a result, all the nodes Q, QB1 and QB2 of the second stage ST2702 which are even-numbered stages ST2702, ST2704, ST2706, ... are maintained in the discharge state in the third period T3.

Next, the operation during the fourth period T4 will be described.

During the fourth period T4, as shown in FIG. 4, only the fourth clock pulse CLK4 remains high. The start pulse Vst, the first to third scan pulses Vout3, and the remaining clock pulses remain low.

 The fourth clock pulse CLK4 is supplied to the enabled fourth stage ST2704. Specifically, the fourth clock pulse CLK4 is supplied to the drain terminal of the pull-up switching device Tru provided in the fourth stage ST2704. Therefore, the pull-up switching device Tru provided in the fourth stage ST2704 outputs the fourth clock pulse CLK4 as a fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line, the fifth stage ST2705, and the third stage ST2703.

That is, the fourth scan pulse Vout4 drives the fourth gate line, enables the fifth stage ST2705, and disables the third stage ST2703.

Here, the second disable node QB2 of the fifth stage ST2705 and the first disable node QB1 of the sixth stage ST2706 are connected to each other, and thus, in the fourth period T4. The first disable node QB1 of the sixth stage ST2706 is also discharged to the second DC voltage source Vdc2.

As the fourth scan pulse Vout4 output from the fourth stage ST2704 disables the third stage ST2703, the third stage that is the odd stage ST2701, ST2703, ST2705, ... ST2703 (that is, a stage supplied with the first AC voltage source Vac1) discharges its enable node Q and the second disable node QB2, and the first disable node QB1. Is charged with a first AC voltage source Vac1.

The fourth disable node QB1 of the disabled third stage ST2703 is connected to the second disable node QB2 of the second stage ST2702, and thus, the fourth period T4. ), The second disable node QB2 of the second stage ST2702 is also charged by the first AC voltage source Vac1.

In other words, during the fourth period T4, the first disable node QB1 of the third stage ST2703 and the second disable node QB2 of the second stage ST2702 are connected to the first AC voltage source ( Vac1).

In this manner, in the sixth period T6, the first disable node QB1 of the fifth stage ST2705 and the second disable node QB2 of the fourth stage ST2704 are connected to the first AC voltage source. It is charged to (Vac1).

Next, the operation during the second frame period will be described.

Operations during the second frame period will be described with reference to FIGS. 28B, 29A, and 29B. During the second frame period, the first AC voltage source Vac1 is kept low and the second AC voltage source Vac2 is kept high.

Therefore, in this second frame period, even-numbered stages ST2702, ST2704, ST2706, ... perform the disable operation by charging their first disable node QB1.

In the second frame period, the odd-numbered stages ST2701, ST2703, ST2705, ... discharge all their nodes Q, QB1, and QB2 to perform the disable operation. At this time, the second disable node QB2 of the odd stages ST2701, ST2703, ST2705, ... is the disc of the even-numbered stages ST2702, ST2704, ST2706,. The change from the discharge state to the charge state is made by the enable operation.

On the other hand, each stage may further comprise a switching device as follows.

FIG. 30 is a diagram illustrating another circuit configuration of the node controller provided in the third stage of FIG. 27.

The circuit shown in FIG. 30 has a structure in which the tenth to twelfth switching elements Tr10 to Tr12 are further included in the circuit configuration shown in FIGS. 28A and 28B.

In this case, each stage may have any one, two, or all three of the tenth to twelfth switching elements Tr10 to Tr12.

The tenth switching device Tr10 provided in the nth stage is turned on or turned off according to the non-state of the start pulse Vst from the timing controller, and when turned on, a second direct current is applied to the common node of the nth stage. Supply voltage source (Vdc2).

For example, the tenth switching device Tr10 included in the third stage ST2703 of FIG. 30 is turned off according to the logic state of the start pulse Vst from the timing controller. The second DC voltage source Vdc2 is supplied to the common node of the third stage ST2703.

To this end, the gate terminal of the tenth switching element Tr10 provided in the third stage ST2703 is connected to a clock transmission line for transmitting the start pulse Vst, and the drain terminal is connected to the common node. The source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The eleventh switching element Tr11 provided in the nth stage is turned on or turned off according to the logic state of the first AC voltage source Vac1 (or the second AC voltage source Vac2). The second DC voltage source Vdc2 is supplied to the second disable node QB2 of the nth stage.

For example, the eleventh switching element Tr11 included in the third stage ST2703 of FIG. 30 is turned on or turned off according to the logic state of the first AC voltage source Vac1, and when turned on, the eleventh switching element T270 is turned on. The second DC voltage source Vdc2 is supplied to the second disable node QB2 of the third stage ST2703.

To this end, the gate terminal of the eleventh switching element Tr11 provided in the third stage ST2703 is connected to a power line for transmitting a first AC voltage source Vac1, and the drain terminal of the third stage ST2703 is connected to the power line. Is connected to a second disable node QB2, and a source terminal thereof is connected to a power line for transmitting the second DC voltage source Vdc2.

The twelfth switching element Tr12 provided in the nth stage is turned on or off according to the logic state of the scan pulse from the n-1th stage, and when turned on, the first disable of the nth stage is disabled. The second DC voltage source Vdc2 is supplied to the dragon node QB1.

For example, the twelfth switching element Tr12 included in the third stage ST2703 of FIG. 30 is turned on or turned on depending on the logic state of the second scan pulse Vout2 from the second stage ST2702. When turned off, the second DC voltage source Vdc2 is supplied to the first disable node QB1 of the third stage ST2703.

On the other hand, each stage may have a circuit configuration as follows.

FIG. 31 is a diagram illustrating still another circuit configuration of the node controller provided in the third stage of FIG. 27.

Each stage includes first to tenth switching elements Tr1 to Tr10 as shown in FIG. 31.

Here, since the first to fourth switching devices Tr1 to Tr4 illustrated in FIG. 31D play the same role as the first to fourth switching devices Tr1 to Tr4 of FIGS. 29A and 29B, description thereof will be omitted.

In addition, the seventh switching device Tr7 illustrated in FIG. 31 plays the same role as the eighth switching device Tr8 of FIGS. 29A and 29B, and the eighth switching device Tr8 illustrated in FIG. 31 is illustrated in FIGS. 29A and 29B. 29B plays the same role as the ninth switching device Tr9, and the ninth switching device Tr9 shown in FIG. 31 plays the same role as the eleventh switching device Tr11 of FIG. 30, and is shown in FIG. 31. Since the tenth switching device Tr10 plays the same role as the twelfth switching device Tr12 of FIG. 30, description thereof will be omitted.

The fifth switching device Tr5 provided in the nth stage is turned on or turned off according to the logic state of the first AC voltage source Vac1 (or the second AC voltage source Vac2), and when turned on, the fifth switching device Tr5 is turned on. The first AC voltage source Vac1 (or the second through voltage source) is supplied to the first disable node QB1 of the n stage.

For example, the fifth switching device Tr5 provided in the third stage ST2703 of FIG. 31 is turned on or turned off according to the logic state of the first AC voltage source Vac1, and when turned on, the fifth switching device Tr5 is turned on. The first AC voltage source Vac1 is supplied to the first disable node QB1 of the third stage ST2703.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 included in the third stage ST2703 are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal of the third stage ST2703 is connected to the third terminal ST2703. It is connected to the first disable node QB1 of the stage ST2703.

The sixth switching device Tr6 provided in the nth stage is turned on or turned off according to the logic state of the scan pulse from the n + 1th stage, and when turned on, the first switching device for the first disablement of the nth stage is performed. The first AC voltage source Vac1 (or the second AC voltage source Vac2) is supplied to the node QB1.

For example, the sixth switching device Tr6 included in the third stage ST2703 of FIG. 31 is turned on or turned on according to the logic state of the fourth scan pulse Vout4 from the fourth stage ST2704. When turned off, the first AC voltage source Vac1 is supplied to the first disable node QB1 of the third stage ST2703.

To this end, the gate terminal of the sixth switching device Tr6 provided in the third stage ST2703 is connected to the output terminal of the fourth stage ST2704, and the drain terminal transmits the first AC voltage source Vac1. The source terminal is connected to the first disable node QB1 of the third stage ST2703.

Hereinafter, the shift register according to the seventh embodiment of the present invention will be described in detail.

32 is a diagram illustrating a shift register according to a seventh embodiment of the present invention, and FIGS. 33A and 33B are diagrams illustrating waveforms of an input signal supplied to each stage of FIG. 32 and an output signal output from each stage.

The shift register according to the seventh embodiment of the present invention has a plurality of stages ST3201, ST3202, ST3203, ... as shown in FIG.

Here, the configuration of each stage ST3201, ST3202, ST3203, ... is the same as that of the sixth embodiment, and only this connection relationship is different between the stages ST3201, ST3202, ST3203, ... This will be described.

The nth stage is enabled in response to the scan pulse from the n-2 stage, and is disabled in response to the scan pulse from the n + 2 stage from the n + 1 stage.

 On the other hand, the stage does not exist in the second front end of the first stage ST3201. Therefore, the first stage ST3201 is enabled in response to the first start pulse Vst1 from the timing controller.

In addition, the stage does not exist in the second front end of the second stage ST3202. Accordingly, the second stage ST3202 is enabled in response to the second start pulse Vst2 from the timing controller.

On the other hand, each stage is supplied with the first to fourth clock pulses CLK1 to CLK4, and the clock pulses output in adjacent periods are simultaneously maintained for a predetermined period. In other words, clock pulses output in adjacent periods are simultaneously in a high state for a predetermined period.

Accordingly, scan pulses output between adjacent stages also exhibit high states for a certain period of time.

The operation of the shift register having the stage configured as described above is as follows.

First, the operation during the first frame period will be described with reference to FIG. 33A. During the first frame period, the first AC voltage source Vac1 is kept high and the second AC voltage source Vac2 is kept low.

In the first initial period T0A, the first stage ST3201 is enabled by the first start pulse Vst1 from the timing controller. That is, in the first initial period T0A, the enabling node Q of the first stage ST3201 is charged with the first DC voltage source Vdc1, and the first and second disable nodes QB1, QB2) is discharged to the second DC voltage source Vdc2.

Accordingly, in the first initial period T0A, the pull-up switching device Tru included in the first stage ST3201 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. -Off.

Meanwhile, since the second disable node QB2 of the first stage ST3201 and the first disable node QB1 of the second stage ST3202 are electrically connected to each other, the first stage ST3201 The second disable node QB2 and the first disable node QB1 of the second stage ST3202 are discharged to the same voltage. That is, in the initial period T0, the first disable node QB1 of the second stage ST3202 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the first stage ST3201 is charged in the first initial period T0A. The first and second disable nodes QB1 and QB2 of the first stage ST3201 and the first disable node QB1 of the second stage ST3202 are discharged.

Thereafter, the second stage ST3202 is enabled by the second start pulse Vst2 from the timing controller in the second initial period T0B. That is, in the second initial period T0B, the enabling node Q of the second stage ST3202 is charged with the first DC voltage source Vdc1, and the first and second disable nodes QB1, QB2) is discharged to the second DC voltage source Vdc2.

Accordingly, in the second initial period T0B, the pull-up switching device Tru included in the second stage ST3202 is turned on, and both of the first and second pull-down switching devices Trd1 and Trd2 are turned on. -Off.

Meanwhile, since the second disable node QB2 of the second stage ST3202 and the first disable node QB1 of the third stage ST3203 are electrically connected to each other, the second stage ST3202 The second disable node QB2 and the first disable node QB1 of the third stage ST3203 are discharged to the same voltage. That is, in the second initial period T0B, the first disable node QB1 of the third stage ST3203 is also discharged to the second DC voltage source Vdc2.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Tru provided in the first stage ST3201 in the first period T1. Then, the pull-up switching device Tru outputs the first scan pulse Vout1 and supplies it to the first gate line and the third stage ST3203.

Therefore, the first gate line is driven in the first period T1, and the third stage ST3203 is enabled.

That is, the enable node Q of the third stage ST3203 is charged with the first DC voltage source Vdc1, and the first and second disable nodes QB1 and QB2 of the third stage ST3203 are charged. ) Is discharged to the second DC voltage source Vdc2.

Accordingly, the pull-up switching device Tru provided in the third stage ST3203 is turned on in the first period T1, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. Is off.

Meanwhile, since the second disable node QB2 of the third stage ST3203 and the first disable node QB1 of the fourth stage ST3204 are electrically connected to each other, the third stage ST3203 The second disable node QB2 and the first disable node QB1 of the fourth stage ST3204 are discharged to the same voltage. That is, in the first period T1, the first disable node QB1 of the fourth stage ST3204 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the third stage ST3203 is charged in the first period T1. The first and second disable nodes QB1 and QB2 of the third stage ST3203 and the first disable node QB1 of the fourth stage ST3204 are discharged.

Thereafter, in the second period T2, the second clock pulse CLK2 is supplied to the pull-up switching device Tru provided in the second stage ST3202. Then, the pull-up switching device Tru outputs the second scan pulse Vout2 and supplies it to the second gate line and the fourth stage ST3204.

Accordingly, the second gate line is driven in the second period T2, and the fourth stage ST3204 is enabled.

Accordingly, in the second period T2, the pull-up switching device Tru included in the fourth stage ST3204 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. Is off.

Meanwhile, since the second disable node QB2 of the fourth stage ST3204 and the first disable node QB1 of the fifth stage ST3205 are electrically connected to each other, the fourth stage ST3204 The second disable node QB2 and the first disable node QB1 of the fifth stage ST3205 are discharged to the same voltage. That is, in the second period T2, the first disable node QB1 of the fifth stage ST3205 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the fourth stage ST3204 is charged in the second period T2. The first and second disable nodes QB1 and QB2 of the fourth stage ST3204 and the first disable node QB1 of the fifth stage ST3205 are discharged.

Thereafter, the third clock pulse CLK3 is supplied to the pull-up switching device Tru provided in the third stage ST3203 in the third period T3. Then, the pull-up switching device Tru outputs the third scan pulse Vout3 and supplies it to the third gate line, the fifth stage ST3205, and the first stage ST3201.

Accordingly, the third gate line is driven in the third period T3 and the fifth stage ST3205 is enabled. In addition, the first stage ST3201 is disabled. That is, the enable node Q and the second disable node QB2 of the first stage ST3201 are discharged to the second DC voltage source Vdc2, and the first disc of the first stage ST3201 is discharged. The enable node QB1 is charged with the first AC voltage source Vac1. In other words, the first AC voltage source Vac1 is supplied to the first stage ST3201 which is the odd stage ST2701, ST2703, ST2705, ..., which is supplied during the first frame period. Since the state is high, only the first disable node QB1 of the first stage ST3201 is maintained in the charged state when the first stage ST3201 is disabled.

In summary, the enable node Q of the fifth stage ST3205 is charged in the third period T3. The first and second disable nodes QB1 and QB2 of the fifth stage ST3205 and the first disable node QB1 of the sixth stage ST3206 are discharged. In addition, the enable node Q and the second disable node QB2 of the first stage ST3201 are discharged, and the first disable node QB1 is charged.

Thereafter, the fourth clock pulse CLK4 is supplied to the pull-up switching device Tru provided in the fourth stage ST3204 in the fourth period T4. Then, the pull-up switching device Tru outputs the fourth scan pulse Vout4 and supplies it to the fourth gate line, the sixth stage ST3206, and the second stage ST3202.

Accordingly, the fourth gate line is driven in the fourth period T4, and the sixth stage ST3206 is enabled. In addition, the second stage ST3202 is disabled. That is, the enable node Q, the first disable node QB1, and the second disable node QB2 of the second stage ST3202 are all discharged. In other words, the second AC voltage source Vac2 is supplied to the second stage ST3202 which is the even-numbered stages ST2702, ST2704, ST2706,... Since the state is low, all the nodes Q, QB1, and QB2 of the second stage ST3202 are discharged when the second stage ST3202 is disabled.

In summary, the enable node Q of the sixth stage ST3206 is charged in the fourth period T4. The first and second disable nodes QB1 and QB2 of the sixth stage ST3206 and the first disable node QB1 of the seventh stage are discharged. In addition, all the nodes Q, QB1, and QB2 of the second stage ST3202 are discharged.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Tru provided in the fifth stage ST3205 in the fifth period T5. Then, the pull-up switching device Tru outputs the fifth scan pulse Vout5 and supplies it to the fifth gate line, the seventh stage, and the third stage ST3203.

Therefore, the fifth gate line is driven in the fifth period T5 and the seventh stage is enabled. In addition, the third stage ST3203 is disabled. That is, the enable node Q and the second disable node QB2 of the third stage ST3203 are discharged, and the first disable node QB1 is charged. In other words, the first AC voltage source Vac1 is supplied to the third stage ST3203 which is the odd-numbered stages ST2701, ST2703, ST2705,... Which is supplied during the first frame period. Since the state is high, when the third stage ST3203 is disabled, only the first disable node QB1 of the third stage ST3203 is maintained in the charged state.

At this time, as the first disable node QB1 of the third stage ST3203 is changed to a charged state in the fifth period T5, the first disable node (3) of the third stage ST3203 is changed. The second disable node QB2 of the second stage ST3202 connected to QB1 is also changed from a discharge state to a charged state.

In summary, the enable node Q of the seventh stage is charged in the fifth period T5. The first and second disable nodes QB1 and QB2 of the seventh stage and the first disable node QB1 of the eighth stage are discharged. Further, the first disable node QB1 of the third stage ST3203 and the second disable node QB2 of the second stage ST3202 are charged.

In this manner, the odd stages ST2701, ST2703, ST2705, ... in the first frame period perform the disable operation by charging their first disable node QB1.

In the first frame period, even-numbered stages ST2702, ST2704, ST2706, ... discharge all their nodes Q, QB1, and QB2 to perform the disable operation. At this time, the second disable node QB2 of the even-numbered stages ST2702, ST2704, ST2706,..., The discs of the odd-numbered stages ST2701, ST2703, ST2705,... The change from the discharge state to the charge state is made by the enable operation.

 Next, the operation during the second frame period will be described with reference to FIG. 33B. During the second frame period, the first AC voltage source Vac1 is kept low and the second AC voltage source Vac2 is kept high.

In the first initial period T0A, the first stage ST3201 is enabled by the first start pulse Vst1 from the timing controller. That is, in the first initial period T0A, the enabling node Q of the first stage ST3201 is charged with the first DC voltage source Vdc1, and the first and second disable nodes QB1, QB2) is discharged to the second DC voltage source Vdc2.

Accordingly, in the first initial period T0A, the pull-up switching device Tru included in the first stage ST3201 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. -Off.

Meanwhile, since the second disable node QB2 of the first stage ST3201 and the first disable node QB1 of the second stage ST3202 are electrically connected to each other, the first stage ST3201 The second disable node QB2 and the first disable node QB1 of the second stage ST3202 are discharged to the same voltage. That is, in the initial period T0, the first disable node QB1 of the second stage ST3202 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the first stage ST3201 is charged in the first initial period T0A. The first and second disable nodes QB1 and QB2 of the first stage ST3201 and the first disable node QB1 of the second stage ST3202 are discharged.

Thereafter, the second stage ST3202 is enabled by the second start pulse Vst2 from the timing controller in the second initial period T0B. That is, in the second initial period T0B, the enabling node Q of the second stage ST3202 is charged with the first DC voltage source Vdc1, and the first and second disable nodes QB1, QB2) is discharged to the second DC voltage source Vdc2.

Accordingly, in the second initial period T0B, the pull-up switching device Tru provided in the second stage ST3202 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. -Off.

Meanwhile, since the second disable node QB2 of the second stage ST3202 and the first disable node QB1 of the third stage ST3203 are electrically connected to each other, the second stage ST3202 The second disable node QB2 and the first disable node QB1 of the third stage ST3203 are discharged to the same voltage. That is, in the second initial period T0B, the first disable node QB1 of the third stage ST3203 is also discharged to the second DC voltage source Vdc2.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Tru provided in the first stage ST3201 in the first period T1. Then, the pull-up switching device Tru outputs the first scan pulse Vout1 and supplies it to the first gate line and the third stage ST3203.

Therefore, the first gate line is driven in the first period T1, and the third stage ST3203 is enabled.

That is, the enable node Q of the third stage ST3203 is charged with the first DC voltage source Vdc1, and the first and second disable nodes QB1 and QB2 of the third stage ST3203 are charged. ) Is discharged to the second DC voltage source Vdc2.

Accordingly, the pull-up switching device Tru provided in the third stage ST3203 is turned on in the first period T1, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. Is off.

Meanwhile, since the second disable node QB2 of the third stage ST3203 and the first disable node QB1 of the fourth stage ST3204 are electrically connected to each other, the third stage ST3203 The second disable node QB2 and the first disable node QB1 of the fourth stage ST3204 are discharged to the same voltage. That is, in the first period T1, the first disable node QB1 of the fourth stage ST3204 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the third stage ST3203 is charged in the first period T1. The first and second disable nodes QB1 and QB2 of the third stage ST3203 and the first disable node QB1 of the fourth stage ST3204 are discharged.

Thereafter, in the second period T2, the second clock pulse CLK2 is supplied to the pull-up switching device Tru provided in the second stage ST3202. Then, the pull-up switching device Tru outputs the second scan pulse Vout2 and supplies it to the second gate line and the fourth stage ST3204.

Accordingly, the second gate line is driven in the second period T2, and the fourth stage ST3204 is enabled.

Accordingly, in the second period T2, the pull-up switching device Tru included in the fourth stage ST3204 is turned on, and both the first and second pull-down switching devices Trd1 and Trd2 are turned on. Is off.

Meanwhile, since the second disable node QB2 of the fourth stage ST3204 and the first disable node QB1 of the fifth stage ST3205 are electrically connected to each other, the fourth stage ST3204 The second disable node QB2 and the first disable node QB1 of the fifth stage ST3205 are discharged to the same voltage. That is, in the second period T2, the first disable node QB1 of the fifth stage ST3205 is also discharged to the second DC voltage source Vdc2.

In summary, the enable node Q of the fourth stage ST3204 is charged in the second period T2. The first and second disable nodes QB1 and QB2 of the fourth stage ST3204 and the first disable node QB1 of the fifth stage ST3205 are discharged.

Thereafter, the third clock pulse CLK3 is supplied to the pull-up switching device Tru provided in the third stage ST3203 in the third period T3. Then, the pull-up switching device Tru outputs the third scan pulse Vout3 and supplies it to the third gate line, the fifth stage ST3205, and the first stage ST3201.

Accordingly, the third gate line is driven in the third period T3 and the fifth stage ST3205 is enabled. In addition, the first stage ST3201 is disabled. That is, the enable node Q, the first disable node QB1, and the second disable node QB2 of the first stage ST3201 are discharged to the second DC voltage source Vdc2. In other words, the first AC voltage source Vac1 is supplied to the first stage ST3201 which is the odd stage ST2701, ST2703, ST2705, ..., during the second frame period. Since it is a low state, when the first stage ST3201 is disabled, all nodes Q, QB1, and QB2 of the first stage ST3201 maintain a discharge state.

In summary, the enable node Q of the fifth stage ST3205 is charged in the third period T3. The first and second disable nodes QB1 and QB2 of the fifth stage ST3205 and the first disable node QB1 of the sixth stage ST3206 are discharged. In addition, all the nodes Q, QB1, and QB2 of the first stage ST3201 are discharged.

Thereafter, the fourth clock pulse CLK4 is supplied to the pull-up switching device Tru provided in the fourth stage ST3204 in the fourth period T4. Then, the pull-up switching device Tru outputs the fourth scan pulse Vout4 and supplies it to the fourth gate line, the sixth stage ST3206, and the second stage ST3202.

Accordingly, the fourth gate line is driven in the fourth period T4, and the sixth stage ST3206 is enabled. In addition, the second stage ST3202 is disabled. That is, the enable node Q and the second disable node QB2 of the second stage ST3202 are discharged, and the first disable node QB1 is charged. In other words, a second AC voltage source Vac2 is supplied to the second stage ST3202 which is the even-numbered stages ST2702, ST2704, ST2706,... Since it is a high state, only the first disable node QB1 of the second stage ST3202 is charged when the second stage ST3202 is disabled.

At this time, as the first disable node QB1 of the second stage ST3202 is changed to a charged state in the fourth period T4, the first disable node (ie, the first disable node of the second stage ST3202). The second disable node QB2 of the first stage ST3201 connected to QB1 is also changed from a discharge state to a charged state.

In summary, the enable node Q of the sixth stage ST3206 is charged in the fourth period T4. The first and second disable nodes QB1 and QB2 of the sixth stage ST3206 and the first disable node QB1 of the seventh stage are discharged. Also, the first disable node QB1 of the second stage ST3202 and the second disable node QB2 of the first stage ST3201 are charged.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Tru provided in the fifth stage ST3205 in the fifth period T5. Then, the pull-up switching device Tru outputs the fifth scan pulse Vout5 and supplies it to the fifth gate line, the seventh stage, and the third stage ST3203.

Therefore, the fifth gate line is driven in the fifth period T5 and the seventh stage is enabled. In addition, the third stage ST3203 is disabled. That is, the enable node Q and the first and second disable nodes QB1 and QB2 of the third stage ST3203 are discharged. In other words, the first AC voltage source Vac1 is supplied to the third stage ST3203 which is the odd-numbered stages ST2701, ST2703, ST2705, ... during the second frame period. Since it is a low state, when the third stage ST3203 is disabled, all nodes Q, QB1, and QB2 of the third stage ST3203 are kept in a discharged state.

In summary, the enable node Q of the seventh stage is charged in the fifth period T5. The first and second disable nodes QB1 and QB2 of the seventh stage and the first disable node QB1 of the eighth stage are discharged. In addition, all the nodes Q, QB1, and QB2 of the third stage ST3203 are discharged.

In this manner, the even-numbered stages ST2702, ST2704, ST2706, ... in the second frame period perform the disable operation by charging their first disable node QB1.

In the second frame period, the odd-numbered stages ST2701, ST2703, ST2705, ... discharge all their nodes Q, QB1, and QB2 to perform the disable operation. At this time, the second disable node QB2 of the odd stages ST2701, ST2703, ST2705, ... is the disc of the even-numbered stages ST2702, ST2704, ST2706,. The change from the discharge state to the charge state is made by the enable operation.

Herein, the configuration of each node controller 3205 provided in each stage will be described in more detail.

34A and 34B are diagrams illustrating a circuit configuration of the node controller provided in the first to fourth stages of FIG. 32.

First, the node controller 3205 included in each stage has first to ninth switching elements Tr1 to Tr9, as illustrated in FIGS. 34A and 34B.

The first to ninth switching elements Tr1 to Tr9 shown in FIGS. 34A and 34B are the same as the first to ninth switching elements Tr1 to Tr9 shown in FIGS. 29A and 29B.

34A and 34B, however, the first and eighth switching elements Tr1 and Tr8 are controlled by the scan pulses from the second front stage, and the fourth switching element Tr4 is controlled from the second next stage. It is controlled by the scan pulse of.

  That is, the first switching device Tr1 provided in the n-th stage is turned on or off according to the logic state of the scan pulse from the n-th stage, and when turned on, the first switching element Tr1 is turned off. The first DC voltage source Vdc1 is supplied to the node Q for the enable.

For example, the first switching device Tr1 included in the third stage ST3203 of FIG. 34B is turned on or turned on according to the logic state of the first scan pulse Vout1 from the first stage ST3201. When turned off, the first DC voltage source Vdc1 is supplied to the enabling node Q of the third stage ST3203 at turn-on.

To this end, the gate terminal of the first switching device Tr1 provided in the third stage ST3203 is connected to the output terminal of the first stage ST3201, and the drain terminal transmits the first DC voltage source Vdc1. The source terminal is connected to the enable node Q of the third stage ST3203.

The fourth switching device Tr4 provided in the nth stage is turned on or off according to the logic state of the scan pulse from the n + 2th stage, and the node for enabling the nth stage is turned on when the fourth switching element Tr4 is turned on. The second DC voltage source Vdc2 is supplied to (Q).

For example, the fourth switching device Tr4 included in the third stage ST3203 of FIG. 34B is turned on or turned off according to the logic state of the scan pulse from the fifth stage ST3205. When turned on, the second DC voltage source Vdc2 is supplied to the enabling node Q of the third stage ST3203.

To this end, the gate terminal of the fourth switching device Tr4 provided in the third stage ST3203 is connected to the output terminal of the fifth stage ST3205, and the drain terminal of the third stage ST3203 is connected to the output terminal of the third stage ST3203. It is connected to the enable node Q, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The eighth switching device Tr8 provided in the nth stage is turned on or off according to the logic state of the scan pulse from the n-2th stage, and when turned on, the second disable of the nth stage is disabled. The second DC voltage source Vdc2 is supplied to the dragon node QB2.

For example, the eighth switching device Tr8 included in the third stage ST3203 of FIG. 34 is turned on or turned on depending on the logic state of the first scan pulse Vout1 from the first stage ST3201. When turned off, the second DC voltage source Vdc2 is supplied to the second disable node QB2 of the third stage ST3203.

To this end, the gate terminal of the eighth switching device Tr8 provided in the third stage ST3203 is connected to the output terminal of the first stage ST3201, and the drain terminal of the third stage ST3203 1 is connected to the disable node (QB1), the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

On the other hand, since the stage does not exist in the second front end of the first stage ST3201 and the second front end of the second stage ST3202, the first and eighth switching elements Tr1, which are provided in the first stage ST3201, Tr8 is turned on or off by receiving the first and second start pulses Vst1 and Vst2 from the timing controller.

The first AC voltage source Vac1 is supplied to the fifth switching device Tr5 provided in the odd stages ST2701, ST2703, ST2705, ... among the stages, and the even-numbered stages ST2702, ST2704, The second AC voltage source Vac2 is supplied to the fifth switching device Tr5 provided in ST2706, ...).

The operation of the shift register with stages to which such a circuit configuration is applied is the same as the operation of the circuit shown in Figs. 29A and 29B.

However, the first and eighth switching elements Tr8 included in the first stage ST3201 of FIGS. 34A and 34B are controlled by the first start pulse Vst1. The first and eighth switching elements Tr1 and Tr8 included in the second stage ST3202 are controlled by the second start pulse Vst2. The first and eighth switching elements Tr1 and Tr8 included in the third stage ST3203 are controlled by the first scan pulse Vout1 from the first stage ST3201. The first and eighth switching elements Tr1 and Tr8 included in the fourth stage ST3204 are controlled by the second scan pulse Vout2 from the second stage ST3202.

In addition, the fourth switching device Tr4 included in the first stage ST3201 is controlled by the third scan pulse Vout3 from the third stage ST3203. The fourth switching device Tr4 provided in the second stage ST3202 is controlled by the fourth scan pulse Vout4 from the fourth stage ST3204. The fourth switching device Tr4 provided in the third stage ST3203 is controlled by the fifth scan pulse Vout5 from the fifth stage ST3205. The fourth switching element Tr4 provided in the fourth stage ST3204 is controlled by the sixth scan pulse Vout6 from the sixth stage ST3206.

Meanwhile, the shift register according to the seventh embodiment of the present invention may have the circuit configuration shown in FIG. 30 or 31.

35 is a diagram illustrating a shift register according to an eighth embodiment of the present invention, and FIG. 36A is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 35 and an output signal output from each stage. FIG. 36B illustrates another waveform of an input signal supplied to each stage of FIG. 35 and an output signal output from each stage.

The shift register according to the eighth embodiment of the present invention has a plurality of stages ST3501, ST3502, ST3503, ... as shown in FIG.

Here, the configuration of each stage ST3501, ST3502, ST3503, ... is the same as that of the sixth embodiment, and only the connection relationship between the stages ST3501, ST3502, ST3503, ... is different. This will be described.

The 2n-1 stage is enabled in response to the scan pulse from the 2n-3 stage and is disabled in response to the scan pulse from the 2n + 2 stage.

The 2n stage is enabled in response to the scan pulse from the 2n-2 stage and is disabled in response to the scan pulse from the 2n + 2 stage.

On the other hand, the stage does not exist in the second front end of the first stage ST3501. Therefore, the first stage ST3501 is enabled in response to the start pulse Vst from the timing controller.

In addition, the stage does not exist in the second front end of the second stage ST3502. Accordingly, the second stage ST3502 is also enabled in response to the start pulse Vst from the timing controller.

The first disable nodes QB1 of two stages adjacent to each other are electrically connected to each other, and the second disable nodes QB2 of two adjacent stages are electrically connected to each other.

Meanwhile, the 2n-1 stage may be enabled by the scan pulse from the 2n + 1 stage instead of the 2n + 2 stage.

Stages ST3501, ST3502, ST3503, ... having such a connection relationship are among the first to fourth clock pulses CLK1 to CLK4 that have a phase difference and do not overlap each other, as shown in FIG. 36A. Either one is supplied and output as a scan pulse.

In addition, the stages ST3501, ST3502, ST3503,... Having such a connection relationship include the first to fourth clock pulses CLK1 to CLK4 overlapped by 1 / 3H periods, as shown in FIG. 36B. ) Can be supplied and output as a scan pulse.

The circuit configuration of the node controller 3505 provided in each of the stages ST3501, ST3502, ST3503, ... is as follows.

FIG. 37 is a diagram illustrating a circuit configuration of the third and fourth stages of FIG. 35.

Among the node controllers of each stage according to the eighth embodiment of the present invention, the node controllers of the 2n-1 stages include the first to ninth switching elements Tr1 to Tr9, and the node controllers of the second nn stages The first to tenth switching elements Tr1 to Tr10 are included.

Since the first to ninth switching elements Tr1 to Tr9 are the same as the first to ninth switching elements Tr1 to Tr9 in FIG. 4, description thereof will be omitted.

The tenth switching element Tr10 of the 2n stage is turned on or off according to the signal state of the enable node Q of the 2n-1 stage, and when turned on, the common node of the second n stage ( N) is discharged to the second DC voltage source Vdc2.

When the first to fourth clock pulses CLK1 to CLK4 are supplied to the circuit, the first to fourth clock pulses CLK1 to CLK4 having overlapping periods as shown in FIG. 36B are applied to the stages ST3501, ST3502, Increase the bootstrapping effect of the enabling node Q of ST3503, ...).

FIG. 38 is a diagram illustrating a shift register according to a ninth embodiment of the present invention, and FIG. 39A is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 38 and an output signal output from each stage.

Hereinafter, all the switching elements, the pull-up switching element, and the pull-down switching element are one of an N-type metal oxide semiconductor (MOS) transistor and a P-type MOS transistor, and the present invention will be described using an N-type MOS transistor.

The shift register according to the ninth embodiment of the present invention has a plurality of stages ST3801, ST3802, ST3803, ... for driving the plurality of gate lines, as shown in FIG.

This shift register includes a number of stage blocks SB1, SB2, ..., each stage block SB1, SB2, ... comprising one server stage and two client stages.

The server stage and the client stage are the node control unit 3805, the enable node Q, the first disable node QB1, and the second disable node QB2, as described above in the previous embodiment. , A pull-up switching device Tru, a first pull-down switching device Trd1, and a second pull-down switching device Trd2.

Since the stage blocks SB1 and SB2 have the same configuration, the server stage, the first client stage, and the second client stage included in the first stage block SB1 will be described as follows.

The server stage (first disabling node QB1 of the first stage ST3801) included in the first stage block SB1 is a first client stage (second stage) provided in the first stage ST3801 block. Node QB1 of the first disable node (ST3802), and the first disable node QB1 of the second client stage (third stage ST3803) provided in the first stage block SB1; Electrically connected.

In addition, the second disable node QB2 of the server stage provided in the first stage block SB1 is the second disable node of the first client stage provided in the first stage block SB1 ( QB2) and the second disable node QB2 of the second client stage provided in the first stage block SB1.

The node controller 3805 included in the server stage in the first stage block SB1 uses the first and second alternating voltage sources Vac1 and Vac2 to perform the client stages (second and third stages ST3802, The signal states of the first and second disable nodes QB1 and QB2) are controlled.

Accordingly, only the server stage is directly supplied with the first and second AC voltage sources Vac1 and Vac2 in the first stage block SB1.

Stages included in the p-th stage block (p is a natural number) are enabled in response to scan pulses from any of the stages included in the p-k-th stage block (k is a natural number less than p).

The stages included in the p-th stage block (p is a natural number) are disabled in response to a scan pulse from any one of the stages included in the p + i-th stage block (i is a natural number larger than p).

For example, the server stage and the client stage provided in the second stage block SB2 are enabled in response to the scan pulse from the server stage provided in the first stage block SB1.

In addition, the server stage and the client stage included in the second stage block SB2 are enabled in response to the scan pulse from the server stage provided in the third stage ST3803.

Here, since the stage block does not exist in the previous stage of the first stage block SB1, the server stage and the client stages included in the first stage block SB1 may respond to the start pulse Vst from the timing controller. Is enabled.

Each stage provided in each shift register described in the first to seventh embodiments controls itself and a node for disabling the stages adjacent to each other while complementary to each other, while the stages included in the shift register described in the eighth embodiment The server stage unilaterally controls the node for disabling of the client stage.

Accordingly, the first and second disable nodes QB1 and QB2 of each client stage may determine the signal states of the first and second disable nodes QB1 and QB2 of the server stage in the stage block in which they are included. To follow.

Each stage included in the shift register having such a configuration receives clock signals (first to sixth clock pulses CLK1 to CLK6) of six phases, as shown in FIG. 36, and sequentially outputs clock pulses. .

39B is a view illustrating another waveform of an input signal supplied to each stage of FIG. 38 and an output signal output from each stage, wherein the shift registers of FIG. 38 are the first to sixth shown in FIG. 39B. Clock pulses CLK1 to CLK6 may be supplied.

The first clock pulse CLK1 exhibits a high state during the 3H period and a low state during the subsequent 3H period. The first clock pulse CLK1 has the high state and the low state repeatedly.

The second clock pulse CLK2 shows a high state for a 1H period and a low state for a subsequent 5H period. The second clock pulse CLK2 has the high state and the low state repeatedly. Here, the high section of the second clock pulse CLK2 is located at the same time zone as the first high section of the high section of the first clock pulse CLK1.

That is, one high section of the first clock pulse CLK1 has a 3H time, and when the high section having the 3H time is divided into three sections having a time of 1H, the second clock pulse CLK2 The high period of overlaps in time with the earliest first time interval of the three periods of the first clock pulse CLK1.

The third clock pulse CLK3 indicates a high state for a 1H period and a low state for a subsequent next 5H period. The third clock pulse CLK3 has the high state and the low state repeatedly. Here, the high section of the third clock pulse CLK3 is located at the same time zone as the second high section of the high section of the first clock pulse CLK1.

That is, one high section of the first clock pulse CLK1 has a 3H time, and when the high section having the 3H time is divided into three sections having a time of 1H, the third clock pulse CLK3 The high period of overlaps in time with the second fastest time period among the three periods of the first clock pulse CLK1.

The fourth clock pulse CLK4 has the same duty ratio as the first clock pulse CLK1 and has a phase inverted 180 degrees with respect to the first clock pulse CLK1.

The fifth clock pulse CLK5 indicates a high state for a 1H period and a low state for a subsequent 5H period. The fifth clock pulse CLK5 has the high state and the low state repeatedly. Here, the high section of the fifth clock pulse CLK5 is located at the same time zone as the first high section of the high section of the fourth clock pulse CLK4.

That is, one high section of the fourth clock pulse CLK4 has a 3H time, and when the high section having the 3H time is divided into three sections having a time of 1H, the fifth clock pulse CLK5 The high period of overlaps temporally with the earliest first time period among the three periods of the fourth clock pulse CLK4.

The sixth clock pulse CLK6 indicates a high state for a 1H period and a low state for a subsequent 5H period. The sixth clock pulse CLK6 has the high state and the low state repeatedly. Here, the high section of the sixth clock pulse CLK6 is located at the same time zone as the second high section of the high section of the fourth clock pulse CLK4.

That is, one high section of the fourth clock pulse CLK4 has a 3H time, and when the high section having the 3H time is divided into three sections having a time of 1H, the sixth clock pulse CLK6 The high period of overlaps in time with the second fastest second time interval of the three periods of the fourth clock pulse CLK4.

Each stage (server stage and client stage) receives one of the above-described first to sixth clock pulses CLK1 to CLK6 and outputs it as a scan pulse.

That is, the 4n + 1 stage receives the first clock pulse CLK1 and outputs the scan pulse. The 4n + 2 stage receives the second clock pulse CLK2 and outputs the scan pulse. The stage receives the third clock pulse CLK3 and outputs the scan pulse, and the fourth n + 4 stage receives the fourth clock pulse CLK4 and outputs the scan pulse.

Here, the stages in one stage block sequentially output scan pulses. However, the output order of this scan pulse does not depend on the position order of the stages.

That is, referring to the first to third scan pulses Vout1 to Vout3 illustrated in FIG. 39B, the first scan pulse Vout1 and the second scan pulse Vout2 are simultaneously output and then the third scan pulse Vout3. Is output.

The first scan pulse Vout1 has a high state for a period of 3H in the same manner as the first clock pulse CLK1 described above, and the second scan pulse Vout2 has the same state as the second clock pulse CLK2 described above. The third scan pulse Vout3 indicates a high state for a 1 H period, similarly to the third clock pulse CLK3 described above.

The data signal synchronized with the second scan pulse Vout2 is supplied to the liquid crystal panel in a period during which the first scan pulse Vout1 and the second scan pulse Vout2 are simultaneously output, that is, the second period T2. The data signal synchronized with the third scan pulse Vout3 is supplied to the liquid crystal panel in a period during which the first scan pulse Vout1 and the third scan pulse Vout3 are simultaneously output, that is, in the third period T3. do. The data signal synchronized with the first scan pulse Vout1 is supplied to the liquid crystal panel in the fourth period T4 in which only the first scan pulse Vout1 has a high state.

Here, since the first scan pulse Vout1 exhibits a high state during the first to third periods T3, the thin film transistor of one pixel supplied with the first scan pulse Vout1 may be configured to be the first to third transistors. The turn-on state is maintained for the period T3. Therefore, the data signal synchronized with the second scan pulse Vout2 and the data signal synchronized with the third scan pulse Vout3 are supplied to this pixel, but eventually the first scan pulse of the third period T3 ( The image signal corresponding to the original data signal is displayed by the data signal synchronized with Vout1).

That is, this pixel displays an image according to a data signal not corresponding to itself during the first and second periods T1 and T2, but eventually displays an image according to a data signal corresponding to itself in the third period T3. Will be displayed.

For example, it is assumed that the first to third stages ST3803 included in the first stage block SB1 output the first to third scan pulses Vout3 and supply them to the first to third gate lines, respectively. lets do it. Suppose that a first pixel is connected to the first gate line, a third pixel is connected to the second gate line, and a third pixel is connected to the third gate line. Also, assume that the first to third pixels are commonly connected to one data line.

Here, in synchronization with the timing at which the scan pulse is output, first to third data signals are sequentially supplied to the data lines. In this case, the first data signal is a signal for displaying an image on a first pixel, the second data signal is a signal for displaying an image on the second pixel, and the third data signal is applied to the third pixel. Assume that this is a signal for displaying an image.

The operation during the first to third periods T1 to T3 is described as follows under this assumption.

In the first period T1, the first and second scan pulses Vout1 and Vout2 simultaneously show a high state, so that the first and second gate lines are driven at the same time, so that the first and second gate lines are simultaneously driven. The thin film transistors of the connected first and second pixels are turned on.

In this first period T1, a second data signal is supplied to the data line and simultaneously supplied to the first and second pixels. Accordingly, the first and second pixels display the image according to the second data signal in the first period T1. Since the second data signal is a signal corresponding to the second pixel, the first pixel displays a wrong image in the first period T1.

Thereafter, since the first and third scan pulses Vout1 and Vout3 simultaneously show a high state in the second period T2, the first and third gate lines are simultaneously driven, thereby providing the first and third gates. The thin film transistors of the first and third pixels connected to the line are turned on.

In this second period T2, a third data signal is supplied to the data line and simultaneously supplied to the first and third pixels. Accordingly, the first and third pixels display an image according to a third data signal in the second period T2. Since the third data signal is a signal corresponding to the third pixel, the first pixel displays an incorrect image in the second period T2.

Thereafter, only the first scan pulse Vout1 has a high state in the third period T3, so that only the first gate line is driven to turn only the thin film transistor of the first pixel connected to the first gate line. Is on.

In this third period T3, a first data signal is supplied to the data line and supplied to the first pixel. Accordingly, the first pixel displays an image according to the first data signal in the third period T3. Since the first data signal is a signal corresponding to the third pixel, the first pixel displays a correct image in this third period T3. As a result, the first pixel finally receives the data signal corresponding to the first pixel to display the correct image.

39C is a diagram illustrating another waveform of an input signal supplied to each stage of FIG. 38 and an output signal output from each stage, wherein the shift registers of FIG. 38 are first to fourth shown in FIG. 39C. Clock pulses CLK1 to CLK4 may be supplied.

The first clock pulse CLK1 exhibits a high state during the 3H period and a low state during the subsequent 3H period. The first clock pulse CLK1 has the high state and the low state repeatedly.

The second clock pulse CLK2 shows a high state for a 1H period and a low state for a subsequent next 2H period. The second clock pulse CLK2 has the high state and the low state repeatedly. Here, the first high section of the second clock pulse CLK2 is located at the same time zone as the first high section of the high section of the first clock pulse CLK1. In addition, the second high period of the second clock pulse CLK2 is located at the same time zone as the first low period of the low period of the first clock pulse CLK1. The first high period and the second high period alternately appear in the first clock pulse CLK1.

That is, one high section of the first clock pulse CLK1 has a 3H time, and when the high section having the 3H time is divided into three sections having a time of 1H, the second clock pulse CLK2 The first high interval of may overlap in time with the earliest first time interval of the three periods of the first clock pulse CLK1.

In addition, one row of the first clock pulse CLK1 has a 3H time, and when the row section having the 3H time is divided into three sections having a time of 1H, the second clock pulse CLK2 The second high interval of may overlap in time with the fastest first interval of the three periods of the first clock pulse CLK1.

The third clock pulse CLK3 shows a high state for a 1H period and a low state for a subsequent next 2H period. The third clock pulse CLK3 has the high state and the low state repeatedly. Here, the first high section of the third clock pulse CLK3 is located at the same time zone as the second high section of the high section of the first clock pulse CLK1. In addition, the second high period of the second clock pulse CLK2 is located at the same time zone as the second low period of the low period of the first clock pulse CLK1. The first high period and the second high period alternately appear in the first clock pulse CLK1.

That is, one high section of the first clock pulse CLK1 has a 3H time, and when the high section having the 3H time is divided into three sections having a time of 1H, the third clock pulse CLK3 The first high interval of may overlap in time with the second fastest second period of the three periods of the first clock pulse CLK1.

In addition, one row of the first clock pulse CLK1 has a 3H time, and when the row section having the 3H time is divided into three sections having a time of 1H, the third clock pulse CLK3 The second high interval of may overlap in time with the second fastest second interval of the three intervals of the first clock pulse CLK1.

The fourth clock pulse CLK4 has the same duty ratio as the first clock pulse CLK1 and has a phase inverted 180 degrees with respect to the first clock pulse CLK1.

Each stage (server stage and client stage) receives one of the first to fourth clock pulses CLK4 described above and outputs it as a scan pulse.

By the clock pulse as described above, the 4n + 1 stage outputs the first scan pulse Vout1 having a high period of 3H time, and the 4n + 2 stage outputs the first high period and the second high period of 1H time. Outputs a second scan pulse Vout2 having a second output pulse, and the fourth n + 3 stage outputs a third scan pulse Vout3 having a first high period and a second high period of 1H time, and a fourth n + 4 stage The fourth scan pulse Vout4 having a high period of 3H time is output.

Since the second and third scan pulses Vout2 and Vout3 have two high periods in one frame period, the thin film transistors of the pixels supplied with the first and third scan pulses Vout3 have two high periods in one frame period. Turn-on once. In this case, the thin film transistor of the pixel is precharged by the data signal of another pixel in the first high period, and correctly charged with the data signal corresponding to the same in the second high period.

Here, the configuration of each stage in more detail as follows.

40 is a diagram illustrating a circuit configuration of the fourth stage of FIG. 38.

The fourth stage ST3804 is a server stage provided in the second stage block SB2, and the node controller 3805 of the server stage includes first to sixteenth switching elements Tr1 to Tr16.

The first switching device Tr1 provided in the server stage of the nth stage block responds to the scan pulse from any one of the stages provided in the n-1th stage block, and enables the node Q of the server stage. ) Is charged to the first DC voltage source Vdc1. That is, the first switching device Tr1 provided in the fourth stage ST3804 responds to the first scan pulse Vout1 from the first stage ST3801, and enables the node of the fourth stage ST3804. (Q) is charged to the first DC voltage source Vdc1. To this end, the gate terminal of the first switching device Tr1 provided in the fourth stage ST3804 is connected to the output terminal of the first stage ST3801, and the drain terminal transmits the first DC voltage source Vdc1. It is connected to the power line, and the source terminal is connected to the enable node (Q) of the fourth stage (ST3804).

The second switching element Tr2 provided in the server stage of the nth stage block responds to the first DC voltage source Vdc1 charged in the enabling node Q of the server stage, and thus, the first disc of the server stage. The enable node QB1 is discharged to the second DC voltage source Vdc2. That is, the second switching device Tr2 provided in the fourth stage ST3804 responds to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST3804. The first disable node QB1 of the fourth stage ST3804 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the second switching element Tr2 provided in the fourth stage ST3804 is connected to the enable node Q of the fourth stage ST3804, and the drain terminal of the fourth stage ST3804. It is connected to the first disable node QB1 of ST3804, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The third switching device Tr3 included in the server stage of the nth stage block responds to the first DC voltage source Vdc1 charged in the enabling node Q of the server stage, and thus, the second disc of the server stage. The enable node QB2 is discharged to the second DC voltage source Vdc2. That is, the third switching device Tr3 included in the fourth stage ST3804 responds to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST3804. The second disable node QB2 of the fourth stage ST3804 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the third switching device Tr3 provided in the fourth stage ST3804 is connected to the enable node Q of the fourth stage ST3804, and the drain terminal of the second switch It is connected to the enable node QB2, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The fourth switching device Tr4 included in the server stage of the nth stage block responds to the scan pulse from any one of the stages included in the n-1th stage block, and thus the server stage provided in the nth stage block. The first disable node QB1 is discharged to the second DC voltage source Vdc2. That is, the fourth switching device Tr4 provided in the fourth stage ST3804 may disable the first of the fourth stage ST3804 in response to the first scan pulse Vout1 from the first stage ST3801. The dragon node QB1 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the fourth switching device Tr4 is connected to the output terminal of the first stage ST3801, the drain terminal is connected to the first disable node QB1, and the source terminal is It is connected to a power line for transmitting the second DC voltage source Vdc2.

The fifth switching device Tr5 provided in the server stage of the nth stage block responds to the scan pulse from any one of the stages provided in the n-1th stage block, and thus, the node for the second disable of the server stage. QB2 is discharged to the second DC voltage source Vdc2. That is, the fifth switching device Tr5 provided in the fourth stage ST3804 disables the second of the fourth stage ST3804 in response to the first scan pulse Vout1 from the first stage ST3801. The dragon node QB2 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the fifth switching element Tr5 provided in the fourth stage ST3804 is connected to the output terminal of the first stage ST3801, and the drain terminal of the fourth stage ST3804 is connected to the second terminal of the fourth stage ST3804. It is connected to the disable node QB2, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The sixth switching device Tr6 provided in the server stage of the nth stage block is turned on or turned off in response to the first AC voltage source Vac1, and outputs the first AC voltage source Vac1 when turned on. do. That is, the sixth switching device Tr6 provided in the fourth stage ST3804 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the sixth switching device Tr6 turns off the first AC voltage source Vac1. Output To this end, the gate terminal and the drain terminal of the sixth switching device Tr6 provided in the fourth stage ST3804 are connected to a power line for transmitting the first AC voltage source Vac1.

The seventh switching device Tr7 included in the server stage of the nth stage block is configured to disable the first stage of the server stage in response to the first AC voltage source Vac1 output from the sixth switching device Tr6. The node QB1 is charged with the first AC voltage source Vac1. That is, the seventh switching device Tr7 included in the fourth stage ST3804 is configured to generate the fourth stage ST3804 in response to the first AC voltage source Vac1 output from the sixth switching device Tr6. The first disable node QB1 is charged with the first AC voltage source Vac1. To this end, the gate terminal of the seventh switching device Tr7 provided in the fourth stage ST3804 is connected to the source terminal of the sixth switching device Tr6, and the drain terminal of the first AC voltage source Vac1. And a source terminal are connected to a first enable node (Q) QB1 of the fourth stage ST3804.

The eighth switching device Tr8 included in the server stage of the nth stage block removes the enable node Q in response to the first AC voltage source Vac1 charged in the first disable node QB1. 2 Discharge to DC voltage source (Vdc2). That is, the eighth switching device Tr8 included in the fourth stage ST3804 responds to the first AC voltage source Vac1 charged in the first disable node QB1 of the fourth stage ST3804. The enable node Q of the fourth stage ST3804 is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the eighth switching element Tr8 of the fourth stage ST3804 is connected to the first disable node QB1 of the fourth stage ST3804, and the drain terminal of the fourth stage ST3804. It is connected to the enabling node Q of ST3804, and the source terminal is connected to a power supply line for transmitting the second DC voltage source Vdc2.

The ninth switching device Tr9 provided in the server stage of the nth stage block responds to the first DC voltage source Vdc1 charged in the enabling node Q of the server stage, and is the seventh switching device Tr7. The seventh switching device Tr7 is turned off by supplying a second DC voltage source Vdc2 to the gate terminal of the second terminal. That is, the ninth switching device Tr9 included in the fourth stage ST3804 responds to the first DC voltage source Vdc1 charged in the enabling node Q of the fourth stage ST3804. The seventh switching device Tr7 is turned off by supplying a second DC voltage source Vdc2 to the gate terminal of the seventh switching device Tr7. To this end, the gate terminal of the ninth switching element Tr9 is connected to the enabling node Q of the fourth stage ST3804, and the drain terminal of the ninth switching element Tr9 is connected to the gate terminal of the seventh switching element Tr7. And a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The tenth switching device Tr10 provided in the server stage of the nth stage block responds to the scan pulse from any one of the stages provided in the n−1th stage block, and thus, the gate terminal of the seventh switching device Tr7. The seventh switching device Tr7 is turned off by supplying a second DC voltage source Vdc2 to the second switching device Tr7. That is, the tenth switching device Tr10 of the fourth stage ST3804 is connected to the gate terminal of the seventh switching device Tr7 in response to the first scan pulse Vout1 from the first stage ST3801. The seventh switching device Tr7 is turned off by supplying a second DC voltage source Vdc2. To this end, the gate terminal of the tenth switching element Tr10 provided in the fourth stage ST3804 is connected to the output terminal of the first stage ST3801, and the drain terminal of the seventh switching element Tr7. It is connected to the gate terminal, and the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The eleventh switching element Tr11 provided in the server stage of the nth stage block is turned on or turned off in response to the second AC voltage source Vac2, and turns on the second AC voltage source Vac2 when turned on. Output That is, the eleventh switching element Tr11 provided in the fourth stage ST3804 is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the eleventh switching element Tr11 turns off the second AC voltage source Vac2. Output To this end, the gate terminal and the drain terminal of the eleventh switching element Tr11 provided in the fourth stage ST3804 are connected to a power line for transmitting the second AC voltage source Vac2.

The twelfth switching element Tr12 included in the server stage of the nth stage block responds to the second alternating voltage source Vac2 output from the eleventh switching element Tr11, and thus provides the second disable node QB2. The second AC voltage source Vac2 is charged. That is, the twelfth switching device Tr12 provided in the fourth stage ST3804 responds to the second AC voltage source Vac2 output from the eleventh switching device Tr11, and thus, the second disable node QB2. Is charged to the second alternating current DC voltage source. To this end, the gate terminal of the twelfth switching element Tr12 provided in the fourth stage ST3804 is connected to the source terminal of the eleventh switching element Tr11, and the drain terminal of the second AC voltage source Vac2. Is connected to a power supply line for transmitting a signal, and a source terminal is connected to a second disable node (QB2).

The thirteenth switching element Tr13 included in the server stage of the nth stage block removes the enable node Q in response to the second AC voltage source Vac2 charged in the second disable node QB2. 2 Discharge to DC voltage source (Vdc2). That is, the thirteenth switching element Tr13 included in the fourth stage ST3804 responds to the enable node Q in response to the second AC voltage source Vac2 charged in the second disable node QB2. Discharge to the second DC voltage source Vdc2. To this end, the gate terminal of the thirteenth switching element Tr13 included in the fourth stage ST3804 is connected to the second disable node QB2, and the drain terminal is connected to the enable node Q. And, the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The fourteenth switching element Tr14 included in the server stage of the nth stage block is the gate terminal of the twelfth switching element Tr12 in response to the first DC voltage source Vdc1 charged in the enable node Q. The twelfth switching element Tr12 is turned off by supplying a second direct voltage voltage source to the twelfth switching element. That is, the fourteenth switching device Tr14 included in the server stage of the nth stage block may be configured in response to the first DC voltage source Vdc1 charged in the enable node Q. The twelfth switching element Tr12 is turned off by supplying a second series voltage source to the gate terminal. To this end, the gate terminal of the fourteenth switching element Tr14 of the fourth stage ST3804 is connected to the enable node Q, and the drain terminal thereof is connected to the gate terminal of the twelfth switching element Tr12. And, the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The fifteenth switching element Tr15 provided in the server stage of the nth stage block responds to a scan pulse from any one of the stages provided in the n-1th stage block, so that the gate of the twelfth switching element Tr12 is gated. The twelfth switching element Tr12 is turned off by supplying a second DC voltage source Vdc2 to the terminal. That is, the fifteenth switching device Tr15 of the fourth stage ST3804 turns off the twelfth switching device Tr12 in response to the first scan pulse Vout1 from the first stage ST3801. Let's do it. To this end, the gate terminal of the fifteenth switching element Tr15 provided in the fourth stage ST3804 is connected to the output terminal of the first stage ST3801, and the drain terminal of the twelfth switching element Tr12 It is connected to the gate terminal, and the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The sixteenth switching element Tr16 included in the server stage of the nth stage block responds to the scan pulse from any one of the stages included in the n + 1th stage block, thereby enabling the node Q for enabling the second node. Discharge to DC voltage source (Vdc2). That is, the sixteenth switching element Tr16 of the fourth stage ST3804 may enable the node Q for enabling the fourth stage ST3804 in response to the seventh scan pulse Vout7 from the seventh stage. ) Is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the sixteenth switching element Tr16 of the fourth stage ST3804 is connected to the output terminal of the seventh stage, the drain terminal is connected to the enable node Q, The source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

Meanwhile, the first, fourth, fifth, tenth, and fifteenth switching elements Tr1, Tr4, Tr5, and Tr10 provided in each of the first to third stages ST3801 to ST3803 in the first stage block SB1. , And Tr15 are turned on by the start pulse Vst.

FIG. 41 is a diagram illustrating a circuit configuration of the fifth and sixth stages of FIG. 38.

The fifth and sixth stages ST3805 and ST3806 are first and second client stages provided in the second stage block SB2, and the node controllers 3805 of the first and second client stages are the first to the second. 4 switching element (Tr4).

Here, since the circuit configurations of the first and second client stages are the same, only the circuit configuration of the first client stage will be described.

The first switching device Tr1 provided in the first client stage of the nth stage block receives scan pulses from any one of the stages provided in the n-1th stage block, and enables the first client stage. The node Q is charged with the first DC voltage source Vdc1. That is, the first switching device Tr1 provided in the fifth stage ST3805 receives the first scan pulse Vout1 from the first stage ST3801 and enables the node Q for enabling the first client stage. Charge to the first DC voltage source (Vdc1). To this end, the gate terminal of the first switching device Tr1 provided in the fifth stage ST3805 is connected to the output terminal of the first stage ST3801, and the drain terminal of the first DC voltage source Vdc1. It is connected to the transmitting power line, and the source terminal is connected to the enable node (Q).

The second switching element Tr2 included in the first client stage of the nth stage block is the first AC voltage source Vac1 supplied to the first enable node Q of the first client stage. The enable node Q of the first client stage is discharged to the second DC voltage source Vdc2. That is, the second switching device Tr2 included in the fifth stage ST3805 may respond to the first AC voltage source Vac1 supplied to the first enable node Q of the fifth stage ST3805. The enable node Q of the first client stage is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the second switching element Tr2 provided in the fifth stage ST3805 is connected to the first disable node QB1, and the drain terminal is connected to the enable node Q. And, the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The third switching element Tr3 provided in the first client stage of the nth stage block is in response to the second AC voltage source Vac2 supplied to the second enable node Q of the first client stage. The enable node Q of the first client stage is discharged to the second DC voltage source Vdc2. That is, the third switching device Tr3 included in the fifth stage ST3805 may respond to the second AC voltage source Vac2 supplied to the second enable node Q of the fifth stage ST3805. The enable node Q of the first client stage is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the second switching element Tr2 provided in the fifth stage ST3805 is connected to the second disable node QB2, and the drain terminal is connected to the enable node Q. And, the source terminal is connected to the power line for transmitting the second DC voltage source (Vdc2).

The fourth switching device Tr4 provided in the first client stage of the nth stage block receives scan pulses from any one of the stages provided in the n + 1th stage block for enabling the first client stage. The node Q is discharged to the second DC voltage source Vdc2. That is, the fourth switching device Tr4 provided in the fifth stage ST3805 receives the seventh scan pulse from the seventh stage and supplies the enable node Q of the fifth stage ST3805 to the second direct current. Discharge to voltage source Vdc2. To this end, the gate terminal of the fourth switching device Tr4 provided in the fifth stage ST3805 is connected to the output terminal of the seventh stage, the drain terminal is connected to the enable node Q, The source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The operation of the shift register according to the embodiment of the present invention configured as described above is as follows.

Here, it is assumed that the first AC voltage source Vac1 is maintained at the positive voltage during the first frame period, and the second AC voltage source Vac2 is maintained at the negative voltage, and the first AC voltage source is maintained during the second frame period. Assume that Vac1 is maintained at a negative voltage, and the second AC voltage source Vac2 is maintained at a positive voltage. That is, assuming that the first AC voltage source Vac1 remains positive and the second AC voltage source Vac2 remains negative during the odd frame period, the first AC voltage source Vac1 during the even frame period. Is maintained at the negative polarity, and the second AC voltage source Vac2 is maintained at the positive polarity.

First, the start pulse Vst turns on the first, fourth, fifth, tenth, and fifteenth switching elements Tr1, Tr4, Tr5, Tr10, and Tr15 of the first stage ST3801. Then, the first DC voltage source Vdc1 is supplied to the enable node Q through the turned-on first switching device Tr1. In this case, as the enable node Q is charged with the first DC voltage source Vdc1, the second, third, ninth, 14, and 14 gate terminals are connected to the enable node Q. And pull-up switching devices Tr2, Tr3, Tr9, Tr14, and Tru are turned on.

The second DC voltage source Vdc2 is supplied to the first disable node QB1 through the turned-on second and fourth switching devices Tr2 and Tr4. Accordingly, the first disable node QB1 is discharged, and the eighth and first pull-down switching devices Tr8 and Trd1 having a gate terminal connected to the first disable node QB1 are turned off. do.

The second DC voltage source Vdc2 is supplied to the second disable node QB2 through the turned-on third and fifth switching devices Tr3 and Tr5. Accordingly, the second disable node QB2 is discharged, and the thirteenth and second pull-down switching devices Tr13 and Trd2 having a gate terminal connected to the second disable node QB2 are turned off. do.

The second DC voltage source Vdc2 is supplied to the gate terminal of the seventh switching device Tr7 through the turned-on ninth and tenth switching devices Tr9 and Tr10. In addition, the seventh switching element is driven by the first alternating voltage source Vac1 through the sixth switching element Tr6 which is always turned on during the first frame period by the first alternating voltage source Vac1 having a positive polarity. It is supplied to the gate terminal of Tr7. Therefore, the second DC voltage source Vdc2 and the first AC voltage source Vac1 are supplied together to the gate terminal of the seventh switching element Tr7. In this case, the number of switching elements for supplying the second DC voltage source Vdc2 to the gate terminal of the seventh switching element Tr7 supplies the first AC voltage source Vac1 to the gate terminal of the seventh switching element Tr7. Since it is larger than the number of switching elements, the gate terminal of the seventh switching element Tr7 is maintained as the second DC voltage source Vdc2. Thus, the seventh switching element Tr7 is turned off.

The second DC voltage source Vdc2 is supplied to the gate terminal of the twelfth switching element Tr12 through the turned on fourteenth and fifteenth switching elements Tr14 and Tr15. Thus, the twelfth switching element Tr12 is turned off. On the other hand, the eleventh switching element Tr11 is always turned off for one frame by the negative second AC voltage source Vac2.

As described above, the enable node Q of the first stage ST3801 is charged by the start pulse Vst, and the first and second disable nodes QB1 and QB2 are discharged. That is, the first stage ST3801 is enabled by the start pulse Vst.

The start pulse Vst is also supplied to the second and third stages ST3802 and ST3803 to enable the second and third stages ST3802 and ST3803.

That is, the start pulse Vst turns on the first switching device Tr1 of the second stage ST3802. Then, the first DC voltage source Vdc1 is supplied to the enable node Q through the turned-on first switching device Tr1. In this case, as the enable node Q is charged with the first DC voltage source Vdc1, the pull-up switching device Tru having a gate terminal connected to the enable node Q is turned on. In addition, since the first disable node QB1 of the second stage ST3802 is electrically connected to the first disable node QB1 of the first stage ST3801, the second disable node QB1 is electrically connected to the first disable node QB1. The first disable node QB1 of ST3802 is maintained in a discharged state. Further, since the second disable node QB2 of the second stage ST3802 is electrically connected to the second disable node QB2 of the first stage ST3801, the second disable node QB2 is electrically connected to the second disable node QB2. The second disable node QB2 of ST3802 is maintained in a discharged state.

Similarly, the enable node Q of the third stage ST3803 is in a charged state, and the first and second disable nodes QB1 and QB2 are in a discharged state.

As described above, the first to third stages ST3801 to ST3803 provided in the first stage block SB1 are enabled by the start pulse Vst.

Subsequently, when the first clock pulse CLK1 is supplied to the pull-up switching device Tru of the first stage ST3801, the pull-up switching device Tru receives the first clock pulse CLK1 as the first scan pulse. Vout1) and supplies it to the stages provided in the first gate line and the second stage block SB2.

That is, the first scan pulse Vout1 output from the first stage ST3801 is applied to the stages (fourth, fifth, and sixth stages ST3804, ST3805, ST3806) of the second stage block SB2. The first scan pulse Vout1 serves as a start pulse Vst for enabling the fourth to sixth stages ST3804 to ST3806. Accordingly, the fourth to sixth stages ST3804 to ST3806 are simultaneously enabled through the operation as described above.

Thereafter, when the second clock pulse CLK2 is supplied to the pull-up switching device Tru of the second stage ST3802, the pull-up switching device Tru receives the second clock pulse CLK2 as a second scan pulse ( Output as Vout2) and supply it to the second gate line.

Thereafter, when the third clock pulse CLK3 is supplied to the pull-up switching device Tru of the third stage ST3803, the pull-up switching device Tru receives the third clock pulse CLK3 as a third scan pulse. Output as Vout3) and supply it to the third gate line.

Thereafter, when the fourth clock pulse CLK4 is supplied to the pull-up switching device Tru of the fourth stage ST3804, the pull-up switching device Tru receives the fourth clock pulse CLK4 as a fourth scan pulse. Vout4) and supplies it to the stages provided in the fourth gate line and the third stage block. In addition, the fourth stage ST3804 supplies the fourth scan pulse Vout4 to stages (first, second, and third stages ST3801, ST3802, ST3803) of the first stage block SB1. Thus, the first to third stages ST3801 to ST3803 are disabled.

This disable operation is described as follows.

That is, the fourth scan pulse Vout4 output from the fourth stage ST3804 is also supplied to the sixteenth switching element Tr16 of the first stage ST3801. That is, the fourth scan pulse Vout4 is supplied to the gate terminal of the sixteenth switching element Tr16 provided in the first stage ST3801. Accordingly, the first stage ST3801 is disabled.

In detail, the fourth scan pulse Vout4 turns on the sixteenth switching element Tr16 included in the first stage ST3801. Then, the second DC voltage source Vdc2 is supplied to the enabling node Q of the first stage ST3801 through the turned-on sixteenth switching element Tr16. As a result, the enable node Q of the first stage ST3801 is discharged. Accordingly, the second, third, ninth, fourteenth, and pull-up switching elements Tr2, Tr3, Tr9, Tr14, and Tru connected to the enabling node Q of the first stage ST3801 are turned on. Is off. In addition, at this time, the first, fourth, fifth, tenth, and fifteenth switching of the first stage ST3801 supplied with the start pulse Vst in the low state as the start pulse Vst changes to low. Elements Tr1, Tr4, Tr5, Tr10, and Tr15 are turned off.

Here, as the second, fourth, ninth, and tenth switching elements Tr2, Tr4, Tr9, and Tr10 of the first stage ST3801 are turned off, the first stage of the first stage ST3801 is turned off. The disable node QB1 is charged with the first AC voltage source Vac1 applied through the seventh switching element Tr7. Therefore, the eighth and first pull-down switching devices Tr8 and Trd1 having the gate terminal connected to the first disable node QB1 of the first stage ST3801 are turned on.

As the third and fifth switching devices Tr3 and Tr5 of the first stage ST3801 are turned off, the second disable node QB2 of the first stage ST3801 maintains a discharge state. do. Accordingly, the thirteenth and second pull-down switching devices Tr13 and Trd2 having the gate terminal connected to the second disable node QB2 of the first stage ST3801 maintain the turn-off state.

In this manner, the enable node Q and the second disable node QB2 of the first stage ST3801 are discharged by the fourth scan pulse Vout4 from the fourth stage ST3804. The first disable node QB1 is charged. That is, the first stage ST3801 is disabled in response to the fourth scan pulse Vout4 from the fourth stage ST3804. The disabled first stage ST3801 outputs the second DC voltage source Vdc2 through the first pull-down switching device Trd1 provided therein. Then, the second DC voltage source Vdc2 is supplied to the first gate line.

The fourth scan pulse Vout4 from the fourth stage ST3804 is also supplied to the second and third stages ST3802 and ST3803 to disable the second and third stages ST3802 and ST3803.

This disable operation is described as follows.

That is, the fourth scan pulse Vout4 output from the fourth stage ST3804 is supplied to the fourth switching device Tr4 of the second stage ST3802. Then, the fourth switching device Tr4 is turned on, and the second DC voltage source Vdc2 is enabled through the turned-on fourth switching device Tr4 to enable the node of the second stage ST3802. Q) is supplied. As a result, the enable node Q is discharged, and the pull-up switching device Tru, which has a gate terminal connected to the discharged enable node Q, is turned on.

The states of the first and second disable nodes QB1 and QB2 of the second stage ST3802 are different from the states of the first and second disable nodes QB1 and QB2 of the first stage ST3801. same.

That is, when the first stage ST3801 is disabled, the first disable node QB1 of the second stage ST3802 is charged, and the second disable node QB2 is discharged. Accordingly, the first pull-down switching device Trd1 of the second stage ST3802 is turned on and the second pull-down switching device Trd2 is turned off.

In summary, when the second stage ST3802 is disabled, the pull-up switching device Tru and the second pull-down switching device Trd2 of the second stage ST3802 are turned off and the first pull-down switching device Trd1) is turned on. The second DC voltage source Vdc2 is supplied to the second gate line through the turned-on first pull-down switching device Trd1.

The third stage ST3803, which receives the fourth scan pulse Vout4, is also disabled in the same manner as the second stage ST3802.

Meanwhile, in the second frame period, the first AC voltage source Vac1 is maintained as negative polarity, and the second AC voltage source Vac2 is maintained as positive polarity. Thus, when the stages ST3801, ST3802, ST3803, ... are disabled, the first disable node QB1 of each stage ST3801, ST3802, ST3803, ... is discharged, The second disable node QB2 is charged. Therefore, when each stage is disabled, the second DC voltage source Vdc2 is output through the second pull-down switching element Trd2 having a gate terminal connected to the second disable node QB2.

On the other hand, the server stage may have the following circuit configuration.

FIG. 42 is a diagram illustrating still another circuit configuration of the fourth stage of FIG. 38.

The first switching device Tr1 provided in the server stage of the nth stage block responds to the scan pulse from any one of the stages provided in the n-1th stage block, thereby enabling the node Q for enabling the first node. Charge with DC voltage source (Vdc1). That is, in response to the first scan pulse Vout1 from the first stage ST3801, the first switching device Tr1 included in the fourth stage ST3804 supplies the enable node Q to the first DC voltage source. Charge to (Vdc1). To this end, the gate terminal of the first switching device Tr1 provided in the fourth stage ST3804 is connected to the output terminal of the first stage ST3801 EST1, and the drain terminal of the first DC voltage source Vdc1. It is connected to the power supply line for transmitting the, and the source terminal is connected to the enable node (Q).

The second switching device Tr2 provided in the server stage of the nth stage block responds to the scan pulse from any one of the stages provided in the n-1th stage block, thereby turning off the first disable node QB1. Discharge to the second DC voltage source Vdc2. That is, the second switching device Tr2 included in the fourth stage ST3804 responds to the first scan pulse Vout1 from the first stage ST3801 and EST1, and thus the first disable node QB1. Is discharged to the second DC voltage source Vdc2. For this purpose, the gate terminal of the second switching element Tr2 provided in the fourth stage ST3804 is connected to the first stage ST3801 EST1, and the drain terminal is the first disable node QB1. And a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

Provided in the server stage of the nth stage block The third switching device Tr3 discharges the second disable node QB2 to the second DC voltage source Vdc2 in response to a scan pulse from any one of the stages provided in the n-1 stage block. . That is, the third switching device Tr3 included in the fourth stage ST3804 responds to the first scan pulse Vout1 from the first stage ST3801 and EST1, and thus the second disable node QB2. ) Is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the third switching element Tr3 is connected to the first stage ST3801 (EST1), the drain terminal is connected to the first disable node QB1, and the source terminal is connected to the second terminal. It is connected to a power supply line that transmits a DC voltage source Vdc2.

The fourth switching device Tr4 provided in the server stage of the nth stage block is turned on or turned off in response to the first AC voltage source Vac1, and turns on the first disable node QB1 at turn-on. The first AC voltage source Vac1 is charged. That is, the fourth switching device Tr4 provided in the fourth stage ST3804 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the first disable node QB1 is turned on. Is charged with a first AC voltage source Vac1. To this end, the gate terminal of the fourth switching element Tr4 provided in the fourth stage ST3804 is connected to a power line for transmitting the first AC voltage source Vac1, and the drain terminal of the fourth switching element Tr4 is connected to the first AC voltage source Vac1. Is connected to a power supply line for transmitting a signal, and a source terminal is connected to a first disable node (QB1).

The fifth switching device Tr5 provided in the server stage of the nth stage block discharges the second disable node QB2 to the second DC voltage source Vdc2 in response to the first AC voltage source Vac1. That is, the fifth switching device Tr5 of the fourth stage ST3804 discharges the second disable node QB2 to the second DC voltage source Vdc2 in response to the first AC voltage source Vac1. . To this end, the gate terminal of the fifth switching device Tr5 provided in the fourth stage ST3804 is connected to a power line for transmitting the first AC voltage source Vac1, and the drain terminal is connected to a second disable node ( QB2), and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The sixth switching device Tr6 included in the server stage of the nth stage block is turned on or turned off in response to the second AC voltage source Vac2, and turns on the second disable node QB2 at turn-on. The second AC voltage source Vac2 is charged. That is, the sixth switching device Tr6 included in the fourth stage ST3804 is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the second disable node QB2 is turned on. Charge to the second AC voltage source (Vac2). To this end, the gate terminal of the sixth switching element Tr6 is connected to a power line for transmitting the second AC voltage source Vac2, and the drain terminal is connected to a power line for transmitting the second AC voltage source Vac2. The source terminal is connected to the second disable node QB2.

The seventh switching device Tr7 included in the server stage of the nth stage block discharges the first disable node QB1 to the second DC voltage source Vdc2 in response to the second AC voltage source Vac2. That is, the seventh switching element Tr7 provided in the fourth stage ST3804 discharges the first disable node QB1 to the second DC voltage source Vdc2 in response to the second AC voltage source Vac2. Let's do it. To this end, the gate terminal of the seventh switching element Tr7 is connected to a power line for transmitting the second AC voltage source Vac2, the drain terminal is connected to the first disable node QB1, and The source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The eighth switching device Tr8 included in the server stage of the nth stage block may select the first disable node QB1 in response to the first DC voltage source Vdc1 charged in the enable node Q. 2 Discharge to DC voltage source (Vdc2). That is, the eighth switching device Tr8 included in the fourth stage ST3804 responds to the first DC voltage source Vdc1 charged in the enabling node Q, and thus, the first disable node QB1 is turned off. Discharge to the second DC voltage source Vdc2. To this end, a gate terminal of the eighth switching element Tr8 is connected to the enable node Q, a drain terminal is connected to the first disable node QB1, and a source terminal of the eighth switching element Tr8 is connected. 2 It is connected to the power line for transmitting DC voltage source (Vdc2).

The ninth switching element Tr9 included in the server stage of the nth stage block responds to the first DC voltage source Vdc1 charged in the enabling node Q, thereby removing the second disable node QB2. 2 Discharge to DC voltage source (Vdc2). That is, the ninth switching element Tr9 provided in the fourth stage ST3804 responds to the first DC voltage source Vdc1 charged in the enable node Q, and thus the second disable node QB2. Discharge to the second DC voltage source Vdc2. To this end, the gate terminal of the ninth switching element Tr9 is connected to the enable node Q, the drain terminal is connected to the second disable node QB2, and the source terminal is connected to the second node. It is connected to a power supply line that transmits a DC voltage source Vdc2.

The tenth switching device Tr10 included in the server stage of the nth stage block may remove the enable node Q in response to the first AC voltage source Vac1 charged in the first disable node QB1. 2 Discharge to DC voltage source (Vdc2). That is, the tenth switching element Tr10 included in the fourth stage ST3804 responds to the first alternating voltage source Vac1 charged in the first disable node QB1 and turns on the enable node Q. FIG. Discharge to the second DC voltage source Vdc2. To this end, the gate terminal of the tenth switching element Tr10 is connected to the first disable node QB1, the drain terminal is connected to the enable node Q, and the source terminal is connected to the second node. It is connected to a power supply line that transmits a DC voltage source Vdc2.

The eleventh switching element Tr11 included in the server stage of the nth stage block removes the enable node Q in response to the second AC voltage source Vac2 charged in the second disable node QB2. 2 Discharge to DC voltage source (Vdc2). That is, the eleventh switching element Tr11 provided in the fourth stage ST3804 responds to the enable node Q in response to the second AC voltage source Vac2 charged in the second disable node QB2. Discharge to the second DC voltage source Vdc2. To this end, the gate terminal of the eleventh switching element Tr11 is connected to the second disable node QB2, the drain terminal is connected to the enable node Q, and the source terminal is connected to the second node. It is connected to a power supply line that transmits a DC voltage source Vdc2.

The twelfth switching element Tr12 provided in the server stage of the nth stage block responds to the scan pulse from any one of the stages provided in the n + 1th stage block, thereby enabling the node Q for enabling the second node. Discharge to DC voltage source (Vdc2). That is, the twelfth switching element Tr12 included in the fourth stage ST3804 discharges the enable node Q to the second DC voltage source Vdc2 in response to the seventh scan pulse from the seventh stage. . To this end, the gate terminal of the twelfth switching element Tr12 provided in the fourth stage ST3804 is connected to the output terminal of the seventh stage, the drain terminal is connected to the enable node Q, and the source terminal. Is connected to a power line for transmitting the second DC voltage source Vdc2.

The thirteenth switching device Tr13 included in the server stage of the nth stage block is connected to the first disable node QB1 in response to a scan pulse from any one of the stages included in the n + 1th stage block. The first AC voltage source Vac1 is supplied. That is, the twelfth switching element Tr12 included in the fourth stage ST3804 may respond to the seventh scan pulse from the seventh stage, so that the first alternating voltage source Q is connected to the first disable node QB1 Q. Supply Vac1). To this end, the gate terminal of the thirteenth switching element Tr13 provided in the fourth stage ST3804 is connected to the output terminal of the seventh stage, and the drain terminal thereof is connected to a power line for transmitting the first AC voltage source Vac1. The source terminal is connected to the first disable node QB1. In this case, the first disable node QB1 is charged or discharged according to the polarity of the first AC voltage source Vac1.

The fourteenth switching element Tr14 included in the server stage of the nth stage block is connected to the second disable node QB2 in response to a scan pulse from any one of the stages included in the n + 1th stage block. The second AC voltage source Vac2 is supplied. That is, the twelfth switching element Tr12 included in the fourth stage ST3804 supplies the second alternating voltage source Vac2 to the second disable node QB2 in response to the seventh scan pulse from the seventh stage. Supply. To this end, the gate terminal of the twelfth switching element Tr12 provided in the fourth stage ST3804 is connected to the output terminal of the seventh stage, and the drain terminal thereof is connected to a power line for transmitting the second AC voltage source Vac2. The source terminal is connected to the second disable node QB2. In this case, the second disable node QB2 is charged or discharged according to the polarity of the second AC voltage source Vac2.

The sub-stage configured as described above receives the clock pulses as described above and outputs the scan pulses.

Hereinafter, the shift register according to the tenth embodiment of the present invention will be described.

43 is a diagram illustrating a shift register according to a tenth embodiment of the present invention, and FIG. 44 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 43 and an output signal output from each stage.

The shift register according to the tenth embodiment of the present invention has a plurality of stages (ST4301, ST4302, ST4303, ...) for driving a plurality of gate lines, as shown in FIG.

This shift register includes a plurality of stage blocks SB1, SB2, ..., each stage block SB1, SB2, ... containing one server stage and two client stages.

The server stage and the client stage are the node control unit 4305, the enable node Q, the first disable node QB1, and the second disable node QB2, as described above in the previous embodiment. , A pull-up switching device Tru, a first pull-down switching device Trd1, and a second pull-down switching device Trd2.

Since the configuration of each stage block SB1, SB2, ... is the same, the server stage, the first client stage, and the second client stage included in the first stage block SB1 will be described as follows.

The first disable node QB1 of the server stage (first stage ST4301) included in the first stage block SB1 is a first client stage (second) provided in the first stage block SB1. The node QB1 for the first disable of the stage ST4302, and the node QB1 for the first disable of the second client stage (the third stage ST4303) included in the first stage block SB1. Is electrically connected to the

The first stage provided in the n-th stage block is enabled in response to the scan pulse from the first stage provided in the n-th stage block. The enabled first stage of the nth stage block is supplied with a clock pulse to output a scan pulse, and the scan pulse is applied to the corresponding gate line, the third stage of the nth stage block, and the n + 1th stage block. The first stage and all stages of the n-th stage block are supplied.

The second stage provided in the n-th stage block is enabled in response to the scan pulse from the third stage provided in the n-th stage block. The enabled second stage of the n-th stage block receives a clock pulse to output a scan pulse, and supplies the scan pulse to a corresponding gate line.

The third stage provided in the nth stage block is enabled in response to the scan pulse from the first stage provided in the nth stage block. The enabled third stage of the nth stage block receives a clock pulse to output a scan pulse, and supplies the scan pulse to the second stage of the corresponding gate line and the n + 1th stage block.

Each stage having such a configuration receives one of the first to fourth clock pulses CLK1 to CLK4 and outputs a scan pulse thereof.

Since the first to fourth clock pulses CLK1 to CLK4 are the same as the first to fourth clock pulses CLK1 to CLK4 described with reference to FIG. 38C, description thereof will be omitted.

The configuration of each stage can have any of the circuit configurations described above.

On the other hand, since the server stage has a larger number of switching elements than the client stage, the size of the server stage is inevitably larger than the size of the client stage.

When the server stage and the client stage thus constructed are arranged in one direction, the width of the shift register including the server stage and the client stage depends on the width of the large server stage.

The width of the server stage may be further reduced by moving some switching elements included in the server stage to the client stage. This reduces the width of the shift register.

Meanwhile, the first switching device Tr1 illustrated in FIGS. 4, 6, 29a, 29b, 30, 31, 34a, 34b, 37, 40, 41, and 42 is as follows. You can change it as well.

45 is a diagram showing another circuit configuration of the first switching device.

First, the first switching device Tr1 of the above-described drawing may have a diode configuration, as shown in FIG. 35A. The first switching device Tr1 configured as described above charges the enable node Q with the start pulse or the scan pulse in response to a start pulse from the timing controller or a scan pulse from the front stage.

The first terminal 511 shown in FIG. 35A has a gate terminal of the eighth switching device Tr8 shown in FIG. 4 (or a gate terminal of the sixth switching device Tr6 shown in FIG. 6). The second terminal is connected to the enable node Q. In such a configuration, the first DC voltage source Vdc1 is not necessary in the present invention.

In addition, the first switching device Tr1 illustrated in the above-described drawings may include the A and B switching devices TrA and TrB connected in series, as shown in FIG. 35B. .

The A switching element TrA has the diode configuration described above, and the drain terminal of the B switching element TrB is connected to the source terminal of the A switching element TrA.

The gate terminal and the drain terminal of the A switching element TrA are supplied with the start pulse Vst from the timing controller or the scan pulse from the previous stage. The gate terminal of the B switching element TrB is supplied with a start pulse supplied to the A switching element TrA or a clock pulse synchronized with the scan pulse.

The first switching device Tr1 configured as described above charges the enable node Q with the start pulse or the scan pulse in response to the start pulse and the clock pulse or the scan pulse and the clock pulse.

The first terminal 521 shown in FIG. 35B has a gate terminal of the eighth switching element Tr8 shown in FIG. 4 (or a gate terminal of the sixth switching element Tr6 shown in FIG. 6). The second terminal 522 is connected to the enabling node Q. When configured in this way, the first DC voltage source (Vdc1) (Vdc1) is not necessary in the present invention. Instead of the first terminal 521, the third terminal 523 may be connected to the gate terminal of the eighth switching device Tr8 (or the gate terminal of the sixth switching device Tr6).

4 and 6, the first switching device Tr1 shown in FIG. 27 (c) may be composed of the A and B switching devices TrA and TrB connected in parallel. Can be.

Here, the A switching device TrA outputs the first DC voltage source Vdc1 in response to the start pulse Vst from the timing controller or the scan pulse from the previous stage. The B switching element TrB outputs the first DC voltage source Vdc1 in response to a clock pulse. The drain terminal of the A switching element TrA is connected to the drain terminal of the B switching element TrB, and the source terminal of the A switching element TrA is the source terminal of the B switching element TrB. And are connected to each other. The clock pulse is synchronized with the start pulse Vst or scan pulse.

The first terminal 531 shown in FIG. 35C has a gate terminal of the eighth switching element Tr8 shown in FIG. 4 (or a gate terminal of the sixth switching element Tr6 shown in FIG. 6). Is connected to the enable node (Q). Instead of the first terminal 531, a third terminal 533 may be connected to the gate terminal of the eighth switching element Tr8 (or the gate terminal of the sixth switching element Tr6).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

In the shift register according to the present invention, the node controller provided in each stage controls not only the state of the node of the stage to which it belongs, but also the state of the node of the other stage.

Therefore, the number of switching elements included in each node controller can be reduced, and the area of each stage can be reduced.

Claims (103)

A shift register having a plurality of stages that sequentially output scan pulses for driving a plurality of conductive lines, At least one stage, An enabling node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage source according to a logic state of each of the disable nodes; And And a node controller for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from itself; Each stage includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and a second pull-down switching element connected to the second disable node. Including; The node controller provided in the 2n-3 (n is a natural number of 2 or more) stages controls the logic states of the enable node and the first disable node provided in the 2n-3th stage, To control the logic state of the first disable node provided in the stage, The node controller provided in the 2n-2th stage controls the logic states of the enable node and the second disable node included in the 2n-2nd stage, and the second control unit provided in the 2n-2nd stage. 1 A shift register controlling the logic state of a node for disabling. delete The method of claim 1, A first disable node provided in the 2n-3rd stage and a first disable node provided in the 2n-2nd stage are electrically connected to each other; And, And a second disable node provided in the 2n-2 th stage and a second disable node provided in the 2n-3 th stage are electrically connected to each other. The method of claim 1, The node control unit provided in the 2n-3rd stage is configured to determine a logic state of the first disable node provided in the 2n-3rd stage and a logic state of the first disable node provided in the 2n-2nd stage. Controlled by the first AC voltage source, The node controller provided in the 2n-2th stage is configured to determine a logic state of a second disable node provided in the 2n-2nd stage and a second disable node provided in the 2n-3rd stage. A shift register, characterized in that controlled by a second alternating current voltage source having a phase inverted with respect to the alternating current voltage source. 5. The method of claim 4, The 2n-1st stage and the 2nth stage are enabled in response to the scan pulses from the 2n-3rd stage and are disabled in response to the scan pulses from the 2n + 2th stage, 2n-3rd stage and 2n-2nd stage are disabled in response to the scan pulse from the 2nth stage, and And a 2n + 1 th stage and a 2n + 2 th stage are enabled in response to the scan pulse from the 2n-1 th stage. delete delete delete delete delete delete 6. The method of claim 5, The node controller provided in the 2n-1th stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-3th stage; A second switching element which is turned on or off in response to a first AC voltage source supplied to a first disable node, and discharges the enable node to a second DC voltage source when it is turned on; Turn on or off in response to a second alternating current voltage source supplied to the second disable node of the 2n-1th stage through a 2nth stage, and enable the 2n-1st stage at turn-on A third switching element for discharging the node to a second DC voltage source; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 2th stage; A turn-on or turn-off in response to the first alternating current voltage source, which, when turned on, charges the first disable node of the 2n-1 stage and the first disable node of the 2nth stage with the first alternating current voltage source; 5 switching elements; A sixth switching device configured to discharge the first disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to the scan pulse from the 2n-3rd stage; And A seventh switching element configured to discharge the first disabling node of the 2n-1st stage and the first disabling node of the 2nth stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; The shift register, characterized in that configured to include. delete delete 13. The method of claim 12, The node controller provided in the 2nth stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-3th stage; The turn-on or turn-off is performed in response to the first AC voltage source supplied to the first disable node of the 2n-th stage through the 2n-1th stage, and the enable node of the 2n-th stage is turned off. A second switching element for discharging to a second DC voltage source; A third switching element that is turned on or turned on in response to a second alternating current voltage source supplied to the second disable node, and discharges the enable node to a second DC voltage source at turn-on; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 2th stage; It is turned on or off in response to the second alternating voltage source, and when turned on, charging the second disable node of the 2n th stage and the second disable node of the 2n-1 st stage with the second alternating voltage source. A fifth switching element; A sixth switching device discharging the second disabling node of the 2n-th stage and the second disabling node of the 2n-1th stage to a second DC voltage source in response to the scan pulse from the 2n-3rd stage; And A seventh switching element discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; The shift register, characterized in that configured to include. 16. The method of claim 15, The node controller provided in the 2nth stage is An eighth switching element for charging or discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second AC voltage source in response to the scan pulse from the 2n + 2th stage; The shift register, characterized in that further comprises. 16. The method of claim 15, The node controller provided in the 2nth stage is And an eighth switching element which is turned on or off in response to the second alternating current voltage source and discharges the first disabling node of the 2n-th stage to a second direct current voltage source during turn-on. Shift register. 5. The method of claim 4, The 2n-1st stage and the 2nth stage are enabled in response to the scan pulses from the 2n-2th stage and are disabled in response to the scan pulses from the 2n + 2th stage, 2n-3rd stage and 2n-2nd stage are disabled in response to the scan pulse from the 2nth stage, and And a 2n + 1th stage and a 2n + 2th stage are enabled in response to the scan pulse from the 2nth stage. The method of claim 18, The node controller provided in the 2n-1th stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-2th stage; A second switching device configured to discharge the enable node to a second DC voltage source in response to a first AC voltage source supplied to a first disable node; A third switching for discharging the enable node of the 2n-1st stage to the second DC voltage source in response to a second AC voltage source supplied to the second disable node of the 2n-1st stage through a 2nth stage; device; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 2th stage; A fifth switching device that is turned on or turned off in response to a first AC voltage source and charges a common node with the first AC voltage source when turned on; A sixth switching device discharging the common node to a second DC voltage source in response to a first DC voltage source charged in the enable node; A seventh switching element configured to charge the first disabling node of the 2n-1st stage and the first disabling node of the 2nth stage with the first AC voltage source in response to the first AC voltage source supplied to the common node; ; An eighth switching element configured to discharge the first disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to a scan pulse from the 2n-2th stage; And A ninth switching for discharging the first disabling node of the 2n-1st stage and the first disabling node of the 2nth stage to a second DC voltage source in response to the first DC voltage source charged in the enable node; A shift register comprising a device. delete delete delete delete delete The method of claim 18, The node controller provided in the 2n-1th stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-2th stage; A second switching element which is turned on or off in response to a first AC voltage source supplied to a first disable node, and discharges the enable node to a second DC voltage source when it is turned on; Turn on or off in response to a second alternating current voltage source supplied to the second disable node of the 2n-1th stage through a 2nth stage, and enable the 2n-1st stage at turn-on A third switching element for discharging the node to a second DC voltage source; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 2th stage; A turn-on or turn-off in response to the first alternating current voltage source, which, when turned on, charges the first disable node of the 2n-1 stage and the first disable node of the 2nth stage with the first alternating current voltage source; 5 switching elements; A sixth switching element configured to discharge the first disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to a scan pulse from the 2n-2nd stage; And A seventh switching element configured to discharge the first disabling node of the 2n-1st stage and the first disabling node of the 2nth stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; The shift register, characterized in that configured to include. delete delete 26. The method of claim 25, The node controller provided in the 2nth stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-2th stage; The turn-on or turn-off is performed in response to the first AC voltage source supplied to the first disable node of the 2n-th stage through the 2n-1th stage, and the enable node of the 2n-th stage is turned off. A second switching element for discharging to a second DC voltage source; A third switching element that is turned on or turned on in response to a second alternating current voltage source supplied to the second disable node, and discharges the enable node to a second DC voltage source at turn-on; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 2th stage; It is turned on or off in response to the second alternating voltage source, and during turn-on, charges the second disable node of the 2n th stage and the second disable node of the 2n-1 th stage with a second alternating voltage source. A fifth switching element to make; A sixth switching element configured to discharge the second disabling node of the 2n-th stage and the second disabling node of the 2n-1th stage to a second DC voltage source in response to the scan pulse from the 2n-2th stage; And A seventh switching element discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; The shift register, characterized in that configured to include. 29. The method of claim 28, The node controller provided in the 2nth stage is An eighth switching element for charging or discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second AC voltage source in response to the scan pulse from the 2n + 2th stage; The shift register, characterized in that further comprises. 29. The method of claim 28, The node controller provided in the 2nth stage is And an eighth switching element which is turned on or off in response to the second alternating current voltage source and discharges the first disabling node of the 2nth stage to a second direct current voltage source when turned on. Shift register. 5. The method of claim 4, The 2n-1st stage and the 2nth stage are enabled in response to the scan pulses from the 2n-3th stage and are disabled in response to the scan pulses from the 2n + 1th stage, 2n-3nd stage and 2n-2nd stage are disabled in response to the scan pulse from the 2n-1st stage, and And a 2n + 1 th stage and a 2n + 2 th stage are enabled in response to the scan pulse from the 2n-1 th stage. delete delete delete delete delete delete 32. The method of claim 31, The node controller provided in the 2n-1th stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-3th stage; A second switching element which is turned on or off in response to a first AC voltage source supplied to a first disable node, and discharges the enable node to a second DC voltage source when it is turned on; Turn on or off in response to a second alternating current voltage source supplied to the second disable node of the 2n-1th stage through a 2nth stage, and enable the 2n-1st stage at turn-on A third switching element for discharging the node to a second DC voltage source; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage; A turn-on or turn-off in response to the first alternating current voltage source, which, when turned on, charges the first disable node of the 2n-1 stage and the first disable node of the 2nth stage with the first alternating current voltage source; 5 switching elements; A sixth switching device configured to discharge the first disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to the scan pulse from the 2n-3rd stage; And A seventh switching element configured to discharge the first disabling node of the 2n-1st stage and the first disabling node of the 2nth stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; The shift register, characterized in that configured to include. delete delete 39. The method of claim 38, The node controller provided in the 2nth stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-3th stage; The turn-on or turn-off is performed in response to the first AC voltage source supplied to the first disable node of the 2n-th stage through the 2n-1th stage, and the enable node of the 2n-th stage is turned off. A second switching element for discharging to a second DC voltage source; A third switching element that is turned on or turned on in response to a second AC voltage source supplied to the second disable node, and discharges the enable node to a second DC voltage source at turn-on; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage; It is turned on or off in response to the second alternating voltage source, and when turned on, charges the second disable node of the 2n th stage and the second disable node of the 2n-1 th stage with a second alternating voltage source. A fifth switching element to make; A sixth switching device discharging the second disabling node of the 2n-th stage and the second disabling node of the 2n-1th stage to a second DC voltage source in response to the scan pulse from the 2n-3rd stage; And A seventh switching element discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; The shift register, characterized in that configured to include. 42. The method of claim 41, The node controller provided in the 2nth stage is An eighth switching element for charging or discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second AC voltage source in response to the scan pulse from the 2n + 1th stage; The shift register, characterized in that further comprises. 42. The method of claim 41, The node controller provided in the 2nth stage is And an eighth switching element which is turned on or off in response to the second alternating current voltage source and discharges the first disabling node of the 2n-th stage to a second direct current voltage source during turn-on. Shift register. 5. The method of claim 4, The 2n-1st stage and the 2nth stage are enabled in response to the scan pulses from the 2n-2th stage and are disabled in response to the scan pulses from the 2n + 1th stage, 2n-3nd stage and 2n-2nd stage are disabled in response to the scan pulse from the 2n-1st stage, and And a 2n + 1th stage and a 2n + 2th stage are enabled in response to the scan pulse from the 2nth stage. delete delete delete delete delete delete 45. The method of claim 44, The node controller provided in the 2n-1th stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-2th stage; A second switching element which is turned on or off in response to a first AC voltage source supplied to a first disable node, and discharges the enable node to a second DC voltage source when it is turned on; Turn on or off in response to a second alternating current voltage source supplied to the second disable node of the 2n-1th stage through a 2nth stage, and enable the 2n-1st stage at turn-on A third switching element for discharging the node to a second DC voltage source; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage; A turn-on or turn-off in response to the first alternating current voltage source, which, when turned on, charges the first disable node of the 2n-1 stage and the first disable node of the 2nth stage with the first alternating current voltage source; 5 switching elements; A sixth switching element configured to discharge the first disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to a scan pulse from the 2n-2nd stage; And A seventh switching element configured to discharge the first disabling node of the 2n-1st stage and the first disabling node of the 2nth stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; The shift register, characterized in that configured to include. delete delete 52. The method of claim 51, The node controller provided in the 2nth stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-2th stage; The turn-on or turn-off is performed in response to the first AC voltage source supplied to the first disable node of the 2n-th stage through the 2n-1th stage, and the enable node of the 2n-th stage is turned off. A second switching element for discharging to a second DC voltage source; A third switching element that is turned on or turned on in response to a second alternating current voltage source supplied to the second disable node, and discharges the enable node to a second DC voltage source at turn-on; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 2th stage; It is turned on or off in response to the second alternating voltage source, and when turned on, charging the second disable node of the 2n th stage and the second disable node of the 2n-1 st stage with the second alternating voltage source. A fifth switching element; A sixth switching device discharging the second disabling node of the 2n-th stage and the second disabling node of the 2n-1th stage to a second DC voltage source in response to a scan pulse from the 2n-1th stage; And A seventh switching element discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second DC voltage source in response to the first DC voltage source charged in the enable node; The shift register, characterized in that configured to include. 55. The method of claim 54, The node controller provided in the 2nth stage is An eighth switching element for charging or discharging the second disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to the second AC voltage source in response to the scan pulse from the 2n + 1th stage; The shift register, characterized in that further comprises. 55. The method of claim 54, The node controller provided in the 2nth stage is And an eighth switching element which is turned on or off in response to the second alternating current voltage source and discharges the first disabling node of the 2n-th stage to a second direct current voltage source during turn-on. Shift register. A shift register having a plurality of stages that sequentially output scan pulses for driving a plurality of conductive lines, At least one stage, An enabling node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage source according to a logic state of each of the disable nodes; And And a node controller for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from itself; Each stage includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, a second pull-down switching element connected to the second disable node, and a first disable node. A third disable node, and a third pull-down switching element connected to the third disable node; The node control unit provided in the 2n-3 (n is a natural number of 2 or more) stages may include a logic state of the enable node provided in the 2n-3rd stage, and a node for the first disable provided in the 2n-3rd stage. To control the logic state of the node, the logic state of the first disable node provided in the 2n-2th stage, and the logic state of the first disable node provided in the 2n-1st stage, The node control unit provided in the 2n-2th stage includes a logic state of the enable node provided in the 2n-2nd stage, a logic state of the second disable node provided in the 2n-2nd stage, and the 2n− Control the logic state of the second disable node provided in the third stage, and the logic state of the second disable node provided in the 2n-1 th stage; The node control unit provided in the 2n-1 st stage includes a logic state of an enable node provided in the 2n-1 th stage, a logic state of a third disable node provided in the 2n-1 th stage, and 2n. And a logic state of the third disable node provided in the second stage, and a logic state of the third disable node provided in the 2n-3rd stage. 58. The method of claim 57, The node control unit provided in the 2n-3 (n is a natural number of 2 or more) stages may include a logic state of the enable node provided in the 2n-3rd stage, and a node for the first disable provided in the 2n-3rd stage. And a logic state of the first disable node provided in the 2n-1st stage, and a logic state of the first disable node provided in the 2n-1st stage as a first AC voltage source. The node control unit provided in the 2n-2th stage includes a logic state of the enable node provided in the 2n-2nd stage, a logic state of the second disable node provided in the 2n-2nd stage, and the 2n− The logic state of the second disable node provided in the third stage and the logic state of the second disable node provided in the 2n-1 th stage are controlled by a second AC voltage source. The node control unit provided in the 2n-1 st stage includes a logic state of an enable node provided in the 2n-1 th stage, a logic state of a third disable node provided in the 2n-1 th stage, and 2n. A shift register controlling the logic state of the third disable node provided in the second stage and the logic state of the third disable node provided in the 2n-3rd stage as a third AC voltage source; . 58. The method of claim 57, The first disable node provided in the 2n-3rd stage, the first disable node provided in the 2n-2nd stage, and the first disable node provided in the 2n-1st stage are electrically connected to each other. Connected The second disable node provided in the 2n-2 th stage, the second disable node provided in the 2n-3 th stage, and the second disable node provided in the 2n-1 th stage are each other. Electrically connected, The third disable node provided in the 2n-1 st stage, the third disable node provided in the 2n-2 th stage, and the third disable node provided in the 2n-3 th stage are each other. A shift register characterized in that it is electrically connected. A shift register having a plurality of stages that sequentially output scan pulses for driving a plurality of conductive lines, At least one stage, An enabling node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage source according to a logic state of each of the disable nodes; And And a node controller for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from itself; Each stage includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and a second pull-down switching element connected to the second disable node. Including; The node control unit provided in the nth stage controls the logic states of the enable node, the first disable node, and the second disable node of the nth stage, and the second disable of the n-1th stage. And a logic register of the node for controlling the logic state of the node for the first disable of the n + 1th stage. delete 64. The method of claim 60, The node control unit of the 2n-1st stage controls the logic states of the first disable node provided in the 2n-1st stage and the second disable node provided in the 2n-2nd stage as a first AC voltage source; And, And the node control unit of the 2nth stage controls the logic states of the first disable node of the 2nth stage and the second disable node of the 2n-1st stage as a second AC voltage source. 63. The method of claim 62, Wherein each stage is enabled in response to a scan pulse from a stage positioned at the front end thereof and disabled in response to a scan pulse from a stage located next from the stage. 64. The method of claim 63, The node controller provided in the 2n-1th stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-2th stage; A second switching device configured to discharge the enable node to a second DC voltage source in response to a first AC voltage source supplied to a first disable node; A third switching for discharging the enable node of the 2n-1st stage to the second DC voltage source in response to a second AC voltage source supplied to the second disable node of the 2n-1st stage through a 2nth stage; device; A fourth switching device for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2nth stage; A fifth switching device that is turned on or turned off in response to the first AC voltage source and charges a common node with the first AC voltage source when turned on; A sixth switching device discharging the common node to a second DC voltage source in response to a first DC voltage source charged in the enable node; A seventh charge of the first disable node of the 2n-1st stage and the second disable node of the 2n-2nd stage to the first AC voltage source in response to the first AC voltage source supplied to the common node; Switching element; An eighth switching device discharging the second disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to the scan pulse from the 2n-2nd stage; And Discharging the first disabling node of the 2n-1st stage and the second disabling node of the 2n-2nd stage to a second DC voltage source in response to the first DC voltage source charged in the enable node. A shift register comprising a switching element. delete delete delete delete delete delete delete 64. The method of claim 63, One of at least two clock pulses having a phase difference is supplied to each pull-up switching element so that the pull-up switching element of each stage outputs the scan pulses, and the clock pulses output in adjacent periods are simultaneously used for a predetermined period. Remain active; The node controller provided in the 2n-1th stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-3th stage; A second switching device configured to discharge the enable node to a second DC voltage source in response to a first AC voltage source supplied to a first disable node; A third switching for discharging the enable node of the 2n-1st stage to the second DC voltage source in response to a second AC voltage source supplied to the second disable node of the 2n-1st stage through a 2nth stage; device; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage; A fifth switching device that is turned on or turned off in response to the first AC voltage source and charges a common node with the first AC voltage source when turned on; A sixth switching device discharging the common node to a second DC voltage source in response to a first DC voltage source charged in the enable node; A seventh charge of the first disable node of the 2n-1st stage and the second disable node of the 2n-2nd stage to the first AC voltage source in response to the first AC voltage source supplied to the common node; Switching element; An eighth switching device discharging the second disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to the scan pulse from the 2n-2nd stage; And Discharging the first disabling node of the 2n-1st stage and the second disabling node of the 2n-2nd stage to a second DC voltage source in response to the first DC voltage source charged in the enable node. A shift register comprising a switching element. delete delete delete delete 64. The method of claim 63, The node controller provided in the 2nth stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-1th stage; A second switching device configured to discharge the enable node to a second DC voltage source in response to a second AC voltage source supplied to a first disable node; A third switching element configured to discharge the enable node of the 2nth stage to a second DC voltage source in response to a first AC voltage source supplied to the second disable node of the 2nth stage through a 2n + 1th stage; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage; The second AC voltage source is turned on or turned off in response to the second AC voltage source, and when turned on, the node for the first disable of the 2n th stage and the second disable node for the 2n-1 th stage are configured as the second AC voltage source. A fifth switching device for charging with; A sixth switch for charging or discharging the first disable node of the 2nth stage and the second disable node of the 2n-1st stage to the second AC voltage source in response to the scan pulse from the 2n + 1th stage; device; A seventh switching element configured to discharge the second disable node of the 2n th stage and the first disable node of the 2n + 1 th stage to a second DC voltage source in response to the scan pulse from the 2n-1 th stage; And An eighth switching for discharging the first disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to a second DC voltage source in response to the first DC voltage source charged in the enable node; A shift register comprising a device. delete delete 64. The method of claim 63, One of at least two clock pulses having a phase difference is supplied to each pull-up switching element so that the pull-up switching element of each stage outputs the scan pulses, and the clock pulses output in adjacent periods are simultaneously used for a predetermined period. Remain active; The node controller provided in the 2n-1th stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-3th stage; A second switching device configured to discharge the enable node to a second DC voltage source in response to a first AC voltage source supplied to a first disable node; A third switching for discharging the enable node of the 2n-1st stage to the second DC voltage source in response to a second AC voltage source supplied to the second disable node of the 2n-1st stage through a 2nth stage; device; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage; A turn-on or turn-off in response to the first alternating current voltage source, the turn-on node turns on the first disable node of the 2n-1st stage and the second disable node of the 2n-2nd stage; A fifth switching device for charging with an AC voltage source; A sixth switch configured to charge or discharge the first disable node of the 2n-1st stage and the second disable node of the 2n-2nd stage to the first AC voltage source in response to the scan pulse from the 2nth stage; device; A seventh switching element configured to discharge the second disable node of the 2n-1st stage and the first disable node of the 2nth stage to a second DC voltage source in response to the scan pulse from the 2n-2th stage; And Discharging the first disabling node of the 2n-1st stage and the second disabling node of the 2n-2nd stage to a second DC voltage source in response to the first DC voltage source charged in the enable node. A shift register comprising 8 switching elements. 64. The method of claim 63, One of at least two clock pulses having a phase difference is supplied to each pull-up switching element so that the pull-up switching element of each stage outputs the scan pulses, and the clock pulses output in adjacent periods are simultaneously used for a predetermined period. Remain active; The node controller provided in the 2nth stage is A first switching device for charging the enable node with a first DC voltage source in response to a scan pulse from the 2n-1th stage; A second switching device configured to discharge the enable node to a second DC voltage source in response to a second AC voltage source supplied to a first disable node; A third switching element configured to discharge the enable node of the 2nth stage to a second DC voltage source in response to a first AC voltage source supplied to the second disable node of the 2nth stage through a 2n + 1th stage; A fourth switching element for discharging the enable node to a second DC voltage source in response to a scan pulse from a 2n + 1th stage; The second AC voltage source is turned on or turned off in response to the second AC voltage source, and when turned on, the node for the first disable of the 2n th stage and the second disable node for the 2n-1 th stage are configured as the second AC voltage source. A fifth switching device for charging with; A sixth switch for charging or discharging the first disable node of the 2nth stage and the second disable node of the 2n-1st stage to the second AC voltage source in response to the scan pulse from the 2n + 1th stage; device; A seventh switching element configured to discharge the second disable node of the 2n th stage and the first disable node of the 2n + 1 th stage to a second DC voltage source in response to the scan pulse from the 2n-1 th stage; An eighth switching for discharging the first disabling node of the 2nth stage and the second disabling node of the 2n-1st stage to a second DC voltage source in response to the first DC voltage source charged in the enable node; A shift register comprising a device. The method of claim 18, Channel width of the pull-up switching device provided in the 2n-th stage (channel width) The shift register, characterized in that it is wider than the channel width of the pull-up switching device provided in the 2n-1st stage. 20. The method of claim 19, The channel width of the pull-up switching device provided in the 2n-th stage is wider by α than the channel width of the pull-up switching device provided in the 2n-th stage, Α is {0.1 * (channel width of the first switching element) * 2 + (channel width of the fourth switching element) * 2 ≦ α ≦ (channel width of the first switching element (channel width) * 2 + (fourth switching) And a channel width of the element Tr4) * 2}. delete delete 5. The method of claim 4, The 2n-1 stage is enabled in response to the scan pulse from the 2n-3 stage and is disabled in response to the scan pulse from the 2n + 2 stage; And, And the second 2n stage is disabled in response to the scan pulse from the 2n-2 stage, and is disabled in response to the scan pulse from the 2n + 2 stage. delete delete delete 5. The method of claim 4, The 2n-1 stage is enabled in response to the scan pulse from the 2n-3 stage and is disabled in response to the scan pulse from the 2n + 1 stage; And, And the second 2n stage is disabled in response to the scan pulse from the 2n-2 stage, and is disabled in response to the scan pulse from the 2n + 2 stage. A shift register having a plurality of stages that sequentially output scan pulses for driving a plurality of conductive lines, At least one stage, An enabling node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage source according to a logic state of each of the disable nodes; And And a node controller for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from itself; The whole stages are divided into a number of stage blocks containing a number of stages, Stages included in one stage block At least one client stage; And At least one server stage which controls the logic state of its enable node and the disable node, and the logic state of the disable node included in the client stage; The shift register of claim 1, wherein the server stage outputs the scan pulse first among the stages included in the one stage block. delete delete delete 92. The method of claim 91, The server stage and the client stage comprise a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and a second disable node connected to the second disable node. A pull-down switching element, The node controller of the server stage provided in one stage block controls the logic states of the enable node, the first disable node, and the second disable node provided in the server stage. And a shift register for controlling the logic states of the provided first and second disable nodes. delete 95. The method of claim 95, The server stage is supplied with the first and second alternating voltage source inverted each other, The node controller of the server stage controls the logic state of the first disable node provided in the server stage and the logic state of the first disable node provided in the client stage as the first AC voltage source; And, The node control unit of the server stage controls the logic state of the second disable node provided in the server stage and the second disable node provided in the client stage as the second AC voltage source. register. 97. The method of claim 97, The node controller provided in the server stage, A first switching element for charging the enable node with a first DC voltage source in response to a start pulse or a scan pulse from a stage provided in the previous stage block; A second switching element configured to discharge the first disable node of the server stage and the client stage to a second DC voltage source in response to the first DC voltage source charged in the enable node; A third switching element configured to discharge a second disable node of the server stage and the client stage to a second DC voltage source in response to a first DC voltage source charged in the enable node; A fourth switching element for discharging the first disable node of the server stage and the client stage to a second DC voltage source in response to a start pulse or a scan pulse from a stage provided in the previous stage block; A fifth switching element for discharging the second disable node of the server stage and the client stage to a second DC voltage source in response to a start pulse or a scan pulse from a stage provided in the previous stage block; A sixth switching element turned on or off in response to a first alternating current voltage source and outputting the first alternating current voltage source when turned on; A seventh switching element configured to charge a first disable node of the server stage and the client stage with a first DC voltage source in response to the first AC voltage source output from the sixth switching element; An eighth switching element for discharging the enable node to the second DC voltage source in response to the first DC voltage source charged in the first disable node; A ninth switching element configured to supply a second DC voltage source to the gate terminal of the seventh switching element in response to the first DC voltage source charged in the enable node; A tenth switching element for supplying a second DC voltage source to the gate terminal of the seventh switching element in response to the start pulse or the scan pulse from the stage provided in the previous stage block; An eleventh switching element turned on or off in response to a second alternating current voltage source and outputting the second alternating current voltage source when turned on; A twelfth switching element configured to charge a second disable node with the second alternating voltage source in response to a second alternating voltage source output from the eleventh switching element; A thirteenth switching element discharging the enable node to the second DC voltage source in response to the second AC voltage source charged in the second disable node; A fourteenth switching element configured to supply a second DC voltage source to the gate terminal of the twelfth switching element in response to the first DC voltage source charged in the enable node; A fifteenth switching element for supplying a second DC voltage source to the gate terminal of the twelfth switching element in response to a start pulse or a scan pulse from a stage provided in the previous stage block; And  And a sixteenth switching element for discharging the enable node to the second DC voltage source in response to the scan pulse from the stage provided in the next stage block. 98. The method of claim 98, The node controller provided in the client stage, A first switching element for charging the enable node with a first DC voltage source in response to a start pulse or a scan pulse from a stage provided in the previous stage block; And discharging the enable node of the client stage to a second DC voltage source in response to a first AC voltage source supplied to the first disable node of the client stage through the first disable node of the server stage. 2 switching elements; A third discharge of the enable node of the client stage to a second DC voltage source in response to a second AC voltage source supplied to the second disable node of the client stage through the second disable node of the server stage; Switching element; And  And a fourth switching element for discharging the enable node of the client stage to a second DC voltage source in response to a scan pulse from a stage provided in a next stage block. 97. The method of claim 97, The node controller provided in the server stage, A first switching element configured to charge the enable node with a first DC voltage source in response to a start pulse or a scan pulse from a stage provided in a previous stage block; A second switching element for discharging the first disable node of the server stage and the client stage to a second DC voltage source in response to a scan pulse from the stage provided in the start pulse or the previous stage block; A third switching device for discharging a second disable node of the server stage and the client stage to a second DC voltage source in response to a scan pulse from the stage provided in the start pulse or the previous stage block; A fourth switching element which is turned on or off in response to a first alternating current voltage source and, when turned on, charges a first disable node of the server stage and the client stage with the first alternating current voltage source; A fifth switching device which is turned on or off in response to the first AC voltage source, and discharges a second disable node of the server stage and the client stage to the second DC voltage source when turned on; A sixth switching element which is turned on or off in response to a second alternating current voltage source and charges a second disable node of the server stage and the client stage with the second alternating current voltage source when turned on; A seventh switching element which is turned on or turned off in response to the second alternating voltage source, and discharges a first disable node of the server stage and the client stage to the second DC voltage source when turned on; An eighth switching element configured to discharge the first disable node of the server stage and the client stage to a second DC voltage source in response to a first DC voltage source applied to the enable node; A ninth switching element configured to discharge a second disable node of the server stage and the client stage to a second DC voltage source in response to a first DC voltage source applied to the enable node; A tenth switching element discharging the enable node to a second DC voltage source in response to a first AC voltage source charged in the first disable node; An eleventh switching element configured to discharge the enable node to a second DC voltage source in response to a second AC voltage source charged in the second disable node; A twelfth switching element discharging the enable node to a second DC voltage source in response to a scan pulse from a stage provided in a next stage block; A twelfth switching element configured to charge or discharge the first disable node with a first AC voltage source in response to a scan pulse from a stage provided in a next stage block; And And a thirteenth switching element configured to charge or discharge the second disable node with a second AC voltage source in response to a scan pulse from a stage provided in a next stage block. delete delete delete

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