KR102029749B1 - Gate driver and flat panel display device inculding the same - Google Patents

Abstract

The present invention discloses a gate driver of a flat panel display. More specifically, the present invention provides a gate driver and a device for improving the deterioration of device characteristics caused by using oxide (Oxide) silicon in place of amorphous (a-Si: H) silicon in the conventional gate driver implementation It relates to a flat panel display device.
According to an exemplary embodiment of the present invention, at least three QB nodes which rapidly deteriorate as a continuous DC voltage is applied in a gate driver to which an oxite thin film transistor is applied are provided to provide a positive stress applied to the thin film transistor. By reducing it to at least 1/3 or less as compared with the related art, the life of the gate driver can be extended.

Description

GATE DRIVER AND FLAT PANEL DISPLAY DEVICE INCULDING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver of a flat panel display device, and in particular, to solve the problem of deterioration of device characteristics caused by using oxide silicon in place of amorphous (a-Si: H) silicon in the conventional gate driver. A gate driver and a flat panel display including the same.

Various portable devices such as mobile phones and laptop computers, and information electronic devices that realize high resolution and high quality images such as HDTVs, have been applied to flat panel display devices. The demand for) is increasing. Such flat panel displays include liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), and organic light emitting diodes (OLEDs).

As described above, the flat panel display requires a thin film transistor (TFT) to be used as a switching and driving element of a display device having excellent performance with an increase in size of a substrate such as glass. Among the thin film transistors, typical amorphous silicon thin film transistors (a-Si: H TFTs) are widely used as devices that can be uniformly formed on a large substrate of more than 2 m at low cost.

However, with the trend toward larger display sizes and higher image quality, device performance is also required, and there is a limit to using an existing a-Si TFT having a mobility of 0.5 cm 2 / Vs as an element of a large flat panel display device.

Therefore, there is a need for a high performance TFT and a manufacturing technology having higher mobility than a-Si TFT. In addition, as a-Si TFT continues to operate as its greatest weakness, the device characteristics continue to deteriorate, thereby including a reliability problem in which initial performance cannot be maintained.

Currently, researches to overcome the limitations of a-Si TFT are continuously underway, and one of them is an oxide-silicon TFT.

Such an oxide silicon TFT has a higher carrier mobility than an amorphous silicon (a-Si) TFT, and thus, a driving circuit for controlling the switching element as well as the switching element in the display panel included in the flat panel display device is implemented. More advantageous.

FIG. 1A is a view schematically illustrating a structure of a gate driver in a driving circuit of a conventional flat panel display, and FIG. 1B is an equivalent circuit diagram of one stage of the gate driver shown in FIG. 1A.

In the conventional flat panel display, the pixels formed on the display panel are sequentially connected with each other in a horizontal line so that a gate driver for sequentially applying a gate output signal to the pixels on each horizontal line is used to display an image. This gate driver is implemented with a conventional shift register.

As shown in FIG. 1A, a plurality of stages for outputting gate output voltages Vout 1 to Vout n to a gate line formed in a display panel (not shown) in synchronization with one or more clock signals CLK. (1ST to nST). Accordingly, the first stage 1ST receives the start signal Vst and outputs the high level first gate output signal Vout1 for one horizontal period 1H, and the second stage 2ST receives the first gate. The output signal Vout2 is input as the start signal Vst to output the high level second gate output signal Vout2. When the n-th gate output signal Vout n is output to the n-th stage n ST, the operation of one frame is completed.

Each of the stages 1ST to nST described above is composed of a plurality of thin film transistors. FIG. 1B illustrates a stage of a gate driver including eight thin film transistors. Referring to FIG. 1B, a first thin film which charges a Q node Q as a diode is connected and connected by a start signal Vst. A sixth thin film transistor T6 for discharging the transistor T1 and the QB node QB, a fifth thin film transistor T5 for conducting the Q node Q by charging and discharging the QB node QB; The second thin film transistor T2, which charges the high potential driving voltage Vdd to the QB node QB in response to the inverted clock signal CLKB, is turned on when the QB node QB is charged. A third thin film transistor T3 for discharging the second thin film transistor T3, a fourth thin film transistor T4 for conducting a charge by the reset signal RST to discharge the Q node Q, and the B node QB to be charged; Is electrically connected to one side of the first Q node Q, and is electrically connected by a high voltage charged to the Q node Q. The seventh thin film transistor T7 passing through the signal CLK and outputting the output signal Out is electrically connected to the seventh thin film transistor T7 by the charged QB node QB and outputted through the seventh thin film transistor T7. It is configured to include an eighth thin film transistor (T8) to induce to fall to a low potential.

In the gate driver of the above-described structure, different Bias Temperature Stress (BTS) is applied to each thin film transistor according to the circuit configuration position, and the cumulative stress of each thin film transistor is changed as the driving time increases. This causes a difference in the degree of degradation of the thin film transistor. In the circuit structure of FIG. 1B, the third thin film transistor T3 and the eighth thin film transistor T8 are degraded more severely than the other thin film transistors, and a high level voltage is continuously applied to the QB node QB. Because it becomes. As a result, the threshold voltages Vth of the third and eighth thin film transistors T3 and T8 determine the lifetime of the gate driver.

In order to overcome the deterioration problem of the thin film transistors, a structure that distributes the stress applied to the thin film transistors connected to each QB node is provided with one more QB node (QB) and alternately driven by odd and even for two QB nodes. Although the proposed a-si silicon thin film transistor maintains a constant level even after a certain time, the oxide thin film transistor has a poor recovery characteristic, and thus the threshold voltage (Vth) over time. ) Will continue to shift positive.

FIG. 2 is a diagram illustrating a threshold voltage change according to a bias stress test of an oxide thin film transistor.

Referring to FIG. 2, when a positive bias temperature stress test is performed on an oxide thin film transistor, a positive DC voltage (DC) and a voltage of a high level pulse of 2,8,40,2000 msec are applied. The threshold voltage increases in proportion to the effective stress time, and according to the negative bias temperature stress test, a constant effective stress time is applied by applying a negative DC voltage (DC) and a high level pulse of 2,8,40,2000 msec. It can be seen that the change of the threshold voltage (Delta Vth) does not occur even if this flow occurs.

That is, while the oxide thin film transistor has a large threshold voltage shift with respect to the positive, the threshold voltage shift does not occur in the negative direction, so the gate driver using the oxide thin film transistor has a long driving time. There is a problem that its life is drastically reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to extend the life of a gate driver of a flat panel display by reducing bias stress of an oxide thin film transistor.

In addition, as the gate driver includes a plurality of QB nodes, it is another object to improve the driving reliability of the gate driver by preventing a floating section from occurring in the output of the QB node in a specific section during driving.

In order to achieve the above object, a gate driver according to a preferred embodiment of the present invention, the first transistor group for charging the Q node and outputs a high level output signal; A second transistor group for discharging at least three QB nodes in accordance with charging of the Q nodes; And a third transistor group for alternately charging the QB node and discharging the Q node in response to a plurality of clock signals, respectively, and outputting a low level output signal.

In addition, a flat panel display device including a gate driver according to an exemplary embodiment of the present invention includes a display panel in which a plurality of gate lines and data lines cross each other and define pixels at intersection points; A gate driver mounted on one side of the display panel and outputting an output signal to the gate line; And a data driver disposed on one side of the display panel to output a data voltage to the data line in synchronization with the output signal, wherein the gate driver outputs a charge of a Q node and an output signal of a high level, At least three QB nodes are discharged according to the charging of the Q node, and the plurality of QB nodes are alternately charged corresponding to a plurality of clock signals, and the Q nodes are discharged to output low level output signals. It includes a transistor.

According to an exemplary embodiment of the present invention, at least three QB nodes which rapidly deteriorate as a continuous DC voltage is applied in a gate driver to which an oxite thin film transistor is applied are provided to provide a positive stress applied to the thin film transistor. By reducing it to at least 1/3 or less compared with the related art, there is an effect of extending the life of the gate driver.

In addition, according to the embodiment of the present invention, by controlling the floating period to not occur in the output of the plurality of QB nodes using a plurality of clock signals has another effect that can improve the driving reliability of the gate driver.

1A is a diagram schematically illustrating a structure of a gate driver of a driving circuit of a conventional flat panel display device.
FIG. 1B illustrates an equivalent circuit diagram of one stage of the gate driver illustrated in FIG. 1A.
2 is a view showing a change in the threshold voltage according to the bias stress test of the oxide thin film transistor.
3 is a diagram illustrating an overall structure of a flat panel display device including a gate driver according to an exemplary embodiment of the present invention.
4 is an equivalent circuit diagram of one stage of a gate driver according to a first exemplary embodiment of the present invention.
5 is a diagram illustrating input and output signal waveforms of the gate driver of FIG. 4.
6 is an equivalent circuit diagram of one stage of a gate driver according to a second exemplary embodiment of the present invention.
FIG. 7 is a diagram illustrating input and output signal waveforms to the gate driver of FIG. 6.

Hereinafter, a gate driver of a flat panel display device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings. The flat panel display device to which the gate driver of the present invention is applied may be a liquid crystal display device or an organic light emitting display device which is widely used.

3 is a diagram illustrating an overall structure of a flat panel display device including a gate driver according to an exemplary embodiment of the present invention.

As shown, the organic light emitting display device including the shift register according to the present invention includes a display panel 100 for implementing an image and a timing signal from an external system to generate a control signal, and to align and convert image signals. Under the control of the timing controller 110 and the timing controller 110, the gate output voltage Vout is generated and output, and the gate driver 120 and the data voltage VDATA, which perform both sequential output and simultaneous output, are output. It includes a data driver 130 for generating and outputting.

The display panel 100 is formed by crossing a plurality of gate lines GL and data lines DL in a matrix on a transparent glass substrate or a plastic substrate, and the gate lines GL are connected to an output terminal of the gate driver 120. The data line DL is connected to the output terminal of the data driver 130. The pixel PX is defined at the intersection of each wiring.

Each pixel PX is formed in the display area A / A and includes at least one thin film transistor (TFT). In the case of a liquid crystal display, the thin film transistor performs a function of a switching element and includes a liquid crystal capacitor. In addition, the organic light emitting display device includes an organic light emitting diode, and further includes a driving element and a capacitor for supplying current to the organic light emitting diode separately from the switching element.

In particular, amorphous silicon is widely used as a material for forming the active layer of the thin film transistor, but the thin film transistor provided in the pixel of the flat panel display device according to the embodiment of the present invention is an oxide forming material. It is characterized by consisting of silicon (oxide silicon).

According to this structure, the switching element is turned on to correspond to the gate output signal Vout input to the gate wiring GL, and the data voltage Vdata corresponding to the gray level is applied to each pixel, and correspondingly, A voltage is charged in the liquid crystal capacitor, or a corresponding current flows in the organic light emitting diode to display an image.

The timing controller 110 receives image data of an image to be displayed from an external system and a timing signal for controlling each of the drivers 120 and 130. In addition, the timing controller 110 generates various control signals GCS and DCS for driving the gate driver 120 and the data driver 130, which will be described later, in response to the timing signal, and supplies them to the drivers 120 and 130. do.

The gate driver 120 supplies the gate output voltage Vout to the plurality of pixels PX arranged on the display panel 100 in response to the gate control signal GCS input from the timing controller 110. The gate control signal GCS described above includes not only the start signal Vst but also the gate shift clock GSC and the gate output enable GOE.

The gate driver 120 is a shift register including a plurality of stages including a plurality of thin film transistors in one non-display area N / A of the display panel 100. Since the shift register is formed in the same process as the thin film transistor on the display area A / A by using a gate in panel (GIP) method in the display panel 100, the thin film transistor of each stage is also an oxide silicon thin film transistor. It consists of.

In addition, the output terminal of the gate driver 120 is connected to the gate line GL of the display panel 100, and through this, the gate having the high level is sequentially formed by two horizontal periods 2H with respect to one gate line GL. Output the output signal (Vout), but output so as to overlap by one horizontal period. During the overlapping period, the switching elements included in the pixel PX are turned on so that the data voltage Vdata output from the data driver 130 is applied to each pixel PX.

The gate driver 120 includes a plurality of stages, each of which includes a Q node charged during a period during which a high level gate output signal Vout is output, and a QB outputting a low level gate output signal Vout. Nodes are defined. In particular, at least three QB nodes are defined in each stage in the gate driver of the present invention.

That is, in the remaining sections of one frame except for the section in which the gate output signal is at the high level, the QB nodes alternately charge and discharge at least three of them while maintaining the gate output signal at the low level. Also applied to the thin film transistors are applied stress is reduced to at least 1/3 or less.

On the other hand, the data driver 130 receives the data control signal DCS and the digital image signal RGB from the timing controller 110, and applies the image signal RGB in response to the data control signal DCS. As a result, the analog signal is converted into an analog data signal Vdata and applied to each pixel PX through the data wiring DL. In this case, the data driver 130 outputs the data signal Vdata to all pixels arranged on one horizontal line in response to the gate output signal Vout.

The data control signal DCS described above includes a source start pulse SSP, a source shift clock SSC, a source output enable SOE, and the like.

In addition, the data driver 130 may be configured as a separate IC, and may be attached to the non-display area N / A of the display panel 100 in a TAB or OOG manner, and each pixel may be connected through the data line DL. Is connected in the vertical direction.

According to such a structure, in the flat panel display including the gate driver of the present invention, at least three QB nodes are defined in the gate driver so that the bias stress is lowered to 1/3 or less, and thus the threshold voltage of the thin film transistor where deterioration is concentrated. (Vth) The shift is minimized.

Hereinafter, the structure of the gate driver of the present invention will be described in detail with reference to the drawings.

4 is a diagram illustrating an equivalent circuit diagram of one stage of a gate driver according to a first exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating input and output signal waveforms of the gate driver of FIG. 4.

In a first embodiment of the present invention, a gate driver using a six-phase clock signal having a high level period of two horizontal periods and overlapping one horizontal period, and the clock signal input to the illustrated stage is in accordance with the order of the stages. The clock signals may be different and do not overlap each other.

In the drawing, the first thin film transistor T1, the sixth thin film transistor T6, and the second c thin film transistor T2c are driven by receiving the first clock signal CLK1, respectively, of the six phase clock signals. 3 and 5 show the stages driven in synchronization with the fifth clock signals CLK1, CLK3, and CLK5, but the clock signals inputted to the respective stages are not fixed. As an example, the next stages are the second, fourth, and sixth stages. It is driven in synchronization with the clock signals CLK2, CLK4, and CLK6. In the following description, the structure and driving method of the gate driver of the present invention will be described as an example of a stage driven in synchronization with the first, third, and fifth clock signals CLK1, CLK3, CLK5.

As shown, one stage of the gate driver of the present invention is composed of a plurality of oxite silicon thin film transistors. In addition, one Q node Q and three QB nodes QB are defined in each stage.

Each thin film transistor charges a voltage to a Q node Q for the current stage to output a high level gate output signal Vout, and includes first and sixth thin film transistors T1 and T6 belonging to the first transistor group. A third n thin film transistor T3n for resetting, a fifth x transistor T5x belonging to a second group for discharging the first to third QB nodes QB, and x is a, b, and c; Outputs the gate output signal Vout of the low level, activates the first to third QB nodes QB1 to QB3, and includes thirdx, fourthx, and fourth belonging to a third group for discharging the Q node Q. The seventh thin film transistors T3x, T4x, and T7x may be broadly classified. Each of the thin film transistors T2x to T5x and T7x is further divided into predetermined pieces according to its role.

The first thin film transistor T1 has a diode connection structure in which a gate and a drain are connected to each other. The first thin film transistor T1 has a high level voltage according to the start signal Vst or the output signal Vout of the front stage, although not shown. Applies to node Q.

Each of the second to second thin film transistors T2a to T2c has a gate connected to a clock signal terminal, a drain connected to a first to third QB nodes QB1 to QB3, and a source connected to a ground voltage terminal. It is. Accordingly, the first to third QB nodes QB1 to QB3 are discharged in response to the first, third, and fifth clock signals CLK1, CLK3, and CLK5, respectively. According to the signal waveform shown in FIG. 5, the first, third, and fifth clock signals CLK1, CLK3, and CLK5 sequentially have high level intervals, but do not overlap each other. During charging, the first QB node QB1 is discharged, and the second QB node QB2 and the third QB node QB3 are sequentially discharged after the Q node Q discharge.

The third n thin film transistor T3n has a gate connected to a reset signal terminal or an output terminal of a next stage, a drain connected to a Q node Q, and a source connected to a ground voltage terminal. Accordingly, when the reset signal Reset or the next output signal Vout is input, the Q node Q is discharged to the ground voltage VSS.

 Each of the third to third thin film transistors T3a to T3c has a gate connected to the first to third QB nodes QB1, QB2, and QB3, a drain connected to a Q node Q, and a source connected to ground. It is connected to the voltage terminal. Accordingly, when the first to third QB nodes QB1, QB2, and QB3 are charged to the high level, the Q node Q is discharged to the ground voltage VSS or maintained in a discharge state.

Each of the 4a to 4c thin film transistors T4a to T4c has a gate connected to a clock signal terminal, a drain connected to a power supply voltage terminal, and a source connected to the first to third QB nodes QB1 to QB3. It is. Accordingly, when the first, third, and fifth clock signals CLK1, CLK3, and CLK5 become high levels, the first to third QB nodes QB1 to QB3 are charged to the power supply voltage VDD.

Each of the fifth transistors 5a to 5c thin film transistors T5a to T5c has a gate connected to a Q node Q, a drain connected to first to third QB nodes QB1 to QB3, and a source connected to a ground voltage terminal. It is connected. Accordingly, when the Q node Q is charged to the high level, all of the first to third QB nodes QB1 to QB3 are discharged to the ground voltage VSS.

The sixth thin film transistor T6 serves as a pull-up transistor, and a gate is connected to the Q node Q, a drain is connected to the clock signal terminal, and a source is connected to the output terminal of the stage. Accordingly, when the Q node Q is charged to the high level, the first clock signal CLK1 is output as the gate output signal Vout.

The seventh to seventh thin film transistors T7a to T7c serve as pull-down transistors, each of which has a gate connected to the first to third QB nodes QB1 to QB3 and a drain connected to the stage output terminal. The source is connected to the ground voltage terminal. Therefore, when each of the first to third QB nodes QB1 to QB3 is charged to the high level, the output terminal is discharged to the ground voltage VSS. That is, the low level gate output signal Vout is output.

According to this structure, when the low level gate output signal Vout is output, the third to third thin film transistors T3a to T3c and the seventh to sevenc thin film transistors T7a to T7c are alternately driven to a high level. As a result, the bias stress applied to each thin film transistor is reduced to 1/3, so that a positive shift of the threshold voltage Vth is minimized.

In particular, the present invention can further secure driving reliability of the circuit by minimizing the floating period by controlling not only the charging of the first to third QB nodes QB1 to QB3 but also the discharge period by the clock signal.

For example, since the third clock signal CLK3 is in the high level state when the second QB node QB2 is at high level charge, the third b thin film transistor T3b causes the Q node Q to discharge together with the second bb. As the thin film transistor T2b is turned on, the first QB node QB1 is discharged at the same time to minimize the floating section. That is, instead of performing the discharge operation according to the voltage of the Q node Q when the QB nodes QB1 to QB3 are discharged (see FIG. 2), the second to second thin film transistors T2a to T2c connected to the clock signal terminals. By performing the discharge drive by) can minimize the floating section at each node has the effect of improving the driving reliability.

Hereinafter, a gate driver according to a second exemplary embodiment of the present invention will be described with reference to the drawings. In the second embodiment of the present invention, the 8-phase clock signal is further used to further reduce the bias stress for each thin film transistor controlled according to the voltage of the QB node, and is further connected to the fourth QB node QB4. By further comprising a group of thin film transistors (T2x ~ T5x, T7x; x is d) relates to a circuit structure for reducing the bias stress to 1/4 when outputting low-level output signal.

6 is a diagram illustrating an equivalent circuit diagram of one stage of a gate driver according to a second exemplary embodiment of the present invention, and FIG. 7 is a diagram illustrating input and output signal waveforms of the gate driver of FIG. 6.

In the second embodiment of the present invention, a gate driver using an 8-phase clock signal having a high level period of two horizontal periods and overlapping one horizontal period, wherein the clock signal input to the illustrated stage is in accordance with the order of the stages. can be different. In addition, a clock signal of a type that does not overlap with each other is also applicable.

In the drawing, the first thin film transistor T1, the sixth thin film transistor T6, and the second d thin film transistor T2d are driven by receiving the first clock signal CLK1, respectively, and among the eight phase clock signals, the first and the second thin film transistors T1 and T2d are driven. Although the stages are driven in synchronization with the third, fifth, and seventh clock signals CLK1, CLK3, CLK5, and CLK7, the clock signals input to the respective stages are not fixed. It is driven in synchronization with the fourth and sixth clock signals CLK2, CLK4, CLK6, and CLK8.

As shown, one Q node Q and four QB nodes QB are defined in one stage of the gate driver according to the second embodiment.

The first thin film transistor T1 has a diode connection structure in which a gate and a drain are connected to each other. The first thin film transistor T1 has a high level voltage according to the start signal Vst or the output signal Vout of the front stage, although not shown. Applies to node Q.

The second to second thin film transistors T2a to T2c have the same role and structure as those of the first embodiment, but the seventh clock signal CLK7 is applied to the gate of the second thin film transistor T2d so that the third QB The node QB3 is discharged.

The 3n thin film transistor T3n, the 3x thin film transistors T3a to T3c, the 4x thin film transistors T4a to T4c, the 5x thin film transistors T5a to T5d and the 7x thin film transistors T7a to T7c are connected thereto. The structure and the role are the same as those of the first embodiment, and the 3d thin film transistor T3d added in the second embodiment is connected between the Q node Q and the ground voltage terminal, so that the fourth QB node QB4 The Q node Q is discharged during charging. The fourth 4D thin film transistor T4d is connected between the power supply voltage terminal and the fourth QB node QB4 to bring the fourth QB node QB4 to the power supply voltage VDD level according to the seventh clock signal CLK7. Will charge.

In addition, the 5d thin film transistor T5d is connected between the fourth QB node QB4 and the ground voltage terminal to discharge the fourth QB node QB4 to the ground voltage VSS level when the Q node Q is charged. The seventh thin film transistor T7d is connected between the output terminal of the stage and the ground voltage terminal to output the low level gate output signal Vout when the fourth QB node QB4 is charged.

According to this structure, when the low level gate output signal Vout is output, the third to third thin film transistors T3a to T3d and the seventh to seventh thin film transistors T7a to T7d alternately drive to a high level. As a result, the bias stress applied to each thin film transistor is reduced to 1/4.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

Q: Q nodes QB1 to QB4: First to third QB nodes
Vst: Start signal Vout: Gate output signal
Reset: Reset signal VDD: Power supply voltage
VSS: Ground Voltage T1, T6: First and Sixth Thin Film Transistors
T2a ~ T2c: Second Thin Film Transistor T3a ~ T3c: Third Thin Film Transistor
T4a to T4c: Fourth Thin Film Transistor T5a to T5c: Fifth Thin Film Transistor
T7a ~ T7c: 7th thin film transistor
CLK 1,3,5: First, third and fifth clock signals

Claims (15)

A first transistor group for charging the Q node and outputting a high level output signal;
A second transistor group for discharging three QB nodes according to the charging of the Q node; And
And a third transistor group for alternately charging the three QB nodes in correspondence with a plurality of clock signals, and simultaneously discharging the Q nodes and outputting a low level output signal.
The plurality of clock signals are six-phase clock signals each having a high level period of two horizontal periods and overlapping adjacent clock signals with one horizontal period.
And the third transistor group sequentially discharges each of the three QB nodes in response to three clock signals that do not overlap each other among the six-phase clock signals.
delete The method of claim 1,
The first transistor group,
A first transistor connected in a diode structure to charge the Q node according to a start signal or a front end output signal; And
And a sixth transistor connected to the Q node to output one of the plurality of clock signals as the output signal when the Q node is charged. The method of claim 1,
The second transistor group,
And transistors 5a, 5b, and 5c connected between the Q node and the ground voltage and discharging the three QB nodes to the ground voltage as the Q node is charged. The method of claim 1,
The third transistor group,
Transistors 4a, 4b, and 4c connected between a power supply voltage terminal and a ground voltage terminal and charging the three QB nodes with a power supply voltage as the plurality of clock signals are applied;
Transistors 3a, 3b, and 3c connected between the Q node and the ground voltage terminal and discharging the Q nodes to the ground voltage as the three QB nodes are alternately charged;
Transistors 7a, 7b, and 7c each having a gate connected to each of the three QB nodes and outputting a ground voltage as the output signal when the three QB nodes are alternately charged; And
2a, 2b, and 2c connected between the three QB nodes and the ground voltage terminals, respectively, and discharging the three QB nodes to ground voltages corresponding to clock signals that do not overlap each other among the plurality of clock signals. A gate driver comprising a transistor. The method of claim 1,
The third transistor group,
And a third n transistor connected between the Q node and a ground voltage terminal and discharging the Q node to a ground voltage according to an output signal of a rear stage. A first transistor group for charging the Q node and outputting a high level output signal;
A second transistor group for discharging at least three QB nodes in accordance with charging of the Q nodes; And
And a third transistor group configured to alternately charge the QB nodes and discharge the Q nodes simultaneously to correspond to a plurality of clock signals, and output a low level output signal. The plurality of clock signals include:
A gate driver having a high level section of two horizontal periods and an eight-phase clock signal overlapping one horizontal period. The method of claim 7, wherein
The second transistor group,
And transistors 5a, 5b, 5c, and 5d that are connected between the Q node and the ground voltage and discharge the QB node to ground voltage as the Q node is charged. The method of claim 7, wherein
The third transistor group,
A fourth 4a, 4b, and 4c transistor connected between a power supply voltage terminal and a ground voltage terminal and charging the QB node with a power supply voltage as the plurality of clock signals are applied;
3a, 3b, 3c, and 3d transistors connected between the Q node and the ground voltage terminal and discharging the Q nodes to ground voltages as the QB node is charged;
Transistors 7a, 7b, 7c, and 7d that output a ground voltage as the output signal when a gate is connected to the QB node and the QB node is charged; And
And a second a, a second b, a second c, and a second d transistor connected between the QB node and the ground voltage terminal and respectively discharging the QB node to the ground voltage in response to the plurality of clock signals. Gate driver. The method of claim 7, wherein
The third transistor group,
And a third n transistor connected between the Q node and a ground voltage terminal and discharging the Q node to a ground voltage according to an output signal of a rear stage. A display panel in which a plurality of gate lines and data lines cross each other and define pixels at intersection points;
A gate driver mounted on one side of the display panel and outputting an output signal to the gate line; And
A data driver disposed on one side of the display panel to output a data voltage to the data line in synchronization with the output signal;
The gate driver,
Composed of a plurality of stages, each stage includes a Q node and three QB nodes,
Outputs the charging of the Q node and a high level output signal, and the three QB nodes are alternately discharged according to the charging of the Q node, and the three QB nodes are alternately corresponding to a plurality of clock signals, respectively. And a plurality of transistors for charging and discharging the Q node to output a low level output signal,
The plurality of clock signals are six-phase clock signals each having a high level period of two horizontal periods and overlapping adjacent clock signals with one horizontal period.
And a plurality of QB nodes are sequentially discharged corresponding to three clock signals which do not overlap each other among the six-phase clock signals. delete The method of claim 11,
The plurality of transistors,
A first transistor connected in a diode structure to charge the Q node according to a start signal or a front end output signal;
A sixth transistor connected to the Q node to output one of the plurality of clock signals as the output signal when the Q node is charged;
Transistors 5a, 5b, and 5c connected between the Q node and the ground voltage and discharging the three QB nodes to the ground voltage as the Q node is charged;
Transistors 4a, 4b, and 4c connected between a power supply voltage terminal and a ground voltage terminal and charging the three QB nodes with a power supply voltage as the plurality of clock signals are applied;
Transistors 3a, 3b, and 3c connected between the Q node and the ground voltage terminal and discharging the Q nodes to ground voltages as the three QB nodes are alternately charged;
Transistors 7a, 7b, and 7c each having a gate connected to each of the three QB nodes and outputting a ground voltage as the output signal when the three QB nodes are alternately charged;
2a, 2b, and 2b, which are connected between the three QB nodes and the ground voltage terminals, respectively, and discharge the three QB nodes to the ground voltage in response to clock signals that do not overlap each other among the plurality of clock signals. 2c transistor; And
And a third n transistor connected between the Q node and a ground voltage terminal and discharging the Q node to a ground voltage according to an output signal of a rear stage. A display panel in which a plurality of gate lines and data lines cross each other and define pixels at intersection points;
A gate driver mounted on one side of the display panel and outputting an output signal to the gate line; And
A data driver disposed on one side of the display panel to output a data voltage to the data line in synchronization with the output signal;
The gate driver,
Composed of a plurality of stages, each stage includes a Q node and at least three QB nodes,
Outputs a charge signal of the Q node and an output signal of a high level, and according to the charge of the Q node, the at least three QB nodes are alternately discharged, and the QB nodes are alternately charged corresponding to a plurality of clock signals, respectively. And discharging the Q node and outputting a low level output signal.
The plurality of clock signals,
A flat panel display device having a high level section of two horizontal periods and an eight-phase clock signal overlapping one horizontal period. The method of claim 14,
The plurality of transistors,
A first transistor connected in a diode structure to charge the Q node according to a start signal or a front end output signal;
A sixth transistor connected to the Q node to output one of the plurality of clock signals as the output signal when the Q node is charged;
Transistors 5a, 5b, 5c, and 5d connected between the Q node and the ground voltage and discharging the QB node to the ground voltage as the Q node is charged;
A fourth, fourth, fourth, and fourth transistors connected between a power supply voltage terminal and a ground voltage terminal and charging the QB node to a power supply voltage as the plurality of clock signals are applied;
3a, 3b, 3c, and 3d transistors connected between the Q node and the ground voltage terminal and discharging the Q nodes to ground voltages as the QB node is charged;
Transistors 7a, 7b, 7c, and 7d that output a ground voltage as the output signal when a gate is connected to the QB node and the QB node is charged;
Second and second transistors respectively connected between the QB node and a ground voltage terminal and discharging the QB node to a ground voltage in response to the plurality of clock signals; And
And a third n transistor connected between the Q node and a ground voltage terminal and discharging the Q node to a ground voltage according to an output signal of a rear stage.

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