CN101556833B - Shift register and grid drive set of liquid crystal display - Google Patents
Shift register and grid drive set of liquid crystal display Download PDFInfo
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- CN101556833B CN101556833B CN2008101038725A CN200810103872A CN101556833B CN 101556833 B CN101556833 B CN 101556833B CN 2008101038725 A CN2008101038725 A CN 2008101038725A CN 200810103872 A CN200810103872 A CN 200810103872A CN 101556833 B CN101556833 B CN 101556833B
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Abstract
The invention relates to a shift register and a grid driver set of a liquid crystal display. The shift register comprises a first thin film transistor, a second thin film transistor, a third thin filmtransistor, a fourth thin film transistor, a first pull-down thin film transistor, a second pull-down thin film transistor, a first pull-down thin film transistor drive unit and a second pull-down th in film transistor drive unit, wherein the first pull-down thin film transistor drive unit is used for controlling the first pull-down thin film transistor to open when a signal output end outputs a low level and a first clock signal input end inputs a high level; and the second pull-down thin film transistor drive unit is used for controlling the second pull-down thin film transistor to open whenthe signal output end outputs a low level and a second clock signal input end inputs a high level. The shift register and the grid drive set of a liquid crystal display can effectively restrain outpu t noise and can ensure that the shift register and each thin film transistor in the grid drive set can not generate great threshold voltage excursion, thereby ensuring the normal service life of the shift register and the grid drive set.
Description
Technical field
The present invention relates to field of liquid crystal display, relate in particular to a kind of shift register and LCD device grid drive device.
Background technology
In the existing shift register, typical structure is four transistors, two capacitance structures of Thomson company, Figure 1 shows that Thomson company four transistors, two electric capacity shift register structure synoptic diagram, Figure 2 shows that the input and output sequential chart of shift register shown in Figure 1, concrete principle is: select the part in the sequential chart shown in Figure 2 and it is divided into five stages, in the phase one, signal input part (INPUT) input signal is a high level, reset signal input end (RESETIN) input signal is a low level, transistor T 103 conductings, transistor T 104 ends, so node PU place also is a high level by transistor T 103 chargings; In subordinate phase, signal input part (INPUT) input signal is a low level, reset signal input end (RESETIN) input signal is a low level, in the phase one, the PU node is pulled to high level, and at subordinate phase relaying height of continuing rising, transistor T 101 conductings, first clock signal input terminal (CLKIN) input signal is a high level, so signal output part (OUTPUT) is a high level; Because transistor T 103, T104 end, then the PU node is floating at this moment empty, and signal output part (OUTPUT) be a high level, by capacitor C 102 to its coupling, so level continues rising on the phase one basis herein; In the phase III, signal input part (INPUT) input signal is a low level, reset signal input end (RESETIN) input signal is a high level, transistor T 102 and T104 conducting, because the source electrode of T102 connects low voltage signal input end (VSSIN), so signal output part (OUTPUT) is a low level; In the quadravalence section, signal input part (INPUT) input signal is a low level, and reset signal input end (RESETIN) input signal is a low level, and the PU node is a low level, so T101, T102, T103, T104 all end, signal output part (OUTPUT) remains low level; At five-stage, signal input part (INPUT) input signal is a low level, and reset signal input end (RESET) input signal is a low level, and each transistor keeps the state of quadravalence section, so signal output part (OUTPUT) still is a low level.In this five stages, phase one signal input part (INPUT) end input high level, subordinate phase signal output part (OUTPUT) is a high level, finish once displacement, phase III reset signal input end (RESETIN) end input high level, finish the operation that resets, so can be the working time of shift register with first, second and third stage definitions, fourth, fifth stage, input signal end (INPUT), reset signal input end (RESETIN) end are low level, so can be the non-working time of shift register with fourth, fifth stage definitions.
As can be seen, on one's own time, input signal end (INPUT), reset signal input end (RESETIN), signal output part (OUTPUT) is low level, when system's first clock signal (CLKIN) raises, stray capacitance Cgd1 by transistor T 101 is coupled to the PU node, make the leakage current of transistor T 101 increase, thereby signal output part (OUTPUT) current potential raises, and because T103 on one's own time, T104, T102 all ends, so when signal output part (OUTPUT) is subjected to influencing current potential and raising of CLKIN end, do not have pull-down transistor that the voltage of signal output part (OUTPUT) is reduced, thereby make signal output part (OUTPUT) output signal produce big noise.
At this problem, Thomson company has proposed the shift register of six transistor arrangements, is illustrated in figure 3 as Thomson company six transistor shift register structure synoptic diagram, Figure 4 shows that the input and output sequential chart of shift register shown in Figure 3.From Fig. 3 and Fig. 4 as can be seen, the PD node keeps high level in the non-working time of shift register, T202 keeps conducting, because the drain electrode of T202 connects low voltage signal input end (VSSIN), so signal output part (OUTPUT) can keep low level, so just be not easy to be subjected to the influence of first clock signal input terminal (CLKIN) input signal.But, when as shown in Figure 3 shift register being applied in the gate drive apparatus of LCD, for scan mode is the LCD of lining by line scan, each shift register is responsible for the opening and closing that delegation is used to control the liquid crystal pixel switching thin-film transistor, when shift register is in the working time, control TFT is opened, and when shift register was in the non-working time, control TFT was closed.If always have 1000 row liquid crystal pixels, a shift register control delegation thin film transistor (TFT), then each shift register is in the time T of liquid crystal display displays one two field picture, have only the time of T/1000 in running order, all the other most times are in off working state, transistor T 202, T204 have been subjected to the bias of intimate direct current like this, can cause T202, T204 to produce bigger threshold voltage shift like this, reduce the reliability of shift register, finally can influence the life-span of shift register.
Summary of the invention
The objective of the invention is to problem at the prior art existence, a kind of shift register and LCD device grid drive device are provided, can suppress the shift register output noise, and can guarantee that each transistor does not produce big threshold voltage shift in the shift register, thereby guarantee the reliability of shift register work.
To achieve these goals, the invention provides a kind of shift register, comprising:
The first film transistor, its drain electrode connects first clock signal input terminal, and grid connects an end of first electric capacity, and source electrode connects the first electric capacity other end and the signal output part respectively;
Second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of signal output part and the first film respectively, and grid connects the reset signal input end, and source electrode is connected with the low voltage signal input end;
The 3rd thin film transistor (TFT), its grid is connected with signal input part, and drain electrode is connected with the high voltage signal input end;
The 4th thin film transistor (TFT), its grid is connected with described reset signal input end, and drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with the low voltage signal input end;
First pull-down thin film, its drain electrode is connected with signal output part and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The first pull-down thin film driver element, be connected with the source electrode of high voltage signal input end, first clock signal input terminal, second clock signal input part, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) and the grid of drain electrode and described first pull-down thin film respectively, be used for when signal output part output low level and the first clock signal input terminal input signal are high level, control described first pull-down thin film and opening;
Second pull-down thin film, its drain electrode is connected with signal output part and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The second pull-down thin film driver element, be connected with the source electrode of the described first pull-down thin film driver element, high voltage signal input end, first clock signal input terminal, second clock signal input part, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) and the grid of drain electrode and described second pull-down thin film respectively, be used for when signal output part output low level and second clock signal input part input signal are high level, control second pull-down thin film and opening.
The present invention also provides a kind of shift register, comprising:
The first film transistor, its drain electrode connects first clock signal input terminal, and grid connects an end of first electric capacity, and source electrode connects the other end and the signal output part of described first electric capacity respectively;
Second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of signal output part and the first film respectively, and grid connects the reset signal input end, and source electrode is connected with the low voltage signal input end;
The 3rd thin film transistor (TFT), its grid all is connected with signal input part with drain electrode;
The 4th thin film transistor (TFT), its grid is connected with described reset signal input end, and drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with the low voltage signal input end;
First pull-down thin film, its drain electrode is connected with signal output part and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The first pull-down thin film driver element, be connected with the source electrode and described first pull-down thin film of first clock signal input terminal, second clock signal input part, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) respectively, be used for when signal output part output low level and the first clock signal input terminal input signal are high level, control first pull-down thin film and opening;
Second pull-down thin film, its drain electrode is connected with signal output part and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The second pull-down thin film driver element, be connected with the source electrode and described second pull-down thin film of the described first pull-down thin film driver element, first clock signal input terminal, second clock signal input part, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) respectively, be used for when signal output part output low level and second clock signal input part input signal are high level, control second pull-down thin film and opening.
The present invention also provides a kind of shift register, comprising:
The first film transistor, its drain electrode connects first clock signal input terminal, and grid connects an end of first electric capacity, and source electrode connects the other end and the signal output part of described first electric capacity respectively;
Second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of signal output part and the first film respectively, and grid connects the reset signal input end, and source electrode is connected with the low voltage signal input end;
The 3rd thin film transistor (TFT), its grid all is connected with signal input part with drain electrode;
The 4th thin film transistor (TFT), its grid is connected with described reset signal input end, and drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with the low voltage signal input end;
First pull-down thin film, its grid connect the described first pull-down thin film driver element, and drain electrode is connected with signal output part, first electric capacity and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The first pull-down thin film driver element, be connected with the source electrode of first clock signal input terminal, second clock signal input part, high voltage signal input end, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) and the grid of described first pull-down thin film respectively, be used for when signal output part output low level and the first clock signal input terminal input signal are high level, control first pull-down thin film and opening;
Second pull-down thin film, its drain electrode is connected with signal output part, first electric capacity and the transistorized source electrode of described the first film respectively, and source electrode connects the low voltage signal input end;
The second pull-down thin film driver element, be connected with the source electrode of the described first pull-down thin film driver element, first clock signal input terminal, second clock signal input part, high voltage signal input end, low voltage signal input end, the transistorized grid of described the first film, the 3rd thin film transistor (TFT) and the grid of described second pull-down thin film respectively, be used for when signal output part output low level and second clock signal input part input signal are high level, control second pull-down thin film and opening.
The present invention also provides a kind of LCD device grid drive device, comprising: be deposited on a plurality of foregoing shift register on the LCD (Liquid Crystal Display) array substrate;
Except that first shift register and last shift register, the signal output part of all the other each shift registers all is connected with the reset signal input end of signal input part that is adjacent next shift register and the last shift register that is adjacent, the signal output part of first shift register is connected with the signal input part of second shift register, and the signal output part of last shift register and the reset signal input end of a last shift register that is adjacent and the reset signal input end of self is connected;
The signal input part incoming frame start signal of first shift register;
The first clock signal input terminal input system, first clock signal of odd number shift register, second clock signal input part input system second clock signal; The first clock signal input terminal input system second clock signal of even number shift register, second clock signal input part input system first clock signal;
The low voltage signal input end input low level signal of each shift register;
The high voltage signal input end input high level signal of each shift register.
The present invention also provides a kind of LCD device grid drive device, comprising: be deposited on a plurality of foregoing shift register on the LCD (Liquid Crystal Display) array substrate;
Except that first shift register and last shift register, the signal output part of all the other each shift registers all is connected with the reset signal input end of signal input part that is adjacent next shift register and the last shift register that is adjacent, the signal output part of first shift register is connected with the signal input part of second shift register, and the signal output part of last shift register is connected with the reset signal input end of a last shift register that is adjacent;
The equal incoming frame start signal of the reset signal input end of the signal input part of first shift register and last shift register;
The first clock signal input terminal input system, first clock signal of odd number shift register, second clock signal input part input system second clock signal; The first clock signal input terminal input system second clock signal of even number shift register, second clock signal input part input system first clock signal;
The low voltage signal input end input low level signal of each shift register;
The high voltage signal input end input high level signal of each shift register.
Shift register provided by the invention and LCD device grid drive device, can effectively suppress output noise, and can guarantee that each thin film transistor (TFT) in shift register and the gate drive apparatus can not produce big threshold voltage shift, thereby guarantee the operate as normal life-span of shift register and gate drive apparatus.
Also in conjunction with the accompanying drawings the present invention is described in further detail below by specific embodiment.
Description of drawings
Figure 1 shows that Thomson company four transistors, two electric capacity shift register structure synoptic diagram;
Figure 2 shows that the input and output sequential chart of shift register shown in Figure 1;
Figure 3 shows that Thomson company six transistor shift register structure synoptic diagram;
Figure 4 shows that the input and output sequential chart of shift register shown in Figure 3;
Figure 5 shows that shift register embodiment one structural representation of the present invention;
Figure 6 shows that shift register embodiment two structural representations of the present invention;
Figure 7 shows that the input and output sequential chart with shift register shown in Figure 6;
Figure 8 shows that shift register embodiment three structural representations of the present invention;
Figure 9 shows that shift register embodiment four structural representations of the present invention;
Figure 10 shows that shift register embodiment five structural representations of the present invention;
Figure 11 shows that shift register embodiment six structural representations of the present invention;
Figure 12 shows that LCD device grid drive device embodiment one structural representation of the present invention;
Figure 13 shows that the input and output sequential chart of LCD device grid drive device shown in Figure 12;
Figure 14 shows that LCD device grid drive device embodiment two structural representations of the present invention.
Embodiment
Be illustrated in figure 5 as shift register embodiment one structural representation of the present invention, this shift register comprises: thin film transistor (TFT) T301, T302, T303, T304, T111, T112, the first pull-down thin film driver element 1 and the second pull-down thin film driver element 2, the drain electrode of T301 is connected with first clock signal input terminal (CLKIN), grid is connected with an end of described first pull-down thin film driver element 1 and capacitor C 301, and source electrode is connected with the other end and the signal output part (OUTPUT) of C301; The drain electrode of T302 is connected with the source electrode of T301, and grid is connected with reset signal input end (RESETIN), and source electrode is connected with low voltage signal input end (VSSIN); The drain electrode of T303 is connected with high voltage signal input end (VDDIN), and grid is connected with input signal end (INPUT); The drain electrode of T304 is connected with the source electrode of T303, and grid is connected with reset signal input end (RESETIN), and source electrode is connected with low voltage signal input end (VSSIN); The first pull-down thin film driver element 1 is connected with drain electrode and low voltage signal input end (VSSIN) with the grid of first clock signal input terminal (CLKIN), second clock signal input part (CLKBIN), high voltage signal input end (VDDIN), T301, the grid of T111, the source electrode of T303 respectively; The second pull-down thin film driver element 2 is connected with the grid of first clock signal input terminal (CLKIN), second clock signal input part (CLKBIN), high voltage signal input end (VDDIN), T112, the source electrode of T303 and the grid and the first pull-down thin film driver element 1 of drain electrode, low voltage signal input end (VSSIN), T301 respectively; The effect of the first pull-down thin film driver element 1 is: in the non-working time of shift register, when first clock signal input terminal (CLKIN) input high level signal, the first pull-down thin film driver element, 1 output high level, oxide-semiconductor control transistors T111 opens, because the source electrode of T111 is connected with low voltage signal input end (VSSIN), drain electrode is connected with signal output part (OUTPUT), thereby can guarantee that signal output part (OUTPUT) is output as low level, output signal can not be subjected to first clock signal input terminal (CLKIN) input signal or other signals disturb the generation noise; The effect of the second pull-down thin film driver element 2 is: in the non-working time of shift register, when second clock signal input part (CLKBIN) input high level signal, the second pull-down thin film driver element, 2 output high level, oxide-semiconductor control transistors T112 opens, because the source electrode of T112 is connected with low voltage signal input end (VSSIN), drain electrode is connected with signal output part (OUTPUT), thereby can guarantee that signal output part (OUTPUT) is output as low level, output signal can not be subjected to second clock signal input part (CLKBIN) input signal or other signals disturb the generation noise.Wherein T111 and T112 are the pull-down thin film that is used to reduce signal output part (OUTPUT) noise in output signal.
Need to prove, thin film transistor (TFT) for field of liquid crystal display, drain electrode and source electrode do not have clear and definite difference, so the source electrode of the thin film transistor (TFT) of being mentioned among the present invention can be the drain electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) also can be the source electrode of thin film transistor (TFT).
The embodiment of the invention one is by two pull-down thin film driver elements and two pull-down thin film, make and to keep low level output in shift register on one's own time, and can not produce noise owing to the interference that is subjected to first clock signal input terminal and second clock signal input part, and the first pull-down thin film driver element is only when signal output part output low level and first clock signal input terminal are input as high level, apply high voltage just can for the grid of thin film transistor (TFT) T111, the second pull-down thin film driver element is only when signal output part output low level and second clock signal input part are input as high level, apply high voltage just can for the grid of thin film transistor (TFT) T112, so just can not make pull-down thin film T111 and T112 be subjected to bias for a long time, can effectively reduce the thin film transistor (TFT) threshold voltage shift, thereby guarantee the operate as normal of each thin film transistor (TFT).
Be illustrated in figure 6 as shift register embodiment two structural representations of the present invention, be illustrated in figure 7 as the input and output sequential chart with shift register shown in Figure 6, shift register shown in Figure 6 is specializing of Fig. 5, among Fig. 6, realize the function of the first pull-down thin film driver element by thin film transistor (TFT) T305, T308, T309, T310, realize the function of the second pull-down thin film driver element by thin film transistor (TFT) T306, T307, T311, T312.
The principle of present embodiment two is specific as follows: select the part of sequential chart shown in Figure 7 and it is divided into five stages, in the phase one, input signal end (INPUT) is a high level, reset signal input end (RESETIN) is a low level, the T303 conducting, the drain electrode of T303 connects high voltage signal input end (VDDIN), node Q place output high level, T301, T310 and T311 conducting; First clock signal input terminal (CLKIN) is a low level, and T306 and T309 end; Second clock signal input part (CLKBIN) is a high level, T305 and T312 conducting, because the source electrode of T312 is connected with low voltage signal input end (VSSIN), so node LN1 place output low level, because T310 conducting, the source electrode of T310 is connected with low voltage signal input end (VSSIN), thus node LN2 place output low level, thus T307, T308, T111 and T112 end; Reset signal input end (RESETIN) is a low level, and T302 and T304 end, signal output part (OUTPUT) output low level.
In subordinate phase, input signal end (INPUT) is a low level, and reset signal input end (RESETIN) is a low level, and first clock signal input terminal (CLKIN) is a high level, T306 and T309 conducting; Second clock signal input part (CLKBIN) is a low level, and T305 and T312 end, and node LN1 and the output of LN2 place still are low level, and T307, T308, T111 and T112 end; Because T304, T307, the T308 that drains and link to each other with node Q, and the T303 that source electrode links to each other with node Q at this moment is in cut-off state, then the Q node is in floating dummy status; When first clock signal input terminal (CLKIN) was high level, the stray capacitance by transistor T 301 made it continue to raise to the coupling of Q node place; Simultaneously, signal output part (OUTPUT) also is a high level, to the coupling of Q node place, makes node Q place level continue to raise by capacitor C 301.So this moment, node Q place output level was the high level after the stack on the phase one basis, T301, T310 and T311 conducting.Reset signal input end (RESETIN) is a low level, and T302 and T304 end, because first clock signal input terminal (CLKIN) is a high level, and the T301 conducting, so signal output part (OUTPUT) is a high level.
In the phase III, input signal end (INPUT) is a low level, reset signal input end (RESETIN) is a high level, T303 ends, T302 and T304 conducting, because the source electrode of T304 is connected with low voltage signal input end (VSSIN), so node Q place is a low level, T301, T310 and T311 end; First clock signal input terminal (CLKIN) is a low level, and T306 and T309 end; Second clock signal input part (CLKBIN) is a high level, and T305 and T312 conducting because the source electrode of T312 is connected with low voltage signal input end (VSSIN), so node LN1 place is a low level, cause T307 and T111 to end; Because T310 ends, the drain electrode of T305 is connected with high voltage signal input end (VDDIN), so node LN2 place is a high level, causes T308 and T112 conducting; Because the T302 conducting, the source electrode of T302 connects low voltage signal input end (VSSIN), so signal output part (OUTPUT) output low level.
In the quadravalence section, input signal end (INPUT) is a low level, and reset signal input end (RESETIN) is a low level, and T303, T304 and T302 end, so node Q place still keeps low level, T301, T310 and T311 end; First clock signal input terminal (CLKIN) is a high level, T306 and T309 conducting; Second clock signal input part (CLKBIN) is a low level, and T305 and T312 end; Because the T306 conducting, and the drain electrode of T306 is connected with high voltage signal input end (VDDIN), and transistor T 312 ends, so node LN1 place exports high level, causes T307 and T111 conducting; Because the T309 conducting, the source electrode of T309 is connected with low voltage signal input end (VSSIN), so node LN2 place output low level causes T308 and T112 to end; Reset signal input end (RESETIN) is a low level, T302 and T304 end, but because node LN1 place exports high level, make the T111 conducting, because the source electrode of T111 is connected with low voltage signal input end (VSSIN), so signal output part (OUTPUT) remains low level.
At five-stage, input signal end (INPUT) is a low level, and reset signal input end (RESETIN) is a low level, and T303, T304 and T302 end, so node Q place still keeps low level, T301, T310 and T311 end; First clock signal input terminal (CLKIN) is a low level, and T306 and T309 end; Second clock signal input part (CLKBIN) is a high level, and T305 and T312 conducting are because the source electrode of T312 is connected with low voltage signal input end (VSSIN), so node LN1 place output low level causes T307 and T314 to end; Because the T305 conducting, T309 ends, and the drain electrode of T305 is connected with high voltage signal input end (VDDIN), so output high level in node LN2 place causes T308 and T112 conducting; Reset signal input end (RESETIN) is a low level, T302 and T304 end, but because node LN2 place exports high level, make the T112 conducting, because the source electrode of T112 is connected with low voltage signal input end (VSSIN), so signal output part (OUTPUT) remains low level.
More than in five stages, input signal end (INPUT) input high level in phase one, signal output part in the subordinate phase (OUTPUT) output high level, finished once displacement, reset signal input end (RESETIN) is a high level in phase III, carried out reset operation, made signal output part (OUTPUT) output low level, the 4th and five-stage be that signal output part (OUTPUT) low level keeps the stage.This shift register is applied in the LCD device grid drive device, first, two, three stages can be regarded as the working time of this shift register, the part sequential chart of shift register has only drawn among Fig. 7, every demonstration one two field picture of LCD, control the shift register of certain delegation's liquid crystal pixel and all can export a high level, input signal end (INPUT), reset signal input end (RESETIN), first clock signal input terminal (CLKIN) and second clock signal input part (CLKBIN) all can repeat one time first, two, triphasic input timing, in the time of liquid crystal display displays one two field picture, remove first, two, all the other times outside three stages, input signal end (INPUT), reset signal input end (RESETIN), first clock signal input terminal (CLKIN) all can repeat the input timing identical with five-stage with the 4th with second clock signal input part (CLKBIN).From above to the detailed description in five stages as can be seen, in the quadravalence section when first clock signal input terminal (CLKIN) input signal is high level, node LN1 place is a high level, control pull-down thin film T111 conducting, thereby holding signal output terminal (OUTPUT) output low level, in the five-stage when first clock signal input terminal (CLKIN) is low level, node LN1 place is a low level, pull-down transistor T111 ends, second clock signal input part (CLKBIN) is a high level, node LN2 place is a high level, pull-down thin film T112 conducting, thereby holding signal output terminal (OUTPUT) output high level, follow-up input timing repeats the 4th, the sequential of five-stage, signal output part (OUTPUT) still keeps low level.Compare with six transistor shift registers of Thomson company in the prior art, pull-down thin film T111 has only when signal output part (OUTPUT) output low level and first clock signal input terminal (CLKIN) input high level in the embodiment of the invention two, just can be subjected to the bias of the high level of node LN1 place output, pull-down thin film T112 has only when signal output part (OUTPUT) output low level and second clock signal input part (CLKBIN) input high level, just can be subjected to the bias of the high level of node LN1 place output, but not most a certain transistors of time all are subjected to the effect of bias voltage as six transistor shift registers of Thomson company, can guarantee like this in the embodiment of the invention two that each thin film transistor (TFT) can both operate as normal, can guarantee the operate as normal life-span of shift register, and, owing to added pull-down thin film T111 and T112, can effectively must make shift register keep low level output on one's own time, suppress noise.
Be illustrated in figure 8 as shift register embodiment three structural representations of the present invention, Fig. 8 is with the difference of shift register shown in Figure 5: the grid of transistor T 303 is connected with signal input part (INPUT) among Fig. 5, drain electrode is connected with high voltage signal input end (VDDIN), and the grid of transistor T 303 all is connected with input signal end (INPUT) with drain electrode among Fig. 8; Among Fig. 5 the first pull-down thin film driver element respectively with first clock signal input terminal (CLKIN), second clock signal input part (CLKBIN), high voltage signal input end (VDDIN), the grid of T301, the grid of T111, the source electrode of T303 is connected with drain electrode and low voltage signal input end (VSSIN), and the first pull-down thin film driver element and first clock signal input terminal (CLKIN) among Fig. 8, second clock signal input part (CLKBIN), the grid of T301, the grid of T111, the source electrode of T303 and low voltage signal input end (VSSIN) connect, and are not connected with the drain electrode of high voltage signal input end (VDDIN) and T303; Among Fig. 5 the second pull-down thin film driver element respectively with first clock signal input terminal (CLKIN), second clock signal input part (CLKBIN), high voltage signal input end (VDDIN), the grid of T112, the source electrode of T303, the low voltage signal input end (VSSIN) and the first pull-down thin film driver element 1 connect, and among Fig. 8 the second pull-down thin film driver element respectively with first clock signal input terminal (CLKIN), second clock signal input part (CLKBIN), the grid of T112, the source electrode of T303, low voltage signal input end (VSSIN), the grid of T301 and the first pull-down thin film driver element connect, and are not connected with the drain electrode of high voltage signal input end (VDDIN) and T303.
Compare with shift register shown in Figure 5, shift register shown in Figure 8, can save high voltage signal input end (VDDIN), and the high voltage signal voltage of high voltage signal input end (VDDIN) input can be lower than the voltage of input signal end (INPUT) input signal usually, adopt shift register structure as shown in Figure 8, just can improve the voltage of node Q place output, increase the grid current of transistor T 301, thereby shorten the rise time of the high level signal of signal output part (OUTPUT) output.
Be illustrated in figure 9 as shift register embodiment four structural representations of the present invention, shift register shown in Figure 9 is specializing of Fig. 8, among Fig. 9, realize the function of the first pull-down thin film driver element by thin film transistor (TFT) T305, T307, T308, T309 and T310, realize the function of the second pull-down thin film driver element by thin film transistor (TFT) T306, T311 and T312.Principle of work and Fig. 6 of Fig. 9 shift register are basic identical, repeat no more herein.
Figure 10 shows that shift register embodiment five structural representations of the present invention, Figure 10 is with the difference of shift register shown in Figure 5: the grid of transistor T 303 is connected with input signal end (INPUT) among Fig. 5, drain electrode is connected with high voltage signal input end (VDDIN), among Figure 10, the grid of thin film transistor (TFT) T303 all is connected with input signal end (INPUT) with drain electrode.Compare with shift register shown in Figure 5, usually the high voltage signal voltage of high voltage signal input end (VDDIN) input can be lower than the voltage of input signal end (INPUT) input signal, adopt shift register structure as shown in figure 10, just can improve the voltage of node Q place output, increase the grid current of transistor T 301, thereby shorten the rise time of the high level signal of signal output part (OUTPUT) output.
Be shift register embodiment six structural representations of the present invention as shown in figure 11, shift register shown in Figure 11 is specializing of Figure 10, among Figure 11, realize the function of the first pull-down thin film driver element by thin film transistor (TFT) T306, T307, T311, T312, realize the function of the second pull-down thin film driver element by thin film transistor (TFT) T305, T308, T309 and T310.Principle of work and Fig. 6 of Figure 11 shift register are basic identical, repeat no more herein.
Be LCD device grid drive device embodiment one structural representation of the present invention as shown in figure 12, be the input and output sequential chart of LCD device grid drive device shown in Figure 12 as shown in figure 13, STV is a frame start signal, STV only is input to the input signal end (INPUT) of first shift register, high voltage signal (VDD) is input to the high voltage signal input end (VDDIN) of each shift register, low voltage signal (VSS) is input to the low voltage signal input end (VSSIN) of each shift register, system first clock signal (CLK) is input to first clock signal input terminal (CLKIN) of odd number shift register, system second clock signal (CLKB) is input to the second clock signal input part (CLKBIN) of even number shift register, except that first shift register and last shift register, the signal output part of each shift register (OUTPUT) all is connected with the input signal end (INPUT) of the reset signal input end (RETSETIN) of a last shift register that is adjacent and next shift register of being adjacent, the signal output part of first shift register (OUTPUT1) only is connected with the input signal end (INPUT) of second shift register, and the output terminal (OUTPUT n+1) of last shift register (the n+1 shift register among the figure as shown in figure 12) is connected with the reset signal input end (RETSETIN) of n the shift register that is adjacent and the reset signal input end (RETSETIN) of self respectively.Thin Film Transistor-LCD adopts the mode of lining by line scan, grid with the thin film transistor (TFT) of connecting with liquid crystal pixel in the delegation all links to each other with same shift register, and the shift register in the LCD device grid drive device can be controlled the conducting that is in the whole thin film transistor (TFT)s among the colleague and end.The concrete principle of LCD device grid drive device is among Figure 12: suppose to have in the panel of LCD the capable liquid crystal pixel of n, referring to sequential chart shown in Figure 13, be input to the input signal end (INPUT) of first shift register in the phase one frame start signal; Subordinate phase, the first shift register signal output terminal (OUTPUT) output high level, this high level signal is input to the input signal end (INPUT) of second shift register simultaneously; Phase III, the second shift register signal output terminal (OUTPUT) output high level, after this each shift register is exported high level successively, is used to control the conducting of the thin film transistor (TFT) of going together that links to each other with this shift register, and principle is with second and third stage; To the quadravalence section, n shift register output high level, the high level of n shift register output simultaneously is as the input signal of the input signal end (INPUT) of n+1 shift register; Five-stage, n+1 shift register output high level, the high level of this n+1 shift register output is not used in the driving load, the i.e. thin film transistor (TFT) of the not responsible drive controlling of n+1 shift register delegation liquid crystal pixel, the high level signal of its output only are used for as n shift register and the reset signal of himself.
Be LCD device grid drive device embodiment two structural representations of the present invention as shown in figure 14, the difference of Figure 14 and gate drive apparatus shown in Figure 12 is: saved n+1 shift register among Figure 14, frame start signal is except that with the input signal end (INPUT) of first shift register is connected, also be connected with the reset signal input end (RESETIN) of n shift register, then the reset signal of n shift register is provided by frame start signal STV, and shift register need increase the reset signal that a shift register produces the n shift register like that and need not as shown in figure 12.
Shift register in the LCD device grid drive device of the present invention can be as Fig. 5, Fig. 6, Fig. 8, Fig. 9, Figure 10, shift register shown in Figure 11.
Shift register that the embodiment of the invention provides and LCD device grid drive device, can effectively suppress output noise, and can guarantee that each thin film transistor (TFT) in shift register and the gate drive apparatus can not produce big threshold voltage shift, thereby guarantee the operate as normal life-span of shift register and gate drive apparatus.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (11)
1. a shift register is characterized in that, comprising:
The first film transistor, its drain electrode connects first clock signal input terminal, and grid connects an end of first electric capacity, and source electrode connects the first electric capacity other end and the signal output part respectively;
Second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of signal output part and the first film respectively, and grid connects the reset signal input end, and source electrode is connected with the low voltage signal input end;
The 3rd thin film transistor (TFT), its grid is connected with signal input part, and drain electrode is connected with the high voltage signal input end;
The 4th thin film transistor (TFT), its grid is connected with described reset signal input end, and drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with the low voltage signal input end;
First pull-down thin film, its drain electrode is connected with signal output part and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The first pull-down thin film driver element, be connected with the source electrode of high voltage signal input end, first clock signal input terminal, second clock signal input part, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) and the grid of drain electrode and described first pull-down thin film respectively, be used for when signal output part output low level and the first clock signal input terminal input signal are high level, control described first pull-down thin film and opening;
Second pull-down thin film, its drain electrode is connected with signal output part and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The second pull-down thin film driver element, be connected with the source electrode of the described first pull-down thin film driver element, high voltage signal input end, first clock signal input terminal, second clock signal input part, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) and the grid of drain electrode and described second pull-down thin film respectively, be used for when signal output part output low level and second clock signal input part input signal are high level, control second pull-down thin film and opening.
2. shift register according to claim 1 is characterized in that, the described first pull-down thin film driver element specifically comprises:
The 6th thin film transistor (TFT), its drain electrode is connected with the drain electrode of described high voltage signal input end and described the 3rd thin film transistor (TFT), and grid is connected with described first clock signal input terminal, and source electrode is connected with the grid of described first pull-down thin film;
The 7th thin film transistor (TFT), its drain electrode is connected with the source electrode and the transistorized grid of described the first film of described the 3rd thin film transistor (TFT), and grid is connected with the source electrode of described the 6th thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 11 thin film transistor (TFT), the source electrode of its described the 6th thin film transistor (TFT) that drains connects, and grid is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 12 thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 6th thin film transistor (TFT), and grid is connected with described second clock signal input part, and source electrode is connected with described low voltage signal input end;
Described first clock signal is the reverse clock signal of second clock signal.
3. shift register according to claim 1 and 2 is characterized in that, the described second pull-down thin film driver element specifically comprises:
The 5th thin film transistor (TFT), its drain electrode is connected with the drain electrode of described high voltage signal input end and described the 3rd thin film transistor (TFT), and grid is connected with described second clock signal input part, and source electrode is connected with the grid of described second pull-down thin film;
The 8th thin film transistor (TFT), its drain electrode is connected with the source electrode and the transistorized grid of described the first film of described the 3rd thin film transistor (TFT), and grid is connected with the source electrode of described the 5th thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 9th thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 5th thin film transistor (TFT), and grid is connected with described first clock signal input terminal, and source electrode is connected with described low voltage signal input end;
The tenth thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 5th thin film transistor (TFT), and grid is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
Described first clock signal is the reverse clock signal of second clock signal.
4. a shift register is characterized in that, comprising:
The first film transistor, its drain electrode connects first clock signal input terminal, and grid connects an end of first electric capacity, and source electrode connects the other end and the signal output part of described first electric capacity respectively;
Second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of signal output part and the first film respectively, and grid connects the reset signal input end, and source electrode is connected with the low voltage signal input end;
The 3rd thin film transistor (TFT), its grid all is connected with signal input part with drain electrode;
The 4th thin film transistor (TFT), its grid is connected with described reset signal input end, and drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with the low voltage signal input end;
First pull-down thin film, its drain electrode is connected with signal output part and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The first pull-down thin film driver element, be connected with the source electrode and described first pull-down thin film of first clock signal input terminal, second clock signal input part, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) respectively, be used for when signal output part output low level and the first clock signal input terminal input signal are high level, control first pull-down thin film and opening;
Second pull-down thin film, its drain electrode is connected with signal output part and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The second pull-down thin film driver element, be connected with the source electrode and described second pull-down thin film of the described first pull-down thin film driver element, first clock signal input terminal, second clock signal input part, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) respectively, be used for when signal output part output low level and second clock signal input part input signal are high level, control second pull-down thin film and opening.
5. shift register according to claim 4 is characterized in that, the described first pull-down thin film driver element specifically comprises:
The 6th thin film transistor (TFT), its drain and gate all are connected with described first clock signal input terminal, and source electrode is connected with the grid of described first pull-down thin film;
The 7th thin film transistor (TFT), its drain electrode is connected with the source electrode and the transistorized grid of the first film of described the 3rd thin film transistor (TFT), and grid is connected with the source electrode of described the 6th thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 11 thin film transistor (TFT), the source electrode of its described the 6th thin film transistor (TFT) that drains connects, and grid is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 12 thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 6th thin film transistor (TFT), and grid is connected with described second clock signal input part, and source electrode is connected with described low voltage signal input end;
Described first clock signal is the reverse clock signal of second clock signal.
6. according to claim 4 or 5 described shift registers, it is characterized in that the described second pull-down thin film driver element specifically comprises:
The 5th thin film transistor (TFT), its drain and gate all are connected with described second clock signal input part, and source electrode is connected with the grid of described second pull-down thin film;
The 8th thin film transistor (TFT), its drain electrode is connected with the transistorized grid of described the first film with the source electrode of described the 3rd thin film transistor (TFT), and grid is connected with the source electrode of described the 5th thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 9th thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 5th thin film transistor (TFT), and grid is connected with described first clock signal input terminal, and source electrode is connected with described low voltage signal input end;
The tenth thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 5th thin film transistor (TFT), and grid is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
Described first clock signal is the reverse clock signal of second clock signal.
7. a shift register is characterized in that, comprising:
The first film transistor, its drain electrode connects first clock signal input terminal, and grid connects an end of first electric capacity, and source electrode connects the other end and the signal output part of described first electric capacity respectively;
Second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of signal output part and the first film respectively, and grid connects the reset signal input end, and source electrode is connected with the low voltage signal input end;
The 3rd thin film transistor (TFT), its grid all is connected with signal input part with drain electrode;
The 4th thin film transistor (TFT), its grid is connected with described reset signal input end, and drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with the low voltage signal input end;
First pull-down thin film, its grid connect the described first pull-down thin film driver element, and drain electrode is connected with signal output part, first electric capacity and the transistorized source electrode of the first film respectively, and source electrode connects the low voltage signal input end;
The first pull-down thin film driver element, be connected with the source electrode of first clock signal input terminal, second clock signal input part, high voltage signal input end, low voltage signal input end, the transistorized grid of the first film, the 3rd thin film transistor (TFT) and the grid of described first pull-down thin film respectively, be used for when signal output part output low level and the first clock signal input terminal input signal are high level, control first pull-down thin film and opening;
Second pull-down thin film, its drain electrode is connected with signal output part, first electric capacity and the transistorized source electrode of described the first film respectively, and source electrode connects the low voltage signal input end;
The second pull-down thin film driver element, be connected with the source electrode of the described first pull-down thin film driver element, first clock signal input terminal, second clock signal input part, high voltage signal input end, low voltage signal input end, the transistorized grid of described the first film, the 3rd thin film transistor (TFT) and the grid of described second pull-down thin film respectively, be used for when signal output part output low level and second clock signal input part input signal are high level, control second pull-down thin film and opening.
8. shift register according to claim 7 is characterized in that, the described first pull-down thin film driver element specifically comprises:
The 6th thin film transistor (TFT), its drain electrode is connected with described high voltage signal input end, and grid is connected with described first clock signal input terminal, and source electrode is connected with the grid of described first pull-down thin film;
The 7th thin film transistor (TFT), its drain electrode is connected with the source electrode and the transistorized grid of the first film of described the 3rd thin film transistor (TFT), and grid is connected with the source electrode of described the 6th thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 11 thin film transistor (TFT), the source electrode of its described the 6th thin film transistor (TFT) that drains connects, and grid is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 12 thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 6th thin film transistor (TFT), and grid is connected with described second clock signal input part, and source electrode is connected with described low voltage signal input end;
Described first clock signal is the reverse clock signal of second clock signal.
9. according to claim 7 or 8 described shift registers, it is characterized in that the described second pull-down thin film driver element specifically comprises:
The 5th thin film transistor (TFT), its drain electrode is connected with described high voltage signal input end, and grid is connected with described second clock signal input part, and source electrode is connected with the grid of described second pull-down thin film;
The 8th thin film transistor (TFT), its drain electrode is connected with the source electrode and the transistorized grid of described the first film of described the 3rd thin film transistor (TFT), and grid is connected with the source electrode of described the 5th thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
The 9th thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 5th thin film transistor (TFT), and grid is connected with described first clock signal input terminal, and source electrode is connected with described low voltage signal input end;
The tenth thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 5th thin film transistor (TFT), and grid is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with described low voltage signal input end;
Described first clock signal is the reverse clock signal of second clock signal.
10. a LCD device grid drive device is characterized in that, comprising: be deposited on a plurality of as the described shift register of arbitrary claim among the claim 1-9 on the LCD (Liquid Crystal Display) array substrate;
Except that first shift register and last shift register, the signal output part of all the other each shift registers all is connected with the reset signal input end of signal input part that is adjacent next shift register and the last shift register that is adjacent, the signal output part of first shift register is connected with the signal input part of second shift register, and the signal output part of last shift register and the reset signal input end of a last shift register that is adjacent and the reset signal input end of self is connected;
The signal input part incoming frame start signal of first shift register;
The first clock signal input terminal input system, first clock signal of odd number shift register, second clock signal input part input system second clock signal; The first clock signal input terminal input system second clock signal of even number shift register, second clock signal input part input system first clock signal;
The low voltage signal input end input low level signal of each shift register;
The high voltage signal input end input high level signal of each shift register.
11. a LCD device grid drive device is characterized in that, comprising: be deposited on a plurality of on the LCD (Liquid Crystal Display) array substrate as the described shift register of arbitrary claim among the claim 1-9;
Except that first shift register and last shift register, the signal output part of all the other each shift registers all is connected with the reset signal input end of signal input part that is adjacent next shift register and the last shift register that is adjacent, the signal output part of first shift register is connected with the signal input part of second shift register, and the signal output part of last shift register is connected with the reset signal input end of a last shift register that is adjacent;
The reset signal input end of the signal input part of first shift register and last shift register is the incoming frame start signal all;
The first clock signal input terminal input system, first clock signal of odd number shift register, second clock signal input part input system second clock signal; The first clock signal input terminal input system second clock signal of even number shift register, second clock signal input part input system first clock signal;
The low voltage signal input end input low level signal of each shift register;
The high voltage signal input end input high level signal of each shift register.
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| CN102654982B (en) | 2011-05-16 | 2013-12-04 | 京东方科技集团股份有限公司 | Shift register unit circuit, shift register, array substrate and liquid crystal display |
| CN102651187B (en) * | 2011-05-16 | 2014-09-24 | 京东方科技集团股份有限公司 | Shift register unit circuit, shift register, array substrate and liquid crystal displayer |
| CN102629444B (en) * | 2011-08-22 | 2014-06-25 | 北京京东方光电科技有限公司 | Circuit of gate drive on array, shift register and display screen |
| CN102646384B (en) * | 2011-09-28 | 2014-10-22 | 京东方科技集团股份有限公司 | Shift register unit, shift register, array substrate and display device |
| CN102708778B (en) * | 2011-11-28 | 2014-04-23 | 京东方科技集团股份有限公司 | Shift register and drive method thereof, gate drive device and display device |
| CN102411917A (en) * | 2011-12-21 | 2012-04-11 | 深圳市华星光电技术有限公司 | Drive circuit of liquid crystal panel and liquid crystal display |
| CN102779493B (en) * | 2011-12-31 | 2015-08-12 | 北京京东方光电科技有限公司 | Shift register cell, shift register and liquid crystal indicator |
| CN102708779B (en) | 2012-01-13 | 2014-05-14 | 京东方科技集团股份有限公司 | Shift register and driving device thereof, grid driving device and display device |
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| US8860652B2 (en) * | 2012-08-23 | 2014-10-14 | Innocom Technology (Shenzhen) Co., Ltd. | Shift registers, display panels, display devices, and electronic devices |
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| CN103021354B (en) * | 2012-11-21 | 2015-07-15 | 京东方科技集团股份有限公司 | Shifting register unit, gate driving circuit and display device |
| CN103489484B (en) * | 2013-09-22 | 2015-03-25 | 京东方科技集团股份有限公司 | Shifting register unit and gate drive circuit |
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