TWI694431B - Pixel circuit and display device - Google Patents

Pixel circuit and display device Download PDF

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TWI694431B
TWI694431B TW108100429A TW108100429A TWI694431B TW I694431 B TWI694431 B TW I694431B TW 108100429 A TW108100429 A TW 108100429A TW 108100429 A TW108100429 A TW 108100429A TW I694431 B TWI694431 B TW I694431B
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terminal
compensation
transistor
electrically connected
signal
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TW108100429A
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TW202001850A (en
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林志隆
陳力榮
陳福星
張瑞宏
鄭貿薰
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友達光電股份有限公司
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Abstract

A pixel circuit includes a light emitting diode, a driving transistor, a compensation transistor, a capacitive coupling circuit, and a first switching transistor. A first terminal of the driving transistor is configured to receive a power signal, and the second terminal of the driving transistor is electrically coupled to the light emitting diode. The compensation transistor is electrically coupled to the second terminal and a control terminal of the driving transistor, and is turned on or turned off according to a first compensation control signal. The capacitive coupling circuit has a first terminal, a first node, and a second node. The second node is electrically coupled to the control terminal of the driving transistor. A first terminal of the first switch transistor is configured to receive a data signal, and a second terminal of the first switch transistor is electrically coupled to the first node.

Description

畫素電路與顯示裝置 Pixel circuit and display device

本揭示內容關於一種畫素電路與顯示裝置,特別是一種可補償驅動電晶體的臨界電壓變異的畫素電路。 The present disclosure relates to a pixel circuit and a display device, and particularly to a pixel circuit capable of compensating for the critical voltage variation of driving transistors.

低溫多晶矽薄膜電晶體(low temperature poly-silicon thin-film transistor)具有高載子遷移率與尺寸小的特點,適合應用於高解析度、窄邊框以及低耗電的顯示面板。目前業界廣泛使用準分子雷射退火(excimer laser annealing)技術來形成低溫多晶矽薄膜電晶體的多晶矽薄膜。然而,由於準分子雷射每一發的掃描功率並不穩定,不同區域的多晶矽薄膜會具有晶粒尺寸與數量的差異。因此,於顯示面板的不同區域中,低溫多晶矽薄膜電晶體的特性便會不同。例如,不同區域的低溫多晶矽薄膜電晶體會有著不同的臨界電壓(threshold voltage)。 Low temperature poly-silicon thin-film transistor (low temperature poly-silicon thin-film transistor) has high carrier mobility and small size, suitable for high-resolution, narrow frame and low power consumption display panel. At present, the industry widely uses excimer laser annealing (excimer laser annealing) technology to form polycrystalline silicon thin films of low-temperature polycrystalline silicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polycrystalline silicon films in different regions will have differences in grain size and number. Therefore, the characteristics of the low-temperature polysilicon thin film transistor will be different in different areas of the display panel. For example, low-temperature polysilicon thin film transistors in different regions will have different threshold voltages.

目前業界廣泛使用畫素內補償之技術方案,以克服上述臨界電壓變異的問題。然而,具有畫素內補償功能之畫素電路具有複雜之電路結構,使得相關之顯示面 板的開口率低下。 At present, the industry widely uses the technical solution of intra-pixel compensation to overcome the above-mentioned critical voltage variation problem. However, the pixel circuit with the internal pixel compensation function has a complicated circuit structure, which lowers the aperture ratio of the related display panel.

本揭示內容之一態樣係一種畫素電路,包含發光二極體、驅動電晶體、補償電晶體、電容耦合電路及第一開關電晶體。驅動電晶體具有第一端、第二端與控制端。驅動電晶體的第一端用以接收電源訊號,驅動電晶體的第二端電性連接發光二極體。補償電晶體具有第一端、第二端與控制端。補償電晶體之第二端電性連接於發光二極體,補償電晶體之控制端用以接收第一補償控制訊號。電容耦合電路具有第一端、第一節點及第二節點。電容耦合電路之第一端電性連接參考電壓源,電容耦合電路之第二節點電性連接於驅動電晶體之控制端與補償電晶體之第一端。第一開關電晶體具有第一端、第二端與控制端。第一開關電晶體的第一端用以接收資料訊號,第一開關電晶體的第二端電性連接第一節點。第一開關電晶體的控制端用以接收閘極訊號。 One aspect of the present disclosure is a pixel circuit including a light emitting diode, a driving transistor, a compensation transistor, a capacitive coupling circuit, and a first switching transistor. The driving transistor has a first end, a second end and a control end. The first end of the driving transistor is used to receive the power signal, and the second end of the driving transistor is electrically connected to the light emitting diode. The compensation transistor has a first end, a second end and a control end. The second terminal of the compensation transistor is electrically connected to the light-emitting diode, and the control terminal of the compensation transistor is used to receive the first compensation control signal. The capacitive coupling circuit has a first end, a first node and a second node. The first end of the capacitive coupling circuit is electrically connected to the reference voltage source, and the second node of the capacitive coupling circuit is electrically connected to the control terminal of the driving transistor and the first end of the compensation transistor. The first switching transistor has a first end, a second end and a control end. The first end of the first switching transistor is used to receive the data signal, and the second end of the first switching transistor is electrically connected to the first node. The control terminal of the first switching transistor is used to receive the gate signal.

本揭示內容之另一態樣係一種畫素電路。畫素電路包含發光二極體、驅動電晶體、補償電晶體及電容耦合電路。驅動電晶體具有第一端、第二端與控制端。驅動電晶體的第一端用以接收電源訊號,驅動電晶體的第二端電性連接於發光二極體,驅動電晶體的控制端用以接收驅動電壓,以根據驅動電壓輸出電源訊號至發光二極體。在一重置期間中,驅動電晶體被關斷,使得發光二極體上的電壓放電。補償電晶體用以根據第一補償訊號選擇性地導通驅動電 晶體之控制端及第二端。電容耦合電路具有第一節點與第二節點。在補償期間,電容耦合電路之第一節點用以接收資料訊號,電容耦合電路之第二節點電性連接至驅動電晶體之控制端。當電容耦合電路之第一節點接收資料訊號時,驅動電壓的電壓準位相應於資料訊號的電壓準位變化而變化。 Another aspect of this disclosure is a pixel circuit. The pixel circuit includes a light-emitting diode, a driving transistor, a compensation transistor, and a capacitive coupling circuit. The driving transistor has a first end, a second end and a control end. The first end of the driving transistor is used to receive the power signal, the second end of the driving transistor is electrically connected to the light emitting diode, and the control end of the driving transistor is used to receive the driving voltage to output the power signal according to the driving voltage to emit light Diode. During a reset period, the driving transistor is turned off, so that the voltage on the light emitting diode is discharged. The compensation transistor is used to selectively turn on the control terminal and the second terminal of the driving transistor according to the first compensation signal. The capacitive coupling circuit has a first node and a second node. During the compensation period, the first node of the capacitive coupling circuit is used to receive the data signal, and the second node of the capacitive coupling circuit is electrically connected to the control terminal of the driving transistor. When the first node of the capacitive coupling circuit receives the data signal, the voltage level of the driving voltage changes according to the change in the voltage level of the data signal.

本揭示內容之又一態樣係一種顯示裝置。顯示裝置包含複數條閘極線、複數條資料線、第一補償控制線及複數個畫素電路。該些閘極線用以分別傳送一閘極訊號。該些資料線用以分別傳送一資料訊號。第一補償控制線用以傳送一第一補償控制訊號。該些畫素電路分別排列為一陣列形狀,且該些畫素電路中的至少一個包含:發光二極體、驅動電晶體、補償電晶體、電容耦合電路及第一開關電晶體。驅動電晶體具有第一端、第二端與控制端,驅動電晶體的第一端用以接收電源訊號,驅動電晶體的第二端電性連接發光二極體。補償電晶體具有第一端、第二端與控制端,補償電晶體之第二端電性連接於發光二極體,補償電晶體之控制端電性連接至第一補償控制線,用以接收第一補償控制訊號。電容耦合電路具有第一端、第一節點及第二端,電容耦合電路之第一端電性連接參考電壓源,電容耦合電路之第二端電性連接於驅動電晶體之控制端與補償電晶體之第一端。第一開關電晶體具有第一端、第二端與控制端,第一開關電晶體的第一端電性連接至些資料線的其中一條,用以接收資料訊號。第一開關電晶體的第二端電性連接第一節點,第一開關電晶體的控制端電性連接於該些閘極線的其中一 條,用以接收閘極訊號。 Another aspect of the disclosure is a display device. The display device includes a plurality of gate lines, a plurality of data lines, a first compensation control line, and a plurality of pixel circuits. The gate lines are used to transmit a gate signal respectively. The data lines are used to transmit a data signal respectively. The first compensation control line is used to transmit a first compensation control signal. The pixel circuits are arranged in an array shape, and at least one of the pixel circuits includes: a light-emitting diode, a driving transistor, a compensation transistor, a capacitive coupling circuit, and a first switching transistor. The driving transistor has a first end, a second end and a control end. The first end of the driving transistor is used to receive a power signal, and the second end of the driving transistor is electrically connected to the light emitting diode. The compensation transistor has a first end, a second end and a control end. The second end of the compensation transistor is electrically connected to the light-emitting diode, and the control end of the compensation transistor is electrically connected to the first compensation control line for receiving The first compensation control signal. The capacitive coupling circuit has a first terminal, a first node and a second terminal. The first terminal of the capacitive coupling circuit is electrically connected to the reference voltage source, and the second terminal of the capacitive coupling circuit is electrically connected to the control terminal of the driving transistor and the compensation circuit The first end of the crystal. The first switching transistor has a first end, a second end and a control end. The first end of the first switching transistor is electrically connected to one of the data lines for receiving data signals. The second terminal of the first switching transistor is electrically connected to the first node, and the control terminal of the first switching transistor is electrically connected to one of the gate lines to receive the gate signal.

本揭示內容之畫素電路與顯示裝置,能透過電容耦合電路中多個電容間的電容耦合效應,對驅動電晶體之控制端進行補償,以克服驅動電晶體之臨界電壓變異的問題,且使畫素電路具有精簡的電路架構。 The pixel circuit and the display device of the present disclosure can compensate the control terminal of the driving transistor through the capacitive coupling effect between multiple capacitors in the capacitive coupling circuit to overcome the problem of the critical voltage variation of the driving transistor, and make The pixel circuit has a simplified circuit architecture.

100‧‧‧畫素電路 100‧‧‧Pixel circuit

110‧‧‧發光二極體 110‧‧‧ LED

120‧‧‧電容耦合電路 120‧‧‧Capacitive coupling circuit

200‧‧‧顯示裝置 200‧‧‧Display device

201‧‧‧顯示區 201‧‧‧Display area

202‧‧‧非顯示區 202‧‧‧non-display area

210‧‧‧源極驅動器 210‧‧‧Source Driver

220‧‧‧閘極驅動器 220‧‧‧Gate driver

230‧‧‧補償電路 230‧‧‧ Compensation circuit

T1‧‧‧驅動電晶體 T1‧‧‧Drive transistor

T2‧‧‧補償電晶體 T2‧‧‧Compensation transistor

T3‧‧‧第一開關電晶體 T3‧‧‧ First switching transistor

T4‧‧‧第二開關電晶體 T4‧‧‧second switching transistor

C1‧‧‧第一電容 C1‧‧‧ First capacitor

C2‧‧‧第二電容 C2‧‧‧Second capacitor

Id‧‧‧驅動電流 Id‧‧‧Drive current

S1‧‧‧第一補償控制訊號 S1‧‧‧First compensation control signal

S2‧‧‧第二補償控制訊號 S2‧‧‧Second compensation control signal

S3‧‧‧閘極訊號 S3‧‧‧Gate signal

Vdd‧‧‧電源訊號 Vdd‧‧‧power signal

Vddl‧‧‧第一低準位電壓 Vddl‧‧‧First low level voltage

VL‧‧‧第二低準位電壓 VL‧‧‧Second low level voltage

Vssl‧‧‧第三低準位電壓 Vssl‧‧‧third lowest level voltage

Vddh‧‧‧第一高準位電壓 Vddh‧‧‧Highest level voltage

Vssh‧‧‧第二高準位電壓 Vssh‧‧‧second highest level voltage

Vref‧‧‧參考準位電壓 Vref‧‧‧reference level voltage

Vdata‧‧‧資料訊號 Vdata‧‧‧Data signal

Vin‧‧‧輸入電壓 Vin‧‧‧Input voltage

Vss‧‧‧參考電壓源 Vss‧‧‧reference voltage source

A‧‧‧第一節點 A‧‧‧First node

B‧‧‧第二節點 B‧‧‧The second node

P1‧‧‧重置期間 P1‧‧‧ reset period

P2‧‧‧補償期間 P2‧‧‧ Compensation period

P3‧‧‧資料寫入期間 P3‧‧‧Data writing period

P4‧‧‧發光期間 P4‧‧‧ during light

第1圖為根據本揭示內容之部分實施例所繪示的畫素電路的示意圖。 FIG. 1 is a schematic diagram of a pixel circuit according to some embodiments of the present disclosure.

第2圖為根據本揭示內容之部分實施例所繪示的畫素電路的運作時序圖。 FIG. 2 is an operation timing diagram of a pixel circuit according to some embodiments of the present disclosure.

第3A~3D圖為本揭示內容之部分實施例中,畫素電路於不同運作時序中的示意圖。 FIGS. 3A to 3D are schematic diagrams of pixel circuits in different operation timings in some embodiments of the present disclosure.

第4A~4D圖為本揭示內容之部分實施例中,畫素電路於不同運作時序中的示意圖。 FIGS. 4A to 4D are schematic diagrams of pixel circuits in different operation timings in some embodiments of the present disclosure.

第5圖為根據本揭示內容之部分實施例所繪示的畫素電路的運作時序圖。 FIG. 5 is an operation timing diagram of a pixel circuit according to some embodiments of the present disclosure.

第6圖為根據本揭示內容之部分實施例所繪示的顯示裝置的示意圖。 FIG. 6 is a schematic diagram of a display device according to some embodiments of the present disclosure.

以下將以圖式揭露本案之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一 併說明。然而,應瞭解到,這些實務上的細節不應用以限制本案。也就是說,在本揭示內容部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。 In the following, a plurality of embodiments of the case will be disclosed in the form of diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the case. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

於本文中,當一元件被稱為「連接」或「耦接」時,可指「電性連接」或「電性耦接」。「連接」或「耦接」亦可用以表示二或多個元件間相互搭配操作或互動。此外,雖然本文中使用「第一」、「第二」、…等用語描述不同元件,該用語僅是用以區別以相同技術用語描述的元件或操作。除非上下文清楚指明,否則該用語並非特別指稱或暗示次序或順位,亦非用以限定本發明。 In this article, when an element is referred to as "connected" or "coupled", it can be referred to as "electrically connected" or "electrically coupled." "Connected" or "coupled" can also be used to indicate that two or more components interact or interact with each other. In addition, although terms such as "first", "second", etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly dictates, the term does not specifically refer to or imply order or order, nor is it intended to limit the present invention.

請參閱第1圖所示,為根據本揭示內容之部分實施例所繪示的畫素電路100的示意圖。畫素電路100包含發光二極體110、驅動電晶體T1、補償電晶體T2、電容耦合電路120及第一開關電晶體T3。驅動電晶體T1具有第一端、第二端與控制端,其中,驅動電晶體T1的第一端用以接收電源訊號Vdd,驅動電晶體T1的第二端電性連接至發光二極體110。 Please refer to FIG. 1, which is a schematic diagram of a pixel circuit 100 according to some embodiments of the present disclosure. The pixel circuit 100 includes a light-emitting diode 110, a driving transistor T1, a compensation transistor T2, a capacitive coupling circuit 120, and a first switching transistor T3. The driving transistor T1 has a first end, a second end and a control end, wherein the first end of the driving transistor T1 is used to receive the power signal Vdd, and the second end of the driving transistor T1 is electrically connected to the light emitting diode 110 .

於本實施例中,補償電晶體T2具有第一端、第二端與控制端,其中,補償電晶體T2的第二端電性連接於發光二極體110,補償電晶體T2之控制端則用以接收第一補償控制訊號S1。另外,電容耦合電路120具有第一端、第一節點A及第二節點B,其中,電容耦合電路120的第一端電性連接參考電壓源Vss,電容耦合電路120的第二節點B 電性連接於驅動電晶體T1之控制端與補償電晶體T2的第一端。 In this embodiment, the compensation transistor T2 has a first end, a second end, and a control end, wherein the second end of the compensation transistor T2 is electrically connected to the light emitting diode 110, and the control end of the compensation transistor T2 is It is used to receive the first compensation control signal S1. In addition, the capacitive coupling circuit 120 has a first terminal, a first node A, and a second node B, wherein the first terminal of the capacitive coupling circuit 120 is electrically connected to the reference voltage source Vss, and the second node B of the capacitive coupling circuit 120 is electrically It is connected to the control terminal of the driving transistor T1 and the first terminal of the compensation transistor T2.

於本實施例中,第一開關電晶體T3具有第一端、第二端與控制端,其中,第一開關電晶體T3的第一端用以接收資料訊號Vdata,第一開關電晶體T3的第二端電性連接第一節點A,而第一開關電晶體T3的控制端用以接收閘極訊號S3。於本實施例中,閘極訊號S3用以控制第一開關電晶體T3的導通或關斷。 In this embodiment, the first switching transistor T3 has a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switching transistor T3 is used to receive the data signal Vdata, and the first switching transistor T3 The second terminal is electrically connected to the first node A, and the control terminal of the first switching transistor T3 is used to receive the gate signal S3. In this embodiment, the gate signal S3 is used to control the on or off of the first switching transistor T3.

在前述實施例之電路架構中,畫素電路100能於重置期間中,預先提升第一節點A的電壓值,並於補償期間時,利用電容耦合電路120內多個電容的電容耦合效應,在驅動電晶體T1之源極與閘極間產生電位差。如此,即可補償臨界電壓的變異,使顯示面板產生均勻亮度。此外,在部分實施例中,可於重置期間中調整電源訊號,釋放發光二極體110的殘餘電壓,以防止顯示面板產生閃爍現象。 In the circuit architecture of the foregoing embodiment, the pixel circuit 100 can advance the voltage value of the first node A during the reset period, and utilize the capacitive coupling effect of multiple capacitors in the capacitive coupling circuit 120 during the compensation period. A potential difference is generated between the source and gate of the driving transistor T1. In this way, the variation of the threshold voltage can be compensated, so that the display panel produces uniform brightness. In addition, in some embodiments, the power signal can be adjusted during the reset period to release the residual voltage of the light emitting diode 110 to prevent the display panel from flickering.

在部分實施例中,電容耦合電路120至少包含第一電容C1及第二電容C2,其中,第一電容C1及第二電容C2相互串聯。具體而言,第一電容C1具有第一端與第二端,第一電容C1的第一端電性連接參考電壓源Vss。而第一電容C1的第二端則電性連接第一節點A。第二電容C2具有第一端與第二端,其中,第二電容C2的第一端電性連接該第一節點A,第二電容C2的第二端則電性連接於驅動電晶體T1的控制端。 In some embodiments, the capacitive coupling circuit 120 includes at least a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 and the second capacitor C2 are connected in series with each other. Specifically, the first capacitor C1 has a first terminal and a second terminal, and the first terminal of the first capacitor C1 is electrically connected to the reference voltage source Vss. The second terminal of the first capacitor C1 is electrically connected to the first node A. The second capacitor C2 has a first end and a second end, wherein the first end of the second capacitor C2 is electrically connected to the first node A, and the second end of the second capacitor C2 is electrically connected to the driving transistor T1 Control terminal.

在部分實施例中,畫素電路100更包含第二 開關電晶體T4,且第二開關電晶體T4具有第一端、第二端與控制端,其中第二開關電晶體T4的第一端用以接收資料訊號Vdata,第二開關電晶體T4的第二端則電性連接於補償電晶體T2的第一端(或第二節點B),而第二開關電晶體T4的控制端用以接收第二補償控制訊號S2。於本實施例中,第二補償控制訊號S2用以控制第二開關電晶體T4導通或關斷。 In some embodiments, the pixel circuit 100 further includes a second switching transistor T4, and the second switching transistor T4 has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switching transistor T4 is used To receive the data signal Vdata, the second terminal of the second switching transistor T4 is electrically connected to the first terminal (or second node B) of the compensation transistor T2, and the control terminal of the second switching transistor T4 is used to receive The second compensation control signal S2. In this embodiment, the second compensation control signal S2 is used to control the second switching transistor T4 to be turned on or off.

第2圖係根據本揭示內容之部分實施例繪製之運作時序圖。畫素電路100的工作週期包括重置期間P1、補償期間P2、資料寫入期間P3及發光期間P4。在部分實施例中,畫素電路100應用於顯示裝置,且顯示裝置之處理器會依序驅動每一排的畫素電路100(請參考第6圖之顯示裝置200示意圖)。第2圖中之S3[n]、S3[n+1]係代表用於驅動相鄰之畫素電路100之閘極訊號S3。 FIG. 2 is an operation timing chart drawn according to some embodiments of the present disclosure. The duty cycle of the pixel circuit 100 includes a reset period P1, a compensation period P2, a data writing period P3, and a light emitting period P4. In some embodiments, the pixel circuit 100 is applied to a display device, and the processor of the display device sequentially drives the pixel circuits 100 of each row (please refer to the schematic diagram of the display device 200 in FIG. 6). S3[n] and S3[n+1] in FIG. 2 represent the gate signal S3 for driving the adjacent pixel circuit 100.

請參閱第2及3A圖,在重置期間P1中,將電源訊號Vdd調降至第一低準位電壓Vddl,使驅動電晶體T1關斷,如此,能確保發光二極體110在重置期間P1時不會有電流流過,且使發光二極體110的正極端的電壓被放電至低電位,避免顯示面板產生閃爍現象。同時,第一補償控制訊號S1為禁能準位,使補償電晶體T2被關斷。閘極訊號S3及第二補償控制訊號S2為致能準位,使第一開關電晶體T3與第二開關電晶體T4分別導通,且第一節點A與第二節點B分別接收資料訊號Vdata,在一實施例中,當重置期間P1,資料訊號Vdata為參考準位電壓Vref,且參考準位電壓Vref 為高電位,以抬升第一節點A及第二節點B之電壓值。舉例而言,在本實施例中,驅動電晶體T1、補償電晶體T2、第一開關電晶體T3及第二開關電晶體T4皆為P型TFT(薄膜電晶體)。如第2圖所示,對於P型TFT而言,禁能準位為高電位、致能準位為低電位。反之,當驅動電晶體T1、補償電晶體T2、第一開關電晶體T3及第二開關電晶體T4皆為N型TFT時,禁能準位為低電位、致能準位為高電位。 Please refer to FIGS. 2 and 3A. During the reset period P1, the power signal Vdd is reduced to the first low level voltage Vddl to turn off the driving transistor T1. In this way, it can ensure that the light emitting diode 110 is reset During the period P1, no current flows, and the voltage of the positive terminal of the light-emitting diode 110 is discharged to a low potential to avoid flickering of the display panel. At the same time, the first compensation control signal S1 is the disabled level, so that the compensation transistor T2 is turned off. The gate signal S3 and the second compensation control signal S2 are enable levels, so that the first switching transistor T3 and the second switching transistor T4 are respectively turned on, and the first node A and the second node B receive the data signal Vdata, In one embodiment, during the reset period P1, the data signal Vdata is the reference level voltage Vref, and the reference level voltage Vref is at a high level, so as to raise the voltage values of the first node A and the second node B. For example, in this embodiment, the driving transistor T1, the compensation transistor T2, the first switching transistor T3, and the second switching transistor T4 are all P-type TFTs (thin film transistors). As shown in FIG. 2, for the P-type TFT, the disable level is high and the enable level is low. Conversely, when the driving transistor T1, the compensation transistor T2, the first switching transistor T3, and the second switching transistor T4 are all N-type TFTs, the disable level is low and the enable level is high.

請參閱第2及3B圖,在補償期間P2,第一補償控制訊號S1及閘極訊號S3為致能準位,使補償電晶體T2及第一開關電晶體T3被導通。第二補償控制訊號S2為禁能準位,以關斷第二開關電晶體T4。資料訊號Vdata則保持在第二低準位電壓VL、電源訊號仍保持在第一低準位電壓Vddl。在一實施例中,第二低準位電壓VL小於第一低準位電壓Vddl。透過將資料訊號Vdata控制在較低的第二低準位電壓VL,將能調降第一節點A的電壓值。同時,透過電容耦合電路120內之電容耦合效應,使第二節點B之電壓值亦下降,如此一來,將可以拉開驅動電晶體T1之源極(第二端)與閘極(控制端)之間的電位差,確保驅動電晶體T1導通。此時,第二節點B的電壓值會被控制在Vddl-|Vth|(驅動電晶體T1之臨界電壓值),而第一節點A的電壓會被控制在第二低準位電壓VL。 Please refer to FIGS. 2 and 3B. During the compensation period P2, the first compensation control signal S1 and the gate signal S3 are enable levels, so that the compensation transistor T2 and the first switching transistor T3 are turned on. The second compensation control signal S2 is the disable level to turn off the second switching transistor T4. The data signal Vdata remains at the second low level voltage VL, and the power signal remains at the first low level voltage Vddl. In one embodiment, the second low level voltage VL is less than the first low level voltage Vddl. By controlling the data signal Vdata at a lower second low level voltage VL, the voltage value of the first node A can be reduced. At the same time, through the capacitive coupling effect in the capacitive coupling circuit 120, the voltage value of the second node B also drops, so that the source (second end) and the gate (control end) of the driving transistor T1 can be pulled apart ) To ensure that the driving transistor T1 is turned on. At this time, the voltage value of the second node B will be controlled at Vddl-|Vth| (the critical voltage value of the driving transistor T1), and the voltage of the first node A will be controlled at the second low level voltage VL.

請參閱第2及3C圖,在資料寫入期間P3,第一補償控制訊號S1及第二補償控制訊號S2為禁能準位,以關斷補償電晶體T2及第二開關電晶體T4。閘極訊號S3為 致能準位,以維持第一開關電晶體T3的導通,在部分實施例中,閘極訊號S3之致能準位為低準位電壓。如第2圖所示,顯示裝置依序對相鄰之畫素電路100進行資料寫入之動作,因此,不同畫素電路100之閘極訊號S3(即,S3[n]、S3[n+1])會依序被控制於低準位電壓。 Please refer to FIGS. 2 and 3C. During the data writing period P3, the first compensation control signal S1 and the second compensation control signal S2 are disabled levels to turn off the compensation transistor T2 and the second switching transistor T4. The gate signal S3 is an enable level to maintain the conduction of the first switching transistor T3. In some embodiments, the enable level of the gate signal S3 is a low level voltage. As shown in FIG. 2, the display device sequentially writes data to adjacent pixel circuits 100. Therefore, the gate signals S3 of different pixel circuits 100 (ie, S3[n], S3[n+ 1]) will be controlled to a low level voltage in sequence.

承上,在資料寫入期間P3,第一節點A透過第一開關電晶體T3的導通而接收資料訊號Vdata。資料訊號Vdata對應於一寫入電壓Vin,用以決定發光二極體110之發光強度。由於在資料寫入期間P3中,第一節點A的電壓值從原先的VL變化為Vin,因此,根據電容耦合效應,第二節點B上的電壓值會產生與第一節點A相同的變化幅度。第一節點的電壓變化幅度為「Vin-VL」,故,第二節點B的電壓值會變成「Vddl-|Vth|+(Vin-VL)」。 According to the above, during the data writing period P3, the first node A receives the data signal Vdata through the conduction of the first switching transistor T3. The data signal Vdata corresponds to a write voltage Vin, which is used to determine the light emitting intensity of the light emitting diode 110. During the data writing period P3, the voltage value of the first node A changes from the original VL to Vin, therefore, according to the capacitive coupling effect, the voltage value on the second node B will have the same variation range as the first node A . The voltage change range of the first node is "Vin-VL", so the voltage value of the second node B becomes "Vddl-|Vth|+(Vin-VL)".

請參閱第2及3D圖,在發光期間P4,第一補償控制訊號S1、閘極訊號S3及第二補償控制訊號S2皆保持在禁能準位,使補償電晶體T2、第一開關電晶體T3及第二開關電晶體T4皆被關斷,且電源訊號為第一高準位電壓Vddh。此時,驅動電晶體T1能將電源訊號Vdd輸出至發光二極體110,使發光二極體110上流經一驅動電流Id,以產生預期之亮度。根據電晶體的電流公式「I=K×(Vsg-|Vth|)2」,其中,K代表驅動電晶體T1的載子遷移率(carrier mobility)、閘極氧化層的單位電容大小以及閘極寬長比三者的乘積。Vsg為驅動電晶體T1之第二端(源極)及控制端之間的電壓差。|Vth|則為驅動電晶體T1的臨界電 壓值。由於在驅動電晶體T1導通時,其第一端及第二端可視為短路,因此,驅動電晶體T1之第二端(源極)可視為第一高準位電壓Vddh。前述公式能被整理為「I=K×(Vddh-Vddl+|Vth|-(Vin-VL)-|Vth|)2」,由於電流與臨界電壓值無關,因此能確保發光二極體110的發光強度不會因為臨界電壓值的變異而受到影響。 Please refer to figures 2 and 3D. During the light-emitting period P4, the first compensation control signal S1, the gate signal S3 and the second compensation control signal S2 are kept at the disabled level, so that the compensation transistor T2 and the first switching transistor Both T3 and the second switching transistor T4 are turned off, and the power signal is the first high level voltage Vddh. At this time, the driving transistor T1 can output the power signal Vdd to the light emitting diode 110, so that a driving current Id flows through the light emitting diode 110 to generate a desired brightness. According to the current formula of the transistor "I=K×(Vsg-|Vth|) 2 ", where K represents the carrier mobility of the driving transistor T1, the unit capacitance of the gate oxide layer and the gate The product of width to length ratio. Vsg is the voltage difference between the second terminal (source) of the driving transistor T1 and the control terminal. |Vth| is the critical voltage value of the driving transistor T1. When the driving transistor T1 is turned on, the first end and the second end thereof can be regarded as a short circuit. Therefore, the second end (source) of the driving transistor T1 can be regarded as the first high level voltage Vddh. The aforementioned formula can be sorted into "I=K×(Vddh-Vddl+|Vth|-(Vin-VL)-|Vth|) 2 ", because the current is independent of the critical voltage value, so that the light emitting diode 110 can be guaranteed to emit light The strength will not be affected by the variation of the critical voltage value.

請參閱第4A~4D及5圖,係根據本揭示內容之其他實施例繪製之示意圖。請參閱第4A及5圖所示,在部分實施例中,驅動電晶體T1的第一端接收固定之電源訊號Vdd,且第二開關電晶體T4之第一端用以接收電源訊號Vdd。驅動電晶體T1的第二端透過發光二極體110電性連接於參考電壓源Vss。 Please refer to FIGS. 4A to 4D and 5 for schematic diagrams drawn according to other embodiments of the present disclosure. Please refer to FIGS. 4A and 5. In some embodiments, the first end of the driving transistor T1 receives the fixed power signal Vdd, and the first end of the second switching transistor T4 is used to receive the power signal Vdd. The second end of the driving transistor T1 is electrically connected to the reference voltage source Vss through the light-emitting diode 110.

在本實施例中,在重置期間P1時,參考電壓源Vss為第二高準位電壓Vssh,以使驅動電晶體T1及發光二極體110關斷,避免發光二極體110產生閃爍現象。第一補償控制訊號S1及閘極訊號S3為禁能準位,第二補償控制訊號S2為致能準位,該資料訊號Vdata則為參考準位電壓Vref。此時,第二節點B之電壓會被控制在電源訊號Vdd。 In this embodiment, during the reset period P1, the reference voltage source Vss is the second highest level voltage Vssh, so that the driving transistor T1 and the light-emitting diode 110 are turned off to avoid the flicker phenomenon of the light-emitting diode 110 . The first compensation control signal S1 and the gate signal S3 are the disable level, the second compensation control signal S2 is the enable level, and the data signal Vdata is the reference level voltage Vref. At this time, the voltage of the second node B will be controlled at the power signal Vdd.

請參閱第4B及5圖,在補償期間P2中,第一補償控制訊號S1及閘極訊號S3為致能準位,以導通補償電晶體T2及第一開關電晶體T3。第二補償控制訊號S2為禁能準位,以關斷第二開關電晶體T4。資料訊號Vdata則為低電位之參考準位電壓Vref。在一實施例中,第二高準位電壓Vssh大於參考準位電壓Vref。此時,第一節點A透過第一開 關電晶體T3接收資料訊號Vdata,使電壓值被控制於低電位。透過電容耦合電路120之電容耦合效應,第二節點B之電壓將相應下降,使驅動電晶體T1能被導通。同時,由於驅動電晶體T1的閘極(控制端)與源極(第二端)透過補償電晶體T2導通,因此,第二節點B的電壓值會被控制在Vdd-|Vth|(驅動電晶體T1之臨界電壓值),而第一節點A的電壓會被控制在參考準位電壓Vref。 Please refer to FIG. 4B and FIG. 5, in the compensation period P2, the first compensation control signal S1 and the gate signal S3 are enable levels to turn on the compensation transistor T2 and the first switching transistor T3. The second compensation control signal S2 is the disable level to turn off the second switching transistor T4. The data signal Vdata is a low-level reference level voltage Vref. In one embodiment, the second high level voltage Vssh is greater than the reference level voltage Vref. At this time, the first node A receives the data signal Vdata through the first switching transistor T3, so that the voltage value is controlled to a low potential. Through the capacitive coupling effect of the capacitive coupling circuit 120, the voltage of the second node B will drop accordingly, so that the driving transistor T1 can be turned on. At the same time, since the gate (control terminal) and source (second terminal) of the driving transistor T1 are conducted through the compensation transistor T2, the voltage value of the second node B will be controlled at Vdd-|Vth| The threshold voltage of the crystal T1), and the voltage of the first node A is controlled at the reference level voltage Vref.

請參閱第4C及5圖所示,在資料寫入期間P3中,第一補償控制訊號S1及第二補償控制訊號S2為禁能準位,以關斷補償電晶體T2及第二開關電晶體T4。該閘極訊號S3為該致能準位。此時,第一節點A透過第一開關電晶體T3接收資料訊號Vdata,資料訊號Vdata對應於寫入電壓Vin,用以決定發光二極體110後續之發光強度。由於在資料寫入期間P3中,第一節點A的電壓值從原先的Vref變化為Vin,因此,根據電容耦合效應,第二節點B上的電壓值會產生與第一節點A相同的變化幅度。第一節點的電壓變化幅度為「Vin-Vref」,故,第二節點B的電壓值會變成「Vdd-|Vth|+(Vin-Vref)」。 Please refer to FIG. 4C and FIG. 5, during the data writing period P3, the first compensation control signal S1 and the second compensation control signal S2 are disabled levels to turn off the compensation transistor T2 and the second switching transistor T4. The gate signal S3 is the enabling level. At this time, the first node A receives the data signal Vdata through the first switching transistor T3, and the data signal Vdata corresponds to the write voltage Vin for determining the subsequent light emitting intensity of the light emitting diode 110. During the data writing period P3, the voltage value of the first node A changes from the original Vref to Vin, therefore, according to the capacitive coupling effect, the voltage value on the second node B will have the same variation range as the first node A . The voltage change range of the first node is "Vin-Vref", so the voltage value of the second node B becomes "Vdd-|Vth|+(Vin-Vref)".

請參閱第4D及5圖所示,在發光期間P4中,第一補償控制訊號S1、閘極訊號S3及第二補償控制訊號S2為禁能準位,以關斷補償電晶體T2、第一開關電晶體T3及第二開關電晶體T4。參考電壓源Vss變化為第三低準位電壓Vssl。根據電容耦合效應,第一節點A及第二節點B會產生電壓值變化,且變化幅度與參考電壓源Vss的電壓值變 化幅度「Vssh-Vssl」將會一致,亦即,第二節點B的電壓值會變成「Vdd-|Vth|+(Vin-Vref)-(Vssh-Vssl)」。此時,驅動電晶體T1能將電源訊號Vdd輸出至發光二極體110,使發光二極體110發光。 Please refer to FIG. 4D and FIG. 5, during the light-emitting period P4, the first compensation control signal S1, the gate signal S3 and the second compensation control signal S2 are disabled levels to turn off the compensation transistor T2, the first The switching transistor T3 and the second switching transistor T4. The reference voltage source Vss changes to the third lowest level voltage Vssl. According to the capacitive coupling effect, the voltage changes of the first node A and the second node B will occur, and the change amplitude will be consistent with the voltage value of the reference voltage source Vss "Vssh-Vssl", that is, the second node B The voltage value will become "Vdd-|Vth|+(Vin-Vref)-(Vssh-Vssl)". At this time, the driving transistor T1 can output the power signal Vdd to the light emitting diode 110 to make the light emitting diode 110 emit light.

由於在驅動電晶體T1導通時,其第一端及第二端可視為短路,因此,驅動電晶體T1之第二端(源極)可視為第一高準位電壓Vddh。電晶體的電流公式能被整理為「I=K×(Vdd-(Vdd-|Vth|+(Vin-Vref)-(Vssh-Vssl)-|Vth|)2」,由於電流與臨界電壓值無關,因此能確保發光二極體110的發光強度不會因為臨界電壓值的變異而受到影響。 When the driving transistor T1 is turned on, the first end and the second end thereof can be regarded as a short circuit. Therefore, the second end (source) of the driving transistor T1 can be regarded as the first high level voltage Vddh. The current formula of the transistor can be sorted into "I=K×(Vdd-(Vdd-|Vth|+(Vin-Vref)-(Vssh-Vssl)-|Vth|) 2 ", because the current has nothing to do with the critical voltage value Therefore, it can be ensured that the light emitting intensity of the light emitting diode 110 is not affected by the variation of the threshold voltage value.

在第3A~3D圖與第4A~4D圖中,分別說明了本揭示內容之二部分實施例,兩者的差異在於,第4A~4D圖之實施例係透過調整參考電壓源Vss之電壓值,控制驅動電晶體T1開啟或關斷,此外,第4A~4D圖之實施例中,第二開關電晶體T4電性連接於電源訊號Vdd,在重置期間P1的控制方式與第3A~3D圖之實施例不同。 Figures 3A~3D and 4A~4D illustrate the two partial embodiments of the disclosure, the difference between the two is that the embodiments of Figures 4A~4D are by adjusting the voltage value of the reference voltage source Vss To control the driving transistor T1 to be turned on or off. In addition, in the embodiment shown in FIGS. 4A to 4D, the second switching transistor T4 is electrically connected to the power signal Vdd. The embodiment of the figure is different.

請參閱第6圖,係根據本揭示內容之部分實施例繪示之顯示裝置200。顯示裝置200中至少包含源極驅動器210、閘極驅動器220及補償電路230。顯示裝置200用以驅動顯示面板,以產生預期之影像。在部分實施例中,顯示面板包括顯示區201及非顯示區202,多個畫素電路100位於顯示區201內,多個補償電路230則位於非顯示區202內。 Please refer to FIG. 6, which is a display device 200 according to some embodiments of the present disclosure. The display device 200 includes at least a source driver 210, a gate driver 220, and a compensation circuit 230. The display device 200 is used to drive a display panel to generate a desired image. In some embodiments, the display panel includes a display area 201 and a non-display area 202, a plurality of pixel circuits 100 are located in the display area 201, and a plurality of compensation circuits 230 are located in the non-display area 202.

在部分實施例中,顯示裝置200更包含多條 閘極線GL、多條資料線DL、至少一條第一補償控制線203及至少一條第二補償控制線204。該些閘極線GL電性連接閘極驅動器220及畫素電路100(如:電性連接至第一開關電晶體T3的控制端),用以分別傳送閘極訊號S3。該些資料線DL電性連接源極驅動器210及畫素電路100(如:電性連接至第一開關電晶體T3及第二開關電晶體T4),用以傳送資料訊號Vdata。第一補償控制線203電性連接補償電路230及畫素電路(如:電性連接至補償電晶體T2的控制端),用以傳送第一補償控制訊號S1。第二補償控制線204電性連接補償電路230及畫素電路(如:電性連接至第二開關電晶體T4的控制端),用以傳送第二補償控制訊號S2。 In some embodiments, the display device 200 further includes a plurality of gate lines GL, a plurality of data lines DL, at least one first compensation control line 203 and at least one second compensation control line 204. The gate lines GL are electrically connected to the gate driver 220 and the pixel circuit 100 (eg, electrically connected to the control end of the first switching transistor T3), and are used to transmit the gate signal S3 respectively. The data lines DL are electrically connected to the source driver 210 and the pixel circuit 100 (eg, electrically connected to the first switching transistor T3 and the second switching transistor T4) for transmitting the data signal Vdata. The first compensation control line 203 is electrically connected to the compensation circuit 230 and the pixel circuit (eg, electrically connected to the control terminal of the compensation transistor T2), and is used to transmit the first compensation control signal S1. The second compensation control line 204 is electrically connected to the compensation circuit 230 and the pixel circuit (eg, electrically connected to the control terminal of the second switching transistor T4), and is used to transmit the second compensation control signal S2.

在部分實施例中,多個畫素電路分別排列為陣列形狀。請參閱第1及6圖所示,畫素電路100包含發光二極體110、驅動電晶體T1、補償電晶體T2、電容耦合電路120、第一開關電晶體T3及第二開關電晶體T4。驅動電晶體T1具有第一端、第二端與控制端。驅動電晶體T1的第一端用以接收電源訊號Vdd該驅動電晶體T1的第二端電性連接於發光二極體110。驅動電晶體T1的控制端用以接收驅動電壓,以根據驅動電壓輸出電源訊號Vdd至發光二極體110。在部分實施例中,驅動電壓為前述資料寫入期間P3中的資料訊號Vdata(即,輸入電壓Vin)。在重置期間P1中,驅動電晶體T1被關斷,使得發光二極體110上的電壓放電。 In some embodiments, multiple pixel circuits are arranged in an array shape. Referring to FIGS. 1 and 6, the pixel circuit 100 includes a light-emitting diode 110, a driving transistor T1, a compensation transistor T2, a capacitive coupling circuit 120, a first switching transistor T3, and a second switching transistor T4. The driving transistor T1 has a first end, a second end and a control end. The first end of the driving transistor T1 is used to receive the power signal Vdd. The second end of the driving transistor T1 is electrically connected to the light emitting diode 110. The control terminal of the driving transistor T1 is used to receive the driving voltage to output the power signal Vdd to the light emitting diode 110 according to the driving voltage. In some embodiments, the driving voltage is the data signal Vdata (ie, the input voltage Vin) in the aforementioned data writing period P3. In the reset period P1, the driving transistor T1 is turned off, so that the voltage on the light emitting diode 110 is discharged.

補償電晶體T2用以根據第一補償訊號S1選擇性地導通驅動電晶體T1之控制端及該第二端。在部分實施 例中,補償電晶體T2之控制端電性連接至第一補償控制線,以接收第一補償控制訊號S1。電容耦合電路120具有第一節點A與第二節點B。在補償期間P2中,電容耦合電路120之第一節點A用以接收資料訊號Vdata(即,前述之輸入電壓Vin),第二節點B電性連接至驅動電晶體T1之該控制端。電容耦合電路120中包含多個電容,以在第一節點A接收資料訊號Vdata時,驅動電晶體T1之控制端之驅動電壓的電壓準位相應於資料訊號Vdata的電壓準位變化而變化。 The compensation transistor T2 is used to selectively turn on the control terminal of the driving transistor T1 and the second terminal according to the first compensation signal S1. In some embodiments, the control terminal of the compensation transistor T2 is electrically connected to the first compensation control line to receive the first compensation control signal S1. The capacitive coupling circuit 120 has a first node A and a second node B. During the compensation period P2, the first node A of the capacitive coupling circuit 120 is used to receive the data signal Vdata (ie, the aforementioned input voltage Vin), and the second node B is electrically connected to the control terminal of the driving transistor T1. The capacitive coupling circuit 120 includes a plurality of capacitors, so that when the first node A receives the data signal Vdata, the voltage level of the driving voltage of the control terminal of the driving transistor T1 changes according to the change in the voltage level of the data signal Vdata.

在部分實施例中,第一開關電晶體T3的第一端電性連接至該些資料線DL的其中一條,用以接收資料訊號Vdata。第一開關電晶體T3的控制端電性連接於該些閘極線GL的其中一條,用以接收閘極訊號S3。第二開關電晶體T4的控制端電性連接於第二補償控制線,用以接收第二補償控制訊號S2。 In some embodiments, the first end of the first switching transistor T3 is electrically connected to one of the data lines DL for receiving the data signal Vdata. The control terminal of the first switching transistor T3 is electrically connected to one of the gate lines GL for receiving the gate signal S3. The control terminal of the second switching transistor T4 is electrically connected to the second compensation control line for receiving the second compensation control signal S2.

在本揭示內容之部分實施例中,顯示裝置200係控制所有畫素電路同時進行重置以及同時進行補償。接著,閘極驅動器220再控制每一列的畫素電路依序進行資料寫入。由於本領域人士能理解顯示面板驅動畫素電路的操作順序,故在此不另贅述。 In some embodiments of the present disclosure, the display device 200 controls all pixel circuits to reset and compensate simultaneously. Then, the gate driver 220 controls the pixel circuits of each column to sequentially write data. Since those skilled in the art can understand the operation sequence of the pixel circuit for driving the display panel, it will not be repeated here.

雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本發明內容,任何熟習此技藝者,在不脫離本發明內容之精神和範圍內,當可作各種更動與潤飾,因此本發明內容之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present disclosure has been disclosed as above by way of implementation, it is not intended to limit the content of the present invention. Anyone who is familiar with this skill can make various changes and modifications within the spirit and scope of the present content, so the present invention The protection scope of the content shall be deemed as defined by the scope of the attached patent application.

100‧‧‧畫素電路 100‧‧‧Pixel circuit

110‧‧‧發光二極體 110‧‧‧ LED

120‧‧‧電容耦合電路 120‧‧‧Capacitive coupling circuit

T1‧‧‧驅動電晶體 T1‧‧‧Drive transistor

T2‧‧‧補償電晶體 T2‧‧‧Compensation transistor

T3‧‧‧第一開關電晶體 T3‧‧‧ First switching transistor

T4‧‧‧第二開關電晶體 T4‧‧‧second switching transistor

C1‧‧‧第一電容 C1‧‧‧ First capacitor

C2‧‧‧第二電容 C2‧‧‧Second capacitor

S1‧‧‧第一補償控制訊號 S1‧‧‧First compensation control signal

S2‧‧‧第二補償控制訊號 S2‧‧‧Second compensation control signal

S3‧‧‧閘極訊號 S3‧‧‧Gate signal

Vdd‧‧‧電源訊號 Vdd‧‧‧power signal

Vdata‧‧‧資料訊號 Vdata‧‧‧Data signal

Vss‧‧‧參考電壓源 Vss‧‧‧reference voltage source

A‧‧‧第一節點 A‧‧‧First node

B‧‧‧第二節點 B‧‧‧The second node

Claims (23)

一種畫素電路,包含:一發光二極體;一驅動電晶體,具有一第一端、一第二端與一控制端,其中該驅動電晶體的該第一端用以接收一電源訊號,該驅動電晶體的該第二端電性連接該發光二極體;一補償電晶體,具有一第一端、一第二端與一控制端,其中該補償電晶體的該第二端電性連接於該發光二極體,該補償電晶體的該控制端用以接收一第一補償控制訊號;一電容耦合電路,具有一第一端、一第一節點及一第二節點,其中該電容耦合電路的該第一端電性連接一參考電壓源,該電容耦合電路的該第二節點電性連接於該驅動電晶體的該控制端與該補償電晶體的該第一端;一第一開關電晶體,具有一第一端、一第二端與一控制端,該第一開關電晶體的該第一端用以接收一資料訊號,該第一開關電晶體的該第二端電性連接該第一節點,該第一開關電晶體的該控制端用以接收一閘極訊號;以及一第二開關電晶體,具有一第一端、一第二端與一控制端,該第二開關電晶體的該第一端用以接收該資料訊號,該第二開關電晶體的該第二端則電性連接於該補償電晶體的該第一端,且該第二開關電晶體的該控制端用以接收一第二補償控制訊號;其中該電容耦合電路更包含:一第一電容,具有一第一端與一第二端,該第一電容的 該第一端電性連接該參考電壓源,而該第一電容的該第二端則電性連接該第一節點;以及一第二電容,具有一第一端與一第二端,該第二電容的該第一端電性連接該第一節點,該第二電容的該第二端則電性連接於該驅動電晶體的該控制端。 A pixel circuit includes: a light-emitting diode; a driving transistor having a first end, a second end and a control end, wherein the first end of the driving transistor is used to receive a power signal, The second end of the driving transistor is electrically connected to the light-emitting diode; a compensation transistor has a first end, a second end and a control end, wherein the second end of the compensation transistor is electrically Connected to the light-emitting diode, the control terminal of the compensation transistor is used to receive a first compensation control signal; a capacitive coupling circuit has a first terminal, a first node and a second node, wherein the capacitor The first end of the coupling circuit is electrically connected to a reference voltage source, and the second node of the capacitive coupling circuit is electrically connected to the control end of the driving transistor and the first end of the compensation transistor; a first The switching transistor has a first end, a second end and a control end, the first end of the first switching transistor is used to receive a data signal, and the second end of the first switching transistor is electrically Connected to the first node, the control terminal of the first switching transistor is used to receive a gate signal; and a second switching transistor has a first terminal, a second terminal and a control terminal, the second The first end of the switching transistor is used to receive the data signal, the second end of the second switching transistor is electrically connected to the first end of the compensation transistor, and the second end of the second switching transistor The control terminal is used to receive a second compensation control signal; wherein the capacitive coupling circuit further includes: a first capacitor having a first terminal and a second terminal, the The first end is electrically connected to the reference voltage source, and the second end of the first capacitor is electrically connected to the first node; and a second capacitor has a first end and a second end, the first The first terminal of the two capacitors is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the control terminal of the driving transistor. 如請求項1所述之畫素電路,其中於一重置期間,該電源訊號為一第一低準位電壓,該第一補償控制訊號為一禁能準位,該閘極訊號及該第二補償控制訊號為一致能準位,該資料訊號則為一參考準位電壓。 The pixel circuit according to claim 1, wherein during a reset period, the power signal is a first low level voltage, the first compensation control signal is a disabled level, the gate signal and the first The second compensation control signal is a uniform energy level, and the data signal is a reference level voltage. 如請求項2所述之畫素電路,其中於一補償期間,該第一補償控制訊號及該閘極訊號為該致能準位,該第二補償控制訊號為該禁能準位,該資料訊號則為一第二低準位電壓。 The pixel circuit according to claim 2, wherein in a compensation period, the first compensation control signal and the gate signal are the enable level, and the second compensation control signal is the disable level, the data The signal is a second low level voltage. 如請求項3所述之畫素電路,其中該第二低準位電壓小於該第一低準位電壓。 The pixel circuit according to claim 3, wherein the second low level voltage is smaller than the first low level voltage. 如請求項4所述之畫素電路,其中於一資料寫入期間,該第一補償控制訊號及該第二補償控制訊號為該禁能準位,該閘極訊號為該致能準位。 The pixel circuit according to claim 4, wherein during a data writing period, the first compensation control signal and the second compensation control signal are the disable level, and the gate signal is the enable level. 如請求項5所述之畫素電路,其中於一發光期 間,該第一補償控制訊號、該閘極訊號及該第二補償控制訊號為該禁能準位。 The pixel circuit as described in claim 5, wherein in a light-emitting period In the meantime, the first compensation control signal, the gate signal and the second compensation control signal are the disable level. 如請求項1所述之畫素電路,其中該驅動電晶體的該第二端電性連接於該參考電壓源,於一重置期間,該參考電壓源為一第一高準位電壓,該第一補償控制訊號及該閘極訊號為一禁能準位,該第二補償控制訊號為一致能準位,該資料訊號則為一參考準位電壓。 The pixel circuit of claim 1, wherein the second terminal of the driving transistor is electrically connected to the reference voltage source, and during a reset period, the reference voltage source is a first high level voltage, the The first compensation control signal and the gate signal are a disabling level, the second compensation control signal is a uniform level, and the data signal is a reference level voltage. 如請求項7所述之畫素電路,其中於一補償期間,該第一補償控制訊號及該閘極訊號為一致能準位,該第二補償控制訊號為該禁能準位。 The pixel circuit according to claim 7, wherein in a compensation period, the first compensation control signal and the gate signal are at a uniform energy level, and the second compensation control signal is the disabled level. 如請求項8所述之畫素電路,其中該第一高準位電壓大於該參考準位電壓。 The pixel circuit according to claim 8, wherein the first high level voltage is greater than the reference level voltage. 如請求項9所述之畫素電路,其中於一資料寫入期間,該第一補償控制訊號及該第二補償控制訊號為該禁能準位,該閘極訊號為該致能準位。 The pixel circuit according to claim 9, wherein during a data writing period, the first compensation control signal and the second compensation control signal are the disable level, and the gate signal is the enable level. 如請求項10所述之畫素電路,其中於一發光期間,該第一補償控制訊號、該閘極訊號及該第二補償控制訊號為該禁能準位。 The pixel circuit according to claim 10, wherein the first compensation control signal, the gate signal and the second compensation control signal are the disable level during a light-emitting period. 一種畫素電路,包含:一發光二極體;一驅動電晶體,具有一第一端、一第二端與一控制端,其中該驅動電晶體的該第一端用以接收一電源訊號,該驅動電晶體的該第二端電性連接於該發光二極體,該驅動電晶體的該控制端用以接收一驅動電壓,以根據該驅動電壓輸出該電源訊號至該發光二極體,其中於一重置期間,該驅動電晶體被關斷,使得該發光二極體上的電壓放電;一補償電晶體,用以根據一第一補償訊號選擇性地導通該驅動電晶體的該控制端及該第二端;以及一電容耦合電路,具有一第一節點與一第二節點,且該電容耦合電路的該第一節點用以於一補償期間接收一資料訊號,該電容耦合電路的該第二節點電性連接至該驅動電晶體的該控制端;其中當該電容耦合電路的該第一節點接收該資料訊號時,該驅動電壓的電壓準位相應於該資料訊號的電壓準位變化而變化。 A pixel circuit includes: a light-emitting diode; a driving transistor having a first end, a second end and a control end, wherein the first end of the driving transistor is used to receive a power signal, The second end of the driving transistor is electrically connected to the light emitting diode, and the control end of the driving transistor is used to receive a driving voltage to output the power signal to the light emitting diode according to the driving voltage, During a reset period, the driving transistor is turned off to discharge the voltage on the light-emitting diode; a compensation transistor is used to selectively turn on the control of the driving transistor according to a first compensation signal End and the second end; and a capacitive coupling circuit, having a first node and a second node, and the first node of the capacitive coupling circuit is used to receive a data signal during a compensation period, the capacitive coupling circuit The second node is electrically connected to the control terminal of the driving transistor; wherein when the first node of the capacitive coupling circuit receives the data signal, the voltage level of the driving voltage corresponds to the voltage level of the data signal Change and change. 如請求項12所述之畫素電路,其中該電容耦合電路包含:一第一電容,具有一第一端與一第二端,其中該第一電容的該第一端電性連接一參考電壓源,該第一電容的該第二端電性連接該第一節點;及一第二電容,具有一第一端與一第二端,其中該第二電 容的該第一端電性連接該第一節點,該第二電容的該第二端電性連接該驅動電晶體的該控制端。 The pixel circuit according to claim 12, wherein the capacitive coupling circuit includes: a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is electrically connected to a reference voltage Source, the second end of the first capacitor is electrically connected to the first node; and a second capacitor has a first end and a second end, wherein the second The first terminal of the capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the control terminal of the driving transistor. 如請求項12所述之畫素電路,更包含:一第一開關電晶體,具有一第一端、一第二端與一控制端,其中該第一開關電晶體的該第一端用以於該補償期間接收該資料訊號,該第一開關電晶體的該第二端電性連接至該第一節點,其中,當該第一開關電晶體導通時,該第一節點透過該第一開關電晶體接收該資料訊號。 The pixel circuit according to claim 12, further comprising: a first switching transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switching transistor is used to Receiving the data signal during the compensation period, the second end of the first switching transistor is electrically connected to the first node, wherein, when the first switching transistor is turned on, the first node passes through the first switch The transistor receives the data signal. 如請求項14所述之畫素電路,更包含:一第二開關電晶體,具有一第一端、一第二端與一控制端,且該第二開關電晶體的該第一端用以接收該資料訊號,該第二開關電晶體的該第二端電性連接該第二節點。 The pixel circuit according to claim 14, further comprising: a second switching transistor having a first terminal, a second terminal and a control terminal, and the first terminal of the second switching transistor is used for Receiving the data signal, the second end of the second switching transistor is electrically connected to the second node. 如請求項15所述之畫素電路,其中於該重置期間,該第一開關電晶體與該第二開關電晶體分別導通,使得該第一節點與該第二節點分別接收一參考準位訊號。 The pixel circuit according to claim 15, wherein during the reset period, the first switching transistor and the second switching transistor are respectively turned on, so that the first node and the second node respectively receive a reference level Signal. 如請求項14所述之畫素電路,其中於一補償期間,該第一開關電晶體及該補償電晶體導通。 The pixel circuit according to claim 14, wherein the first switching transistor and the compensation transistor are turned on during a compensation period. 如請求項14所述之畫素電路,更包含:一第二開關電晶體,具有一第一端、一第二端與一控制 端,其中該第二開關電晶體之該第一端用以接收該電源訊號,該第二開關電晶體之該第二端電性連接該第二節點。 The pixel circuit according to claim 14, further comprising: a second switching transistor having a first terminal, a second terminal and a control Terminal, wherein the first terminal of the second switching transistor is used to receive the power signal, and the second terminal of the second switching transistor is electrically connected to the second node. 一種顯示裝置,包含:複數條閘極線,用以分別傳送一閘極訊號;複數條資料線,用以分別傳送一資料訊號;一第一補償控制線,用以傳送一第一補償控制訊號;一第二補償控制線,用以傳送一第二補償控制訊號;以及複數個畫素電路,分別排列為一陣列形狀,該些畫素電路中的至少一個包含:一發光二極體;一驅動電晶體,具有一第一端、一第二端與一控制端,其中該驅動電晶體的該第一端用以接收一電源訊號,該驅動電晶體的該第二端電性連接該發光二極體;一補償電晶體,具有一第一端、一第二端與一控制端,其中該補償電晶體的該第二端電性連接於該發光二極體,該補償電晶體的該控制端電性連接至該第一補償控制線,用以接收該第一補償控制訊號;一電容耦合電路,具有一第一端、一第一節點及一第二端,其中該電容耦合電路的該第一端電性連接一參考電壓源,該電容耦合電路的該第二端電性連接於該驅動電晶體的該控制端與該補償電晶體的該第一端;一第一開關電晶體,具有一第一端、一第二端與一控制 端,該第一開關電晶體的該第一端電性連接至該些資料線的其中一條,用以接收該資料訊號,該第一開關電晶體的該第二端電性連接該第一節點,該第一開關電晶體的該控制端電性連接於該些閘極線的其中一條,用以接收該閘極訊號;以及一第二開關電晶體,具有一第一端、一第二端與一控制端,該第二開關電晶體的該第一端用以接收該資料訊號,該第二開關電晶體的該第二端則電性連接於該補償電晶體的該第一端,且該第二開關電晶體的該控制端電性連接於該第二補償控制線,用以接收該第二補償控制訊號。 A display device includes: a plurality of gate lines for transmitting a gate signal; a plurality of data lines for transmitting a data signal; a first compensation control line for transmitting a first compensation control signal A second compensation control line for transmitting a second compensation control signal; and a plurality of pixel circuits, arranged in an array shape, at least one of the pixel circuits includes: a light emitting diode; The driving transistor has a first end, a second end and a control end, wherein the first end of the driving transistor is used to receive a power signal, and the second end of the driving transistor is electrically connected to the light emitting Diode; a compensation transistor with a first end, a second end and a control end, wherein the second end of the compensation transistor is electrically connected to the light-emitting diode, the compensation transistor The control terminal is electrically connected to the first compensation control line for receiving the first compensation control signal; a capacitive coupling circuit has a first terminal, a first node and a second terminal, wherein the The first terminal is electrically connected to a reference voltage source, the second terminal of the capacitive coupling circuit is electrically connected to the control terminal of the driving transistor and the first terminal of the compensation transistor; a first switching transistor , With a first end, a second end and a control End, the first end of the first switching transistor is electrically connected to one of the data lines for receiving the data signal, and the second end of the first switching transistor is electrically connected to the first node , The control terminal of the first switching transistor is electrically connected to one of the gate lines for receiving the gate signal; and a second switching transistor has a first end and a second end And a control end, the first end of the second switching transistor is used to receive the data signal, the second end of the second switching transistor is electrically connected to the first end of the compensation transistor, and The control terminal of the second switching transistor is electrically connected to the second compensation control line for receiving the second compensation control signal. 如請求項19的顯示裝置,其中於一重置期間,該第一補償控制訊號為一禁能準位,該第二補償控制訊號為一致能準位。 The display device of claim 19, wherein during a reset period, the first compensation control signal is a disabling level, and the second compensation control signal is a uniform level. 如請求項20的顯示裝置,其中於一補償期間,該第一補償控制訊號為該致能準位,該第二補償控制訊號為該禁能準位。 The display device of claim 20, wherein in a compensation period, the first compensation control signal is the enabling level, and the second compensation control signal is the disabling level. 如請求項21的顯示裝置,其中於一資料寫入期間,該第一補償控制訊號及該第二補償控制訊號為該禁能準位。 The display device according to claim 21, wherein during a data writing period, the first compensation control signal and the second compensation control signal are the disable level. 如請求項22的顯示裝置,其中於一發光期間, 該第一補償控制訊號及該第二補償控制訊號為該禁能準位。 The display device according to claim 22, wherein during a light-emitting period, The first compensation control signal and the second compensation control signal are the disable level.
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
TWI728749B (en) * 2020-03-16 2021-05-21 友達光電股份有限公司 Backlight module and repairing method thereof
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201432650A (en) * 2013-02-08 2014-08-16 Au Optronics Corp Pixel structure and driving method thereof
CN105679244A (en) * 2016-03-17 2016-06-15 深圳市华星光电技术有限公司 AMOLED pixel driving circuit and pixel driving circuit
CN106057126A (en) * 2016-05-26 2016-10-26 上海天马有机发光显示技术有限公司 Pixel circuit and drive method thereof
TW201643530A (en) * 2015-06-03 2016-12-16 友達光電股份有限公司 Pixel circuit
US20170061868A1 (en) * 2015-08-26 2017-03-02 Everdisplay Optronics (Shanghai) Limited Pixel driving circuit, driving method thereof and display device using the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2490858A1 (en) * 2004-12-07 2006-06-07 Ignis Innovation Inc. Driving method for compensated voltage-programming of amoled displays
US8576217B2 (en) * 2011-05-20 2013-11-05 Ignis Innovation Inc. System and methods for extraction of threshold and mobility parameters in AMOLED displays
KR102025120B1 (en) * 2013-05-24 2019-09-26 삼성디스플레이 주식회사 A compensation unit and organic light emitting display device including the same
CN104252845B (en) * 2014-09-25 2017-02-15 京东方科技集团股份有限公司 Pixel driving circuit, pixel driving method, display panel and display device
TWI556213B (en) * 2015-12-11 2016-11-01 國立交通大學 pixel compensation device and display having current compensation mechanism
CN106920801B (en) * 2015-12-24 2020-07-14 群创光电股份有限公司 Display device
CN105702214B (en) * 2016-04-12 2018-03-06 深圳市华星光电技术有限公司 AMOLED pixel-driving circuits and image element driving method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201432650A (en) * 2013-02-08 2014-08-16 Au Optronics Corp Pixel structure and driving method thereof
TW201643530A (en) * 2015-06-03 2016-12-16 友達光電股份有限公司 Pixel circuit
US20170061868A1 (en) * 2015-08-26 2017-03-02 Everdisplay Optronics (Shanghai) Limited Pixel driving circuit, driving method thereof and display device using the same
CN105679244A (en) * 2016-03-17 2016-06-15 深圳市华星光电技术有限公司 AMOLED pixel driving circuit and pixel driving circuit
CN106057126A (en) * 2016-05-26 2016-10-26 上海天马有机发光显示技术有限公司 Pixel circuit and drive method thereof

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