TWI694433B - Pixel circuit - Google Patents
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本揭示文件有關一種畫素電路,尤指一種可補償驅動電晶體臨界電壓變異的畫素電路。 This disclosure relates to a pixel circuit, especially a pixel circuit that can compensate for the variation of the critical voltage of the driving transistor.
低溫多晶矽薄膜電晶體(low temperature poly-silicon thin-film transistor,LTPS TFT)具有高載子遷移率與尺寸小的特點,適合應用於高解析度、窄邊框以及低耗電的顯示面板。目前業界廣泛使用準分子雷射退火(excimer laser annealing,ELA)技術來形成低溫多晶矽薄膜電晶體的多晶矽薄膜。然而,由於準分子雷射每一發的掃描功率並不穩定,不同區域的多晶矽薄膜會具有晶粒尺寸與數量的差異。因此,於顯示面板的不同區域中,低溫多晶矽薄膜電晶體的特性便會不同。 Low temperature poly-silicon thin-film transistors (LTPS TFT) have the characteristics of high carrier mobility and small size, and are suitable for display panels with high resolution, narrow bezels and low power consumption. At present, excimer laser annealing (ELA) technology is widely used in the industry to form polycrystalline silicon thin films of low-temperature polycrystalline silicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polycrystalline silicon films in different regions will have differences in grain size and number. Therefore, the characteristics of the low-temperature polysilicon thin film transistor will be different in different areas of the display panel.
舉例而言,不同區域的低溫多晶矽薄膜電晶體會有著不同的臨界電壓(threshold voltage),臨界電壓不同將會造成驅動電流產生差異,導致低溫多晶矽薄膜電晶體的發光亮度不一致。在此情況下,顯示面板在顯示像時將會面臨顯示畫面亮度不均勻的問題。 For example, low-temperature polysilicon thin film transistors in different regions will have different threshold voltages. Different threshold voltages will cause differences in driving currents, resulting in inconsistent luminous brightness of low-temperature polysilicon thin film transistors. In this case, the display panel will face the problem of uneven brightness of the display screen when displaying images.
本發明提供一種畫素電路,其主要係利用外部補償電路以及緩衝電路,將補償電壓傳送至畫素電路內部進行補償,解決臨界電壓變異產生的電流不均勻性,達到防止顯示面板顯示黑畫面時的閃爍現象的功效。 The invention provides a pixel circuit, which mainly uses an external compensation circuit and a buffer circuit to transmit the compensation voltage to the pixel circuit for compensation, solve the current unevenness caused by the critical voltage variation, and prevent the display panel from displaying a black screen The effect of the flicker phenomenon.
本案之第一態樣是在提供一種畫素電路。該畫素電路包含資料寫入電路、發光二極體、驅動電路以及補償電路。寫入電路電性耦接至資料線、第一節點以及第二節點,用以接收掃描訊號以及資料電壓。發光二極體電性耦接至第二節點,用以接收第一電壓。驅動電路電性耦接至第一節點以及第二節點並用以接收第二電壓。補償電路電性耦接至寫入電路及接地端,用以接收控制訊號、第一電壓以及參考電壓,並將補償電壓輸出至寫入電路。 The first aspect of this case is to provide a pixel circuit. The pixel circuit includes a data writing circuit, a light emitting diode, a driving circuit and a compensation circuit. The write circuit is electrically coupled to the data line, the first node and the second node, and is used to receive the scanning signal and the data voltage. The light emitting diode is electrically coupled to the second node for receiving the first voltage. The driving circuit is electrically coupled to the first node and the second node and used to receive the second voltage. The compensation circuit is electrically coupled to the writing circuit and the ground, and is used to receive the control signal, the first voltage and the reference voltage, and output the compensation voltage to the writing circuit.
本案之第二態樣是在提供一種畫素電路。該畫素電路包含資料寫入電路、驅動電路、發光二極體以及補償電路。寫入電路電性耦接至資料線以及第一節點,用以接收掃描訊號。驅動電路電性耦接至第一節點以及第二節點,用以接收第一電壓。發光二極體電性耦接至驅動電路並用以接收第二電壓。補償電路電性耦接至寫入電路及接地端,用以接收控制訊號以及第一電壓,並將補償電壓輸出至寫入電路。 The second aspect of this case is to provide a pixel circuit. The pixel circuit includes a data writing circuit, a driving circuit, a light emitting diode and a compensation circuit. The write circuit is electrically coupled to the data line and the first node to receive the scanning signal. The driving circuit is electrically coupled to the first node and the second node for receiving the first voltage. The light emitting diode is electrically coupled to the driving circuit and used to receive the second voltage. The compensation circuit is electrically coupled to the writing circuit and the ground, and is used to receive the control signal and the first voltage, and output the compensation voltage to the writing circuit.
本案之第三態樣是在提供一種畫素電路。該畫素電路包含資料寫入電路、驅動電路、發光二極體以及補償電路。寫入電路電性耦接至資料線以及第一節點,用以 接收掃描訊號以及資料電壓。驅動電路電性耦接至寫入電路以及第二節點,用以接收第一電壓。發光二極體電性耦接至驅動電路並用以接收第二電壓。補償電路電性耦接至電流源以及寫入電路,用以接收電流源以及第一電壓,並將資料電壓輸出至寫入電路。 The third aspect of this case is to provide a pixel circuit. The pixel circuit includes a data writing circuit, a driving circuit, a light emitting diode and a compensation circuit. The write circuit is electrically coupled to the data line and the first node to receive the scan signal and the data voltage. The driving circuit is electrically coupled to the writing circuit and the second node for receiving the first voltage. The light emitting diode is electrically coupled to the driving circuit and used to receive the second voltage. The compensation circuit is electrically coupled to the current source and the write circuit for receiving the current source and the first voltage and outputting the data voltage to the write circuit.
本發明之畫素電路可利用外部補償電路以及緩衝電路,將外部補償電路產生的補償電壓傳送至畫素電路內部進行補償,解決臨界電壓變異產生的電流不均勻性,達到防止顯示面板顯示黑畫面時的閃爍現象的功效。 The pixel circuit of the present invention can utilize an external compensation circuit and a buffer circuit to transmit the compensation voltage generated by the external compensation circuit to the interior of the pixel circuit for compensation, solve the current unevenness caused by the critical voltage variation, and prevent the display panel from displaying a black screen The effect of the flashing phenomenon at the time.
100、200、300‧‧‧畫素電路 100, 200, 300 ‧‧‧ pixel circuit
110、210、310‧‧‧寫入電路 110, 210, 310‧‧‧ write circuit
120、220、320‧‧‧發光二極體 120, 220, 320 ‧‧‧ LED
130、230、330‧‧‧驅動電路 130, 230, 330 ‧‧‧ drive circuit
140、240、340‧‧‧補償電路 140, 240, 340‧‧‧ Compensation circuit
141、341‧‧‧運算放大器 141,341‧‧‧Operational amplifier
241‧‧‧加法器 241‧‧‧Adder
DL‧‧‧資料線 DL‧‧‧Data cable
VDATA‧‧‧資料電壓 V DATA ‧‧‧Data voltage
IDATA‧‧‧資料源 I DATA ‧‧‧Data source
SCAN[n]‧‧‧掃描訊號 SCAN[n]‧‧‧scanning signal
N1、N2、N3、N4、N5、N6、N7、N8、N9‧‧‧節點 N1, N2, N3, N4, N5, N6, N7, N8, N9
VDD‧‧‧工作電壓 VDD‧‧‧Working voltage
VSS‧‧‧系統低電壓 VSS‧‧‧System low voltage
Vref‧‧‧參考電壓 Vref‧‧‧Reference voltage
CTL‧‧‧控制訊號 CTL‧‧‧Control signal
PH‧‧‧高準位 PH‧‧‧High level
PL‧‧‧低準位 PL‧‧‧Low level
Id1、Id2、Id3‧‧‧驅動電流 Id1, Id2, Id3 ‧‧‧ drive current
T1~T12‧‧‧電晶體 T1~T12‧‧‧Transistor
C1~C6‧‧‧電容 C1~C6‧‧‧Capacitance
TP1‧‧‧重置階段 TP1‧‧‧Reset phase
TP2‧‧‧補償階段 TP2‧‧‧ compensation stage
TP3‧‧‧寫入階段 TP3‧‧‧ Writing stage
TP4‧‧‧發光階段 TP4‧‧‧Lighting stage
為讓揭示文件之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖為根據本揭示文件一實施例的畫素電路的電路圖;第2圖為根據本揭示文件一實施例的畫素電路的運作時序圖;第3圖為根據本揭示文件一實施例的畫素電路的電路圖;第4圖為根據本揭示文件一實施例的畫素電路的運作時序圖;第5圖為根據本揭示文件一實施例的畫素電路的電路圖;以及第6圖為根據本揭示文件一實施例的畫素電路的運作 時序圖。 In order to make the above and other objects, features, advantages and embodiments of the disclosure document more obvious and understandable, the drawings are described as follows: FIG. 1 is a circuit diagram of a pixel circuit according to an embodiment of the disclosure document; section 2 FIG. 3 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure; FIG. 3 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure; FIG. 4 is a pixel according to an embodiment of the present disclosure The operation timing diagram of the circuit; FIG. 5 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure; and FIG. 6 is an operation timing diagram of a pixel circuit according to an embodiment of the present disclosure.
以下將配合相關圖式來說明本發明的實施例。在圖式中,相同的標號表示相同或類似的元件或方法流程。 The embodiments of the present invention will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.
請參閱第1圖。第1圖為根據本揭示文件一實施例的畫素電路100的電路圖。如第1圖所繪示,畫素電路100包含資料寫入電路110、發光二極體120、驅動電路130以及補償電路140。畫素電路100可控制流經發光二極體120的驅動電流Id1的大小,進而使發光二極體120產生不同的灰階亮度。 Please refer to Figure 1. FIG. 1 is a circuit diagram of a
承上述,寫入電路110電性耦接至資料線DL、節點N1及N2,用以接收掃描訊號SCAN[n]以及由資料線DL輸入的資料電壓VDATA。發光二極體120的第一端電性耦接至節點N2,發光二極體120的第二端用以接收工作電壓VDD。驅動電路130電性耦接至節點N1及N2,並用以接收系統低電壓VSS。補償電路140電性耦接至寫入電路110及接地端,用以接收控制訊號CTL、工作電壓VDD以及參考電壓Vref,並將補償電壓輸出至寫入電路110。 According to the above, the
寫入電路110包含電晶體T1及T2,電晶體T1的第一端電性耦接至資料線DL,電晶體T1的第二端電性耦接至節點N1,電晶體T1的控制端電性耦接至掃描訊號SCAN[n]。電晶體T2的第一端電性耦接至節點N2,電晶體T2的第二端電性耦接至補償電路140,電晶體T2的控制端 電性耦接至掃描訊號SCAN[n]。寫入電路110用以根據掃描訊號SCAN[n]和資料電壓VDATA決定節點N1的電壓準位,以及根據補償電路140輸入的補償電壓決定節點N2的電壓。 The
驅動電路130包含電晶體T3及電容C1,電晶體T3的第一端用以接收系統低電壓VSS,電晶體T3的第二端電性耦接至節點N2,電晶體T3的控制端電性耦接至節點N1。電容C1的第一端電性耦接至節點N1,電容C1的第二端電性耦接至節點N2,驅動電路130用以產生驅動電流Id1至發光二極體120。 The driving
補償電路140包含電晶體T4及T5、電容C2以及運算放大器141,電晶體T4的第一端電性耦接至工作電壓VDD,電晶體T4的第二端電性耦接至節點N3,電晶體T4的控制端電性耦接至控制訊號CTL。電晶體T5的第一端電性耦接至接地端,電晶體T5的第二端電性耦接至節點N3,電晶體T5的控制端電性耦接至參考電壓Vref。電容C2的第一端電性耦接至節點N3,電容C2的第二端電性耦接至接地端。運算放大器141的第一輸入端電性耦接至節點N3,運算放大器141的第二輸入端電性耦接至運算放大器141的輸出端,運算放大器141的輸出端電性耦接至資料線DL及寫入電路110,運算放大器141用以輸出補償電壓。 The
實作上,電晶體T1~T5可以用P型的低溫多晶矽薄膜電晶體來實現,但本實施例並不以此為限。例如,電晶體T1~T5也可以用P型的非晶矽(amorphous silicon) 薄膜電晶體或其他型式的薄膜電晶體來實現。 In practice, the transistors T1 to T5 can be implemented with P-type low-temperature polycrystalline silicon thin film transistors, but this embodiment is not limited thereto. For example, the transistors T1 to T5 can also be implemented with P-type amorphous silicon thin-film transistors or other types of thin-film transistors.
以下將配合第1圖和第2圖來進一步說明畫素電路100的運作方式,第2圖為根據本揭示文件一實施例的畫素電路100的運作時序圖。如第2圖所示,在畫素電路100的運作過程中,工作電壓VDD工作於高準位VHIGH(高於參考電壓Vref),控制訊號CTL和掃描訊號SCAN[n]會於高準位PH和低準位PL之間切換。 The operation mode of the
於此實施例中,由於雷射掃描的方向與資料線DL的方向平行,因此如果雷射發出的能量一致,即可假設補償電路140中電晶體T5的特性(例如,臨界電壓)與電晶體T3的特性類似,因此可以將節點N3的電壓用於對同一行的畫素電路進行補償。 In this embodiment, since the direction of the laser scanning is parallel to the direction of the data line DL, if the energy emitted by the laser is the same, it can be assumed that the characteristics (eg, critical voltage) of the transistor T5 in the
承上述,在重置階段TP1中,控制訊號CTL為低準位PL,使得電晶體T4為導通狀態,將節點N3的電壓位準重置到高準位VHIGH。接著,於補償階段TP2中,控制訊號CTL為高準位PH,使得電晶體T4從導通狀態轉態為關閉狀態,因此節點N3的電壓會放透過電晶體T5將原本於高準位VHIGH的電壓放電至補償電壓Vref+|VTH5|。接著運算放大器141由於虛接地(Virtual ground)的特性,會讓運算放大器141的正端及負端的電壓值相同,而運算放大器141的負端又耦接至輸出端,因此運算放大器141會將補償電壓Vref+|VTH5|輸出至寫入電路110的電晶體T2。 According to the above, in the reset phase TP1, the control signal CTL is at the low level PL, so that the transistor T4 is turned on, and resets the voltage level of the node N3 to the high level V HIGH . Then, in the compensation stage TP2, the control signal CTL is at the high level PH, so that the transistor T4 is switched from the on state to the off state, so the voltage of the node N3 will be discharged through the transistor T5 to be originally at the high level V HIGH The voltage is discharged to the compensation voltage Vref+|V TH5 |. Then, due to the characteristics of virtual ground, the
承上述,於寫入階段TP3中,掃描訊號SCAN[n]為低準位PL,使得電晶體T1及T2為導通狀態, 資料電壓VDATA由資料線DL輸入至節點N1,補償電壓Vref+|VTH5|由補償電路140輸入至節點N2。接著,於發光階段TP4中,掃描訊號SCAN[n]為高準位PH,使得電晶體T1及T2轉態為關閉狀態,由於節點N1資料電壓VDATA和節點N2的補償電壓Vref+|VTH5|的電壓差值,使得電晶體T3為導通狀態,使得電晶體T3產生的驅動電流Id1由《公式1》可得知。再者,由於假設電晶體T3的特性與電晶體T5類似,因此電晶體T3的臨界電壓|VTH3|與電晶體T5的臨界電壓|VTH5|相同,兩者可相互抵消,《公式1》如下所示:Id=K(Vref+|VTH5|-VDATA-|VTH3|)2=K(Vref-VDATA)2 《公式1》 According to the above, in the writing stage TP3, the scanning signal SCAN[n] is at the low level PL, so that the transistors T1 and T2 are in the conducting state, the data voltage V DATA is input from the data line DL to the node N1, and the compensation voltage Vref+|V TH5 | is input to the node N2 by the
於此實施例中,由《公式1》可知,驅動電流Id1與驅動電路130的臨界電壓無關。因此,即使顯示面板中不同區域的驅動電晶體130具有不同的特性(例如,不同的臨界電壓),驅動電流Id1和資料電壓VDATA仍會維持固定的對應關係。 In this embodiment, it can be known from “
於另一實施例中,請參閱第3圖。第3圖為根據本揭示文件一實施例的畫素電路200的電路圖。如第3圖所繪示,畫素電路200包含資料寫入電路210、發光二極體220、驅動電路230以及補償電路240。畫素電路200可控制流經發光二極體220的驅動電流Id2的大小,進而使發光二極體220產生不同的灰階亮度。 In another embodiment, please refer to FIG. 3. FIG. 3 is a circuit diagram of the
承上述,寫入電路210電性耦接至資料線DL以及節點N1,用以接收掃描訊號SCAN[n]以及由資料線DL 輸入的資料電壓VDATA和補償電壓。驅動電路230電性耦接至節點N1及N2,用以接收工作電壓VDD。發光二極體220電性耦接至驅動電路230並用以接收系統低電壓VSS。補償電路240電性耦接至寫入電路210及接地端,用以接收控制訊號CTL以及工作電壓VDD,並將補償電壓輸出至寫入電路210。 According to the above, the
寫入電路210包含電晶體T6,電晶體T6的第一端電性耦接至資料線DL,電晶體T6的第二端電性耦接至節點N4,電晶體T6的控制端電性耦接至掃描訊號SCAN[n]。寫入電路210用以根據掃描訊號SCAN[n]以及資料電壓VDATA和補償電壓的總和決定節點N4的電壓準位。 The
驅動電路230包含電晶體T7及電容C3,電晶體T7的第一端電性耦接至節點N5,電晶體T7的第二端電性耦接至發光二極體220,電晶體T7的控制端電性耦接至節點N4。電容C3的第一端電性耦接至節點N4,電容C3的第二端電性耦接至節點N5,驅動電路230用以產生驅動電流Id2至發光二極體220。 The driving
補償電路240包含電晶體T8及T9、電容C4以及加法器241,電晶體T8的第一端電性耦接至接地端,電晶體T8的第二端電性耦接至節點N6,電晶體T8的控制端電性耦接至控制訊號CTL。電晶體T9的第一端電性耦接至工作電壓VDD,電晶體T5的第二端電性耦接至節點N6,電晶體T9的控制端電性耦接至節點N6。電容C4的第一端電性耦接至節點N6。加法器241電性耦接至電容C4的第二端、資 料線DL及寫入電路210,加法器241接收源極積體電路(Source IC)輸入的資料電壓VDATA後,會將資料電壓VDATA和補償電壓合併後輸出。 The
實作上,電晶體T6~T9可以用P型的低溫多晶矽薄膜電晶體來實現,但本實施例並不以此為限。例如,電晶體T6~T9也可以用P型的非晶矽(amorphous silicon)薄膜電晶體或其他型式的薄膜電晶體來實現。 In practice, the transistors T6~T9 can be implemented with P-type low-temperature polycrystalline silicon thin film transistors, but this embodiment is not limited thereto. For example, the transistors T6 to T9 can also be implemented with P-type amorphous silicon thin-film transistors or other types of thin-film transistors.
以下將配合第3圖和第4圖來進一步說明畫素電路200的運作方式,第4圖為根據本揭示文件一實施例的畫素電路200的運作時序圖。如第4圖所示,在畫素電路200的運作過程中,工作電壓VDD工作於高準位VHIGH(高於參考電壓Vref),控制訊號CTL和掃描訊號SCAN[n]會於高準位PH和低準位PL之間切換。 The operation mode of the
於此實施例中,補償電路240中電晶體T9的特性(例如,臨界電壓)與電晶體T7的特性類似,且電晶體T9與電晶體T7位於同一行,因此可以將節點N6的電壓用於對同一行的畫素電路進行補償。 In this embodiment, the characteristics (eg, critical voltage) of the transistor T9 in the
承上述,在重置階段TP1中,控制訊號CTL為低準位PL,使得電晶體T8為導通狀態,將節點N6的電壓位準拉低至低準位VLOW。接著,於補償階段TP2中,控制訊號CTL為高準位PH,使得電晶體T8從導通狀態轉態為關閉狀態,因此節點N6的電壓會放透過電晶體T9將原本於低準位VLOW的電壓充電至補償電壓VDD-|VTH9|。接著加法器241會將補償電壓VDD-|VTH9|與資料電壓VDATA相加後再 輸出至寫入電路210的電晶體T6。 According to the above, in the reset phase TP1, the control signal CTL is at the low level PL, so that the transistor T8 is turned on, and the voltage level of the node N6 is pulled down to the low level V LOW . Then, in the compensation stage TP2, the control signal CTL is at the high level PH, so that the transistor T8 is switched from the on state to the off state, so the voltage of the node N6 will be discharged through the transistor T9 to be originally at the low level V LOW The voltage is charged to the compensation voltage VDD-|V TH9 |. The
承上述,於寫入階段TP3中,掃描訊號SCAN[n]為低準位PL,使得電晶體T6為導通狀態,補償電壓VDD-|VTH9|與資料電壓VDATA由資料線DL輸入至節點N4。接著,於發光階段TP4中,掃描訊號SCAN[n]為高準位PH,使得電晶體T6轉態為關閉狀態,由於節點N4的電壓為VDATA+VDD-|VTH9|和節點N5的工作電壓VDD的電壓差值,使得電晶體T7為導通狀態,使得電晶體T7產生的驅動電流Id2由《公式2》可得知。再者,由於假設電晶體T9的特性與電晶體T7類似,因此電晶體T9的臨界電壓|VTH9|與電晶體T7的臨界電壓|VTH7|相同,兩者可相互抵消,《公式2》如下所示:Id=K(VSG-|VTH7|)2=K(VDD-VDATA-VDD+|VTH9|-|VTH7|)2=k(-VDATA)2《公式2》 According to the above, in the writing stage TP3, the scanning signal SCAN[n] is at the low level PL, so that the transistor T6 is in an on state, the compensation voltage VDD-|V TH9 | and the data voltage V DATA are input to the node from the data line DL N4. Next, in the light-emitting phase TP4, the scanning signal SCAN[n] is at the high level PH, so that the transistor T6 is turned off, because the voltage of the node N4 is V DATA +VDD-|V TH9 | and the operation of the node N5 The voltage difference of the voltage VDD makes the transistor T7 in an on state, so that the driving current Id2 generated by the transistor T7 can be known from "Formula 2". Furthermore, because the characteristics of transistor T9 are assumed to be similar to transistor T7, the critical voltage of transistor T9 |V TH9 | is the same as the critical voltage of transistor T7 |V TH7 |, the two can cancel each other, "Equation 2" As follows: Id=K(V SG -|V TH7 |) 2 =K(VDD-V DATA -VDD+|V TH9 |-|V TH7 |) 2 =k(-V DATA ) 2 "Formula 2"
於此實施例中,由《公式2》可知,驅動電流Id2與驅動電路230的臨界電壓無關。因此,即使顯示面板中不同區域的驅動電晶體230具有不同的特性(例如,不同的臨界電壓),驅動電流Id2和資料電壓VDATA仍會維持固定的對應關係。 In this embodiment, it can be known from "Formula 2" that the driving current Id2 has nothing to do with the threshold voltage of the driving
於另一實施例中,請參閱第5圖。第5圖為根據本揭示文件一實施例的畫素電路300的電路圖。如第5圖所繪示,畫素電路300包含資料寫入電路310、發光二極體320、驅動電路330以及補償電路340。畫素電路300可控制 流經發光二極體320的驅動電流Id3的大小,進而使發光二極體320產生不同的灰階亮度。 In another embodiment, please refer to FIG. 5. FIG. 5 is a circuit diagram of a
承上述,寫入電路310電性耦接至資料線DL以及節點N1,用以接收掃描訊號SCAN[n]以及由資料線DL輸入的電流源IDATA。驅動電路330電性耦接至節點N7及N8,用以接收工作電壓VDD。發光二極體320電性耦接至驅動電路330並用以接收系統低電壓VSS。補償電路340電性耦接至寫入電路310及接地端,用以根據電流源IDATA決定資料電壓VDATA,並將資料電壓VDATA輸出至寫入電路310。 According to the above, the
寫入電路310包含電晶體T10,電晶體T10的第一端電性耦接至資料線DL,電晶體T10的第二端電性耦接至節點N7,電晶體T10的控制端電性耦接至掃描訊號SCAN[n]。寫入電路310用以根據掃描訊號SCAN[n]以及電流源IDATA決定節點N7的電壓準位。 The
驅動電路330包含電晶體T11及電容C5,電晶體T11的第一端電性耦接至節點N8,電晶體T11的第二端電性耦接至發光二極體320,電晶體T11的控制端電性耦接至節點N7。電容C5的第一端電性耦接至節點N7,電容C5的第二端電性耦接至節點N8,驅動電路330用以產生驅動電流Id3至發光二極體320。 The driving
補償電路340包含電晶體T12、電容C6以及運算放大器341,電晶體T12的第一端電性耦接至工作電壓VDD,電晶體T12的第二端電性耦接至電流源IDATA,電晶 體T4的控制端電性耦接至節點N9。電容C6的第一端電性耦接至電晶體T12的第一端,電容C6的第二端電性耦接至節點N9。運算放大器341的第一輸入端電性耦接至節點N9,運算放大器341的第二輸入端電性耦接至運算放大器341的輸出端,運算放大器341的輸出端電性耦接至資料線DL及寫入電路310,運算放大器341用以輸出資料電壓VDATA。 The
實作上,電晶體T10~T12可以用P型的低溫多晶矽薄膜電晶體來實現,但本實施例並不以此為限。例如,電晶體T10~T12也可以用P型的非晶矽(amorphous silicon)薄膜電晶體或其他型式的薄膜電晶體來實現。 In practice, the transistors T10 to T12 can be implemented with P-type low-temperature polycrystalline silicon thin film transistors, but this embodiment is not limited thereto. For example, the transistors T10 to T12 can also be implemented with P-type amorphous silicon thin-film transistors or other types of thin-film transistors.
以下將配合第5圖和第6圖來進一步說明畫素電路300的運作方式,第5圖為根據本揭示文件一實施例的畫素電路300的運作時序圖。如第6圖所示,在畫素電路300的運作過程中,工作電壓VDD工作於高準位VHIGH,掃描訊號SCAN[n]會於高準位PH和低準位PL之間切換。 The operation mode of the
於此實施例中補償電路340中電晶體T12的特性(例如,臨界電壓)與電晶體T11的特性類似,且電晶體T11和電晶體T12位於同一行,因此可以將節點N9的電壓用於對同一行的畫素電路進行補償。 In this embodiment, the characteristics (eg, critical voltage) of the transistor T12 in the
於寫入階段TP3中,源極積體電路(Source IC)提供的電流源IDATA流過電晶體T12,可以決定節點N9的電壓,節點N9的電壓可由《公式3》得知,接著將節點N9的電壓視為資料電壓VDATA。接著,運算放大器341由於虛接地(Virtual ground)的特性,會讓運算放大器341的正端及 負端的電壓值相同,而運算放大器341的負端又耦接至輸出端,因此運算放大器341會將資料電壓VDATA輸出至寫入電路310的電晶體T10,並且此時掃描訊號SCAN[n]為低準位PL,使得電晶體T10為導通狀態,資料電壓VDATA由資料線DL輸入至節點N7。《公式3》如下所示:
接著,於發光階段TP4中,掃描訊號SCAN[n]為高準位PH,使得電晶體T10轉態為關閉狀態,由於節點N7資料電壓VDATA和節點N8的工作電壓VDD的電壓差值,使得電晶體T11為導通狀態,使得電晶體T11產生的驅動電流Id3由《公式4》可得知。再者,由於假設電晶體T11的特性與電晶體T12類似,因此電晶體T11的臨界電壓|VTH11|與電晶體T12的臨界電壓|VTH12|相同,兩者可相互抵消,《公式4》如下所示:
於此實施例中,由《公式4》可知,驅動電流Id3與驅動電路330的臨界電壓無關。因此,即使顯示面板中不同區域的驅動電晶體330具有不同的特性(例如,不同 的臨界電壓),驅動電流Id3和資料源IDATA仍會維持固定的對應關係。 In this embodiment, it can be known from "Formula 4" that the driving current Id3 has nothing to do with the threshold voltage of the driving
綜上所述,本發明之畫素電路可利用外部補償電路、緩衝電路(Buffer circuit)或是加法器的電路架構,將外部補償電路產生的補償電壓傳送至畫素電路內部進行補償,解決臨界電壓變異產生的電流不均勻性,達到防止顯示面板顯示黑畫面時的閃爍現象,進而增加顯示畫面的對比度的功效。 In summary, the pixel circuit of the present invention can utilize the circuit architecture of an external compensation circuit, a buffer circuit or an adder to transmit the compensation voltage generated by the external compensation circuit to the interior of the pixel circuit for compensation to solve the criticality The current non-uniformity caused by the voltage variation can prevent the flicker phenomenon when the display panel displays a black screen, thereby increasing the contrast of the display screen.
在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件。然而,所屬技術領域中具有通常知識者應可理解,同樣的元件可能會用不同的名詞來稱呼。說明書及申請專利範圍並不以名稱的差異做為區分元件的方式,而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍所提及的「包含」為開放式的用語,故應解釋成「包含但不限定於」。另外,「耦接」在此包含任何直接及間接的連接手段。因此,若文中描述第一元件耦接於第二元件,則代表第一元件可通過電性連接或無線傳輸、光學傳輸等信號連接方式而直接地連接於第二元件,或者通過其他元件或連接手段間接地電性或信號連接至該第二元件。 Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The specification and the scope of patent application do not use the difference in names as a way to distinguish the components, but the difference in the functions of the components as the basis for distinguishing. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to." In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.
另外,除非說明書中特別指明,否則任何單數格的用語都同時包含複數格的涵義。 In addition, unless otherwise specified in the description, any singular case also includes the meaning of the plural case.
以上僅為本發明的較佳實施例,凡依本發明請求項所做的均等變化與修飾,皆應屬本發明的涵蓋範圍。 The above are only preferred embodiments of the present invention, and any equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.
100‧‧‧畫素電路 100‧‧‧Pixel circuit
110‧‧‧寫入電路 110‧‧‧ Writing circuit
120‧‧‧發光二極體 120‧‧‧ LED
130‧‧‧驅動電路 130‧‧‧Drive circuit
140‧‧‧補償電路 140‧‧‧ Compensation circuit
141‧‧‧運算放大器 141‧‧‧Operational amplifier
DL‧‧‧資料線 DL‧‧‧Data cable
VDATA‧‧‧資料電壓 V DATA ‧‧‧Data voltage
SCAN[n]‧‧‧掃描訊號 SCAN[n]‧‧‧scanning signal
N1、N2、N3‧‧‧節點 N1, N2, N3 ‧‧‧ node
VDD‧‧‧工作電壓 VDD‧‧‧Working voltage
Vref‧‧‧參考電壓 Vref‧‧‧Reference voltage
CTL‧‧‧控制訊號 CTL‧‧‧Control signal
Id1‧‧‧驅動電流 Id1‧‧‧ drive current
T1~T5‧‧‧電晶體 T1~T5‧‧‧Transistor
C1~C2‧‧‧電容 C1~C2‧‧‧Capacitance
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TW202001858A (en) | 2020-01-01 |
TW202001850A (en) | 2020-01-01 |
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