TWI685833B - Pixel circuit - Google Patents

Abstract

A pixel circuit includes a first data input circuit, a second data input circuit, a first stabilizing circuit, a second stabilizing circuit, a first compensating circuit, a second compensating circuit, a first driving circuit, a second driving circuit, a reset circuit, a first LED and, a second LED. The first data input circuit is configured to receive a first scanning signal and a data voltage. The second data input circuit is configured to receive a second scanning signal and the data voltage. The first driving circuit is coupled to a first point and the first compensating circuit, and the first driving circuit is configured to receive a reference voltage. The second driving circuit is coupled to a second point and the second compensating circuit, and the first driving circuit is configured to receive the reference voltage. The reset circuit is coupled to the first driving circuit and the second driving circuit, and the reset circuit is configured to receive a first control signal.

Description

Pixel circuit

This disclosure relates to a pixel circuit, especially a pixel circuit that can compensate for the variation of the critical voltage of the driving transistor.

Low temperature poly-silicon thin-film transistors (LTPS TFT) have the characteristics of high carrier mobility and small size, and are suitable for display panels with high resolution, narrow bezels and low power consumption. At present, excimer laser annealing (ELA) technology is widely used in the industry to form polycrystalline silicon thin films of low-temperature polycrystalline silicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polycrystalline silicon films in different regions will have differences in grain size and number. Therefore, the characteristics of the low-temperature polysilicon thin film transistor will be different in different areas of the display panel.

For example, low-temperature polysilicon thin film transistors in different regions will have different threshold voltages. Different threshold voltages will cause differences in driving currents, resulting in inconsistent luminous brightness of low-temperature polysilicon thin film transistors. In this case, the display panel will face the problem of uneven brightness of the display screen when displaying images.

The main purpose of the present invention is to provide a pixel circuit, which mainly uses two identical pixel circuits and a transistor to form a symmetrical circuit architecture, and then uses a synchronous light-emitting driving method to compensate for the critical voltage to solve the problem caused by the variation of the critical voltage The current non-uniformity achieves the effect of preventing flicker when the display panel displays a black picture.

To achieve the above purpose, this case provides a pixel circuit. The pixel circuit includes a first data writing circuit, a second data writing circuit, a first voltage stabilizing circuit, a second voltage stabilizing circuit, a first compensation circuit, a second compensation circuit, a first driving circuit, a second driving circuit , A reset circuit, a first light-emitting diode and a second light-emitting diode. The first data writing circuit is electrically coupled to the data line for receiving the first scanning signal and the data voltage. The second data writing circuit is electrically coupled to the data line for receiving the second scan signal and the data voltage. The first voltage stabilizing circuit is electrically coupled to the first data writing circuit and the first node for receiving the first reference voltage. The second voltage stabilizing circuit is electrically coupled to the second data writing circuit and the second node for receiving the reference voltage. The first compensation circuit is electrically coupled to the first node for receiving the first control signal. The second compensation circuit is electrically coupled to the second node for receiving the second control signal. The first driving circuit is electrically coupled to the first node and the first compensation circuit for receiving the reference voltage. The second driving circuit is electrically coupled to the second node and the second compensation circuit for receiving the reference voltage. The reset circuit is electrically coupled to the first driving circuit and the second driving circuit for receiving the first control signal. The first light-emitting diode is electrically coupled to the first compensation circuit, the first driving circuit, and the reset circuit, and is used to receive the light-emitting control signal. First The two light-emitting diodes are electrically coupled to the second compensation circuit, the second driving circuit, and the reset circuit, and are used to receive light-emitting control signals.

The pixel circuit of the present invention can utilize two identical pixel circuits and a transistor to form a symmetrical pixel circuit architecture, and then use the synchronous light-emitting drive method to compensate for the critical voltage, solve the current unevenness caused by the variation of the critical voltage, and prevent The effect of flicker when the display panel displays a black screen.

100‧‧‧Pixel circuit

110, 120‧‧‧ data writing circuit

130、140‧‧‧Regulatory circuit

150, 160‧‧‧ Compensation circuit

170, 180‧‧‧ drive circuit

190‧‧‧Reset circuit

OLED1, OLED2 ‧‧‧ LED

DL‧‧‧Data cable

VDATA‧‧‧Data voltage

S1[N], S1[N+1]‧‧‧Scan signal

Nodes A, E, B, F, D, H‧‧‧

ELVDD‧‧‧Reference voltage

ELVSS‧‧‧Luminous control signal

CTL1, CTL2‧‧‧Control signal

V _DDH , V _SSH , PH1‧‧‧ High level

V _DDL , V _SSL , PL1‧‧‧Low level

Id1, Id2 ‧‧‧ drive current

Vref‧‧‧Reference level

V _DATA ‧‧‧ gray level

T1~T7‧‧‧Transistor

C1~C4‧‧‧Capacitance

TP1‧‧‧Reset phase

TP2‧‧‧ compensation stage

TP3‧‧‧ Writing stage

TP4‧‧‧Lighting stage

In order to make the above and other objects, features, advantages and embodiments of the disclosed document more obvious and understandable, the drawings are described as follows: FIG. 1 is a circuit diagram of a pixel circuit according to an embodiment of the disclosed document; and 2 is an operation timing diagram of a pixel circuit according to an embodiment of the present disclosure.

The embodiments of the present invention will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

Please refer to Figure 1. FIG. 1 is a circuit diagram of a pixel circuit 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the pixel circuit 100 includes data writing circuits 110 and 120, voltage stabilizing circuits 130 and 140, compensation circuits 150 and 160, driving circuits 170 and 180, reset circuit 190, and light emitting diode OLED1 And OLED2. The pixel circuit 100 can control the size of the driving currents Id1 and Id2 flowing through the light-emitting diodes OLED1 and OLED2, thereby enabling The light-emitting diodes OLED1 and OLED2 produce the same or different gray-scale brightness.

According to the above, the data writing circuit 110 is electrically coupled to the data line DL to receive the scanning signal S1[N] and the data voltage VDATA; the data writing circuit 120 is electrically coupled to the data line DL to receive the scanning signal S1[N+1] and the data voltage VDATA. The voltage stabilizing circuit 130 is electrically coupled to the data writing circuit 110 and the node B to receive the reference voltage ELVDD; the voltage stabilizing circuit 140 is electrically coupled to the data writing circuit 120 and the node F to receive the reference voltage ELVDD. The compensation circuit 150 is electrically coupled to the node B for receiving the control signal CTL1; the compensation circuit 160 is electrically coupled to the node F for receiving the control signal CTL2. The driving circuit 170 is electrically coupled to the node B and the compensation circuit 150 to receive the reference voltage ELVDD; the driving circuit 180 is electrically coupled to the node F and the compensation circuit 160 to receive the reference voltage ELVDD. The reset circuit 190 is electrically coupled to the driving circuits 170 and 180 and used to receive the control signal CTL1; the light emitting diode OLED1 is electrically coupled to the compensation circuit 150, the driving circuit 170 and the reset circuit 190 to receive the light emitting control signal ELVSS; the light emitting diode OLED2 is electrically coupled to the compensation circuit 160, the driving circuit 180, and the reset circuit 190 for receiving the light emission control signal ELVSS.

The data writing circuit 110 includes a transistor T1, a first end of the transistor T1 is electrically coupled to the data line DL, a control end of the transistor T1 is electrically coupled to the scan signal S1[N], and the data writing circuit 110 is used The voltage level of the node A is determined according to the scan signal S1[N] and the data voltage VDATA. The data writing circuit 120 includes a transistor T2, a first end of the transistor T2 is electrically coupled to the data line DL, and a control end of the transistor T2 is electrically coupled to the scan signal S1[N+1], the data writing circuit 120 is used to determine the voltage level of the node E according to the scan signal S1[N+1] and the data voltage VDATA. In this embodiment, the scan signal S1[N+1] is the scan signal S1[N] of the adjacent row.

The voltage stabilizing circuit 130 includes capacitors C1 and C2, the first end of the capacitor C1 is electrically coupled to the second end of the transistor T1, the second end of the capacitor C1 is electrically coupled to the node B, and the first end of the capacitor C2 is electrically The second terminal of the capacitor C2 is electrically coupled to the reference voltage ELVDD. The voltage stabilizing circuit 130 is used to stabilize the voltage of the node A. The voltage stabilizing circuit 140 includes capacitors C3 and C4, the first end of the capacitor C3 is electrically coupled to the second end of the transistor T2, the second end of the capacitor C3 is electrically coupled to the node F, and the first end of the capacitor C4 is electrically It is coupled to the first end of the capacitor C3, and the second end of the capacitor C4 is electrically coupled to the reference voltage ELVDD. The voltage stabilizing circuit 140 is used to stabilize the voltage of the node E.

The compensation circuit 150 includes a transistor T3, a first end of the transistor T3 is electrically coupled to the node B, a second end of the transistor T3 is electrically coupled to the node D, and a control end of the transistor T3 is electrically coupled to the control The signal CTL1, when the control signal CTL1 is enabled, the transistor T3 is turned on so that the reference voltage ELVDD charges the node B through the transistor T3, thereby compensating the critical voltage of the driving circuit 170. The compensation circuit 160 includes a transistor T4, a first end of the transistor T4 is electrically coupled to the node F, a second end of the transistor T4 is electrically coupled to the node H, and a control end of the transistor T4 is electrically coupled to the control The signal CTL2, when the control signal CTL2 is enabled, the transistor T4 is turned on so that the reference voltage ELVDD charges the node F through the transistor T4, thereby compensating the critical voltage of the driving circuit 180.

The driving circuit 170 includes the transistor T5, the first of the transistor T5 The terminal is electrically coupled to the reference voltage ELVDD, the second terminal of the transistor T5 is electrically coupled to the node D, and the control terminal of the transistor T5 is electrically coupled to the node B for outputting the driving current Id1 to the light emitting diode OLED1. The driving circuit 180 includes a transistor T6, a first terminal of the transistor T6 is electrically coupled to the reference voltage ELVDD, a second terminal of the transistor T6 is electrically coupled to the node H, and a control terminal of the transistor T6 is electrically coupled to The node F is used to output the driving current Id2 to the light emitting diode OLED2.

The reset circuit 190 includes a first terminal of the transistor T7 electrically coupled to the node D, a second terminal of the transistor T7 electrically coupled to the node H, and a control terminal of the transistor T7 electrically coupled to the control signal CTL1. The reset circuit 190 is used to reset the voltages of the nodes B, D, and H to the low level V _DDL according to the control signal CTL1.

In practice, the transistors T1~T7 can be implemented with P-type low-temperature polycrystalline silicon thin film transistors, but this embodiment is not limited thereto. For example, the transistors T1 to T7 can also be implemented with P-type amorphous silicon thin-film transistors.

The operation mode of the pixel circuit 100 will be further described below with reference to FIGS. 1 and 2. FIG. 2 is a timing diagram of operation of the pixel circuit according to an embodiment of the present disclosure. As shown in FIG. 2, during the operation of the pixel circuit 100, the reference voltage ELVDD will be switched between the high level V _DDH and the low level V _DDL , and the light emission control signal ELVSS will be at the high level V _SSH and Switch between low level V _SSL , the data voltage VDATA will switch between the reference level Vref and the gray level V _DATA , and the scanning signals S1[N] and S1[N+1] and the control signals CTL1 and CTL2 will Switch between high level PH1 and low level PL1. Among them, the high level V _DDH , the high level V _SSH and the high level PH1 may be the same or different, and the low level V _DDL , the low level V _SSL and the low level PL1 may also be the same or different.

According to the above, in the reset phase TP1, the reference voltage ELV DD is the low level V _DDL and the light emission control signal ELVSS is the high level V _SSH so that the cathode terminal voltage of the light emitting diodes OLED1 and OLED2 is higher than the anode terminal voltage. Therefore, the light-emitting diodes OLED1 and OLED2 will be in the off state to prevent the light-emitting diodes OLED1 and OLED2 from generating unintended grayscale brightness independent of the data voltage VDATA during the reset phase TP1.

On the other hand, the scanning signal S1[N] is at the low level PL1, so that the transistor T1 is in the on state, and the voltage at the node A is the reference level Vref. The control signal CTL1 is at the low level PL1, so that the transistors T3 and T7 are turned on. The control signal CTL2 is the high level PH1, so that the transistor T4 is turned off. Therefore, during the reset phase TP1, since the node F is in a floating state and the reference voltage ELVDD transitions to the low level V _DDL , the voltage of the node F is pulled down, so that the transistor T6 operates in the linear region , Reset the voltage of nodes B, D and H to the low level V _DDL .

According to the above, in the compensation stage TP2, the light emission control signal ELVSS is maintained at the high level V _SSH to prevent the light-emitting diodes OLED1 and OLED2 from generating unintended gray-scale brightness independent of the data voltage VDATA in the compensation stage TP2. The reference voltage ELVDD transitions to the high level V _DDH , the scan signal S1[N] continues to be the low level PL1 and the scan signal S1[N+1] transitions to the low level PL1, so the transistors T1 and T2 are in the on state . The control signal CTL1 continues to be at the low level PL1, the transistors T3 and T7 continue to be in the on state, and the control signal CTL2 transitions to the low level PL1, and the transistor T4 is in the on state.

According to the above, in one embodiment, the nodes B and F are simultaneously charged in the compensation stage TP2, and in the reset stage TP1, the voltages V _B and V _{F of the} nodes B and _F are both V _DDL in the compensation stage In TP2, since the transistors T3 and T5 are in a conducting state, the node B is charged, and the voltage V _{B of the} node _B can be expressed by the following "Formula 1", where V _TH5 represents the critical voltage of the transistor T5. The charging of node F is similar to that of node B. Since transistors T4 and T6 are in the on state, node F is charged. The voltage V _{F of} node _F can be expressed by the following "Formula 1", where V _TH6 represents the transistor T6 Critical voltage. "Formula 1" is as follows: V _B =V _DDH -|V _TH5 | V _F =V _DDH -|V _TH6 | "Formula 1"

It is worth mentioning that when the pixel circuits 100 of the Nth and N+1th columns of the display panel are in the compensation stage, the other column pixel circuits 100 of the display panel (for example: N+2 and N+ Column 3) will also perform the compensation stage at the same time. In other words, each pixel circuit 100 has sufficient time to perform the operation of the compensation stage, so the variation of the compensation threshold voltage is not limited by the resolution of the panel.

According to the above, in the writing stage TP3, the light emission control signal ELVSS is maintained at the high level V _SSH , so the light emitting diodes OLED1 and OLED2 maintain the off state. The reference voltage ELVDD is maintained at the high level V _DDH , the control signal CTL1 and the control signal CTL2 are switched to the high level PH1, and the transistors T3, T4, and T7 are turned off. On the other hand, in the writing stage TP3, the transistors T1 and T2 will first switch from the on state to the off state, and then turn on sequentially to sequentially write the specific data voltage V _data corresponding to the specific gray level brightness. Therefore, the scan signal S1[N] will first switch from the high level PH1 to the low level PL1 to turn on the transistor T1 and transfer the specific data voltage V _data to the node A. Then, the scan signal S1[N] will change from The low level PL1 is switched to the high level PH1, and the transistor T1 is turned off again.

In this case, the voltage V _{A of the} node A will change from the reference level Vref to the specific gray level V _DATA , and the amount of voltage change of the node A will be transferred to the node B by the capacitive coupling effect of the capacitor C1, and Node B is in a floating state, so in the writing phase TP3, the voltage V _{B of} node B is as shown in the following "Formula 2": V _B = V _DDH -|V _TH5 |+V _DATA -V _Ref "Formula 2"

According to the above, the scan signal S1[N+1] will be switched from the high level PH1 to the low level PL1 after the scan signal S1[N] is switched to the high level to turn on the transistor T2 and convert the specific data voltage V _data Passed to the node E, similar to the above operation, the voltage V _{E of the} node E will also change from the reference level Vref to a specific gray level V _DATA , and the voltage change of the node E will be coupled by the capacitance of the capacitor C3 The effect is transferred to the node F, and the node F is in the floating state. Therefore, in the writing phase TP3, the voltage V _{F of the} node F is as shown in the following "Formula 3": V _F = V _DDH -|V _TH6 |+ V _DATA -V _Ref "Formula 3"

Next, in the light-emitting phase TP4, the light-emitting control signal ELVSS is switched from the high level V _SSH to the low level V _SSL , so that the light-emitting diodes OLED1 and OLED2 are switched from the off state to the on state. On the other hand, the control signals CTL1 and CTL2 are both high level PH1, so that the transistors T3, T4, and T7 are all in the off state. At this time, the node B voltage V _B will still have the voltage value as shown in "Formula 2", so that the driving current Id1 generated by the transistor T5 is as shown in the following "Formula 4":

According to the above, in the same light-emitting stage TP4, the node F voltage V _F will still have the voltage value as shown in "Formula 3", so that the driving current Id2 generated by the transistor T6 is as shown in the following "Formula 5":

As can be seen from "Formula 4" and "Formula 5", in the pixel circuit 100 of this embodiment, in the light-emitting stage TP4, the current magnitudes of the driving currents Id1 and Id2 are not affected by the device characteristics of the driving transistors T5 and T6 (for example: critical voltage Size), the drive currents Id1 and Idr2 and the data voltage VDATA will still maintain a fixed correspondence.

In summary, the pixel circuit of the present invention can use two identical pixel circuits and a transistor to form a symmetrical pixel circuit architecture, and then reuse The synchronous light-emitting driving method compensates for the threshold voltage, solves the current non-uniformity caused by the variation of the threshold voltage, and prevents the flicker phenomenon when the display panel displays a black screen, thereby increasing the contrast of the display screen.

Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The specification and the scope of patent application do not use the difference in names as a way to distinguish the components, but the difference in the functions of the components as the basis for distinguishing. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to." In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.

In addition, unless otherwise specified in the description, any singular case also includes the meaning of the plural case.

The above are only preferred embodiments of the present invention, and any equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

100‧‧‧Pixel circuit

110, 120‧‧‧ data writing circuit

130、140‧‧‧Regulatory circuit

150, 160‧‧‧ Compensation circuit

170, 180‧‧‧ drive circuit

190‧‧‧Reset circuit

OLED1, OLED2 ‧‧‧ LED

DL‧‧‧Data cable

VDATA‧‧‧Data voltage

S1[N], S1[N+1]‧‧‧Scan signal

Nodes A, E, B, F, D, H‧‧‧

ELVDD‧‧‧Reference voltage

ELVSS‧‧‧Luminous control signal

CTL1, CTL2‧‧‧Control signal

Id1, Id2 ‧‧‧ drive current

T1~T7‧‧‧Transistor

C1~C4‧‧‧Capacitance

Claims (14)

A pixel circuit includes: a first data writing circuit electrically coupled to a data line for receiving a first scanning signal and a data voltage; and a second data writing circuit electrically coupled to The data line is used to receive a second scanning signal and the data voltage; a first voltage stabilizing circuit is electrically coupled to the first data writing circuit and a first node to receive a reference voltage; The second voltage stabilizing circuit is electrically coupled to the second data writing circuit and a second node for receiving the reference voltage; a first compensation circuit is electrically coupled to the first node for receiving A first control signal; a second compensation circuit electrically coupled to the second node for receiving a second control signal; a first driving circuit electrically coupled to the first node and the first A compensation circuit is used to receive the reference voltage; a second driving circuit is electrically coupled to the second node and the second compensation circuit to receive the reference voltage; a reset circuit is electrically coupled to the The first driving circuit and the second driving circuit are used to receive the first control signal; a first light-emitting diode is electrically coupled to the first compensation circuit, the first driving circuit, and the reset circuit for To receive a light-emitting control signal; and a second light-emitting diode, electrically coupled to the second compensation circuit, the The second driving circuit and the reset circuit are used to receive the light-emitting control signal. The pixel circuit of claim 1, wherein the first data writing circuit includes: a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal is electrically coupled to In the data line, the control terminal is electrically coupled to the first scan signal. The pixel circuit of claim 1, wherein the second data writing circuit includes: a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal is electrically coupled to The data line, the control terminal is electrically coupled to the second scan signal. The pixel circuit of claim 1, wherein the first voltage stabilizing circuit includes: a first capacitor having a first terminal and a second terminal, the second terminal being electrically coupled to the first node; and A second capacitor has a third terminal and a fourth terminal, the third terminal is electrically coupled to the first terminal, and the fourth terminal is electrically coupled to the reference voltage. The pixel circuit according to claim 1, wherein the second voltage stabilizing circuit includes: A third capacitor has a first end and a second end, the second end is electrically coupled to the second node; and a fourth capacitor has a third end and a fourth end, the third The terminal is electrically coupled to the first terminal, and the fourth terminal is electrically coupled to the reference voltage. The pixel circuit of claim 1, wherein the first compensation circuit includes: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal is electrically coupled to the first At a node, the second terminal is electrically coupled to the first driving circuit, the reset circuit, and the first light-emitting diode, and the control terminal is electrically coupled to the first control signal. The pixel circuit of claim 1, wherein the second compensation circuit includes: a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal is electrically coupled to the first In two nodes, the second terminal is electrically coupled to the second driving circuit, the reset circuit and the second light-emitting diode, and the control terminal is electrically coupled to the second control signal. The pixel circuit of claim 1, wherein the first driving circuit comprises: a fifth transistor having a first terminal, a second terminal and a control terminal, the first terminal is electrically coupled to the reference Voltage, the second terminal is electrically coupled to the first compensation circuit, the reset circuit and the first light-emitting diode, And the control terminal is electrically coupled to the first node. The pixel circuit of claim 8, wherein the second driving circuit includes: a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal is electrically coupled to the reference Voltage, the second terminal is electrically coupled to the second compensation circuit, the reset circuit, and the second light-emitting diode, and the control terminal is electrically coupled to the second node. The pixel circuit of claim 9, wherein the reset circuit includes: a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal is electrically coupled to the first The compensation circuit, the first driving circuit and the first light-emitting diode, the second terminal is electrically coupled to the second compensation circuit, the second driving circuit and the second light-emitting diode, and the control terminal Sexually coupled to the first control signal. The pixel circuit according to claim 1, wherein the reference voltage is a first level, the light emission control signal is a fourth level, the first scanning signal and the first control signal in a first period It is a fifth level, the second scan signal and the second control signal are a sixth level, and the data voltage is a reference level. The pixel circuit according to claim 1, wherein a During the second period, the reference voltage is a second level, the light-emitting control signal is a fourth level, and the first scan signal, the second scan signal, the first control signal, and the second control signal are one The fifth level, the data voltage is a reference level. The pixel circuit according to claim 1, wherein the reference voltage is a second level, the light emission control signal is a fourth level, the first scan signal and the second scan signal in a third period It sequentially changes to a sixth level, the first control signal and the second control signal are a sixth level, and the data voltage is a gray level. The pixel circuit according to claim 1, wherein the reference voltage is a second level in a fourth period, the light emission control signal is a third level, the first scan signal and the second scan signal The first control signal and the second control signal are a sixth level, and the data voltage is a reference level.

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