TWI708230B - Display panel - Google Patents

Display panel Download PDF

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Publication number
TWI708230B
TWI708230B TW107141319A TW107141319A TWI708230B TW I708230 B TWI708230 B TW I708230B TW 107141319 A TW107141319 A TW 107141319A TW 107141319 A TW107141319 A TW 107141319A TW I708230 B TWI708230 B TW I708230B
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Taiwan
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terminal
electrically coupled
node
transistor
voltage
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TW107141319A
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Chinese (zh)
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TW202020840A (en
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林志隆
陳柏勳
陳力榮
賴柏成
鄭貿薰
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友達光電股份有限公司
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Priority to TW107141319A priority Critical patent/TWI708230B/en
Priority to CN201811596596.0A priority patent/CN109473066B/en
Publication of TW202020840A publication Critical patent/TW202020840A/en
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Publication of TWI708230B publication Critical patent/TWI708230B/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Abstract

A display panel includes a source driver, a gate driver, a plurality of pixel circuits, and a plurality of compensating circuits. The source driver is electrically coupled to a plurality of data lines. The gate driver is electrically coupled to a plurality of gate lines. The pixel circuit is electrically coupled to the data lines, the gate lines and a grounding end. The pixel circuit is configured to receive a data voltage and a source voltage, and supply a driving voltage according to a scanning signal. The compensating circuit is electrically coupled to the data lines and the grounding end. The compensating circuit is configured to receive a first control signal, a second control signal, and a reference voltage and output a compensating voltage to the pixel circuit.

Description

顯示面板 Display panel

本揭示文件有關一種顯示面板，尤指一種可補償驅動電晶體臨界電壓變異的顯示面板。 This disclosure relates to a display panel, in particular to a display panel that can compensate for the variation of the threshold voltage of the driving transistor.

低溫多晶矽薄膜電晶體(low temperature poly-silicon thin-film transistor，LTPS TFT)具有高載子遷移率與尺寸小的特點，適合應用於高解析度、窄邊框以及低耗電的顯示面板。然而，由於不同區域的矽薄膜會具有晶粒尺寸與數量的差異。因此，於顯示面板的不同區域中，薄膜電晶體的特性便會不同。 Low temperature poly-silicon thin-film transistor (LTPS TFT) has the characteristics of high carrier mobility and small size, and is suitable for high-resolution, narrow-frame and low-power display panels. However, the silicon film in different regions will have differences in the size and number of crystal grains. Therefore, in different regions of the display panel, the characteristics of the thin film transistors are different.

舉例而言，不同區域的薄膜電晶體會有著不同的臨界電壓(threshold voltage)，臨界電壓不同將會造成驅動電流產生差異，導致薄膜電晶體所驅動的顯示元件發光亮度不一致。在此情況下，顯示面板在顯示成像時將會面臨顯示畫面亮度不均勻的問題。 For example, thin film transistors in different regions have different threshold voltages, and different threshold voltages will cause differences in driving currents, resulting in inconsistent luminous brightness of display elements driven by thin film transistors. In this case, the display panel will face the problem of uneven brightness of the display screen when displaying images.

本揭示內容之主要目的係在提供一種顯示面板，其主要係利用外部補償電路或是內部補償電路，將補 償電壓傳送至畫素電路進行補償，解決臨界電壓變異產生的電流不均勻性，達到防止閃爍現象的功效。 The main purpose of this disclosure is to provide a display panel, which mainly uses an external compensation circuit or an internal compensation circuit to compensate The compensation voltage is transmitted to the pixel circuit for compensation, which solves the current unevenness caused by the variation of the critical voltage and achieves the effect of preventing flicker.

為達成上述目的，本案之第一態樣是在提供一種顯示面板。顯示面板包含源極驅動器、閘極驅動器、複數個畫素電路以及複數個補償電路。源極驅動器電性耦接至複數條資料線，閘極驅動器電性耦接至複數條閘極線。畫素電路電性耦接至資料線、閘極線及接地端，畫素電路用以接收資料電壓以及電源電壓，並根據掃描訊號提供驅動電壓。補償電路電性耦接至資料線及接地端，補償電路用以接收第一控制訊號、第二控制訊號以及參考電壓，並將補償電壓輸入至畫素電路。 To achieve the above objective, the first aspect of this case is to provide a display panel. The display panel includes a source driver, a gate driver, a plurality of pixel circuits, and a plurality of compensation circuits. The source driver is electrically coupled to a plurality of data lines, and the gate driver is electrically coupled to a plurality of gate lines. The pixel circuit is electrically coupled to the data line, the gate line and the ground terminal. The pixel circuit is used to receive the data voltage and the power supply voltage, and provide a driving voltage according to the scan signal. The compensation circuit is electrically coupled to the data line and the ground terminal. The compensation circuit is used to receive the first control signal, the second control signal and the reference voltage, and input the compensation voltage to the pixel circuit.

本案之第二態樣是在提供一種顯示面板。顯示面板包含源極驅動器、閘極驅動器以及複數個畫素電路。源極驅動器電性耦接至複數條資料線，閘極驅動器電性耦接至複數條閘極線。畫素電路電性耦接至資料線及閘極線，畫素電路包含：寫入電路電性耦接至資料線以及第一節點，用以接收掃描訊號以及資料電壓。驅動電路電性耦接至第一節點以及第二節點，用以接收電源電壓。發光二極體電性耦接至驅動電路及接地端。補償電路電性耦接至資料線及接地端，用以接收控制訊號以及參考電壓，並將補償電壓輸入至寫入電路。 The second aspect of this case is to provide a display panel. The display panel includes a source driver, a gate driver, and a plurality of pixel circuits. The source driver is electrically coupled to a plurality of data lines, and the gate driver is electrically coupled to a plurality of gate lines. The pixel circuit is electrically coupled to the data line and the gate line. The pixel circuit includes: a writing circuit is electrically coupled to the data line and the first node for receiving the scan signal and the data voltage. The driving circuit is electrically coupled to the first node and the second node for receiving the power supply voltage. The light emitting diode is electrically coupled to the driving circuit and the ground terminal. The compensation circuit is electrically coupled to the data line and the ground terminal to receive the control signal and the reference voltage, and input the compensation voltage to the writing circuit.

本揭示內容之顯示面板可利用外部補償電路或是內部補償電路，將補償電壓傳送至畫素電路進行補償，解決臨界電壓變異產生的電流不均勻性，達到防止閃爍現 象的功效。 The display panel of the present disclosure can use an external compensation circuit or an internal compensation circuit to transmit the compensation voltage to the pixel circuit for compensation, solve the current unevenness caused by the critical voltage variation, and prevent flicker. The effect of the elephant.

100、200:顯示面板 100, 200: display panel

110、210:源極驅動器 110, 210: source driver

120、220:閘極驅動器 120, 220: gate driver

130、230:畫素電路[1,1]~[n,m] 130, 230: Pixel circuit [1,1]~[n,m]

140:補償電路[1]~[m] 140: Compensation circuit [1]~[m]

234:補償電路[1,1]~[n,m] 234: Compensation circuit [1,1]~[n,m]

DL:資料線 DL: Data line

GL:閘極線 GL: Gate line

VDATA:資料電壓 V DATA : data voltage

SCAN[n]:掃描訊號 SCAN[n]: Scan signal

OLED、233:發光二極體 OLED, 233: light-emitting diode

N1、N2、N3、N4、N5、N6:節點 N1, N2, N3, N4, N5, N6: Node

VDD:工作電壓 VDD: working voltage

Vref:參考電壓 Vref: reference voltage

CTL1、CTL2、CTL:控制訊號 CTL1, CTL2, CTL: control signal

PH:高準位 PH: high level

PL:低準位 PL: Low level

Id1、Id2:驅動電流 Id1, Id2: drive current

T1~T9:電晶體 T1~T9: Transistor

C1~C4:電容 C1~C4: Capacitance

TP1:重置及補償階段 TP1: Reset and compensation stage

TP2:寫入階段 TP2: write phase

TP3:發光階段 TP3: Luminous stage

為讓揭示文件之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：第1圖為根據本揭示文件一實施例的顯示面板的電路圖；第2圖為根據本揭示文件一實施例的畫素電路及補償電路的電路圖；第3圖為根據本揭示文件一實施例的顯示面板的運作時序圖；第4圖為根據本揭示文件一實施例的顯示面板的電路圖；第5圖為根據本揭示文件一實施例的畫素電路的電路圖；以及第6圖為根據本揭示文件一實施例的顯示面板的運作時序圖。 In order to make the above and other objectives, features, advantages and embodiments of the disclosure document more comprehensible, the description of the accompanying drawings is as follows: Figure 1 is a circuit diagram of a display panel according to an embodiment of the disclosure; Figure 2 Is a circuit diagram of a pixel circuit and a compensation circuit according to an embodiment of this disclosure; FIG. 3 is an operation timing diagram of a display panel according to an embodiment of this disclosure; FIG. 4 is a display according to an embodiment of this disclosure The circuit diagram of the panel; FIG. 5 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure; and FIG. 6 is an operation timing diagram of the display panel according to an embodiment of the present disclosure.

以下將配合相關圖式來說明本揭示內容的實施例。在圖式中，相同的標號表示相同或類似的元件或方法流程。 The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

請參閱第1圖。第1圖為根據本揭示文件一實施例的顯示面板100的電路圖。如第1圖所繪示，顯示面板100 包含源極驅動器110、閘極驅動器120、m*n個畫素電路130以及m個補償電路140。m是指資料線DL的數量，n是指閘極線GL的數量，以下將以第1個補償電路140以及第[1,1]個畫素電路130為例說明顯示面板100的操作。 Please refer to Figure 1. FIG. 1 is a circuit diagram of a display panel 100 according to an embodiment of the present disclosure. As shown in Figure 1, the display panel 100 It includes a source driver 110, a gate driver 120, m*n pixel circuits 130, and m compensation circuits 140. m refers to the number of data lines DL, and n refers to the number of gate lines GL. In the following, the first compensation circuit 140 and the [1,1]th pixel circuit 130 will be used as examples to describe the operation of the display panel 100.

承上述，源極驅動器110電性耦接至複數條資料線DL，並用以透過資料線DL連接至畫素電路130及補償電路140，閘極驅動器120電性耦接至複數條閘極線GL，並用以透過閘極線GL連接至畫素電路130。畫素電路130電性耦接至資料線DL、閘極線GL及接地端，畫素電路130用以接收資料電壓VDATA以及電源電壓VDD，補償電路140電性耦接至資料線DL及接地端。 In view of the above, the source driver 110 is electrically coupled to a plurality of data lines DL and is used to connect to the pixel circuit 130 and the compensation circuit 140 through the data lines DL, and the gate driver 120 is electrically coupled to a plurality of gate lines GL , And used to connect to the pixel circuit 130 through the gate line GL. The pixel circuit 130 is electrically coupled to the data line DL, the gate line GL and the ground terminal. The pixel circuit 130 is used to receive the data voltage V DATA and the power supply voltage VDD. The compensation circuit 140 is electrically coupled to the data line DL and ground. end.

請參閱第2圖。第2圖為根據本揭示文件一實施例的畫素電路130及補償電路140的電路圖。如第2圖所示，畫素電路130用以根據掃描訊號SCAN[n]提供驅動電壓，可控制流經發光二極體的驅動電流Id1的大小，進而使發光二極體產生不同的灰階亮度。補償電路140用以接收控制訊號CTL1、控制訊號CTL2以及參考電壓Vref，並將補償電壓輸入至連接到同一條資料線DL的畫素電路130。 Please refer to Figure 2. FIG. 2 is a circuit diagram of the pixel circuit 130 and the compensation circuit 140 according to an embodiment of the present disclosure. As shown in Figure 2, the pixel circuit 130 is used to provide a driving voltage according to the scan signal SCAN[n], which can control the size of the driving current Id1 flowing through the light-emitting diode, so that the light-emitting diode generates different gray levels brightness. The compensation circuit 140 is used to receive the control signal CTL1, the control signal CTL2, and the reference voltage Vref, and input the compensation voltage to the pixel circuit 130 connected to the same data line DL.

承上述，畫素電路130包含電晶體T1及T2、電容C1以及發光二極體OLED。電晶體T1的第一端電性耦接至資料線DL，電晶體T1的第二端電性耦接至節點N1，電晶體T1的控制端電性耦接至掃描訊號SCAN[n]，電晶體T1用以根據掃描訊號SCAN[n]和資料電壓VDATA決定節點N1的電壓準位。電晶體T2的第一端電性耦接至節點N2，電晶 體T2的第二端電性耦接至發光二極體OLED，電晶體T2的控制端電性耦接至節點N1。電容C1的第一端電性耦接至節點N1，電容C1的第二端電性耦接至節點N2，電晶體T2用以產生驅動電流Id1至發光二極體OLED。 In view of the above, the pixel circuit 130 includes transistors T1 and T2, a capacitor C1, and a light emitting diode OLED. The first end of the transistor T1 is electrically coupled to the data line DL, the second end of the transistor T1 is electrically coupled to the node N1, and the control end of the transistor T1 is electrically coupled to the scan signal SCAN[n]. The crystal T1 is used to determine the voltage level of the node N1 according to the scan signal SCAN[n] and the data voltage V DATA . The first end of the transistor T2 is electrically coupled to the node N2, the second end of the transistor T2 is electrically coupled to the light emitting diode OLED, and the control end of the transistor T2 is electrically coupled to the node N1. The first terminal of the capacitor C1 is electrically coupled to the node N1, the second terminal of the capacitor C1 is electrically coupled to the node N2, and the transistor T2 is used to generate a driving current Id1 to the light emitting diode OLED.

補償電路140包含電晶體T3、T4及T5以及電容C2，電晶體T3的第一端電性耦接至資料線DL，電晶體T3的第二端電性耦接至節點N3，電晶體T3的控制端電性耦接至控制訊號CTL1。電晶體T4的第一端電性耦接至節點N3，電晶體T4的第二端電性耦接至接地端，電晶體T4的控制端電性耦接至參考電壓Vref。電晶體T5的第一端及第二端電性耦接至資料線DL，電晶體T5的控制端電性耦接至控制訊號CTL2。控制訊號CTL2用以控制電晶體T5導通或不導通，以根據電晶體T5之導通或不導通狀態來導通或斷開和電晶體T5的第一端及第二端電性耦接之資料線DL。電容C2的第一端電性耦接至節點N3，電容C2的第二端電性耦接至接地端。補償電路140用以將節點N3的電壓傳輸至畫素電路130進行電壓補償。 The compensation circuit 140 includes transistors T3, T4, and T5, and a capacitor C2. The first end of the transistor T3 is electrically coupled to the data line DL, the second end of the transistor T3 is electrically coupled to the node N3, and the second end of the transistor T3 is electrically coupled to the node N3. The control terminal is electrically coupled to the control signal CTL1. The first terminal of the transistor T4 is electrically coupled to the node N3, the second terminal of the transistor T4 is electrically coupled to the ground terminal, and the control terminal of the transistor T4 is electrically coupled to the reference voltage Vref. The first terminal and the second terminal of the transistor T5 are electrically coupled to the data line DL, and the control terminal of the transistor T5 is electrically coupled to the control signal CTL2. The control signal CTL2 is used to control the conduction or non-conduction of the transistor T5 to conduct or disconnect the data line DL electrically coupled to the first end and the second end of the transistor T5 according to the conduction or non-conduction state of the transistor T5 . The first terminal of the capacitor C2 is electrically coupled to the node N3, and the second terminal of the capacitor C2 is electrically coupled to the ground terminal. The compensation circuit 140 is used to transmit the voltage of the node N3 to the pixel circuit 130 for voltage compensation.

實作上，電晶體T1~T5可以用P型的低溫多晶矽薄膜電晶體來實現，但本實施例並不以此為限。例如，電晶體T1~T5也可以用P型的非晶矽(amorphous silicon)薄膜電晶體來實現。在一些實施方式中，也可以採用N型的薄膜電晶體來實現，本發明不限制所採用的電晶體型態。 In practice, the transistors T1 to T5 can be implemented by P-type low-temperature polysilicon thin film transistors, but this embodiment is not limited to this. For example, the transistors T1 to T5 can also be implemented by P-type amorphous silicon thin film transistors. In some embodiments, N-type thin film transistors can also be used for implementation, and the present invention does not limit the type of transistors used.

以下將配合第2圖和第3圖來進一步說明畫素電路130以及補償電路140的運作方式，第3圖為根據本揭 示文件一實施例的顯示面板100的運作時序圖。如第2圖所示，在畫素電路130及補償電路140的運作過程中，工作電壓VDD工作於高準位VHIGH(高於參考電壓Vref)，控制訊號CTL1及CTL2和掃描訊號SCAN[n]會於高準位PH和低準位PL之間切換。 The operation of the pixel circuit 130 and the compensation circuit 140 will be further described below in conjunction with FIGS. 2 and 3. FIG. 3 is an operation timing diagram of the display panel 100 according to an embodiment of the present disclosure. As shown in Figure 2, during the operation of the pixel circuit 130 and the compensation circuit 140, the working voltage VDD works at the high level V HIGH (higher than the reference voltage Vref), the control signals CTL1 and CTL2 and the scan signal SCAN[n ] Will switch between high level PH and low level PL.

於此實施例中，電晶體T4和電晶體T2位於同一行，因此可以將節點N3的電壓用於對同一行的畫素電路130進行補償。 In this embodiment, the transistor T4 and the transistor T2 are located in the same row, so the voltage of the node N3 can be used to compensate the pixel circuits 130 in the same row.

承上述，在重置及補償階段TP1中，控制訊號CTL1為低準位PL，使得電晶體T3為導通狀態，控制訊號CTL2為高準位PH，使得電晶體T5為不導通狀態。由源極驅動器110將節點N3的電壓位準重置到高準位VHIGH。接著，源極驅動器110不再給出高準位VHIGH維持節點N3的電壓，因此節點N3的電壓會透過電晶體T4將原本於高準位VHIGH的電壓放電至電壓Vref+|VTH4|，其中VTH4是電晶體T4的臨界電壓。此時，源極驅動器110會讀取節點N3的電壓Vref+|VTH4|並儲存至其內部的記憶體中。 In view of the above, in the reset and compensation phase TP1, the control signal CTL1 is at the low level PL, so that the transistor T3 is in the conducting state, and the control signal CTL2 is at the high level PH, so that the transistor T5 is in the non-conducting state. The source driver 110 resets the voltage level of the node N3 to the high level V HIGH . Then, the source driver 110 no longer provides the high level V HIGH to maintain the voltage of the node N3, so the voltage of the node N3 will discharge the voltage originally at the high level V HIGH to the voltage Vref+|V TH4 | through the transistor T4, Among them, V TH4 is the critical voltage of transistor T4. At this time, the source driver 110 reads the voltage Vref+|V TH4 | of the node N3 and stores it in its internal memory.

承上述，於寫入階段TP2中，控制訊號CTL1為高準位PH，使得電晶體T3為不導通；掃描訊號SCAN[n]由高準位PH轉態為低準位PL，使得電晶體T1為導通狀態，資料電壓VDATA由資料線DL輸入至節點N1。而控制訊號CTL2由高準位PH轉態為低準位PL，使得電晶體T5為導通狀態，源極驅動器110會將補償電壓VDATA-|VTH4|輸入至畫素電路130的節點N1。補償電壓是先將節點N3的電壓 Vref+|VTH4|中的參考電壓Vref減去，再將電晶體T4的臨界電壓|VTH4|轉換為負值，最後再加上資料電壓VDATA得到VDATA-|VTH4|。接著，於發光階段TP3中，控制訊號CTL1仍為高準位PH，使得電晶體T3為不導通；掃描訊號SCAN[n]為高準位PH，使得電晶體T1轉態為關閉狀態，由於節點N1的電壓為VDATA-|VTH4|，使得電晶體T2為導通狀態，電晶體T2產生的驅動電流Id1由《公式1》可得知。再者，由於假設電晶體T4的特性與電晶體T2類似，因此電晶體T4的臨界電壓|VTH4|與電晶體T2的臨界電壓|VTH2|相同，兩者可相互抵消，《公式1》如下所示：

Figure 107141319-A0305-02-0009-1
In view of the above, in the writing phase TP2, the control signal CTL1 is at the high level PH, making the transistor T3 non-conductive; the scan signal SCAN[n] changes from the high level PH to the low level PL, making the transistor T1 In the ON state, the data voltage V DATA is input to the node N1 from the data line DL. The control signal CTL2 transitions from the high level PH to the low level PL, so that the transistor T5 is turned on, and the source driver 110 inputs the compensation voltage V DATA -|V TH4 | to the node N1 of the pixel circuit 130. The compensation voltage is to first subtract the reference voltage Vref in the node N3 voltage Vref+|V TH4 |, then convert the threshold voltage of the transistor T4 |V TH4 | to a negative value, and finally add the data voltage V DATA to obtain V DATA -|V TH4 |. Then, in the light-emitting stage TP3, the control signal CTL1 is still at the high level PH, making the transistor T3 non-conducting; the scan signal SCAN[n] is at the high level PH, making the transistor T1 turn off. The voltage of N1 is V DATA -|V TH4 |, so that the transistor T2 is turned on, and the drive current Id1 generated by the transistor T2 can be known from "Formula 1". Furthermore, since it is assumed that the characteristics of transistor T4 are similar to those of transistor T2, the threshold voltage of transistor T4 |V TH4 | is the same as the threshold voltage of transistor T2 |V TH2 |, and the two can cancel each other out, "Formula 1" As follows:
Figure 107141319-A0305-02-0009-1

於此實施例中，由《公式1》可知，驅動電流Id1與驅動電路140的臨界電壓無關。因此，即使顯示面板中不同區域的驅動電晶體具有不同的特性(例如，不同的臨界電壓)，驅動電流Id1和資料電壓VDATA仍會維持固定的對應關係。 In this embodiment, it can be seen from "Equation 1" that the driving current Id1 has nothing to do with the threshold voltage of the driving circuit 140. Therefore, even if the driving transistors in different regions of the display panel have different characteristics (for example, different threshold voltages), the driving current Id1 and the data voltage V DATA will still maintain a fixed corresponding relationship.

於另一實施例中，請一併參閱第4圖和第5圖。第4圖為根據本揭示文件一實施例的顯示面板200的電路圖。如第4圖所繪示，顯示面板200包含源極驅動器210以及閘極驅動器220、m*n個畫素電路230。畫素電路230包含寫入電路231、驅動電路232、發光二極體233以及補償電路234。m是指資料線DL的數量，n是指閘極線GL的數 量，以下將以第1個畫素電路130為例說明顯示面板200的操作。 In another embodiment, please refer to FIG. 4 and FIG. 5 together. FIG. 4 is a circuit diagram of a display panel 200 according to an embodiment of the present disclosure. As shown in FIG. 4, the display panel 200 includes a source driver 210, a gate driver 220, and m*n pixel circuits 230. The pixel circuit 230 includes a writing circuit 231, a driving circuit 232, a light emitting diode 233, and a compensation circuit 234. m refers to the number of data lines DL, n refers to the number of gate lines GL In the following, the operation of the display panel 200 will be described by taking the first pixel circuit 130 as an example.

承上述，源極驅動器120電性耦接至複數條資料線DL，並用以透過資料線DL連接至畫素電路230及補償電路234，閘極驅動器220電性耦接至複數條閘極線GL，並用以透過閘極線GL連接至畫素電路230。畫素電路230電性耦接至資料線DL、閘極線GL及接地端，畫素電路230用以接收資料電壓VDATA以及電源電壓VDD。 In accordance with the above, the source driver 120 is electrically coupled to a plurality of data lines DL, and is used to connect to the pixel circuit 230 and the compensation circuit 234 through the data lines DL, and the gate driver 220 is electrically coupled to a plurality of gate lines GL , And used to connect to the pixel circuit 230 through the gate line GL. The pixel circuit 230 is electrically coupled to the data line DL, the gate line GL and the ground terminal, and the pixel circuit 230 is used for receiving the data voltage V DATA and the power supply voltage VDD.

請參閱第5圖。第5圖為根據本揭示文件一實施例的畫素電路230的電路圖。畫素電路230可控制流經發光二極體233的驅動電流Id2的大小，進而使發光二極體233產生不同的灰階亮度。如第5圖所示，寫入電路231電性耦接至資料線DL的其中之一以及節點N1，用以接收掃描訊號以及資料電壓VDATA。驅動電路232電性耦接至節點N4以及節點N5，用以接收電源電壓VDD。發光二極體233電性耦接至驅動電路232及接地端；補償電路234電性耦接至資料線DL的其中之一及接地端，用以接收控制訊號CTL以及參考電壓Vref，並將補償電壓輸入至寫入電路231。 Please refer to Figure 5. FIG. 5 is a circuit diagram of a pixel circuit 230 according to an embodiment of the present disclosure. The pixel circuit 230 can control the size of the driving current Id2 flowing through the light-emitting diode 233, so that the light-emitting diode 233 generates different grayscale brightness. As shown in FIG. 5, the writing circuit 231 is electrically coupled to one of the data lines DL and the node N1 for receiving the scan signal and the data voltage V DATA . The driving circuit 232 is electrically coupled to the node N4 and the node N5 for receiving the power supply voltage VDD. The light emitting diode 233 is electrically coupled to the driving circuit 232 and the ground terminal; the compensation circuit 234 is electrically coupled to one of the data lines DL and the ground terminal to receive the control signal CTL and the reference voltage Vref, and compensate The voltage is input to the writing circuit 231.

承上述，寫入電路231包含電晶體T6，電晶體T6的第一端電性耦接至資料線DL，電晶體T6的第二端電性耦接至節點N4，電晶體T6的控制端電性耦接至掃描訊號SCAN[n]。寫入電路231用以根據掃描訊號SCAN[n]以及資料電壓VDATA和補償電壓決定節點N4的電壓準位。 In view of the above, the writing circuit 231 includes a transistor T6. The first terminal of the transistor T6 is electrically coupled to the data line DL, the second terminal of the transistor T6 is electrically coupled to the node N4, and the control terminal of the transistor T6 is electrically connected. Sexually coupled to the scan signal SCAN[n]. The writing circuit 231 is used for determining the voltage level of the node N4 according to the scan signal SCAN[n], the data voltage V DATA and the compensation voltage.

承上述，驅動電路232包含電晶體T7及電容 C3，電晶體T7的第一端電性耦接至節點N5，電晶體T7的第二端電性耦接至發光二極體233，電晶體T7的控制端電性耦接至節點N4。電容C3的第一端電性耦接至節點N4，電容C3的第二端電性耦接至節點N5，驅動電路232用以產生驅動電流Id2至發光二極體233。 In view of the above, the driving circuit 232 includes a transistor T7 and a capacitor C3, the first terminal of the transistor T7 is electrically coupled to the node N5, the second terminal of the transistor T7 is electrically coupled to the light emitting diode 233, and the control terminal of the transistor T7 is electrically coupled to the node N4. The first end of the capacitor C3 is electrically coupled to the node N4, the second end of the capacitor C3 is electrically coupled to the node N5, and the driving circuit 232 is used to generate a driving current Id2 to the light emitting diode 233.

承上述，補償電路234包含電晶體T8、T9以及電容C4，電晶體T8的第一端電性耦接至資料線DL，電晶體T8的第二端電性耦接至節點N6，電晶體T8的控制端電性耦接至控制訊號CTL。電晶體T9的第一端電性耦接至節點N6，電晶體T9的第二端電性耦接至接地端，電晶體T9的控制端電性耦接至節點N6。電容C4的第一端電性耦接至節點N6，電容C4的第二端電性耦接至接地端。 In view of the above, the compensation circuit 234 includes transistors T8, T9 and a capacitor C4. The first end of the transistor T8 is electrically coupled to the data line DL, the second end of the transistor T8 is electrically coupled to the node N6, and the transistor T8 The control terminal is electrically coupled to the control signal CTL. The first terminal of the transistor T9 is electrically coupled to the node N6, the second terminal of the transistor T9 is electrically coupled to the ground terminal, and the control terminal of the transistor T9 is electrically coupled to the node N6. The first terminal of the capacitor C4 is electrically coupled to the node N6, and the second terminal of the capacitor C4 is electrically coupled to the ground terminal.

實作上，電晶體T6~T9可以用P型的低溫多晶矽薄膜電晶體來實現，但本實施例並不以此為限。例如，電晶體T6~T9也可以用P型的非晶矽(amorphous silicon)薄膜電晶體來實現。 In practice, the transistors T6 to T9 can be implemented by P-type low temperature polysilicon thin film transistors, but this embodiment is not limited to this. For example, transistors T6 to T9 can also be implemented by P-type amorphous silicon thin film transistors.

以下將配合第5圖和第6圖來進一步說明畫素電路230的運作方式，第6圖為根據本揭示文件一實施例的畫素電路230的運作時序圖。如第6圖所示，在畫素電路230的運作過程中，工作電壓VDD工作於高準位VHIGH(高於參考電壓Vref)，控制訊號CTL和掃描訊號SCAN[n]會於高準位PH和低準位PL之間切換。 Hereinafter, the operation of the pixel circuit 230 will be further described in conjunction with FIGS. 5 and 6. FIG. 6 is a timing diagram of the operation of the pixel circuit 230 according to an embodiment of the present disclosure. As shown in Figure 6, during the operation of the pixel circuit 230, the working voltage VDD works at the high level V HIGH (higher than the reference voltage Vref), and the control signal CTL and the scan signal SCAN[n] are at the high level Switch between PH and low level PL.

承上述，在重置及補償階段TP1中，控制訊號CTL為低準位PL，使得電晶體T8為導通狀態，由源極驅動 器210將節點N6的電壓位準重置到高準位VHIGH。接著，源極驅動器210不再給出高準位VHIGH維持節點N6的電壓，因此節點N6的電壓會透過電晶體T9將原本於高準位VHIGH的電壓放電至電壓Vref+|VTH9|，其中VTH9是電晶體T9的臨界電壓。此時，源極驅動器110會讀取節點N6的電壓Vref+|VTH9|並儲存至其內部的記憶體中。 In view of the above, in the reset and compensation phase TP1, the control signal CTL is at the low level PL, so that the transistor T8 is turned on, and the source driver 210 resets the voltage level of the node N6 to the high level V HIGH . Then, the source driver 210 no longer provides the high level V HIGH to maintain the voltage of the node N6, so the voltage of the node N6 will discharge the voltage originally at the high level V HIGH to the voltage Vref+|V TH9 | through the transistor T9, Among them, V TH9 is the threshold voltage of transistor T9. At this time, the source driver 110 reads the voltage Vref+|V TH9 | of the node N6 and stores it in its internal memory.

承上述，於寫入階段TP2中，掃描訊號SCAN[n]由高準位PH轉態為低準位PL，使得電晶體T6為導通狀態，源極驅動器210會將補償電壓VDATA-|VTH9|由資料線DL輸入至畫素電路230的節點N4。補償電壓是先將節點N6的電壓Vref+|VTH9|中的參考電壓Vref減去，再將電晶體T9的臨界電壓|VTH9|轉換為負值，最後再加上資料電壓VDATA得到VDATA-|VTH9|。接著，於發光階段TP3中，控制訊號CTL仍為高準位PH，使得電晶體T8為不導通；掃描訊號SCAN[n]為高準位PH，使得電晶體T6轉態為關閉狀態，由於節點N4的電壓為VDATA+|VTH9|，使得電晶體T7為導通狀態，電晶體T7產生的驅動電流Id2由《公式2》可得知。再者，由於假設電晶體T9的特性與電晶體T7類似，因此電晶體T9的臨界電壓|VTH9|與電晶體T7的臨界電壓|VTH7|相同，兩者可相互抵消，《公式2》如下所示：

Figure 107141319-A0305-02-0012-2
In view of the above, in the writing phase TP2, the scan signal SCAN[n] changes from the high level PH to the low level PL, so that the transistor T6 is turned on, and the source driver 210 will compensate the voltage V DATA -|V TH9 | Input from the data line DL to the node N4 of the pixel circuit 230. The compensation voltage is to first subtract the reference voltage Vref in the node N6 voltage Vref+|V TH9 |, then convert the threshold voltage of the transistor T9 |V TH9 | to a negative value, and finally add the data voltage V DATA to obtain V DATA -|V TH9 |. Then, in the light-emitting stage TP3, the control signal CTL is still at the high level PH, making the transistor T8 non-conducting; the scan signal SCAN[n] is at the high level PH, making the transistor T6 turn off. The voltage of N4 is V DATA +|V TH9 |, so that the transistor T7 is turned on, and the drive current Id2 generated by the transistor T7 can be known from "Equation 2". Furthermore, since it is assumed that the characteristics of the transistor T9 are similar to those of the transistor T7, the threshold voltage of the transistor T9 |V TH9 | is the same as the threshold voltage of the transistor T7 |V TH7 |, and the two can cancel each other out, "Formula 2" As follows:
Figure 107141319-A0305-02-0012-2

於此實施例中，由《公式2》可知，驅動電流 Id2與驅動電路230的臨界電壓無關。因此，即使顯示面板中不同區域的驅動電晶體230具有不同的特性(例如，不同的臨界電壓)，驅動電流Id2和資料電壓VDATA仍會維持固定的對應關係。 In this embodiment, it can be seen from "Equation 2" that the driving current Id2 has nothing to do with the threshold voltage of the driving circuit 230. Therefore, even if the driving transistors 230 in different regions of the display panel have different characteristics (for example, different threshold voltages), the driving current Id2 and the data voltage V DATA will still maintain a fixed corresponding relationship.

綜上所述，本揭示內容之畫素電路可利用外部補償電路或是內部補償電路，將補償電壓傳送至畫素電路內部進行補償，解決臨界電壓變異產生的電流不均勻性，達到防止閃爍現象，進而增加顯示畫面的對比度的功效。 In summary, the pixel circuit of the present disclosure can use an external compensation circuit or an internal compensation circuit to transmit the compensation voltage to the pixel circuit for compensation, solve the current unevenness caused by the critical voltage variation, and prevent flicker. , Thereby increasing the contrast of the display screen.

在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件。然而，所屬技術領域中具有通常知識者應可理解，同樣的元件可能會用不同的名詞來稱呼。說明書及申請專利範圍並不以名稱的差異做為區分元件的方式，而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍所提及的「包含」為開放式的用語，故應解釋成「包含但不限定於」。另外，「耦接」在此包含任何直接及間接的連接手段。因此，若文中描述第一元件耦接於第二元件，則代表第一元件可通過電性連接或無線傳輸、光學傳輸等信號連接方式而直接地連接於第二元件，或者通過其他元件或連接手段間接地電性或信號連接至該第二元件。 Certain words are used in the specification and the scope of the patent application to refer to specific elements. However, those with ordinary knowledge in the technical field should understand that the same element may be called by different terms. The specification and the scope of the patent application do not use the difference in names as a way of distinguishing elements, but the difference in function of the elements as the basis for distinguishing. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection methods, or through other elements or connections. The means is indirectly connected to the second element electrically or signally.

另外，除非說明書中特別指明，否則任何單數格的用語都同時包含複數格的涵義。 In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.

雖然本揭示內容已以實施方式揭露如上，然其並非用以限定本揭示內容，任何熟習此技藝者，在不脫離本揭示 內容之精神和範圍內，當可作各種更動與潤飾，因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。 Although the content of this disclosure has been disclosed in the above manner, it is not used to limit the content of this disclosure. Anyone who is familiar with this technique will not depart from this disclosure. Various changes and modifications can be made within the spirit and scope of the content. Therefore, the protection scope of this disclosure shall be subject to the scope of the attached patent application.

100‧‧‧顯示面板 100‧‧‧Display Panel

110‧‧‧源極驅動器 110‧‧‧Source Driver

120‧‧‧閘極驅動器 120‧‧‧Gate Driver

130‧‧‧畫素電路[1,1]~[n,m] 130‧‧‧Pixel circuit [1,1]~[n,m]

140‧‧‧補償電路[1]~[m] 140‧‧‧Compensation circuit[1]~[m]

DL‧‧‧資料線 DL‧‧‧Data line

GL‧‧‧閘極線 GL‧‧‧Gate line

Claims (8)

一種顯示面板，包含：一源極驅動器，電性耦接至複數條資料線，根據一掃描訊號提供一驅動電壓；一閘極驅動器，電性耦接至複數條閘極線；複數個畫素電路，電性耦接至該些資料線、該些閘極線及一接地端，該些畫素電路用以接收一資料電壓以及一電源電壓，並根據該掃描訊號接收該驅動電壓；以及複數個補償電路，電性耦接至該些資料線及該接地端，該些補償電路用以接收一第一控制訊號、一第二控制訊號以及一參考電壓，並將一補償電壓輸入至該些畫素電路，其中，該些補償電路包含：一第三電晶體，具有一第一端、一第二端以及一第一控制端，該第一端電性耦接至該資料線，該第二端電性耦接至一節點，該第一控制端用以接收該第一控制訊號；一第四電晶體，具有一第三端、一第四端以及一第二控制端，該第三端電性耦接至該節點，該第四端電性耦接至該接地端，該第二控制端用以接收該參考電壓；一第五電晶體，具有一第五端以及一第六端以及一第三控制端，該第五端電性耦接至該資料線，該第六端電性耦接至該資料線，該第三控制端電性耦接該第二控制訊號，該第二控制訊號控制該第五電晶體導通或不 導通，以根據該第五電晶體之該導通或該不導通狀態來導通或斷開和該第五端和該第六端電性耦接的該資料線；以及一第二電容，具有一第七端以及一第八端，該第七端電性耦接至該節點，該第八端電性耦接至該接地端。 A display panel includes: a source driver electrically coupled to a plurality of data lines and providing a driving voltage according to a scan signal; a gate driver electrically coupled to a plurality of gate lines; a plurality of pixels A circuit electrically coupled to the data lines, the gate lines and a ground terminal, the pixel circuits are used to receive a data voltage and a power supply voltage, and receive the driving voltage according to the scanning signal; and A compensation circuit is electrically coupled to the data lines and the ground terminal. The compensation circuits are used to receive a first control signal, a second control signal and a reference voltage, and input a compensation voltage to the Pixel circuit, wherein the compensation circuits include: a third transistor having a first terminal, a second terminal, and a first control terminal, the first terminal is electrically coupled to the data line, the first terminal Two terminals are electrically coupled to a node. The first control terminal is used to receive the first control signal; a fourth transistor has a third terminal, a fourth terminal, and a second control terminal. Terminal is electrically coupled to the node, the fourth terminal is electrically coupled to the ground terminal, the second control terminal is used for receiving the reference voltage; a fifth transistor has a fifth terminal and a sixth terminal And a third control terminal, the fifth terminal is electrically coupled to the data line, the sixth terminal is electrically coupled to the data line, the third control terminal is electrically coupled to the second control signal, the first The second control signal controls the fifth transistor to turn on or not Conduction to conduct or disconnect the data line electrically coupled to the fifth terminal and the sixth terminal according to the conduction or non-conduction state of the fifth transistor; and a second capacitor having a first capacitor Seven terminals and an eighth terminal, the seventh terminal is electrically coupled to the node, and the eighth terminal is electrically coupled to the ground terminal. 如請求項1的顯示面板，其中，該些畫素電路包含：一第一電晶體，具有一第一端、一第二端以及一第一控制端，該第一端電性耦接至該資料線，該第二端電性耦接至一第一節點，該第一控制端電性用以接收該掃描訊號；一第二電晶體，具有一第三端、一第四端以及一第二控制端，該第三端電性耦接至一第二節點，該第二控制端電性耦接至該第一節點；一第一電容，具有一第五端以及一第六端，該第五端電性耦接至該第一節點，該第六端電性耦接至該第二節點；以及一發光二極體，具有一第七端及一第八端，該第七端電性耦接至該第四端，該第八端電性耦接至該接地端。 The display panel of claim 1, wherein the pixel circuits include: a first transistor having a first terminal, a second terminal, and a first control terminal, the first terminal is electrically coupled to the Data line, the second terminal is electrically coupled to a first node, the first control terminal is electrically used to receive the scan signal; a second transistor has a third terminal, a fourth terminal and a first node Two control terminals, the third terminal is electrically coupled to a second node, the second control terminal is electrically coupled to the first node; a first capacitor having a fifth terminal and a sixth terminal, the The fifth terminal is electrically coupled to the first node, and the sixth terminal is electrically coupled to the second node; and a light emitting diode having a seventh terminal and an eighth terminal, the seventh terminal electrically The fourth terminal is electrically coupled to the fourth terminal, and the eighth terminal is electrically coupled to the ground terminal. 如請求項1的顯示面板，其中在一寫入階段內該第五電晶體接收到該第二控制訊號，用以將該補償 電壓輸入至該些畫素電路的其中之一，該補償電壓係根據該節點的電壓以及該資料電壓所產生。 Such as the display panel of claim 1, wherein the fifth transistor receives the second control signal in a writing phase to compensate The voltage is input to one of the pixel circuits, and the compensation voltage is generated according to the voltage of the node and the data voltage. 如請求項1的顯示面板，其中在一重置及補償階段內該第一控制訊號為一第一位準，該掃描訊號為一第四位準，該第二控制訊號為一第六位準，在一寫入階段內該第一控制訊號為一第二位準，該掃描訊號為一第三位準，該第二控制訊號為一第五位準，在一發光階段內該第一控制訊號為該第二位準，該掃描訊號為該第四位準，該第二控制訊號為該第六位準。 For example, in the display panel of claim 1, in a reset and compensation phase, the first control signal is a first level, the scan signal is a fourth level, and the second control signal is a sixth level In a writing phase, the first control signal is a second level, the scan signal is a third level, the second control signal is a fifth level, and the first control signal is a light-emitting phase The signal is the second level, the scan signal is the fourth level, and the second control signal is the sixth level. 一種顯示面板，包含：一源極驅動器，電性耦接至複數條資料線；一閘極驅動器，電性耦接至複數條閘極線；以及複數個畫素電路，電性耦接至該些資料線及該些閘極線，該些畫素電路更包含：一寫入電路，電性耦接至該些資料線以及一第一節點，用以接收一掃描訊號以及一資料電壓；一驅動電路，電性耦接至該第一節點以及一第二節點，用以接收一電源電壓；一發光二極體，電性耦接至該驅動電路及一接地端；以及一補償電路，電性耦接至該些資料線及該接地端，用以接收一控制訊號以及一參考電壓，並將一補償 電壓輸入至該寫入電路，其中該補償電路包含：一第三電晶體，具有一第一端、一第二端以及一第一控制端，該第一端電性耦接至該資料線，該第一控制端電性耦接至該控制訊號；一第四電晶體，具有一第三端、一第四端以及一第二控制端，該第三端電性耦接至該第二端，該第四端電性耦接至該接地端，該第二控制端電性耦接至該參考電壓；一第二電容，具有一第五端以及一第六端，該第五端電性耦接至該第二端及該第四端，該第六端電性耦接至該接地端。 A display panel includes: a source driver electrically coupled to a plurality of data lines; a gate driver electrically coupled to a plurality of gate lines; and a plurality of pixel circuits electrically coupled to the The data lines and the gate lines, and the pixel circuits further include: a write circuit electrically coupled to the data lines and a first node for receiving a scan signal and a data voltage; A driving circuit electrically coupled to the first node and a second node for receiving a power supply voltage; a light emitting diode electrically coupled to the driving circuit and a ground terminal; and a compensation circuit, Is coupled to the data lines and the ground terminal to receive a control signal and a reference voltage, and compensate Voltage is input to the write circuit, wherein the compensation circuit includes a third transistor having a first terminal, a second terminal and a first control terminal, the first terminal is electrically coupled to the data line, The first control terminal is electrically coupled to the control signal; a fourth transistor has a third terminal, a fourth terminal and a second control terminal, the third terminal is electrically coupled to the second terminal , The fourth terminal is electrically coupled to the ground terminal, the second control terminal is electrically coupled to the reference voltage; a second capacitor has a fifth terminal and a sixth terminal, the fifth terminal is electrically coupled Is coupled to the second terminal and the fourth terminal, and the sixth terminal is electrically coupled to the ground terminal. 如請求項5的顯示面板，其中該寫入電路包含：一第一電晶體，具有一第一端、一第二端以及一控制端，該第一端電性耦接至該資料線，該第二端電性耦接至該第一節點，該控制端電性耦接至該掃描訊號。 For example, the display panel of claim 5, wherein the writing circuit includes: a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal is electrically coupled to the data line, the The second terminal is electrically coupled to the first node, and the control terminal is electrically coupled to the scan signal. 如請求項5的顯示面板，其中，該驅動電路包含：一第二電晶體，具有一第一端、一第二端以及一控制端，該第一端電性耦接至該第二節點，該第二端電性耦接至該發光二極體，該控制端電性耦接至該第一節點；以及一第一電容，具有一第三端以及一第四端，該第三端 電性耦接至該第一節點，該第四端電性耦接至該第二節點。 The display panel of claim 5, wherein the driving circuit includes: a second transistor having a first terminal, a second terminal and a control terminal, the first terminal is electrically coupled to the second node, The second terminal is electrically coupled to the light-emitting diode, the control terminal is electrically coupled to the first node; and a first capacitor having a third terminal and a fourth terminal, the third terminal The fourth terminal is electrically coupled to the first node, and the fourth terminal is electrically coupled to the second node. 如請求項5的顯示面板，其中在一重置及補償階段內該控制訊號為一第一位準，該掃描訊號為一第四位準，在一寫入階段內該控制訊號一該第二位準，該掃描訊號為一第三位準，在一發光階段內該控制訊號為該第二位準，該掃描訊號為該第四位準。 For example, in the display panel of claim 5, in a reset and compensation phase, the control signal is a first level, the scanning signal is a fourth level, and the control signal is a second level in a writing phase. Level, the scan signal is at a third level, the control signal is at the second level in a light-emitting phase, and the scan signal is at the fourth level.
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