TWI723903B - Pixel driving circuit - Google Patents

Abstract

A pixel circuit includes a light emitting diode, a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. The first transistor is configured to provide a driving current to the light emitting diode. The light emitting diode, the second transistor, the first transistor and the third transistor are series coupled and electrically coupled between first system voltage terminal and second system voltage terminal. The capacitor electrically couple to the gate terminal of the first transistor. The fourth transistor and the fifth transistor are series coupled and electrically coupled to first terminal of the first transistor. The sixth transistor is coupled to the second terminal of the first transistor. The capacitor is configured to provide an adjustable voltage to the gate terminal of the first transistor to adjust the driving current provided to the light emitting diode.

Description

Pixel drive circuit

This case is about a pixel drive circuit, especially a pixel drive circuit for light-emitting diodes.

In current display panels, organic light-emitting diodes (OLEDs) have large-area light-emitting surfaces, and have the characteristics of being transparent and flexible. According to different driving methods, OLEDs can be divided into active driving and passive driving.

In the operation of an active OLED display panel, the driving current is affected by the threshold voltage of the driving transistor. Since the threshold voltages of the driving transistors of different display units in the active OLED display panel have certain errors, the driving currents are different. The difference in driving current makes the OLED light-emitting brightness inconsistent, resulting in uneven screen brightness when the active OLED display panel displays images.

This disclosure provides a pixel driving circuit. The pixel driving circuit includes: a light emitting diode, a first transistor, a capacitor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. the first The transistor is used to provide a driving current to the light emitting diode; the second transistor is coupled to a current path of the driving current; the third transistor is coupled to the first transistor and a first system voltage terminal Between, the third transistor is coupled to the current path of the drive current; the fourth transistor is coupled between the first terminal of the first transistor and the gate terminal of the first transistor, the fourth transistor The crystal is used to compensate a threshold voltage of the first transistor; the fifth transistor is coupled to the gate terminal of the first transistor, and the fifth transistor is used to reset the voltage of the gate terminal of the first transistor; The first end of the transistor receives a data signal, the second end of the sixth transistor is coupled to the second end of the first transistor, and the sixth transistor is used to input the data signal to the second end of the first transistor The first terminal of the capacitor is electrically coupled to the gate terminal of the first transistor. When entering a light emitting period, the pixel driving circuit changes the voltage level of the first terminal of the capacitor from a first level To a second level to adjust the size of the drive current.

In summary, the pixel driving circuit of the present disclosure compensates for the threshold voltage of the first transistor, so that the driving current flowing through the light-emitting diode is not affected by the threshold voltage. In addition, a capacitor is set and the voltage amplitude provided to the gate of the first transistor is adjusted by the capacitor to adjust the driving current flowing through the light-emitting diode, so that the brightness of the light-emitting diode can be further controlled.

The following examples are given in conjunction with the accompanying drawings for detailed description, but the examples provided are not intended to limit the scope of the disclosure, and the description of the structure and operation is not intended to limit the execution order, any recombination of components The structure and the devices produced with these functions are all covered by this disclosure. In addition, the illustrations are for illustrative purposes only, and are not drawn according to the original dimensions. To facilitate understanding, the same or similar elements in the following description will be described with the same symbols.

The terms (terms) used in the entire specification and the scope of the patent application, unless otherwise specified, usually have the usual meaning of each term used in this field, in the content disclosed here, and in the special content.

Regarding the "first", "second", "third"... etc. used in this article, they do not specifically refer to the order or sequence, nor are they used to limit this disclosure, but only to distinguish the same technology The term describes the element or operation only.

Please refer to Figure 1. FIG. 1 is a circuit structure diagram of a pixel driving circuit 100 according to an embodiment of the disclosure. As shown in Figure 1, the pixel driving circuit 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor. C1 and light-emitting diode L1.

In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, and the light emitting diode L1 are connected in series. The first transistor T1 is used to provide a driving current Id to the light emitting diode L1. The second transistor T2 is coupled to the current path of the driving current Id. The third transistor T3 is coupled between the first transistor T1 and the first system voltage terminal VSS, and the third transistor T3 is coupled to the current path of the driving current Id. The second terminal of the capacitor C1 is electrically connected to the gate terminal of the first transistor T1. When entering the light-emitting period, the pixel driving circuit 100 changes the voltage level of the first terminal of the capacitor C1 from the first level to the second level to adjust the size of the driving power.

The fourth transistor T4 and the fifth transistor T5 are connected in series and electrically connected to the first end of the first transistor T1. The fourth transistor T4 is coupled between the first terminal of the first transistor T1 and the gate terminal of the first transistor T1, and the fourth transistor T4 is used to compensate the threshold voltage Vth of the first transistor T1. The fifth transistor T5 is coupled to the gate terminal of the first transistor T1, and the fifth transistor T5 is used to reset the voltage of the gate terminal of the first transistor T1. The sixth transistor T6 is electrically connected to the second end of the first transistor T1, the first end of the sixth transistor T6 receives the data signal Vdata, and the second end of the sixth transistor T6 is coupled to the first transistor T1 At the second end, the sixth transistor T6 is used to input the data signal Vdata to the second end of the first transistor T1.

Among them, the node N1 is the connection between the capacitor C1 and the gate terminal of the first transistor T1, the node N2 is the connection between the fourth transistor T4 and the first transistor T1, and the node N3 is the sixth transistor T6 and the first transistor T1. The junction of a transistor T1.

The above-mentioned transistors respectively have a first terminal, a second terminal and a gate terminal (Gate). When the first terminal of one of the transistors is the drain terminal (source terminal), the second terminal of the transistor is the source terminal (drain terminal). In addition, the above-mentioned capacitors also have a first end and a second end respectively.

In the embodiment shown in Figure 1, the first terminal of the capacitor C1 is used to receive the fourth control signal CS, and the second terminal of the capacitor C1 is electrically connected to the gate terminal of the first transistor T1 (as shown in Figure 1 In some embodiments, the fourth control signal CS is a control signal for brightness compensation/brightness enhancement. By controlling the level of the fourth control signal CS through the coupling of the capacitor C1, the voltage of the node N1 can be adjusted Level. In some embodiments of the present disclosure, the fourth control signal CS is switched between the high level VA1 and the low level VB1, and the difference between the high level VA1 and the low level VB1 can be used to increase accordingly The gate voltage of the first transistor T1 increases the light-emitting current flowing through the first transistor T1. It should be noted that the voltage level of the high level VA1 and the low level VB1 can be adjusted according to the ambient brightness or needs The brightness enhancement ratio is dynamically changed, which will be described in further detail in subsequent embodiments.

Please continue to refer to Figure 1. The first end of the first transistor T1 is electrically connected to the second end of the second transistor T2, and the second end of the first transistor T1 is electrically connected to the first end of the third transistor T3. The first end of the second transistor T2 is electrically connected to the first end of the light emitting diode L1, and the second end of the light emitting diode L1 is electrically connected to the second system voltage terminal VDD. The second terminal of the third transistor T3 is electrically connected to the first system voltage terminal VSS. The gate terminals of the second transistor T2 and the third transistor T3 are used for receiving the third control signal EM. In some embodiments, the third control signal EM is a light emission control signal of the pixel driving circuit 100, and when the third control signal EM is at a high level, the pixel driving circuit 100 can be driven to emit light.

In addition, the first terminal of the fourth transistor T4 is electrically connected to the second terminal of the capacitor C1 and the gate terminal of the first transistor T1, and the second terminal of the fourth transistor T4 is electrically connected to the second terminal of the first transistor T1. The first end (such as node N2 in Figure 1). The gate terminal of the fourth transistor T4 is used to receive the second control signal SN. The first terminal and the gate terminal of the fifth transistor T5 are used to receive the first control signal SN-1, and the second terminal of the fifth transistor T5 is electrically connected to the second terminal of the capacitor C1 and the second terminal of the fourth transistor T4. One end and the gate terminal of the first transistor T1 (such as the node N1 in Figure 1). The first end of the sixth transistor T6 is used to receive the data signal Vdata, and the second end of the sixth transistor T6 is electrically connected to the second end of the first transistor T1 and the first end of the third transistor T3 (such as Node N3 in Figure 1). The gate terminal of the sixth transistor T6 is used to receive the second control signal SN.

For the convenience of description, the pixel driving circuit 100 shown in Figure 1 is a single-stage driving circuit for driving one column (or row) of display pixels on the display panel. In practical applications, the pixel driving circuit 100 may include multiple The above-mentioned multi-level driving circuit is used to sequentially drive the display pixels of each column (or each row), that is, the pixel driving circuit 100 may have a plurality of single-level driving circuits as shown in FIG. 1 structure. In some embodiments, the second control signal SN is the scan signal of the current stage in the pixel driving circuit 100, and the first control signal SN-1 is the scan signal of the previous stage.

In the embodiment shown in FIG. 1, the above-mentioned transistors T1 to T6 are illustrated by using N-type MOSFET (NMOS) switches as an example, but this disclosure does not Limit this. In another embodiment, those skilled in the art can replace the above-mentioned transistors T1 to T6 with P-type MOSFET (PMOS) switches, C-type metal oxide Semiconductor field-effect transistor (C-type MOSFET, CMOS) switches or other similar switching elements, and control the system voltage (for example, the second system voltage terminal VDD and the first system voltage terminal VSS) and control signals (for example, the control signal SN-1, SN, CS, EM) and the logic level of the data signal Vdata are adjusted correspondingly, and the same function as this embodiment can also be achieved.

FIG. 2A is a timing diagram of control signals and data signals of the pixel driving circuit 100 in FIG. 1 according to an embodiment. FIG. 2B is a timing diagram of control signals and data signals of the pixel driving circuit 100 in FIG. 1 according to another embodiment.

As shown in FIG. 2A, in this embodiment, a display period in the control sequence of the pixel driving circuit 100 can be divided into three periods, which are the reset period P1, the compensation and data input period P2, and the light emission period. Period P3. It should be particularly noted that the time lengths of these periods in Figure 2A are only for example, and are not intended to limit the disclosure.

In order to make the overall operation of the pixel driving circuit 100 clearer and easier to understand, please refer to FIG. 1 and FIG. 2A together below.

FIG. 3A is a circuit state diagram of the pixel driving circuit 100 in FIG. 1 during the reset period P1. As shown in FIG. 2A, during the reset period P1, the first control signal SN-1 is at a high level. The third control signal EM, the second control signal SN, and the data signal Vdata are at low levels. The fourth control signal CS is the low level VB1. Correspondingly, as shown in 3A, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are in the off state, and the first transistor T1 and the fifth transistor T5 are in the on state .

During the reset period P1, the current in the pixel driving circuit 100 flows from the first control signal SN-1 to the gate terminal of the first transistor T1 via the fifth transistor T5 and the node N1 in sequence. Since the gate terminal of the first transistor T1 is electrically connected to the second terminal of the capacitor C1, this current path also causes the second terminal of the capacitor C1 to receive the first control signal SN-1 to set the node N1 to a high level. The first terminal of the capacitor C1 is at a low level based on the fourth control signal CS, so the potential difference VD is stored between the two ends of the capacitor C1 (between the first terminal and the second terminal). In addition, the first control signal SN-1 turns on the first transistor T1, so that the potential of the node N2 is pulled to be equal to the node N3.

That is, at the end of the reset period P1. The voltage at the gate terminal (node N1) of the first transistor T1 is at a high level.

FIG. 3B is a circuit state diagram of the pixel driving circuit 100 in FIG. 1 during the compensation and data input period P2. As shown in FIG. 2A, during the compensation and data input period P2, the second control signal SN and the data signal Vdata are at a high level, and the first control signal SN-1 and the third control signal EM are at a low level. The fourth control signal CS is the low level VB1. Correspondingly, as shown in Figure 3B, the second transistor T2, the third transistor T3, and the fifth transistor T5 are in the off state, and the first transistor T1, the fourth transistor T4, and the sixth transistor T6 are in the on state. status.

During the compensation and data input period P2, the potential difference VD stored in the capacitor C1 during the reset period P1 causes the node N1 to temporarily maintain a high level, thereby maintaining the first transistor T1 in a conductive state. In addition, the potential of the aforementioned node N1 will flow to the data signal Vdata via the fourth transistor T4, the node N2, the first transistor T1, the node N3, and the sixth transistor T6 during the compensation and data input period P2, that is, the node The level of N1 will slowly discharge through the above path. The above-mentioned current path will continue until the potential difference VD stored in the capacitor C1 gradually decreases, and until the potential of the node N1 decreases to the point where the first transistor T1 cannot be turned on. Wherein, when the voltage difference between the gate electrode and the source electrode of the transistor is a threshold voltage, the transistor is in an off state. That is, when the potential of the gate terminal of the first transistor T1 drops to only a threshold voltage Vth higher than the data signal Vdata, the first transistor T1 is turned off. In this embodiment, the above-mentioned threshold voltage Vth is the threshold voltage (Vth) of the first transistor T1.

At this time, the potentials of the node N1 (the gate terminal of the first transistor T1) and the node N2 are both equal to the data signal Vdata plus a threshold voltage Vth, and the first transistor T1 will be turned off (entering an off state).

That is, at the end of the compensation and data input period P2. The voltage of the gate terminal (node N1) of the first transistor T1 is (Vdata+Vth). The voltage of the source terminal (node N3) of the first transistor T1 is Vdata.

FIG. 3C is a circuit state diagram of the pixel driving circuit 100 in FIG. 1 during the light-emitting period P3. As shown in FIG. 2A, during the light-emitting period P3, the third control signal EM is at a high level. The fourth control signal CS is the high level VA1. The first control signal SN-1, the second control signal SN, and the data signal Vdata are at low levels. Correspondingly, as shown in Figure 3C, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are in the off state, and the first transistor T1, the second transistor T2, and the third transistor T3 are in the on state. status.

In the light-emitting period P3, in the light-emitting period P3, the voltage on the node N1 is (Vdata+Vth). The third control signal EM turns on the second transistor T2 and the third transistor T3. The potential of the second terminal of the first transistor T1 drops to be consistent with the first system voltage terminal VSS, causing the voltage difference between the gate and source of the first transistor T1 to be greater than the threshold voltage Vth, and the gate terminal of the first transistor T1 passes through The capacitor C1 is pulled high by the fourth control signal Cs, so that the first transistor T1 is turned on. Therefore, the light-emitting current flows from the second system voltage terminal VDD to the first system voltage terminal VSS via the light-emitting diode L1, the second transistor T2, the first transistor T1, and the third transistor T3 in sequence.

In detail, in the reset period P1 and the compensation and data input period P2 before the light emitting period P3, the fourth control signal CS is at the low level VB1. In the light-emitting period P3, the fourth control signal CS is at the high level VA1. Therefore, when entering the light-emitting period P3, the difference between the low level VB1 and the high level VA1 of the fourth control signal CS can be transmitted to the gate terminal (node N1) of the first transistor T1 through the capacitor C1.

At this time, the voltage at the gate terminal (node N1) of the first transistor T1 is the data signal Vdata plus a threshold voltage Vth, plus the voltage between the high level VA1 and the low level VB1 of the fourth control signal CS Difference.

That is, in the light emitting period P3. The voltage of the gate terminal (node N1) of the first transistor T1 is (Vdata+Vth+VA1-VB1). The voltage of the source terminal (node N3) of the first transistor T1 is consistent with the voltage of the first system voltage terminal VSS.

During the light emitting period P3, since the current flowing through the light emitting diode L1 is equal to the current flowing through the first transistor T1, the driving current flowing through the first transistor T1 is represented by Id. Generally speaking, the driving current Id that the N-type transistor can provide will comply with the following formula: driving current Id=k(Vg-Vs-Vth) ² . In the disclosed embodiment, k is a constant related to the element characteristics of the first transistor T1.

Substituting the gate terminal voltage (Vg) and source terminal voltage (Vs) of the first transistor T1 into the formula of driving current Id, it can be calculated: Id=k(Vg-Vs-Vth) ²

Id=k[(Vdata+Vth+VA1-VB1)-0-Vth] ²

Id=k[Vdata+VA1-VB1] ²

According to the formula of the driving current Id, the driving current Id is related to the difference between the high level VA1 and the low level VB1 of the data signal Vdata and the fourth control signal CS, but is not affected by the threshold voltage Vth.

In some embodiments of the present disclosure, the high level VA1 and the low level VB1 of the fourth control signal CS are adjustable amplitude values. The voltage amplitudes of the high level VA1 and the low level VB1 of the fourth control signal CS are adjusted according to the environmental conditions to increase or decrease the voltage amplitude difference between the high level VA1 and the low level VB1. In this way, the voltage amplitude difference between the high level VA1 and the low level VB1 of the fourth control signal CS can be modulated. Therefore, according to the aforementioned formula of the driving current Id, the brightness of the light-emitting diode L1 can be adjusted. And compared with the data signal Vdata which is a DC signal, the adjustable voltage amplitude difference can more greatly adjust the brightness of the light-emitting diode L1.

Please refer to Figure 2A and Figure 2B together. As shown in Figure 2A, in an outdoor environment where the ambient light source is bright, the voltage amplitude difference between the high level VA1 and the low level VB1 of the fourth control signal CS is increased to provide the gate of the first transistor T1 The extreme voltage increases, the current flowing through the first transistor T1 increases, and the brightness of the light-emitting diode L1 increases. As shown in Figure 2B, in a room where the ambient light source is dark, the gate of the first transistor T1 is provided by reducing the voltage amplitude difference between the high level VA2 and the low level VB2 of the fourth control signal CS The extreme voltage decreases and flows through the first transistor T1 The current decreases, and the brightness of the light-emitting diode L1 decreases. In this way, the brightness of the light-emitting diode L1 can be controlled according to the environmental state.

For example, when it is judged that the ambient light source is bright, the pixel driving circuit 100 shown in FIG. 2A can adjust the adjustable voltage amplitude between the low level VB1 and the high level VA1 of the fourth control signal CS The difference is set from 0V to 8V; when it is judged that the ambient light source is dark, as shown in Figure 2B, the pixel driving circuit 100 can adjust the high level VA1 and the low level VB2 of the fourth control signal CS. The voltage amplitude difference is set to 0V to 4V. In this way, when the ambient light source is bright, the gate of the first transistor T1 can be raised to a higher level.

FIG. 4 is a circuit structure diagram of the pixel driving circuit 200 according to an embodiment of the disclosure. In the embodiment shown in Figure 4, the pixel driving circuit 200 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor. Crystal T6, capacitor C1 and light emitting diode L1. Compared with the pixel driving circuit 100 in the embodiment of FIG. 1, the difference of the pixel driving circuit 200 in the embodiment of FIG. 4 is that the second end of the light emitting diode L1 receives the third control signal EM, and also That is, in this embodiment, the second terminal of the light emitting diode L1 is not connected to the second system voltage terminal VDD, but is instead connected to the third control signal EM.

Please refer to Figure 4 and Figure 2A together. During the reset period P1 and the compensation and data input period P2, since the second transistor T2 and the fourth transistor T4 are both turned off, no current flows through the light emitting diode L1. During the light-emitting period P3, when a driving current Id is generated to pass through the light-emitting diode L1, the third control signal EM has been switched to a high level, which is similar in function to the second The system voltage terminal VDD can be used to drive the second terminal of the light-emitting diode L1 with the third control signal EM at the high level during the light-emitting period P3. The other detailed connection relationships and operation modes of the pixel driving circuit 200 are substantially the same as those of the pixel driving circuit 100 in the previous embodiment in FIG. 1, and will not be described here.

FIG. 5 is a circuit structure diagram of the pixel driving circuit 300 according to an embodiment of the disclosure. FIG. 6 is a circuit structure diagram of the pixel driving circuit 400 according to an embodiment of the disclosure. Fig. 7 is a timing chart of control signals and data signals of the pixel driving circuit in Figs. 5 and 6.

In the embodiment shown in FIG. 5, the pixel driving circuit 300 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor. Crystal T6, capacitor C1 and light emitting diode L1. Compared with the pixel driving circuit 100 in the embodiment in FIG. 1, the pixel driving circuit 300 in the embodiment in FIG. 5 is different in that the first end of the capacitor C1 is used to receive the third control signal EM. That is, in this embodiment, the capacitor C1 does not receive the fourth control signal CS, but instead receives the third control signal EM. More specifically, the gate terminal of the second transistor T2, the gate terminal of the third transistor T3, and the capacitor C1 all receive the third control signal EM.

Please refer to Figure 5 and Figure 7 together. During the reset period P1 and the compensation and data input period P2, since the second transistor T2 is turned off, no current flows through the light emitting diode L1. During the light-emitting period P3, the third control signal EM is switched to a high level. In this embodiment, the third control signal EM is functionally similar to the fourth control signal CS, and the third high level can be used. The control signal EM raises the voltage of the gate terminal of the first transistor T1 through the capacitor C1. The other detailed connection relationships and operation modes of the pixel driving circuit 300 are substantially the same as those of the pixel driving circuit 100 in the previous embodiment in FIG. 1, and will not be described here.

In the embodiment shown in FIG. 6, the pixel driving circuit 400 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor. Crystal T6, capacitor C1 and light emitting diode L1. Compared with the pixel driving circuit 100 in the embodiment of FIG. 1, the pixel driving circuit 400 in the embodiment of FIG. 5 is different in that the first end of the capacitor C1 is used to receive the third control signal EM and emit light The second end of the diode L1 receives the third control signal EM, that is, the first end of the capacitor C1 in this embodiment does not receive the fourth control signal CS, but instead receives the third control signal EM. Moreover, the second terminal of the light emitting diode L1 is not connected to the second system voltage terminal VDD, but is instead connected to the third control signal EM. More specifically, the gate terminal of the second transistor T2, the gate terminal of the third transistor T3, the second terminal of the light emitting diode L1, and the capacitor C1 all receive the third control signal EM.

In this embodiment, please refer to FIG. 6 and FIG. 7 together. During the reset period P1 and the compensation and data input period P2, since the second transistor T2 and the fourth transistor T4 are both turned off, no current flows through the light emitting diode L1. During the light-emitting period P3, when the driving current Id is generated to pass through the light-emitting diode L1, the third control signal EM has been switched to a high level. The third control signal EM at the high level in the light-emitting period P3 can be used to pull up the first voltage. The voltage at the gate terminal of the crystal T1 and the second terminal of the driving light-emitting diode L1. Regarding other detailed connection relationships and operation modes of the pixel driving circuit 400, they are substantially the same as those of the pixel driving circuit 100 in the previous embodiment in FIG. 1, and will not be described here.

Because the capacitor C1 in FIG. 5 and FIG. 6 both receive the third control signal EM, instead of the fourth control signal CS. Therefore, the timing diagram in Figure 7 is compared with the timing diagram in Figure 2A. The difference is that there is no fourth control signal CS. The other signal timings of the timing diagram in the embodiment in FIG. 7 are substantially the same as the timing diagram in the embodiment in FIG. 2A, and will not be repeated here.

In summary, the pixel driving circuit of the present disclosure compensates the threshold voltage Vth of the first transistor T1, so that the current flowing through the light-emitting diode L1 is not affected by the variation of the threshold voltage Vth. In addition, the capacitor C1 is set and the voltage amplitude provided to the gate of the first transistor T1 is adjusted by the capacitor C1 to adjust the driving current Id flowing through the light-emitting diode L1, so that the brightness of the light-emitting diode L1 can be further improved Regulation.

Although this disclosure has been disclosed in the above implementation manner, it is not intended to limit this disclosure. Anyone with general knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection disclosed shall be subject to the scope of the attached patent application.

In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the attached symbols is as follows:

100, 200, 300, 400: pixel drive circuit

L1: Light-emitting diode

C1: Capacitance

T1: The first transistor

T2: second transistor

T3: third transistor

T4: The fourth transistor

T5: fifth transistor

T6: sixth transistor

Vdata: data signal

VSS: The first system voltage terminal

VDD: the second system voltage terminal

SN-1: The first control signal

EM: Third control signal

SN: Second control signal

CS: Fourth control signal

N1, N2, N3: Node

P1: During reset

P2: Compensation and data input period

P3: During light emission

Id: drive current

In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more comprehensible, the description of the accompanying drawings is as follows: Figure 1 is a circuit structure diagram of a pixel driving circuit of an embodiment of the present disclosure. FIG. 2A is a timing diagram of control signals and data signals of the pixel driving circuit in FIG. 1 according to an embodiment. FIG. 2B is a timing diagram of control signals and data signals of the pixel driving circuit in FIG. 1 according to another embodiment. FIG. 3A is a circuit state diagram of the pixel driving circuit in FIG. 1 during the reset period. FIG. 3B is a circuit state diagram of the pixel driving circuit in FIG. 1 during the compensation and data input period. FIG. 3C is a circuit state diagram of the pixel driving circuit in FIG. 1 during the light-emitting period. FIG. 4 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure. FIG. 5 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure. FIG. 6 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the disclosure. Fig. 7 is a timing chart of control signals and data signals of the pixel driving circuit in Figs. 5 and 6.

Domestic deposit information (please note in the order of deposit institution, date and number) no Foreign hosting information (please note in the order of hosting country, institution, date, and number) no

100: Pixel drive circuit

L1: Light-emitting diode

C1: Capacitance

T1: The first transistor

T2: The second transistor

T3: third transistor

T4: The fourth transistor

T5: fifth transistor

T6: sixth transistor

Vdata: data signal

VSS: The first system voltage terminal

VDD: the second system voltage terminal

SN-1: The first control signal

SN: Second control signal

EM: Third control signal

CS: Fourth control signal

N1, N2, N3: Node

Claims (10)

A pixel driving circuit, comprising: a light emitting diode; a first transistor for providing a driving current to the light emitting diode; a second transistor coupled to a current path of the driving current ; A third transistor, coupled between the first transistor and a first system voltage terminal, coupled to the current path of the drive current; a fourth transistor, coupled to the first transistor Between the first terminal of the crystal and the gate terminal of the first transistor, it is used to compensate a threshold voltage of the first transistor; a fifth transistor is coupled to the gate terminal of the first transistor for resetting Set the voltage of the gate terminal of the first transistor; a sixth transistor, the first terminal of which receives a data signal, and the second terminal is coupled to the second terminal of the first transistor for inputting the data signal to The second terminal of the first transistor; and a capacitor, the first terminal of which is electrically coupled to the gate terminal of the first transistor. When entering a light-emitting period, the pixel driving circuit turns the capacitor on its first terminal The voltage level of is changed from a first level to a second level to adjust the magnitude of the driving current. The pixel driving circuit according to claim 1, wherein: the first terminal of the fifth transistor is used to receive a first control signal, and the second terminal of the fifth transistor is coupled to the gate of the first transistor Extreme, the The gate terminal of the fifth transistor is used to receive the first control signal; and during a reset period of one of the pixel driving circuits, the first control signal is at a high level, causing the fifth transistor to be turned on, so that the first The control signal is input to the gate terminal of the first transistor. The pixel driving circuit according to claim 1, wherein: the first terminal of the fourth transistor is coupled to the gate terminal of the first transistor, and the second terminal of the fourth transistor is coupled to the first transistor The first terminal of the fourth transistor is used for receiving a second control signal; the first terminal of the sixth transistor is used for receiving the data signal, and the second terminal of the sixth transistor is coupled to the The second terminal of the first transistor, and the gate terminal of the sixth transistor for receiving the second control signal; and during a compensation and data input period of the pixel driving circuit, the second control signal and the data signal At a high level, the sixth transistor and the fourth transistor are turned on, and the voltage of the gate terminal of the first transistor is continuously discharged through the fourth transistor until the first transistor is turned off. The pixel driving circuit according to claim 1, wherein: the first terminal of the light-emitting diode is coupled to the first terminal of the second transistor; the second terminal of the second transistor is coupled to the first transistor The first end of the crystal and the gate end of the second transistor are used to receive a third control signal; the first end of the third transistor is coupled to the second end of the first transistor, and the second end of the third transistor is The second terminal is coupled to the first system voltage terminal, and the gate terminal of the third transistor is used for receiving the third control signal; The first terminal of the capacitor is used to receive a fourth control signal, and the second terminal of the capacitor is coupled to the gate terminal of the first transistor; when the light-emitting period of the pixel driving circuit is entered, the fourth control signal From the first level to the second level, the level of the gate terminal of the first transistor is correspondingly changed to adjust the magnitude of the driving current; and during the light-emitting period of the pixel driving circuit, the second The three control signals are at a high level, which causes the second transistor and the third transistor to be turned on, so that the driving current flows through the light emitting diode. The pixel driving circuit according to claim 4, wherein the second terminal of the light emitting diode is coupled to a second system voltage terminal. The pixel driving circuit according to claim 4, wherein the second end of the light emitting diode is used to receive the third control signal. The pixel driving circuit according to claim 4, wherein the fourth control signal has an adjustable voltage amplitude difference, and the fourth control signal is adjusted and provided to the light emitting device through the adjustable voltage amplitude difference The driving current of the diode. The pixel driving circuit according to claim 7, wherein the magnitude of the adjustable voltage amplitude difference is positively correlated with the intensity of an ambient light source. The pixel driving circuit according to claim 1, wherein: the first terminal of the light-emitting diode is coupled to the first terminal of the second transistor; the second terminal of the second transistor is coupled to the first transistor The first end of the crystal and the gate end of the second transistor are used to receive a third control signal; the first end of the third transistor is coupled to the second end of the first transistor, and the second end of the third transistor is The second terminal is coupled to the first system voltage terminal, the gate terminal of the third transistor is used to receive the third control signal; the first terminal of the capacitor is used to receive the third control signal, and the second terminal of the capacitor Is coupled to the gate terminal of the first transistor; when entering the light-emitting period of the pixel driving circuit, the third control signal changes from the first level to the second level, so that the first transistor is The level of the gate terminal is changed accordingly to adjust the magnitude of the driving current; and during the light-emitting period of the pixel driving circuit, the third control signal is at a high level, causing the second transistor and the third transistor to be turned on , So that the driving current flows through the light-emitting diode. The pixel driving circuit according to claim 9, wherein the second terminal of the light emitting diode is coupled to a second system voltage terminal or used to receive the third control signal.

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