WO2020252913A1 - Pixel drive circuit and display panel - Google Patents

Pixel drive circuit and display panel Download PDF

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Publication number
WO2020252913A1
WO2020252913A1 PCT/CN2019/102970 CN2019102970W WO2020252913A1 WO 2020252913 A1 WO2020252913 A1 WO 2020252913A1 CN 2019102970 W CN2019102970 W CN 2019102970W WO 2020252913 A1 WO2020252913 A1 WO 2020252913A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
control signal
node
potential
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Application number
PCT/CN2019/102970
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French (fr)
Chinese (zh)
Inventor
聂诚磊
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020252913A1 publication Critical patent/WO2020252913A1/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • OLED(Organic Light Emitting Diode (Organic Light Emitting Diode) display panels have the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, etc., and have been widely used in the field of high-performance displays.
  • the pixels are arranged in a matrix with multiple rows and multiple columns.
  • Each pixel is usually composed of two transistors and one capacitor, commonly known as 2T1C circuit.
  • the transistor has the problem of threshold voltage drift.
  • OLED pixel drive circuit needs corresponding compensation structure.
  • the compensation structure of the OLED pixel drive circuit is relatively complicated, which occupies a lot of area when designing the layout, which is not conducive to the design of high PPI (Pixels Per Inch, pixel density) display panels; in addition, the compensation structure of the existing OLED pixel drive circuit compensates It takes a long time.
  • the purpose of the embodiments of the present application is to provide a pixel drive circuit and a display panel, which can solve the technical problems that the compensation structure of the existing pixel drive circuit is relatively complicated, takes up a lot of area when designing the layout, and requires a long time for compensation. .
  • An embodiment of the application provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage;
  • the threshold voltage of the third transistor is greater than or equal to the threshold voltage of the first transistor; the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage;
  • the data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  • the first control signal is a high potential
  • the second control signal is a high potential
  • the data signal is the reference potential
  • the first control signal in the threshold voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
  • the first control signal in the data voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the display potential.
  • the first control signal in the light-emitting phase, is at a low potential, the second control signal is at a low potential, and the data signal is at a low potential.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon Thin film transistors.
  • An embodiment of the present application also provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage;
  • the data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  • the first control signal is a high potential
  • the second control signal is a high potential
  • the data signal is the reference potential
  • the first control signal in the threshold voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
  • the first control signal in the data voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the display potential.
  • the first control signal in the light-emitting phase, is at a low potential, the second control signal is at a low potential, and the data signal is at a low potential.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon Thin film transistors.
  • the threshold voltage of the third transistor is greater than or equal to the threshold voltage of the first transistor.
  • the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
  • An embodiment of the present application also provides a display panel, which includes a pixel drive circuit, and the pixel drive circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage;
  • the data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  • the first control signal is a high potential
  • the second control signal is a high potential
  • the data signal is the reference potential
  • the first control signal in the threshold voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel, and the time required for compensation is relatively short.
  • the compensation of the pixel drive circuit The structure is relatively simple, so it does not need to take up a lot of area when designing.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the initial stage of the driving timing shown in FIG. 2;
  • FIG. 4 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage acquisition phase under the driving sequence shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the data voltage acquisition phase under the driving timing shown in FIG. 2;
  • FIG. 6 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase under the driving timing shown in FIG. 2.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit provided by the embodiment of the present application includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a capacitor C, and a light emitting device OLED.
  • the light emitting device OLED may be an organic light emitting diode. That is, the embodiment of the present application adopts a pixel driving circuit with a 4T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, and uses fewer components, has a simple and stable structure, and saves costs.
  • the first transistor T1 in the pixel driving circuit is a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the first node G
  • the source of the first transistor T1 is electrically connected to the first power supply voltage VDD
  • the drain of the first transistor T1 is electrically connected to the second node S .
  • the gate of the second transistor T2 is electrically connected to the first control signal WR
  • the source of the second transistor T2 is electrically connected to the data signal D
  • the drain of the second transistor T2 is electrically connected to the first node G.
  • the gate and source of the third transistor T3 are electrically connected to the first node G
  • the drain of the third transistor T3 is electrically connected to the source of the fourth transistor T4.
  • the gate of the fourth transistor T4 is electrically connected to the second control signal RD, and the drain of the fourth transistor T4 is electrically connected to the second node S.
  • the first end of the capacitor C is electrically connected to the first node G, and the second end of the capacitor C is electrically connected to the second node S.
  • the anode terminal of the light emitting device OLED is electrically connected to the second node S, and the cathode terminal of the light emitting device OLED is electrically connected to the second power supply voltage Vss.
  • both the first power supply voltage VDD and the second power supply voltage Vss are used to output a predetermined voltage value.
  • the output voltage value of the first power supply voltage VDD is greater than the output voltage value of the second power supply voltage Vss.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 2 is a timing diagram of the pixel driving circuit provided by an embodiment of the application.
  • the combination of the first control signal WR, the second control signal RD, and the data signal D corresponds to the initial stage t1, the threshold voltage acquisition stage t2, the data voltage acquisition stage t3, and the light-emitting stage t4.
  • the data signal D includes a reference potential V REF and a display potential V DATA . It can be understood that the potential value of the reference potential V REF is greater than the threshold voltage of the third transistor T3, and the potential value of the reference potential V REF is less than the potential value of the display potential V DATA .
  • the first control signal WR is at a high potential
  • the second control signal RD is at a high potential
  • the data signal D is the reference potential V REF .
  • the first control signal WR is at a high level
  • the second control signal RD is at a low level
  • the data signal D is at the reference potential V REF .
  • the first control signal WR is at a high level
  • the second control signal RD is at a low level
  • the data signal D is at the display level V DATA .
  • the first control signal WR is at a low level
  • the second control signal RD is at a low level
  • the data signal D is at a low level
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the initial stage t1 under the driving timing shown in FIG. 2.
  • the first control signal WR is at a high potential
  • the second control signal RD is at a high potential
  • both the second transistor T2 and the fourth transistor T4 are turned on.
  • the data signal D to the reference potential V REF, the data signal D via the reference voltage V REF through the second transistor T2 output node G i.e., the reference potential V REF through the second transistor T2 output data signal D
  • the first end of capacitor C the first control signal WR is at a high potential
  • the second control signal RD is at a high potential
  • both the second transistor T2 and the fourth transistor T4 are turned on.
  • the third transistor T3 since the gate and drain of the third transistor T3 are short-circuited, and the reference potential V REF of the data signal D is greater than the threshold voltage V th_T3 of the third transistor T3, the third transistor T3 is turned on.
  • the reference potential V REF of the data signal D is output to the second node S through the third transistor T3 and the fourth transistor T4, that is, the reference potential V REF of the data signal D is output to the capacitor C through the third transistor T3 and the fourth transistor T4 The second end.
  • the threshold voltage V th_T3 of the third transistor T3 is greater than or equal to the threshold voltage V th_T1 of the first transistor T1, at this time, the first transistor T1 is turned on.
  • FIG. 4 is a schematic diagram of the path of the threshold voltage obtaining stage t2 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal WR is at a high potential
  • the second control signal RD is at a low potential
  • the second transistor T2 is turned on
  • the fourth transistor T4 is turned off.
  • the data signal D remains the reference potential V REF, the data signal D via the reference voltage V REF through the second transistor T2 output node G, i.e., the reference potential of the data signal D V REF through the second transistor T2 Output to the first end of capacitor C.
  • the potential of the first node G remains unchanged at the initial stage t1.
  • the capacitor C is discharged through the first transistor T1 until the voltage difference between the gate and the drain of the first transistor T1 is equal to the threshold voltage of the first transistor T1.
  • the transistor T1 is turned off, so that the threshold voltage of the first transistor T1 can be obtained. It should be noted that, since the difference between the threshold voltage V th_T3 of the third transistor T3 and the threshold voltage V th_T1 of the first transistor T1 is small, the threshold voltage V th_T1 of the first transistor T1 can be quickly obtained, thereby shortening the compensation cost . The time required.
  • FIG. 5 is a schematic diagram of the data voltage acquisition phase t3 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal WR is at a high level
  • the second control signal RD is at a low level
  • the second transistor T2 is turned on
  • the fourth transistor T4 is turned off.
  • the data voltage V DATA signal D the potential of V DATA display data signal D is output through the second transistor T2 is displayed to the first node G, i.e., the potential of V DATA display data signal D is output through the second transistor T2 To the first end of capacitor C.
  • the potential of the first node G jumps from the reference potential V REF to the display potential V DATA , and due to the capacitance C coupling effect of the capacitor C, the potential of the second node S also changes accordingly.
  • FIG. 6 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting stage t4 under the driving timing shown in FIG. 2.
  • the first control signal WR is at a low potential
  • the second control signal RD is at a low potential
  • the second transistor T2 is turned off
  • the fourth transistor T4 is turned off. Due to the storage effect of the capacitor C, the potential of the first node G still maintains the potential of the first node G during the data voltage acquisition phase t3, and the potential of the second node S still maintains the potential of the second node S during the data voltage acquisition phase t3.
  • I OLED 1/2Cox( ⁇ W/L)(V gs -V th_T1 ) 2 , where I OLED is the current flowing through the light-emitting device OLED, ⁇ is the carrier mobility of the first transistor T1, W and L are respectively The width and length of the channel of the first transistor T1, Vgs is the voltage difference between the first node G and the second node S. In the embodiment of the present application, the voltage difference between the gate and the drain of the first transistor T1 is equal to the voltage difference between the first node G and the second node S.
  • I OLED 1/2Cox( ⁇ W/L) ⁇ C oled (V DATA -V REF )/(C oled +C) ⁇ 2
  • the current of the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1, and the compensation function is realized.
  • the light emitting device OLED emits light, and the current flowing through the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1.
  • the embodiment of the application itself also provides a display panel, which includes the above-mentioned pixel driving circuit.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • the pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel, and the time required for compensation is relatively short.
  • the compensation of the pixel drive circuit The structure is relatively simple, so it does not need to take up a lot of area when designing.

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  • Computer Hardware Design (AREA)
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Abstract

The pixel drive circuit and display panel provided by the embodiments of the present application use a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel, and the time required for compensation is relatively short, the compensation structure of the pixel drive circuit is relatively simple, and thus it does not need to occupy a large area during design.

Description

像素驱动电路及显示面板Pixel driving circuit and display panel 技术领域Technical field
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
背景技术Background technique
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。其中，在OLED显示器面板中，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个晶体管与一个电容构成，俗称2T1C电路，但晶体管存在阈值电压漂移的问题，因此，OLED像素驱动电路需要相应的补偿结构。目前，OLED像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积，不利于高PPI(Pixels Per Inch，像素密度)显示面板的设计；另外，现有的OLED像素驱动电路的补偿结构补偿所需的时间较长。OLED(Organic Light Emitting Diode (Organic Light Emitting Diode) display panels have the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, etc., and have been widely used in the field of high-performance displays. Among them, in the OLED display panel, the pixels are arranged in a matrix with multiple rows and multiple columns. Each pixel is usually composed of two transistors and one capacitor, commonly known as 2T1C circuit. However, the transistor has the problem of threshold voltage drift. , OLED pixel drive circuit needs corresponding compensation structure. At present, the compensation structure of the OLED pixel drive circuit is relatively complicated, which occupies a lot of area when designing the layout, which is not conducive to the design of high PPI (Pixels Per Inch, pixel density) display panels; in addition, the compensation structure of the existing OLED pixel drive circuit compensates It takes a long time.
技术问题technical problem
本申请实施例的目的在于提供一种像素驱动电路及显示面板，能够解决现有的像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积，且补偿所需的时间较长的技术问题。The purpose of the embodiments of the present application is to provide a pixel drive circuit and a display panel, which can solve the technical problems that the compensation structure of the existing pixel drive circuit is relatively complicated, takes up a lot of area when designing the layout, and requires a long time for compensation. .
技术解决方案Technical solutions
本申请实施例提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；An embodiment of the application provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；The gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；The gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
所述第三晶体管的栅极以及源极均电性连接于所述第一节点，所述第三晶体管的漏极与所述第四晶体管的源极电性连接；The gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的漏极电性连接于所述第二节点；The gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；A first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压；The anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage;
所述第三晶体管的阈值电压大于或等于所述第一晶体管的阈值电压；所述第一电源电压的电压值大于所述第二电源电压的电压值。The threshold voltage of the third transistor is greater than or equal to the threshold voltage of the first transistor; the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
在本申请所述的像素驱动电路中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于初始阶段、阈值电压获取阶段，数据电压获取阶段以及发光阶段；所述数据信号包括参考电位以及显示电位，所述参考电位大于所述第三晶体管的阈值电压，且所述参考电位小于所述显示电位。In the pixel driving circuit of the present application, the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage; The data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
在本申请所述的像素驱动电路中，在所述初始阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考电位。In the pixel driving circuit of the present application, in the initial stage, the first control signal is a high potential, the second control signal is a high potential, and the data signal is the reference potential.
在本申请所述的像素驱动电路中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述参考电位。In the pixel driving circuit of the present application, in the threshold voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
在本申请所述的像素驱动电路中，在所述数据电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述显示电位。In the pixel driving circuit of the present application, in the data voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the display potential.
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述数据信号为低电位。In the pixel driving circuit of the present application, in the light-emitting phase, the first control signal is at a low potential, the second control signal is at a low potential, and the data signal is at a low potential.
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。In the pixel driving circuit of the present application, the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon Thin film transistors.
本申请实施例还提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；An embodiment of the present application also provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；The gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；The gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
所述第三晶体管的栅极以及源极均电性连接于所述第一节点，所述第三晶体管的漏极与所述第四晶体管的源极电性连接；The gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的漏极电性连接于所述第二节点；The gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；A first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压。The anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
在本申请所述的像素驱动电路中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于初始阶段、阈值电压获取阶段，数据电压获取阶段以及发光阶段；所述数据信号包括参考电位以及显示电位，所述参考电位大于所述第三晶体管的阈值电压，且所述参考电位小于所述显示电位。In the pixel driving circuit of the present application, the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage; The data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
在本申请所述的像素驱动电路中，在所述初始阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考电位。In the pixel driving circuit of the present application, in the initial stage, the first control signal is a high potential, the second control signal is a high potential, and the data signal is the reference potential.
在本申请所述的像素驱动电路中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述参考电位。In the pixel driving circuit of the present application, in the threshold voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
在本申请所述的像素驱动电路中，在所述数据电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述显示电位。In the pixel driving circuit of the present application, in the data voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the display potential.
在本申请所述的像素驱动电路中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述数据信号为低电位。In the pixel driving circuit of the present application, in the light-emitting phase, the first control signal is at a low potential, the second control signal is at a low potential, and the data signal is at a low potential.
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。In the pixel driving circuit of the present application, the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon Thin film transistors.
在本申请所述的像素驱动电路中，所述第三晶体管的阈值电压大于或等于所述第一晶体管的阈值电压。In the pixel driving circuit described in the present application, the threshold voltage of the third transistor is greater than or equal to the threshold voltage of the first transistor.
在本申请所述的像素驱动电路中，所述第一电源电压的电压值大于所述第二电源电压的电压值。In the pixel driving circuit described in the present application, the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
本申请实施例还提供一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；An embodiment of the present application also provides a display panel, which includes a pixel drive circuit, and the pixel drive circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；The gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；The gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
所述第三晶体管的栅极以及源极均电性连接于所述第一节点，所述第三晶体管的漏极与所述第四晶体管的源极电性连接；The gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的漏极电性连接于所述第二节点；The gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；A first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压。The anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
在本申请所述的显示面板中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于初始阶段、阈值电压获取阶段，数据电压获取阶段以及发光阶段；所述数据信号包括参考电位以及显示电位，所述参考电位大于所述第三晶体管的阈值电压，且所述参考电位小于所述显示电位。In the display panel of the present application, the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage; The data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
在本申请所述的显示面板中，在所述初始阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考电位。In the display panel described in the present application, in the initial stage, the first control signal is a high potential, the second control signal is a high potential, and the data signal is the reference potential.
在本申请所述的显示面板中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述参考电位。In the display panel of the present application, in the threshold voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
有益效果Beneficial effect
本申请实施例提供的像素驱动电路及显示面板，采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，且补偿所需的时间较短，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。The pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel, and the time required for compensation is relatively short. The compensation of the pixel drive circuit The structure is relatively simple, so it does not need to take up a lot of area when designing.
附图说明Description of the drawings
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
图1为本申请实施例提供的像素驱动电路的结构示意图；FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application;
图2为本申请实施例提供的像素驱动电路的时序图；FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application;
图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的初始阶段的通路示意图；3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the initial stage of the driving timing shown in FIG. 2;
图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压获取阶段的通路示意图；4 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage acquisition phase under the driving sequence shown in FIG. 2;
图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据电压获取阶段的通路示意图；以及FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the data voltage acquisition phase under the driving timing shown in FIG. 2; and
图6为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。FIG. 6 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase under the driving timing shown in FIG. 2.
本发明的实施方式Embodiments of the invention
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of this application.
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。The transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
请参阅图1，图1为本申请实施例提供的像素驱动电路的结构示意图。如图1所示，本申请实施例提供的像素驱动电路，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、电容C以及发光器件OLED。发光器件OLED可以为有机发光二极管。也即，本申请实施例采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，用了较少的元器件，结构简单稳定，节约了成本。该像素驱动电路中的第一晶体管T1为驱动晶体管。Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application. As shown in FIG. 1, the pixel driving circuit provided by the embodiment of the present application includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a capacitor C, and a light emitting device OLED. The light emitting device OLED may be an organic light emitting diode. That is, the embodiment of the present application adopts a pixel driving circuit with a 4T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, and uses fewer components, has a simple and stable structure, and saves costs. The first transistor T1 in the pixel driving circuit is a driving transistor.
其中，第一晶体管T1的栅极电性连接于第一节点G，第一晶体管T1的源极电性连接于第一电源电压VDD，第一晶体管T1的漏极电性连接于第二节点S。第二晶体管T2的栅极电性连接于第一控制信号WR，第二晶体管T2的源极电性连接于数据信号D，第二晶体管T2的漏极电性连接于第一节点G。第三晶体管T3的栅极以及源极均电性连接于第一节点G，第三晶体管T3的漏极与第四晶体管T4的源极电性连接。第四晶体管T4的栅极电性连接于第二控制信号RD，第四晶体管T4的漏极电性连接于第二节点S。电容C的第一端电性连接于第一节点G，电容C的第二端电性连接于第二节点S。发光器件OLED的阳极端电性连接于第二节点S，发光器件OLED的阴极端电性连接于第二电源电压Vss。Wherein, the gate of the first transistor T1 is electrically connected to the first node G, the source of the first transistor T1 is electrically connected to the first power supply voltage VDD, and the drain of the first transistor T1 is electrically connected to the second node S . The gate of the second transistor T2 is electrically connected to the first control signal WR, the source of the second transistor T2 is electrically connected to the data signal D, and the drain of the second transistor T2 is electrically connected to the first node G. The gate and source of the third transistor T3 are electrically connected to the first node G, and the drain of the third transistor T3 is electrically connected to the source of the fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the second control signal RD, and the drain of the fourth transistor T4 is electrically connected to the second node S. The first end of the capacitor C is electrically connected to the first node G, and the second end of the capacitor C is electrically connected to the second node S. The anode terminal of the light emitting device OLED is electrically connected to the second node S, and the cathode terminal of the light emitting device OLED is electrically connected to the second power supply voltage Vss.
在一些实施例中，第一电源电压VDD和第二电源电压Vss均用于输出一预设电压值。此外，在本申请实施例中，第一电源电压VDD的输出的电压值大于第二电源电压Vss输出的电压值。In some embodiments, both the first power supply voltage VDD and the second power supply voltage Vss are used to output a predetermined voltage value. In addition, in the embodiment of the present application, the output voltage value of the first power supply voltage VDD is greater than the output voltage value of the second power supply voltage Vss.
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors. The transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
请参阅图2，图2为本申请实施例提供的像素驱动电路的时序图。如图2所示，第一控制信号WR、第二控制信号RD、数据信号D相组合先后对应于初始阶段t1、阈值电压获取阶段t2，数据电压获取阶段t3以及发光阶段t4。数据信号D包括参考电位V REF以及显示电位V DATA。可以理解的，参考电位V REF的电位值大于第三晶体管T3的阈值电压，且参考电位V REF的电位值小于显示电位V DATA的电位值。 Please refer to FIG. 2. FIG. 2 is a timing diagram of the pixel driving circuit provided by an embodiment of the application. As shown in FIG. 2, the combination of the first control signal WR, the second control signal RD, and the data signal D corresponds to the initial stage t1, the threshold voltage acquisition stage t2, the data voltage acquisition stage t3, and the light-emitting stage t4. The data signal D includes a reference potential V REF and a display potential V DATA . It can be understood that the potential value of the reference potential V REF is greater than the threshold voltage of the third transistor T3, and the potential value of the reference potential V REF is less than the potential value of the display potential V DATA .
在一些实施例中，在初始阶段t1，第一控制信号WR为高电位，第二控制信号RD为高电位，数据信号D为所述参考电位V REF。 In some embodiments, in the initial stage t1, the first control signal WR is at a high potential, the second control signal RD is at a high potential, and the data signal D is the reference potential V REF .
在一些实施例中，在阈值电压获取阶段t2，第一控制信号WR为高电位，第二控制信号RD为低电位，数据信号D为参考电位V REF。 In some embodiments, in the threshold voltage acquisition phase t2, the first control signal WR is at a high level, the second control signal RD is at a low level, and the data signal D is at the reference potential V REF .
在一些实施例中，在数据电压获取阶段t3，第一控制信号WR为高电位，第二控制信号RD为低电位，数据信号D为显示电位V DATA。 In some embodiments, in the data voltage acquisition phase t3, the first control signal WR is at a high level, the second control signal RD is at a low level, and the data signal D is at the display level V DATA .
在一些实施例中，在发光阶段t4，第一控制信号WR为低电位，第二控制信号RD为低电位，数据信号D为低电位。In some embodiments, during the light-emitting period t4, the first control signal WR is at a low level, the second control signal RD is at a low level, and the data signal D is at a low level.
具体的，请参阅图3，图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的初始阶段t1的通路示意图。首先，结合图2、图3所示，在初始阶段t1，第一控制信号WR为高电位，第二控制信号RD为高电位，第二晶体管T2以及第四晶体管T4均打开。与此同时，数据信号D为参考电位V REF，数据信号D的参考电位V REF经第二晶体管T2输出至第一节点G，也即，数据信号D的参考电位V REF经第二晶体管T2输出至电容C的第一端。另外，由于第三晶体管T3的栅极与漏极短接，且数据信号D的参考电位V REF大于第三晶体管T3的阈值电压V th_T3，使得第三晶体管T3打开。数据信号D的参考电位V REF经第三晶体管T3以及第四晶体管T4输出至第二节点S，也即，数据信号D的参考电位V REF经第三晶体管T3以及第四晶体管T4输出至电容C的第二端。另外，由于第三晶体管T3的阈值电压V th_T3大于或等于第一晶体管T1的阈值电压V th_T1，此时，第一晶体管T1打开。 Specifically, please refer to FIG. 3. FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the initial stage t1 under the driving timing shown in FIG. 2. First, as shown in FIG. 2 and FIG. 3, in the initial stage t1, the first control signal WR is at a high potential, the second control signal RD is at a high potential, and both the second transistor T2 and the fourth transistor T4 are turned on. At the same time, the data signal D to the reference potential V REF, the data signal D via the reference voltage V REF through the second transistor T2 output node G, i.e., the reference potential V REF through the second transistor T2 output data signal D To the first end of capacitor C. In addition, since the gate and drain of the third transistor T3 are short-circuited, and the reference potential V REF of the data signal D is greater than the threshold voltage V th_T3 of the third transistor T3, the third transistor T3 is turned on. The reference potential V REF of the data signal D is output to the second node S through the third transistor T3 and the fourth transistor T4, that is, the reference potential V REF of the data signal D is output to the capacitor C through the third transistor T3 and the fourth transistor T4 The second end. In addition, since the threshold voltage V th_T3 of the third transistor T3 is greater than or equal to the threshold voltage V th_T1 of the first transistor T1, at this time, the first transistor T1 is turned on.
在该初始阶段t1，第一节点G的电位和第二节点S的电位可以根据以下公式进行设置：V g=V REF，V s=V REF-V th_T3，其中，V g为第一节点G的电位，V s为第二节点S的电位。 In this initial stage t1, the potential of the first node G and the potential of the second node S can be set according to the following formula: V g =V REF , V s =V REF -V th_T3 , where V g is the first node G V s is the potential of the second node S.
接着，请参阅图4，图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压获取阶段t2的通路示意图。结合图2、图4所示，在阈值电业获取阶段，第一控制信号WR为高电位，第二控制信号RD为低电位，第二晶体管T2打开，第四晶体管T4关闭。与此同时，数据信号D仍为参考电位V REF，数据信号D的参考电位V REF经第二晶体管T2输出至第一节点G，也即，数据信号D的参考电位V REF经第二晶体管T2输出至电容C的第一端。此时，第一节点G的电位仍保持初始阶段t1时第一节点G的电位不变。另外，由于在初始阶段t1时第一晶体管T1打开，电容C此时通过第一晶体管T1放电直至第一晶体管T1的栅极与漏极的压差等于第一晶体管T1的阈值电压时，第一晶体管T1关闭，从而可以获取第一晶体管T1的阈值电压。需要说明的是，由于第三晶体管T3的阈值电压V th_T3与第一晶体管T1的阈值电压V th_T1的差值较小，因此可以快速获取第一晶体管T1的阈值电压V th_T1，从而可以缩短补偿所需的时间。 Next, please refer to FIG. 4. FIG. 4 is a schematic diagram of the path of the threshold voltage obtaining stage t2 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2. As shown in FIG. 2 and FIG. 4, in the threshold voltage acquisition stage, the first control signal WR is at a high potential, the second control signal RD is at a low potential, the second transistor T2 is turned on, and the fourth transistor T4 is turned off. At the same time, the data signal D remains the reference potential V REF, the data signal D via the reference voltage V REF through the second transistor T2 output node G, i.e., the reference potential of the data signal D V REF through the second transistor T2 Output to the first end of capacitor C. At this time, the potential of the first node G remains unchanged at the initial stage t1. In addition, since the first transistor T1 is turned on at the initial stage t1, the capacitor C is discharged through the first transistor T1 until the voltage difference between the gate and the drain of the first transistor T1 is equal to the threshold voltage of the first transistor T1. The transistor T1 is turned off, so that the threshold voltage of the first transistor T1 can be obtained. It should be noted that, since the difference between the threshold voltage V th_T3 of the third transistor T3 and the threshold voltage V th_T1 of the first transistor T1 is small, the threshold voltage V th_T1 of the first transistor T1 can be quickly obtained, thereby shortening the compensation cost . The time required.
在该阈值电压获取阶段t2，第一节点G的电位和第二节点S的电位可以根据以下公式进行设置：V g=V REF，V s=V REF-V th_T1，其中，V g为第一节点G的电位，V s为第二节点S的电位。 In the threshold voltage acquisition phase t2, the potential of the first node G and the potential of the second node S can be set according to the following formula: V g =V REF , V s =V REF -V th_T1 , where V g is the first The potential of the node G, and V s is the potential of the second node S.
随后，请参阅图5，图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据电压获取阶段t3的通路示意图。结合图2、图5所示，第一控制信号WR为高电位，第二控制信号RD为低电位，第二晶体管T2打开，第四晶体管T4关闭。与此同时，数据信号D为显示电位V DATA，数据信号D的显示电位V DATA经第二晶体管T2输出至第一节点G，也即，数据信号D的显示电位V DATA经第二晶体管T2输出至电容C的第一端。第一节点G的电位由参考电位V REF跳变至显示电位V DATA，由于电容C的电容C耦合效应，第二节点S的电位也相应变化。 Subsequently, please refer to FIG. 5. FIG. 5 is a schematic diagram of the data voltage acquisition phase t3 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2. As shown in FIGS. 2 and 5, the first control signal WR is at a high level, the second control signal RD is at a low level, the second transistor T2 is turned on, and the fourth transistor T4 is turned off. At the same time, the data voltage V DATA signal D, the potential of V DATA display data signal D is output through the second transistor T2 is displayed to the first node G, i.e., the potential of V DATA display data signal D is output through the second transistor T2 To the first end of capacitor C. The potential of the first node G jumps from the reference potential V REF to the display potential V DATA , and due to the capacitance C coupling effect of the capacitor C, the potential of the second node S also changes accordingly.
在该数据电压获取阶段t3，第一节点G的电位和第二节点S的电位可以根据以下公式进行设置：V g=V DATA，V s=V REF-V th_T1+C oled（V DATA-V REF）/（C oled+C），其中，V g为第一节点G的电位，V s为第二节点S的电位，C oled为发光器件OLED的电容C值。 In the data voltage acquisition phase t3, the potential of the first node G and the potential of the second node S can be set according to the following formula: V g =V DATA , V s =V REF -V th_T1 +C oled (V DATA -V REF )/(C oled +C), where V g is the potential of the first node G, V s is the potential of the second node S, and Coed is the capacitance C value of the light-emitting device OLED.
最后，请参阅图6，图6为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段t4的通路示意图。结合图2、图6所示，第一控制信号WR为低电位，第二控制信号RD为低电位，第二晶体管T2关闭，第四晶体管T4关闭。由于电容C的存储作用，第一节点G的电位仍保持数据电压获取阶段t3时第一节点G的电位，第二节点S的电位仍保持数据电压获取阶段t3时第二节点S的电位。Finally, please refer to FIG. 6, which is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting stage t4 under the driving timing shown in FIG. 2. As shown in FIGS. 2 and 6, the first control signal WR is at a low potential, the second control signal RD is at a low potential, the second transistor T2 is turned off, and the fourth transistor T4 is turned off. Due to the storage effect of the capacitor C, the potential of the first node G still maintains the potential of the first node G during the data voltage acquisition phase t3, and the potential of the second node S still maintains the potential of the second node S during the data voltage acquisition phase t3.
在该发光阶段t4，第一节点G与第二节点S之间的压差可根据以下公式获得：V gs=V g-Vs=V th_T1-C oled（V DATA-V REF）/（C oled+C），其中，V g为第一节点G的电位，V s为第二节点S的电位，C oled为发光器件OLED的电容C值。 In this light-emitting stage t4, the voltage difference between the first node G and the second node S can be obtained according to the following formula: V gs =V g -Vs=V th_T1 -C oled (V DATA -V REF )/(C oled +C), where V g is the potential of the first node G, V s is the potential of the second node S, and Coed is the capacitance C value of the light-emitting device OLED.
进一步地，计算流经发光器件OLED的电流的公式为：Further, the formula for calculating the current flowing through the light-emitting device OLED is:
I OLED＝1/2Cox(μW/L)(V gs－V th_T1) 2，其中I OLED为流经发光器件OLED的电流，μ为第一晶体管T1的载流子迁移率，W和L分别为第一晶体管T1的沟道的宽度和长度，Vgs为第一节点G与第二节点S之间的压差。在本申请实施例中，第一晶体管T1的栅极与漏极之间的压差等于第一节点G与第二节点S之间的压差。将第一节点G与第二节点S之间的压差V gs=V th_T1-C oled（V DATA-V REF）/（C oled+C）代入上式，即有： I OLED = 1/2Cox(μW/L)(V gs －V th_T1 ) 2 , where I OLED is the current flowing through the light-emitting device OLED, μ is the carrier mobility of the first transistor T1, W and L are respectively The width and length of the channel of the first transistor T1, Vgs is the voltage difference between the first node G and the second node S. In the embodiment of the present application, the voltage difference between the gate and the drain of the first transistor T1 is equal to the voltage difference between the first node G and the second node S. Substituting the voltage difference between the first node G and the second node S V gs =V th_T1 -C oled (V DATA -V REF )/(C oled +C) into the above formula, we have:
I OLED＝1/2Cox(μW/L)【C oled（V DATA-V REF）/（C oled+C）】 2 I OLED ＝1/2Cox(μW/L)【C oled (V DATA -V REF )/(C oled +C)】 2
由此可见，发光器件OLED的电流与第一晶体管T1的阈值电压无关，实现了补偿功能，发光器件OLED发光，且流经发光器件OLED的电流与第一晶体管T1的阈值电压无关。It can be seen that the current of the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1, and the compensation function is realized. The light emitting device OLED emits light, and the current flowing through the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1.
本身申请实施例还提供一种显示面板，其包括以上所述的像素驱动电路，具体可参照以上对该像素驱动电路的描述，在此不做赘述。The embodiment of the application itself also provides a display panel, which includes the above-mentioned pixel driving circuit. For details, please refer to the above description of the pixel driving circuit, which will not be repeated here.
本申请实施例提供的像素驱动电路及显示面板，采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，且补偿所需的时间较短，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。The pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel, and the time required for compensation is relatively short. The compensation of the pixel drive circuit The structure is relatively simple, so it does not need to take up a lot of area when designing.
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。The above are only the embodiments of the present invention and do not limit the scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the description and drawings of the present invention, or directly or indirectly applied to other related technical fields, The same principles are included in the scope of patent protection of the present invention.

Claims (20)

  1. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；A pixel driving circuit, which includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；The gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；The gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
    所述第三晶体管的栅极以及源极均电性连接于所述第一节点，所述第三晶体管的漏极与所述第四晶体管的源极电性连接；The gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的漏极电性连接于所述第二节点；The gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
    所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；A first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压；The anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage;
    所述第三晶体管的阈值电压大于或等于所述第一晶体管的阈值电压；所述第一电源电压的电压值大于所述第二电源电压的电压值。The threshold voltage of the third transistor is greater than or equal to the threshold voltage of the first transistor; the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于初始阶段、阈值电压获取阶段，数据电压获取阶段以及发光阶段；所述数据信号包括参考电位以及显示电位，所述参考电位大于所述第三晶体管的阈值电压，且所述参考电位小于所述显示电位。The pixel driving circuit according to claim 1, wherein the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light emission Stage; the data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  3. 根据权利要求2所述的像素驱动电路，其中，在所述初始阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考电位。3. The pixel driving circuit according to claim 2, wherein, in the initial stage, the first control signal is a high potential, the second control signal is a high potential, and the data signal is the reference potential.
  4. 根据权利要求2所述的像素驱动电路，其中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述参考电位。2. The pixel driving circuit according to claim 2, wherein, in the threshold voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the reference potential .
  5. 根据权利要求2所述的像素驱动电路，其中，在所述数据电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述显示电位。2. The pixel driving circuit according to claim 2, wherein, in the data voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the display potential .
  6. 根据权利要求2所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述数据信号为低电位。3. The pixel driving circuit according to claim 2, wherein in the light-emitting phase, the first control signal is at a low potential, the second control signal is at a low potential, and the data signal is at a low potential.
  7. 根据权利要求1所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。The pixel driving circuit according to claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or non- Crystalline silicon thin film transistors.
  8. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；A pixel driving circuit, which includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；The gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；The gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
    所述第三晶体管的栅极以及源极均电性连接于所述第一节点，所述第三晶体管的漏极与所述第四晶体管的源极电性连接；The gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的漏极电性连接于所述第二节点；The gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
    所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；A first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压。The anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
  9. 根据权利要求8所述的像素驱动电路，其中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于初始阶段、阈值电压获取阶段，数据电压获取阶段以及发光阶段；所述数据信号包括参考电位以及显示电位，所述参考电位大于所述第三晶体管的阈值电压，且所述参考电位小于所述显示电位。8. The pixel driving circuit according to claim 8, wherein the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light emission Stage; the data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  10. 根据权利要求9所述的像素驱动电路，其中，在所述初始阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考电位。9. The pixel driving circuit according to claim 9, wherein in the initial stage, the first control signal is a high potential, the second control signal is a high potential, and the data signal is the reference potential.
  11. 根据权利要求9所述的像素驱动电路，其中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述参考电位。9. The pixel driving circuit according to claim 9, wherein, in the threshold voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the reference potential .
  12. 根据权利要求9所述的像素驱动电路，其中，在所述数据电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述显示电位。9. The pixel driving circuit according to claim 9, wherein, in the data voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the display potential .
  13. 根据权利要求9所述的像素驱动电路，其中，在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述数据信号为低电位。9. The pixel driving circuit according to claim 9, wherein in the light-emitting phase, the first control signal is at a low potential, the second control signal is at a low potential, and the data signal is at a low potential.
  14. 根据权利要求8所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。The pixel driving circuit according to claim 8, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or non- Crystalline silicon thin film transistor.
  15. 根据权利要求8所述的像素驱动电路，其中，所述第三晶体管的阈值电压大于或等于所述第一晶体管的阈值电压。8. The pixel driving circuit according to claim 8, wherein the threshold voltage of the third transistor is greater than or equal to the threshold voltage of the first transistor.
  16. 根据权利要求8所述的像素驱动电路，其中，所述第一电源电压的电压值大于所述第二电源电压的电压值。8. The pixel driving circuit according to claim 8, wherein the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
  17. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、电容以及发光器件；A display panel includes a pixel drive circuit, the pixel drive circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第一电源电压，所述第一晶体管的漏极电性连接于第二节点；The gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
    所述第二晶体管的栅极电性连接于第一控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第一节点；The gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
    所述第三晶体管的栅极以及源极均电性连接于所述第一节点，所述第三晶体管的漏极与所述第四晶体管的源极电性连接；The gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
    所述第四晶体管的栅极电性连接于第二控制信号，所述第四晶体管的漏极电性连接于所述第二节点；The gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
    所述电容的第一端电性连接于所述第一节点，所述电容的第二端电性连接于所述第二节点；A first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
    所述发光器件的阳极端电性连接于所述第二节点，所述发光器件的阴极端电性连接于第二电源电压。The anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
  18. 根据权利要求17所述的显示面板，其中，所述第一控制信号、所述第二控制信号、所述数据信号相组合先后对应于初始阶段、阈值电压获取阶段，数据电压获取阶段以及发光阶段；所述数据信号包括参考电位以及显示电位，所述参考电位大于所述第三晶体管的阈值电压，且所述参考电位小于所述显示电位。17. The display panel of claim 17, wherein the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage The data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  19. 根据权利要求18所述的显示面板，其中，在所述初始阶段，所述第一控制信号为高电位，所述第二控制信号为高电位，所述数据信号为所述参考电位。18. The display panel of claim 18, wherein, in the initial stage, the first control signal is a high potential, the second control signal is a high potential, and the data signal is the reference potential.
  20. 根据权利要求18所述的显示面板，其中，在所述阈值电压获取阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号为所述参考电位。18. The display panel of claim 18, wherein, in the threshold voltage acquisition phase, the first control signal is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
PCT/CN2019/102970 2019-06-20 2019-08-28 Pixel drive circuit and display panel WO2020252913A1 (en)

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Publication number Priority date Publication date Assignee Title
CN110827754B (en) * 2019-11-04 2021-05-11 Oppo广东移动通信有限公司 Compensating circuit of OLED (organic light emitting diode) driving circuit and display
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100013806A1 (en) * 2008-07-21 2010-01-21 Samsung Mobile Display Co.Ltd. Pixel and organic light emitting display device using the same
US8791889B2 (en) * 2008-11-26 2014-07-29 Samsung Display Co., Ltd. Pixel and organic light emitting display device using the same
CN104637443A (en) * 2013-11-14 2015-05-20 乐金显示有限公司 Organic light-emitting display device and driving method thereof
CN104835452A (en) * 2015-05-28 2015-08-12 京东方科技集团股份有限公司 Pixel circuit and driving method and related devices thereof
CN106920518A (en) * 2015-12-25 2017-07-04 昆山工研院新型平板显示技术中心有限公司 Image element circuit and its driving method and active matrix/organic light emitting display

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290027B (en) * 2010-06-21 2013-10-30 北京大学深圳研究生院 Pixel circuit and display device
CN104778917B (en) * 2015-01-30 2017-12-19 京东方科技集团股份有限公司 Pixel-driving circuit and its driving method and display device
CN105185300B (en) * 2015-08-03 2017-07-28 深圳市华星光电技术有限公司 AMOLED pixel-driving circuits and image element driving method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100013806A1 (en) * 2008-07-21 2010-01-21 Samsung Mobile Display Co.Ltd. Pixel and organic light emitting display device using the same
US8791889B2 (en) * 2008-11-26 2014-07-29 Samsung Display Co., Ltd. Pixel and organic light emitting display device using the same
CN104637443A (en) * 2013-11-14 2015-05-20 乐金显示有限公司 Organic light-emitting display device and driving method thereof
CN104835452A (en) * 2015-05-28 2015-08-12 京东方科技集团股份有限公司 Pixel circuit and driving method and related devices thereof
CN106920518A (en) * 2015-12-25 2017-07-04 昆山工研院新型平板显示技术中心有限公司 Image element circuit and its driving method and active matrix/organic light emitting display

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