WO2020252913A1 - Circuit d'attaque de pixel et panneau d'affichage - Google Patents

Circuit d'attaque de pixel et panneau d'affichage Download PDF

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Publication number
WO2020252913A1
WO2020252913A1 PCT/CN2019/102970 CN2019102970W WO2020252913A1 WO 2020252913 A1 WO2020252913 A1 WO 2020252913A1 CN 2019102970 W CN2019102970 W CN 2019102970W WO 2020252913 A1 WO2020252913 A1 WO 2020252913A1
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Prior art keywords
transistor
electrically connected
control signal
node
potential
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PCT/CN2019/102970
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English (en)
Chinese (zh)
Inventor
聂诚磊
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020252913A1 publication Critical patent/WO2020252913A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • OLED(Organic Light Emitting Diode (Organic Light Emitting Diode) display panels have the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, etc., and have been widely used in the field of high-performance displays.
  • the pixels are arranged in a matrix with multiple rows and multiple columns.
  • Each pixel is usually composed of two transistors and one capacitor, commonly known as 2T1C circuit.
  • the transistor has the problem of threshold voltage drift.
  • OLED pixel drive circuit needs corresponding compensation structure.
  • the compensation structure of the OLED pixel drive circuit is relatively complicated, which occupies a lot of area when designing the layout, which is not conducive to the design of high PPI (Pixels Per Inch, pixel density) display panels; in addition, the compensation structure of the existing OLED pixel drive circuit compensates It takes a long time.
  • the purpose of the embodiments of the present application is to provide a pixel drive circuit and a display panel, which can solve the technical problems that the compensation structure of the existing pixel drive circuit is relatively complicated, takes up a lot of area when designing the layout, and requires a long time for compensation. .
  • An embodiment of the application provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage;
  • the threshold voltage of the third transistor is greater than or equal to the threshold voltage of the first transistor; the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage;
  • the data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  • the first control signal is a high potential
  • the second control signal is a high potential
  • the data signal is the reference potential
  • the first control signal in the threshold voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
  • the first control signal in the data voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the display potential.
  • the first control signal in the light-emitting phase, is at a low potential, the second control signal is at a low potential, and the data signal is at a low potential.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon Thin film transistors.
  • An embodiment of the present application also provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage;
  • the data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  • the first control signal is a high potential
  • the second control signal is a high potential
  • the data signal is the reference potential
  • the first control signal in the threshold voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
  • the first control signal in the data voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the display potential.
  • the first control signal in the light-emitting phase, is at a low potential, the second control signal is at a low potential, and the data signal is at a low potential.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon Thin film transistors.
  • the threshold voltage of the third transistor is greater than or equal to the threshold voltage of the first transistor.
  • the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.
  • An embodiment of the present application also provides a display panel, which includes a pixel drive circuit, and the pixel drive circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a first power supply voltage, and the drain of the first transistor is electrically connected to a second node;
  • the gate of the second transistor is electrically connected to the first control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the first node;
  • the gate and source of the third transistor are electrically connected to the first node, and the drain of the third transistor is electrically connected to the source of the fourth transistor;
  • the gate of the fourth transistor is electrically connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node;
  • a first end of the capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the second node;
  • the anode terminal of the light emitting device is electrically connected to the second node, and the cathode terminal of the light emitting device is electrically connected to a second power supply voltage.
  • the combination of the first control signal, the second control signal, and the data signal sequentially corresponds to an initial stage, a threshold voltage acquisition stage, a data voltage acquisition stage, and a light-emitting stage;
  • the data signal includes a reference potential and a display potential, the reference potential is greater than the threshold voltage of the third transistor, and the reference potential is less than the display potential.
  • the first control signal is a high potential
  • the second control signal is a high potential
  • the data signal is the reference potential
  • the first control signal in the threshold voltage acquisition phase, is a high potential, the second control signal is a low potential, and the data signal is the reference potential.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel, and the time required for compensation is relatively short.
  • the compensation of the pixel drive circuit The structure is relatively simple, so it does not need to take up a lot of area when designing.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the initial stage of the driving timing shown in FIG. 2;
  • FIG. 4 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage acquisition phase under the driving sequence shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the data voltage acquisition phase under the driving timing shown in FIG. 2;
  • FIG. 6 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase under the driving timing shown in FIG. 2.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit provided by the embodiment of the present application includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a capacitor C, and a light emitting device OLED.
  • the light emitting device OLED may be an organic light emitting diode. That is, the embodiment of the present application adopts a pixel driving circuit with a 4T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, and uses fewer components, has a simple and stable structure, and saves costs.
  • the first transistor T1 in the pixel driving circuit is a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the first node G
  • the source of the first transistor T1 is electrically connected to the first power supply voltage VDD
  • the drain of the first transistor T1 is electrically connected to the second node S .
  • the gate of the second transistor T2 is electrically connected to the first control signal WR
  • the source of the second transistor T2 is electrically connected to the data signal D
  • the drain of the second transistor T2 is electrically connected to the first node G.
  • the gate and source of the third transistor T3 are electrically connected to the first node G
  • the drain of the third transistor T3 is electrically connected to the source of the fourth transistor T4.
  • the gate of the fourth transistor T4 is electrically connected to the second control signal RD, and the drain of the fourth transistor T4 is electrically connected to the second node S.
  • the first end of the capacitor C is electrically connected to the first node G, and the second end of the capacitor C is electrically connected to the second node S.
  • the anode terminal of the light emitting device OLED is electrically connected to the second node S, and the cathode terminal of the light emitting device OLED is electrically connected to the second power supply voltage Vss.
  • both the first power supply voltage VDD and the second power supply voltage Vss are used to output a predetermined voltage value.
  • the output voltage value of the first power supply voltage VDD is greater than the output voltage value of the second power supply voltage Vss.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 2 is a timing diagram of the pixel driving circuit provided by an embodiment of the application.
  • the combination of the first control signal WR, the second control signal RD, and the data signal D corresponds to the initial stage t1, the threshold voltage acquisition stage t2, the data voltage acquisition stage t3, and the light-emitting stage t4.
  • the data signal D includes a reference potential V REF and a display potential V DATA . It can be understood that the potential value of the reference potential V REF is greater than the threshold voltage of the third transistor T3, and the potential value of the reference potential V REF is less than the potential value of the display potential V DATA .
  • the first control signal WR is at a high potential
  • the second control signal RD is at a high potential
  • the data signal D is the reference potential V REF .
  • the first control signal WR is at a high level
  • the second control signal RD is at a low level
  • the data signal D is at the reference potential V REF .
  • the first control signal WR is at a high level
  • the second control signal RD is at a low level
  • the data signal D is at the display level V DATA .
  • the first control signal WR is at a low level
  • the second control signal RD is at a low level
  • the data signal D is at a low level
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the initial stage t1 under the driving timing shown in FIG. 2.
  • the first control signal WR is at a high potential
  • the second control signal RD is at a high potential
  • both the second transistor T2 and the fourth transistor T4 are turned on.
  • the data signal D to the reference potential V REF, the data signal D via the reference voltage V REF through the second transistor T2 output node G i.e., the reference potential V REF through the second transistor T2 output data signal D
  • the first end of capacitor C the first control signal WR is at a high potential
  • the second control signal RD is at a high potential
  • both the second transistor T2 and the fourth transistor T4 are turned on.
  • the third transistor T3 since the gate and drain of the third transistor T3 are short-circuited, and the reference potential V REF of the data signal D is greater than the threshold voltage V th_T3 of the third transistor T3, the third transistor T3 is turned on.
  • the reference potential V REF of the data signal D is output to the second node S through the third transistor T3 and the fourth transistor T4, that is, the reference potential V REF of the data signal D is output to the capacitor C through the third transistor T3 and the fourth transistor T4 The second end.
  • the threshold voltage V th_T3 of the third transistor T3 is greater than or equal to the threshold voltage V th_T1 of the first transistor T1, at this time, the first transistor T1 is turned on.
  • FIG. 4 is a schematic diagram of the path of the threshold voltage obtaining stage t2 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal WR is at a high potential
  • the second control signal RD is at a low potential
  • the second transistor T2 is turned on
  • the fourth transistor T4 is turned off.
  • the data signal D remains the reference potential V REF, the data signal D via the reference voltage V REF through the second transistor T2 output node G, i.e., the reference potential of the data signal D V REF through the second transistor T2 Output to the first end of capacitor C.
  • the potential of the first node G remains unchanged at the initial stage t1.
  • the capacitor C is discharged through the first transistor T1 until the voltage difference between the gate and the drain of the first transistor T1 is equal to the threshold voltage of the first transistor T1.
  • the transistor T1 is turned off, so that the threshold voltage of the first transistor T1 can be obtained. It should be noted that, since the difference between the threshold voltage V th_T3 of the third transistor T3 and the threshold voltage V th_T1 of the first transistor T1 is small, the threshold voltage V th_T1 of the first transistor T1 can be quickly obtained, thereby shortening the compensation cost . The time required.
  • FIG. 5 is a schematic diagram of the data voltage acquisition phase t3 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the first control signal WR is at a high level
  • the second control signal RD is at a low level
  • the second transistor T2 is turned on
  • the fourth transistor T4 is turned off.
  • the data voltage V DATA signal D the potential of V DATA display data signal D is output through the second transistor T2 is displayed to the first node G, i.e., the potential of V DATA display data signal D is output through the second transistor T2 To the first end of capacitor C.
  • the potential of the first node G jumps from the reference potential V REF to the display potential V DATA , and due to the capacitance C coupling effect of the capacitor C, the potential of the second node S also changes accordingly.
  • FIG. 6 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting stage t4 under the driving timing shown in FIG. 2.
  • the first control signal WR is at a low potential
  • the second control signal RD is at a low potential
  • the second transistor T2 is turned off
  • the fourth transistor T4 is turned off. Due to the storage effect of the capacitor C, the potential of the first node G still maintains the potential of the first node G during the data voltage acquisition phase t3, and the potential of the second node S still maintains the potential of the second node S during the data voltage acquisition phase t3.
  • I OLED 1/2Cox( ⁇ W/L)(V gs -V th_T1 ) 2 , where I OLED is the current flowing through the light-emitting device OLED, ⁇ is the carrier mobility of the first transistor T1, W and L are respectively The width and length of the channel of the first transistor T1, Vgs is the voltage difference between the first node G and the second node S. In the embodiment of the present application, the voltage difference between the gate and the drain of the first transistor T1 is equal to the voltage difference between the first node G and the second node S.
  • I OLED 1/2Cox( ⁇ W/L) ⁇ C oled (V DATA -V REF )/(C oled +C) ⁇ 2
  • the current of the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1, and the compensation function is realized.
  • the light emitting device OLED emits light, and the current flowing through the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1.
  • the embodiment of the application itself also provides a display panel, which includes the above-mentioned pixel driving circuit.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • the pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application adopt a pixel drive circuit with a 4T1C structure to effectively compensate the threshold voltage of the drive transistor in each pixel, and the time required for compensation is relatively short.
  • the compensation of the pixel drive circuit The structure is relatively simple, so it does not need to take up a lot of area when designing.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

Le circuit d'attaque de pixel et le panneau d'affichage décrits par les modes de réalisation de la présente invention utilisent un circuit d'attaque de pixel ayant une structure 4T1C pour compenser efficacement la tension de seuil du transistor d'attaque dans chaque pixel, et le temps nécessaire à la compensation est relativement court, la structure de compensation du circuit d'attaque de pixel est relativement simple, et il n'est donc pas nécessaire d'occuper une grande surface pendant la conception.
PCT/CN2019/102970 2019-06-20 2019-08-28 Circuit d'attaque de pixel et panneau d'affichage WO2020252913A1 (fr)

Applications Claiming Priority (2)

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CN201910534535.XA CN110349538B (zh) 2019-06-20 2019-06-20 像素驱动电路及显示面板
CN201910534535.X 2019-06-20

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CN112331147A (zh) * 2020-10-23 2021-02-05 福建华佳彩有限公司 一种提升显示效果的像素补偿电路及驱动方法

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