CN107863057B - Shift register, driving method thereof, driving control circuit and related device - Google Patents

Shift register, driving method thereof, driving control circuit and related device Download PDF

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CN107863057B
CN107863057B CN201711043493.7A CN201711043493A CN107863057B CN 107863057 B CN107863057 B CN 107863057B CN 201711043493 A CN201711043493 A CN 201711043493A CN 107863057 B CN107863057 B CN 107863057B
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signal
transistor
node
electrode
clock signal
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CN107863057A (en
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冷传利
李元
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Shanghai Tianma Microelectronics Co Ltd
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Shanghai Tianma Microelectronics Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

The invention discloses a shift register, a driving method thereof, a driving control circuit, a display panel and a display device.A third control module is arranged to keep the signal stability of a first node under the control of the signal of the first node, and couple the signal of a third clock signal end to the first node when the first node is in floating connection, so that the signal of the first node can be kept from being influenced by the signal of the third clock signal end when an effective pulse signal is output from a signal output end, and the signal influence of a second control module on the third node can be avoided. And the transmission control module is arranged to enable the potential of the signal of the second node to be the same as the potential of the signal of the third node at least under the control of the signal of the second node, so that the signal can be directly and quickly output to the third node, the risk of signal transmission competition can be avoided, the output competition relationship of the shift register can be avoided, and the shift register can stably output the signal in a shifting way.

Description

Shift register, driving method thereof, driving control circuit and related device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a driving control circuit, a display panel, and a display device.
Background
A conventional shift register, as shown in fig. 1, includes: transistors TFT 1-TFT 10, and capacitors C01-C03. As shown in fig. 2, in the shift stage t1, the clock signal CK is low, so that the transistors TFT1 and TFT2 are both turned on. The turned-on transistor TFT2 turns on the transistor TFT6 to charge the capacitor C02 by setting the potential at the node N02 to a low potential. Since the clock signal XCK is at a high potential, both the transistor TFT4 and the transistor TFT7 are turned off. The turned-on first transistor TFT1 makes the potential at the node N01 low, so as to control the transistors TFT8 and TFT10 to be turned on. The turned-on transistor TFT8 makes the potential of the node N03 high to control the transistor TFT9 to be turned off. The conducting transistor TFT10 causes the output signal terminal Out to output a low-level signal. In the output phase t2, since the clock signal CK is at a high level, both the transistor TFT1 and the transistor TFT2 are turned off, and the node N02 is in a floating state. Since the capacitor C02 keeps the potential at the node N02 low, the transistor TFT5 and the transistor TFT6 are both turned on. Since the clock signal XCK is at a low potential, both the transistor TFT4 and the transistor TFT7 are turned on. The turned-on transistors of the TFT5 and the TFT4 can make the potential of the node N01 high to control the turning-off of the transistors of the TFT8 and the TFT 10. The conducting transistor TFT6 and the conducting transistor TFT7 can make the potential of the node N03 be low, so as to control the transistor TFT9 to conduct, and make the output signal terminal Out output a high-potential signal.
However, the capacitance value of the capacitor C01 is generally set to be large, and in the shift register, since the potential of the end of the capacitor C01 connected to the clock signal XCK is high and the potential of the end of the capacitor C01 connected to the node N01 is high in the shift stage t 1. When the shift phase t1 goes to the output phase t2, the node N01 is also floating, and the clock signal XCK changes from high to low, the node N01 may be pulled low due to the coupling effect of the capacitor C01, so that the transistor TFT3, the transistor TFT8, and the transistor TFT10 may be turned on. The turned-on transistor TFT3 causes the node N02 to be at a high potential, so that the transistor TFT6 is turned off, and the low potential signal of the clock signal CKB cannot be successfully supplied to the node N03. Also, the turned-on transistor TFT8 provides the high voltage signal VGH to the node N03, thereby causing the transistor TFT9 to be turned off, so that the high potential signal VGH cannot be provided to the output signal terminal Out. The turned-on transistor TFT10 provides the low voltage signal VGL to the output signal terminal Out, which causes an abnormal output at the output signal terminal Out, and further causes the problem that the shift register has a competitive risk and cannot normally shift and output.
Disclosure of Invention
The embodiment of the invention provides a shift register, a driving method thereof, a driving control circuit, a display panel and a display device, which are used for solving the problem that the shift register in the prior art cannot normally shift and output due to the competitive risk.
Accordingly, an embodiment of the present invention provides a shift register, including: the system comprises an input module, a transmission control module, a first control module, a second control module, a third control module and an output module;
the input module is respectively connected with an input signal end, a first clock signal end, a first reference signal end, a first node and a second node, and is used for providing a signal of the input signal end to the first node and providing a signal of the first reference signal end to the second node under the control of the first clock signal end;
the first control module is respectively connected with the input signal end, the second clock signal end, the second reference signal end and the second node, and is used for providing a signal of the second reference signal end to the second node under the control of the input signal end and the second clock signal end;
the second control module is respectively connected with a second reference signal terminal, the first node and a third node, and is configured to provide a signal of the second reference signal terminal to the third node under the control of the signal of the first node;
the third control module is respectively connected with a third clock signal terminal and the first node, and is used for keeping the signal of the first node stable under the control of the signal of the first node and coupling the signal of the third clock signal terminal to the first node when the first node is floated;
the transmission control module is respectively connected with a third clock signal end, the second node and the third node, and is at least used for enabling the potential of the signal of the second node to be the same as the potential of the signal of the third node under the control of the signal of the second node;
the output module is respectively connected to the first reference signal terminal, the second reference signal terminal, the first node, the third node and the signal output terminal, and is configured to provide the signal of the first reference signal terminal to the signal output terminal under the control of the signal of the first node, and provide the signal of the second reference signal terminal to the signal output terminal under the control of the signal of the third node.
Correspondingly, an embodiment of the present invention further provides a driving control circuit, including: a plurality of cascaded shift registers provided by the embodiments of the present invention;
the input signal end of the first-stage shift register is connected with the initial signal end;
except the first stage of shift register, the input signal ends of the other shift registers are respectively connected with the signal output end of the adjacent shift register of the previous stage.
Correspondingly, an embodiment of the present invention further provides a display panel, including: the embodiment of the invention provides the drive control circuit.
Correspondingly, the embodiment of the invention also provides a display device which comprises the display panel provided by the embodiment of the invention.
Correspondingly, an embodiment of the present invention further provides a driving method of the shift register, including: a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage and a seventh stage;
in the first stage, a first potential signal is provided to the input signal end, the second clock signal end and the third clock signal end respectively, a second potential signal is provided to the first clock signal end, and the signal output end outputs the second potential signal;
in the second stage, a first potential signal is provided to the input signal end, the first clock signal end and the third clock signal end respectively, a second potential signal is provided to the second clock signal end, and the signal output end outputs the second potential signal;
in the third stage, a first potential signal is provided to the input signal terminal, the first clock signal terminal and the second clock signal terminal, a second potential signal is provided to the third clock signal terminal, and the signal output terminal outputs the first potential signal;
in the fourth stage, a first potential signal is provided to the input signal end, the second clock signal end and the third clock signal end respectively, a second potential signal is provided to the first clock signal end, and the signal output end outputs the first potential signal;
in the fifth stage, a first potential signal is provided to the first clock signal end and the third clock signal end respectively, a second potential signal is provided to the input signal end and the second clock signal end respectively, and the signal output end outputs a potential signal;
in the sixth stage, a first potential signal is provided to the first clock signal end and the second clock signal end respectively, a second potential signal is provided to the input signal end and the third clock signal end respectively, and the signal output end outputs the first potential signal;
in the seventh stage, a first potential signal is provided to the second clock signal terminal and the third clock signal terminal, a second potential signal is provided to the input signal terminal and the first clock signal terminal, and the signal output terminal outputs the second potential signal.
The invention has the following beneficial effects:
the shift register, the driving method thereof, the driving control circuit, the display panel and the display device provided by the embodiment of the invention comprise the following steps: the system comprises an input module, a transmission control module, a first control module, a second control module, a third control module and an output module; the input module is used for providing a signal of an input signal end to a first node under the control of a first clock signal end and providing a signal of a first reference signal end to a second node; the first control module is used for providing a signal of a second reference signal end to a second node under the control of the input signal end and a second clock signal end; the second control module is used for providing a signal of a second reference signal end to a third node under the control of the signal of the first node; the third control module is used for keeping the signal of the first node stable under the control of the signal of the first node and coupling the signal of the third clock signal end to the first node when the first node is floated; the transmission control module is at least used for enabling the potential of the signal of the second node to be the same as the potential of the signal of the third node under the control of the signal of the second node; the output module is used for providing the signal of the first reference signal end to the signal output end under the control of the signal of the first node, and providing the signal of the second reference signal end to the signal output end under the control of the signal of the third node. Therefore, by arranging the third control module to keep the signal of the first node stable under the control of the signal of the first node and coupling the signal of the third clock signal terminal to the first node when the first node is floating, it is possible to keep the signal of the first node unaffected by the signal of the third clock signal terminal and avoid the signal of the third node from being affected by the second control module when the signal output terminal outputs the valid pulse signal. And the transmission control module is arranged to enable the potential of the signal of the second node to be the same as the potential of the signal of the third node at least under the control of the signal of the second node, so that the signal can be directly and quickly output to the third node, the risk of signal transmission competition can be avoided, the output competition relationship of the shift register can be avoided, and the shift register can stably output the signal in a shifting way.
Drawings
FIG. 1 is a schematic diagram of a shift register according to the prior art;
FIG. 2 is a timing diagram of the shift register shown in FIG. 1;
FIG. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a specific structure of a shift register according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a circuit according to an embodiment of the present invention;
FIG. 6 is a second timing diagram of the circuit according to the embodiment of the present invention;
fig. 7 is a second schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 8 is a third schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 9 is a fourth exemplary diagram of a shift register according to an embodiment of the present invention;
FIG. 10 is a fifth exemplary diagram of a shift register according to an embodiment of the present invention;
FIG. 11 is a sixth exemplary diagram of a shift register according to an embodiment of the present invention;
fig. 12 is a seventh schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 13 is an eighth schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 14 is a ninth block diagram illustrating a specific structure of a shift register according to an embodiment of the present invention;
fig. 15 is a flowchart of a driving method according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of a driving control circuit according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a shift register, a driving method thereof, a driving control circuit, a display panel and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
An embodiment of the present invention provides a shift register, as shown in fig. 3, including: the system comprises an input module 1, a transmission control module 2, a first control module 3, a second control module 4, a third control module 5 and an output module 6;
the input module 1 is respectively connected to an input signal terminal IN, a first clock signal terminal CK1, a first reference signal terminal VREF1, a first node N1 and a second node N2, and is configured to provide a signal of the input signal terminal IN to the first node N1 and a signal of the first reference signal terminal VREF1 to the second node N2 under the control of the first clock signal terminal CK 1;
the first control module 3 is respectively connected to the input signal terminal IN, the second clock signal terminal CK2, the second reference signal terminal VREF2 and the second node N2, and is configured to provide a signal of the second reference signal terminal VREF2 to the second node N2 under the control of the input signal terminal IN and the second clock signal terminal CK 2;
the second control module 4 is respectively connected to the second reference signal terminal VREF2, the first node N1 and the third node N3, and is configured to provide the signal of the second reference signal terminal VREF2 to the third node N3 under the control of the signal of the first node N1;
the third control module 5 is respectively connected to the third clock signal terminal CK3 and the first node N1, and is configured to keep the signal of the first node N1 stable under the control of the signal of the first node N1, and couple the signal of the third clock signal terminal CK3 to the first node N1 when the first node N1 is floating;
the transmission control module 2 is respectively connected to the third clock signal terminal CK3, the second node N2 and the third node N3, and at least used for making the potential of the signal of the second node N2 and the potential of the signal of the third node N3 the same under the control of the signal of the second node N2;
the output module 6 is respectively connected to the first reference signal terminal VREF1, the second reference signal terminal VREF2, the first node N1, the third node N3 and the signal output terminal OUT, and is configured to provide the signal of the first reference signal terminal VREF1 to the signal output terminal OUT under the control of the signal of the first node N1 and provide the signal of the second reference signal terminal VREF2 to the signal output terminal OUT under the control of the signal of the third node N3.
The shift register provided in the embodiment of the present invention includes: the system comprises an input module, a transmission control module, a first control module, a second control module, a third control module and an output module; the third control module is arranged to keep the signal of the first node stable under the control of the signal of the first node, and couple the signal of the third clock signal end to the first node when the first node is in floating connection, so that the signal of the first node can be kept from being influenced by the signal of the third clock signal end when the signal output end outputs an effective pulse signal, and the signal of the third node can be prevented from being influenced by the second control module. And the transmission control module is arranged to enable the potential of the signal of the second node to be the same as the potential of the signal of the third node at least under the control of the signal of the second node, so that the signal can be directly and quickly output to the third node, the risk of signal transmission competition can be avoided, the output competition relationship of the shift register can be avoided, and the shift register can stably output the signal in a shifting way.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the potential of the effective pulse signal at the input signal end is a high potential, the potential of the signal at the first reference signal end is a low potential, and the potential of the signal at the second reference signal end is a high potential. When the potential of the effective pulse signal of the input signal end is low potential, the potential of the signal of the first reference signal end is high potential, and the potential of the signal of the second reference signal end is low potential.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
The first embodiment,
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the input module 1 may include: a tenth transistor M10 and an eleventh transistor M11;
a control electrode of the tenth transistor M10 is connected to the first clock signal terminal CK1, a first electrode of the tenth transistor M10 is connected to the first reference signal terminal VREF1, and a second electrode of the tenth transistor M10 is connected to the second node N2;
a control electrode of the eleventh transistor M11 is connected to the first clock signal terminal CK1, a first electrode of the eleventh transistor M11 is connected to the input signal terminal IN, and a second electrode of the eleventh transistor M11 is connected to the first node N1.
In the shift register provided in the embodiment of the invention, when the tenth transistor is in a turned-on state under control of the signal of the first clock signal terminal, the signal of the first reference signal terminal may be supplied to the second node. The eleventh transistor may supply a signal of the input signal terminal to the first node when being in a turned-on state under control of a signal of the first clock signal terminal.
In a specific implementation, the transmission control module may be specifically configured to provide the signal at the first reference signal end to the third node under common control of the signals at the second node and the third clock signal end, so that the potential of the signal at the second node is the same as the potential of the signal at the third node. In the shift register provided in the embodiment of the present invention, as shown in fig. 4, the transmission control module 2 may include: a first transistor M1 and a second transistor M2;
a control electrode of the first transistor M1 is connected to the second node N2, a first electrode of the first transistor M1 is connected to the first reference signal terminal VREF1, a second electrode of the first transistor M1 is connected to a first electrode of the second transistor M2, a control electrode of the second transistor M2 is connected to the third clock signal terminal CK3, and a second electrode of the second transistor M2 is connected to the third node N3.
In a specific implementation, the signal of the first reference signal terminal may be provided to the first pole of the second transistor when the first transistor is in a conducting state under control of the signal of the second node. The second transistor may supply a signal input to a first pole thereof to the third node when being in a turned-on state under control of a signal of the third clock signal terminal. That is, when the first transistor and the second transistor are simultaneously turned on, a signal of the first reference signal terminal may be supplied to the third node.
In specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the first control module 3 may include: a fourth transistor M4, a fifth transistor M5, and a first capacitor C1; a first end of the first capacitor C1 is connected to the second node N2, and a second end of the first capacitor C1 is connected to the second reference signal terminal VREF 2;
a control electrode of the fourth transistor M4 is connected to the input signal terminal IN, a first electrode of the fourth transistor M4 is connected to the second reference signal terminal VREF2, a second electrode of the fourth transistor M4 is connected to a first electrode of the fifth transistor M5, a control electrode of the fifth transistor M5 is connected to the second clock signal terminal CK2, and a second electrode of the fifth transistor M5 is connected to the second node N2.
In an implementation, when the fourth transistor is in a conducting state under the control of the signal of the input signal terminal, the signal of the second reference signal terminal may be provided to the first pole of the fifth transistor. The fifth transistor may supply a signal input to a first pole thereof to the second node when being in a turn-on state under control of a signal of the second clock signal terminal. That is, when the fourth transistor and the fifth transistor are turned on simultaneously, the signal of the second reference signal terminal can be provided to the second node, so that the signal of the second reference signal terminal is prevented from being input erroneously, and the stable output of the shift register is further ensured. The first capacitor can keep the voltage difference between the second reference signal terminal and the second node stable.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the second control module 4 may include: a sixth transistor M6 and a second capacitor C2;
a control electrode of the sixth transistor M6 is connected to the first node N1, a first electrode of the sixth transistor M6 is connected to the second reference signal terminal VREF2, and a second electrode of the sixth transistor M6 is connected to the third node N3;
a first terminal of the second capacitor C2 is connected to the third node N3, and a second terminal of the second capacitor C2 is connected to the second reference signal terminal VREF 2.
In an implementation, the sixth transistor may provide a signal of the second reference signal terminal to the third node when being in a turned-on state under control of the signal of the first node. The second capacitor may keep a voltage difference between the third node and the second reference signal terminal stable.
In specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the third control module 5 may include: a seventh transistor M7 and a third capacitor C3; a first terminal of the third capacitor C3 is connected to the first node N1, and a second terminal of the third capacitor C3 is connected to a first pole of the seventh transistor M7; a control electrode of the seventh transistor M7 is connected to the first node N1, and a second electrode of the seventh transistor M7 is connected to the third clock signal terminal CK 3.
In a specific implementation, when the seventh transistor is in a conducting state under the control of the signal of the first node, the third capacitor may be conducted with the third clock signal terminal. The third capacitor may keep a signal of the first node stable, and may keep a voltage difference between the first node and the third clock signal terminal stable when the first node is in a floating state and the third capacitor is turned on with the third clock signal terminal.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the output module 6 may include: an eighth transistor M8 and a ninth transistor M9;
a control electrode of the eighth transistor M8 is connected to the first node N1, a first electrode of the eighth transistor M8 is connected to the first reference signal terminal VREF1, and a second electrode of the eighth transistor M8 is connected to the signal output terminal OUT;
a control electrode of the ninth transistor M9 is connected to the third node N3, a first electrode of the ninth transistor M9 is connected to the second reference signal terminal VREF2, and a second electrode of the ninth transistor M9 is connected to the signal output terminal OUT.
In an implementation, the eighth transistor may provide a signal of the first reference signal terminal to the signal output terminal when the eighth transistor is in a conducting state under control of the signal of the first node. The ninth transistor may provide a signal of the second reference signal terminal to the signal output terminal when it is in a turn-on state under control of a signal of the third node.
In a specific implementation, in the shift register provided in the embodiment of the present invention, the transistors are all illustrated as P-type transistors, and in the case where the transistors are N-type transistors, the design principle is the same as that of the present invention, and the shift register also belongs to the protection scope of the present invention. In the following embodiments, p-type transistors are exemplified.
The above is merely an example to illustrate the specific structure of each module in the shift register provided in the embodiment of the present invention, and in the implementation, the specific structure of each module is not limited to the structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Specifically, in the shift register provided in the embodiment of the present invention, each Transistor may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), which is not limited herein. The control electrode of each transistor is a gate electrode thereof, and a first electrode of each transistor can be a source electrode thereof and a second electrode thereof can be a drain electrode thereof according to the type of each transistor and the signal of the gate electrode of each transistor; or conversely, the first pole of the transistor is used as the drain thereof, and the second pole is used as the source thereof, which are not specifically distinguished herein.
The operation of the shift register shown in fig. 4 will be described with reference to a circuit timing chart. In the following description, 1 denotes a high potential, and 0 denotes a low potential. It should be noted that 1 and 0 are logic potentials, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values.
Fig. 5 shows a timing chart of a shift register circuit shown in fig. 4. Specifically, seven stages of T1, T2, T3, T4, T5, T6, and T7 in the circuit timing chart shown in fig. 5 are mainly selected. The signal of the first reference signal terminal VREF1 is at a low potential, and the signal of the second reference signal terminal VREF2 is at a high potential.
IN stage T1, IN is 1, CK1 is 0, CK2 is 1, and CK3 is 1. Since IN is 1, the fourth transistor M4 is turned off. Since CK2 is equal to 1, the fifth transistor M5 is turned off. Since CK3 is equal to 1, the second transistor M2 is turned off. Since CK1 is equal to 0, both the tenth transistor M10 and the eleventh transistor M11 are turned on. The turned-on eleventh transistor M11 supplies the high potential signal of the input signal terminal IN to the first node N1 to make the potential of the first node N1 high, so as to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to be turned off. Therefore, the third node N3 is floated, and the third node N3 is kept at a high potential by the second capacitor C2, so as to control the ninth transistor M9 to be turned off, thereby keeping the signal output terminal OUT at a low potential. The turned-on tenth transistor M10 provides a low-level signal of the first reference signal terminal VREF1 to the second node N2, so that the second node N2 is at a low level to charge the first capacitor C1.
IN stage T2, IN is 1, CK1 is 1, CK2 is 0, and CK3 is 1. Since CK3 is equal to 1, the second transistor M2 is turned off. Since CK1 is equal to 1, both the tenth transistor M10 and the eleventh transistor M11 are turned off. Since CK2 is equal to 0, the fifth transistor M5 is turned on, but since IN is equal to 1, the fourth transistor M4 is turned off. Therefore, the first node N1, the second node N2, and the third node N3 are all in a floating state. The potential of the second node N2 can be kept low due to the first capacitor C1. The potential of the third node N3 may be maintained at a high potential due to the second capacitor C2 to control the ninth transistor M9 to be turned off. The third capacitor C3 can keep the potential of the first node N1 at a high level, so as to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to be turned off, thereby keeping the signal output terminal OUT at a low level.
IN stage T3, IN is 1, CK1 is 1, CK2 is 1, and CK3 is 0. Since IN is 1, the fourth transistor M4 is turned off. Since CK1 is equal to 1, both the tenth transistor M10 and the eleventh transistor M11 are turned off. Since CK2 is equal to 1, the fifth transistor M5 is turned off. Therefore, the second node N2 is in a floating state, and the potential of the second node N2 can be kept low due to the first capacitor C1, so as to control the first transistor M1 to be turned on. Since CK3 is equal to 0, the second transistor M2 is turned on. Since the first transistor M1 and the second transistor M2 are both turned on, the low level signal of the third clock signal terminal CK3 can be provided to the third node N3, the potential of the third node N3 is made low, so that the second capacitor C2 is charged, and the ninth transistor M9 is controlled to be turned on to provide the high level signal of the VREF2 of the second reference signal terminal to the signal output terminal OUT, so that the signal output terminal OUT outputs a high level signal. The third capacitor C3 can keep the potential of the first node N1 at a high level to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to be turned off, and since the seventh transistor M7 is turned off, the potential of the first node N1 is not affected when the third clock signal terminal CK3 changes from a high level to a low level, so that the shift register can stably output a high-level signal.
IN stage T4, IN is 1, CK1 is 0, CK2 is 1, and CK3 is 1. Since IN is 1, the fourth transistor M4 is turned off. Since CK2 is equal to 1, the fifth transistor M5 is turned off. Since CK1 is equal to 0, both the tenth transistor M10 and the eleventh transistor M11 are turned on. The turned-on eleventh transistor M11 supplies the high potential signal of the input signal terminal IN to the first node N1, and again turns the potential of the first node N1 high to control the sixth, seventh and eighth transistors M6, M7 and M8 to be turned off. Since CK3 is equal to 1, the second transistor M2 is turned off, the third node N3 is in a floating state, and the potential of the third node N3 can be kept low due to the second capacitor C2, so as to control the ninth transistor M9 to be turned on and provide the high-potential signal of the VREF2 at the second reference signal terminal to the signal output terminal OUT, so that the signal output terminal OUT outputs a high-potential signal. The turned-on tenth transistor M10 provides a low-level signal of the first reference signal terminal VREF1 to the second node N2, so that the second node N2 is at a low level, and charges the first capacitor C1 again.
IN stage T5, IN is 0, CK1 is 1, CK2 is 0, and CK3 is 1. Since CK1 is equal to 1, both the tenth transistor M10 and the eleventh transistor M11 are turned off. Since CK3 is equal to 1, the second transistor M2 is turned off. Since CK2 is equal to 0, the fifth transistor M5 is turned on, and since IN is equal to 0, the fourth transistor M4 is turned on. The turned-on fourth transistor M4 and the turned-on fifth transistor M5 can provide the high level signal of the second reference signal terminal VREF2 to the second node N2, so that the potential of the second node N2 is high, thereby controlling the turning-off of the first transistor M1. Therefore, the first node N1 and the third node N3 are both floating. The third capacitor C3 can keep the potential of the first node N1 at a high level to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to turn off. The second capacitor C2 can keep the potential of the third node N3 low, so as to control the ninth transistor M9 to turn on and provide the high potential signal of the VREF2 of the second reference signal terminal to the signal output terminal OUT, thereby enabling the signal output terminal OUT to output a high potential signal.
IN stage T6, IN is 0, CK1 is 1, CK2 is 1, and CK3 is 0. Since CK1 is equal to 1, both the tenth transistor M10 and the eleventh transistor M11 are turned off. Since CK2 is equal to 1, the fifth transistor M5 is turned off, and the second node N2 is in a floating state. The potential of the second node N2 can be kept high due to the first capacitor C1, so as to control the first transistor M1 to be turned off. Therefore, the first node N1 and the third node N3 are both floating. The third capacitor C3 can keep the potential of the first node N1 at a high level to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to turn off. The second capacitor C2 can keep the potential of the third node N3 low, so as to control the ninth transistor M9 to turn on and provide the high potential signal of the VREF2 of the second reference signal terminal to the signal output terminal OUT, thereby enabling the signal output terminal OUT to output a high potential signal.
IN stage T7, IN is 0, CK1 is 0, CK2 is 1, and CK3 is 1. Since CK2 is equal to 1, the fifth transistor M5 is turned off. Since CK3 is equal to 1, the second transistor M2 is turned off. Since CK1 is equal to 0, both the tenth transistor M10 and the eleventh transistor M11 are turned on. The turned-on eleventh transistor M11 provides the low-level signal of the input signal terminal IN to the first node N1, and makes the first node N1 have a low level, so as to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to be turned on. The turned-on sixth transistor M6 provides the high potential signal of the VREF2 of the second reference signal terminal to the third node N3 to control the ninth transistor M9 to be turned off. The turned-on seventh transistor M7 turns on the third capacitor C3 and the third clock signal terminal CK 3. The turned-on eighth transistor M8 provides the low-level signal of the first reference signal terminal VREF1 to the signal output terminal OUT, thereby causing the signal output terminal OUT to output a low-level signal. The turned-on tenth transistor M10 provides the low-level signal of the first reference signal terminal VREF1 to the second node N2, so that the potential of the second node N2 is low, but the second transistor M2 is turned off, and thus the potential of the third node N3 is not affected.
After the stage T7, the method may further include: stages T8 and T9. IN stage T8, IN is 0, CK1 is 1, CK2 is 0, and CK3 is 1. Since IN is equal to 0, the fourth transistor M4 is turned on, and since CK2 is equal to 0, the fifth transistor M5 is turned on, and thus a high potential signal of VREF2 of the second reference signal terminal may be supplied to the second node N2 to control the first transistor M1 to be turned off. Since CK1 is equal to 1, both the tenth transistor M10 and the eleventh transistor M11 are turned off. Therefore, the first node N1 is in a floating state, and the third capacitor C3 can keep the potential of the first node N1 at a low level, so as to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to be turned on. The turned-on sixth transistor M6 provides the high potential signal of the VREF2 of the second reference signal terminal to the third node N3 to control the ninth transistor M9 to be turned off. The turned-on seventh transistor M7 turns on the third capacitor C3 and the third clock signal terminal CK 3. The turned-on eighth transistor M8 provides the low-level signal of the first reference signal terminal VREF1 to the signal output terminal OUT, thereby causing the signal output terminal OUT to output a low-level signal.
IN stage T9, IN is 0, CK1 is 1, CK2 is 1, and CK3 is 0. Since CK2 is equal to 1, the fifth transistor M5 is turned off, the second node N2 is in a floating state, and the potential of the second node N2 can be kept high due to the first capacitor C1, so as to control the first transistor M1 to be turned off. Since CK1 is equal to 1, both the tenth transistor M10 and the eleventh transistor M11 are turned off. Therefore, the first node N1 is in a floating state, and the third capacitor C3 can keep the first node N1 at a low voltage level, so as to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to be turned on. The turned-on seventh transistor M7 turns on the third capacitor C3 and the third clock signal terminal CK 3. Since CK3 is equal to 0, and the third capacitor C3 further pulls the potential of the first node N1 low, so as to avoid the influence of the threshold loss of the eighth transistor M8 when transmitting the low-potential signal of the first reference signal terminal VREF1 on the transmission of the low-potential signal, so that the sixth transistor M6 can transmit the high-potential signal of the VREF2 of the second reference signal terminal to the third node N3 without voltage loss, so as to control the ninth transistor M9 to turn off. The eighth transistor M8, which is turned on, may provide the low-potential signal of the first reference signal terminal VREF1 to the signal output terminal OUT without voltage loss, thereby causing the signal output terminal OUT to output a low-potential signal.
In the first embodiment, after the stage T9, the operation process from the stage T7 to the stage T9 is repeated until the signal at the input signal terminal is the high potential signal again.
In the first embodiment, in the shift register provided by the embodiment of the invention, in the stage T3, since the seventh transistor is turned off, the coupling influence on the signal of the first node when the signal of the third clock signal terminal transitions from a high potential to a low potential can be avoided. And, since the fourth transistor is turned off, the influence of the high potential signal of the second reference signal terminal on the second node is avoided. And, since the first transistor M1 and the second transistor M2 can be turned on in time to directly supply the low potential signal to the third node, and the ninth transistor is controlled to be turned on in time to output the high potential signal, thereby maintaining the stable output of the output waveform and stabilizing the operation of the circuit of the shift register.
Example II,
Taking the structure of the shift register shown IN fig. 4 as an example, a T0 stage is inserted between the T4 stage and the T5 stage IN the circuit timing diagram of the first embodiment, that is, the duration of the high-potential signal of the input signal terminal IN is extended by one clock cycle on the basis of the circuit timing diagram of the first embodiment, the corresponding circuit timing diagram is shown IN fig. 6, and eight stages, T1, T2, T3, T4, T0, T5, T6, and T7, are mainly selected; the T0 stage is divided into a T01 sub-stage, a T02 sub-stage and a T03 sub-stage.
Since the structure of the shift register in the second embodiment is the same as that of the shift register in the first embodiment, and the potentials of the signals in the stages T1 to T4 and T5 to T7 in the circuit timing diagram in the second embodiment are respectively the same as the potentials of the signals in the stages T1 to T7 in the first embodiment, the working processes of the shift register in the stages T1 to T4 and T5 to T7 in the second embodiment can be referred to the working processes in the stages T1 to T7 in the shift register in the first embodiment, which is not described herein again. The following is a detailed description of the operation process only in stage T0.
IN the T01 sub-stage of the T0 stage, IN is 1, CK1 is 1, CK2 is 0, and CK3 is 1. Since IN is 1, the fourth transistor M4 is turned off. Since CK1 is equal to 1, both the tenth transistor M10 and the eleventh transistor M11 are turned off. Since CK3 is equal to 1, the second transistor M2 is turned off. Therefore, the first node N1 and the third node N3 are both floating. The third capacitor C3 can keep the potential of the first node N1 at a high level to control the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 to turn off. The second capacitor C2 can keep the potential of the third node N3 low, so as to control the ninth transistor M9 to turn on and provide the high potential signal of the VREF2 of the second reference signal terminal to the signal output terminal OUT, thereby enabling the signal output terminal OUT to output a high potential signal.
IN the sub-stage T02, IN is 1, CK1 is 1, CK2 is 1, and CK3 is 0. The specific working process of this stage is substantially the same as the working process of the stage T3 in the first embodiment, and is not described herein again.
IN the sub-stage T03, IN is 1, CK1 is 0, CK2 is 1, and CK3 is 1. The specific working process of this stage is substantially the same as the working process of the stage T4 in the first embodiment, and is not described herein again.
In the second embodiment, based on the signal input to the signal output terminal in the first embodiment, the duration of the valid pulse signal input to the signal output terminal is extended by one clock cycle, and the valid pulse signal output from the signal output terminal is correspondingly extended by one clock cycle.
Further, two T0 phases are inserted between the T4 phase and the T5 phase IN the circuit timing diagram of the first embodiment, that is, the duration of the high-potential signal of the input signal terminal IN is extended by two clock cycles on the basis of the circuit timing diagram of the first embodiment, and the corresponding circuit timing diagram has two T0 phases between the T4 phase and the T5 phase IN the circuit timing diagram of the first embodiment. Specifically, the working processes of the two stages T0 are substantially the same as those of the stage T0 in the second embodiment, and reference may be made to the specific implementation in the second embodiment, which is not described herein again. And the duration of the effective pulse signal of the input signal end is prolonged by three, four, five … clock cycles, and so on.
Therefore, in the shift register provided in the embodiment of the present invention, in the specific implementation, the effective pulse signal at the input signal end is extended by M clock cycles, and the effective pulse signal at the output signal end is correspondingly extended by M clock cycles; wherein M is a positive integer. Therefore, the extension of the effective pulse signal output by the signal output end can be realized only by prolonging the duration of the effective pulse signal of the input signal end without changing the signal of the clock signal end and changing the circuit and the process, so that the difficulty of the preparation process can be reduced.
Example III,
The structure of the shift register corresponding to this embodiment is as shown in fig. 7, and it only aims at the first embodiment that the connection mode of the first transistor M1 and the second transistor M2 in the transmission control module 2 of fig. 4 is modified, so that the transmission control module can be specifically used for providing the signal of the third clock signal end to the third node under the common control of the signals of the second node and the third clock signal end, so that the potential of the signal of the second node is the same as the potential of the signal of the third node. The connection manner of the other transistors is the same as that of fig. 4 in the first embodiment, and is not described herein again.
In specific implementation, in the shift register provided in the embodiment of the invention, as shown in fig. 7, in the transmission control module 2, the control electrode of the first transistor M1 is connected to the second node N2, the first electrode of the first transistor M1 is connected to the third clock signal terminal CK3, the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, the control electrode of the second transistor M2 is connected to the third clock signal terminal CK3, and the second electrode of the second transistor M2 is connected to the third node N3.
In a specific implementation, when the first transistor is in a conducting state under the control of the signal of the second node, the signal of the third clock signal terminal may be provided to the first pole of the second transistor. The second transistor may supply a signal input to a first pole thereof to the third node when being in a turned-on state under control of a signal of the third clock signal terminal. That is, when the first transistor and the second transistor are simultaneously turned on, a signal of the third clock signal terminal may be supplied to the third node.
The timing diagrams of the shift register shown in fig. 7 may be those shown in fig. 5 and 6. Compared with the shift register shown in fig. 4, the shift register shown in fig. 7 only differs in the operation process thereof in that: when the first transistor and the second transistor are turned on simultaneously, a low-potential signal of the third clock signal terminal is provided to the third node, so that the potential of the third node is low. In addition, the rest of the working processes of the shift register shown in fig. 7 may refer to the specific implementation of the working processes in the first embodiment and the second embodiment, which are not described herein again.
Example four,
The structure of the shift register corresponding to this embodiment is as shown in fig. 8, and it only aims at the first embodiment that the connection mode of the first transistor M1 and the second transistor M2 in the transmission control module 2 of fig. 4 is modified, so that the transmission control module can be specifically used for providing the signal of the first reference signal end to the third node under the common control of the signals of the second node and the third clock signal end, so that the potential of the signal of the second node is the same as the potential of the signal of the third node. The connection manner of the other transistors is the same as that of fig. 4 in the first embodiment, and is not described herein again.
In a specific implementation, in the shift register according to the embodiment of the invention, as shown in fig. 8, in the transmission control module 2, a control electrode of the first transistor M1 is connected to the third clock signal terminal CK3, a first electrode of the first transistor M1 is connected to the first reference signal terminal VREF1, a second electrode of the first transistor M1 is connected to a first electrode of the second transistor M2, a control electrode of the second transistor M2 is connected to the second node N2, and a second electrode of the second transistor M2 is connected to the third node N3.
In a specific implementation, when the first transistor is in a conducting state under the control of the signal of the third clock signal terminal, the signal of the first reference signal terminal may be provided to the first pole of the second transistor. The second transistor may supply a signal input to a first pole thereof to the third node when it is in a turned-on state under control of a signal of the second node. That is, when the first transistor and the second transistor are simultaneously turned on, a signal of the first reference signal terminal may be supplied to the third node.
The timing charts of the shift register shown in fig. 8 may be those shown in fig. 5 and 6. In addition, turning on and off of the first transistor in the shift register shown in fig. 8 can refer to turning on and off of the second transistor in the shift register in the first and second embodiments. As for turning on and off of the second transistor in the shift register shown in fig. 8, refer to the turning on and off processes of the first transistor in the shift register in the first embodiment and the second embodiment. In addition, the rest of the working processes of the shift register shown in fig. 8 may refer to the specific implementation of the working processes in the first embodiment and the second embodiment, which are not described herein again.
Example V,
Fig. 9 shows a structure diagram of a shift register according to this embodiment, which is only a modification of the connection manner between the first transistor M1 and the second transistor M2 in the transmission control module 2 of fig. 4 in the first embodiment, so that the transmission control module can be specifically used to provide the signal of the third clock signal terminal to the third node under the common control of the signals of the second node and the third clock signal terminal, so that the potential of the signal of the second node is the same as the potential of the signal of the third node. The connection manner of the other transistors is the same as that of fig. 4 in the first embodiment, and is not described herein again.
In specific implementation, in the shift register according to the embodiment of the invention, as shown in fig. 9, in the transmission control module 2, the control electrode and the first electrode of the first transistor M1 are both connected to the third clock signal terminal CK3, the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, the control electrode of the second transistor M2 is connected to the second node N2, and the second electrode of the second transistor M2 is connected to the third node N3.
In a specific implementation, when the first transistor is in a conducting state under the control of the signal of the third clock signal terminal, the signal of the third clock signal terminal may be provided to the first pole of the second transistor. The second transistor may supply a signal input to a first pole thereof to the third node when it is in a turned-on state under control of a signal of the second node. That is, when the first transistor and the second transistor are simultaneously turned on, a signal of the third clock signal terminal may be supplied to the third node.
The timing charts of the shift register shown in fig. 9 may be those shown in fig. 5 and 6. In addition, turning on and off of the first transistor in the shift register shown in fig. 9 can refer to the turning on and off processes of the second transistor in the shift register in the first and second embodiments; as for turning on and off of the second transistor in the shift register shown in fig. 9, refer to the turning on and off processes of the first transistor in the shift register in the first embodiment and the second embodiment. In this embodiment, when the first transistor and the second transistor are turned on simultaneously, a signal of the third clock signal terminal may be provided to the third node, and the rest of the working processes may refer to specific implementation of the working processes in the first embodiment and the second embodiment, which is not described herein again.
Example six,
In a specific implementation, in the shift register provided in the embodiment of the present invention, the transmission control module may also use only one transistor for control, so that the transmission control module can be specifically configured to provide the signal at the third clock signal end to the third node under the control of the signal at the second node, so that the potential of the signal at the second node is the same as the potential of the signal at the third node. Thereby reducing the footprint of the overall circuit.
Specifically, as shown in fig. 10, the transmission control module 2 may also include: a third transistor M3; a control electrode of the third transistor M3 is coupled to the second node N2, a first electrode of the third transistor M3 is coupled to the third clock signal terminal CK3, and a second electrode of the third transistor M3 is coupled to the third node N3. The connection manner of the rest of the transistors in the shift register shown in fig. 10 is the same as that in fig. 4 of the first embodiment, and is not described herein again.
The operation of the shift register shown in fig. 10 will be described with reference to the timing diagrams of the circuits shown in fig. 5 and 6, respectively. In the following description, 1 denotes a high potential, and 0 denotes a low potential. It should be noted that 1 and 0 are logic potentials, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values.
IN the circuit timing diagram shown IN fig. 5, IN stage T1, IN is 1, CK1 is 0, CK2 is 1, and CK3 is 1. The potential of the second node N2 is low to control the third transistor M3 to be turned on and to provide the high potential signal of the third clock signal terminal CK3 to the third node N3 to control the ninth transistor M9 to be turned off. The rest of the working process at this stage is substantially the same as the working process at stage T1 in the first embodiment, and is not described herein again.
IN stage T2, IN is 1, CK1 is 1, CK2 is 0, and CK3 is 1. The potential of the second node N2 is low to control the third transistor M3 to be turned on and to provide the high potential signal of the third clock signal terminal CK3 to the third node N3 to control the ninth transistor M9 to be turned off. The rest of the working process at this stage is substantially the same as the working process at stage T2 in the first embodiment, and is not described herein again.
IN stage T3, IN is 1, CK1 is 1, CK2 is 1, and CK3 is 0. The potential of the second node N2 is low to control the third transistor M3 to be turned on and to provide a low potential signal of the third clock signal terminal CK3 to the third node N3 to control the ninth transistor M9 to be turned on. The rest of the working process at this stage is substantially the same as the working process at stage T3 in the first embodiment, and is not described herein again.
IN stage T4, IN is 1, CK1 is 0, CK2 is 1, and CK3 is 1. The potential of the second node N2 is low to control the third transistor M3 to be turned on and to provide the high potential signal of the third clock signal terminal CK3 to the third node N3 to control the ninth transistor M9 to be turned off, so that the signal output terminal OUT maintains the high potential signal for output. The rest of the working process at this stage is substantially the same as the working process at stage T4 in the first embodiment, and is not described herein again.
IN stage T5, IN is 0, CK1 is 1, CK2 is 0, and CK3 is 1. The potential of the second node N2 is high to control the third transistor M3 to turn off, and the third node N3 is in a floating state. The potential of the third node N3 can be kept high due to the second capacitor C2, so as to control the ninth transistor M9 to be turned off, and the signal output terminal OUT keeps outputting the signal with high potential. The rest of the working process at this stage is substantially the same as the working process at stage T5 in the first embodiment, and is not described herein again.
IN stage T6, IN is 0, CK1 is 1, CK2 is 1, and CK3 is 0. The potential of the second node N2 is high to control the third transistor M3 to turn off, and the third node N3 is in a floating state. The potential of the third node N3 can be kept high due to the second capacitor C2, so as to control the ninth transistor M9 to be turned off, and the signal output terminal OUT keeps outputting the signal with high potential. The rest of the working process at this stage is substantially the same as the working process at stage T6 in the first embodiment, and is not described herein again.
IN stage T7, IN is 0, CK1 is 0, CK2 is 1, and CK3 is 1. The potential of the second node N2 is low to control the third transistor M3 to be turned on and to provide the high signal of the third clock signal terminal CK3 to the third node N3 to further control the ninth transistor M9 to be turned off. The rest of the working process at this stage is substantially the same as the working process at stage T7 in the first embodiment, and is not described herein again.
The T8 and T9 phases may also be included after the T7 phase. IN stage T8, IN is 0, CK1 is 1, CK2 is 0, and CK3 is 1. The potential of the second node N2 is high to control the third transistor M3 to turn off. The rest of the working process at this stage is substantially the same as the working process at stage T8 in the first embodiment, and is not described herein again.
IN stage T9, IN is 0, CK1 is 1, CK2 is 1, and CK3 is 0. The potential of the second node N2 is high to control the third transistor M3 to turn off. The rest of the working process at this stage is substantially the same as the working process at stage T9 in the first embodiment, and is not described herein again.
Similarly, regarding the circuit timing diagram shown in fig. 6, the working process of the shift register shown in fig. 10 can be described with reference to the second embodiment and the sixth embodiment, which is not repeated herein.
Example seven,
Fig. 11 shows a structure of a shift register corresponding to this embodiment, which is a modification of the connection manner between the fourth transistor M4 and the fifth transistor M5 in the first control module 3 of fig. 4 in the first embodiment, so as to implement the function of the first control module 3 in other manners. The connection manner of the other transistors is the same as that of fig. 4 in the first embodiment, and is not described herein again.
IN specific implementation, IN the shift register provided IN the embodiment of the invention, as shown IN fig. 11, IN the first control module 3, the control electrode of the fourth transistor M4 is connected to the second clock signal terminal CK2, the first electrode of the fourth transistor M4 is connected to the second reference signal terminal VREF2, the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5, the control electrode of the fifth transistor M5 is connected to the input signal terminal IN, and the second electrode of the fifth transistor M5 is connected to the second node N2.
In an implementation, when the fourth transistor is in a conducting state under the control of the signal of the second clock signal terminal, the signal of the second reference signal terminal may be provided to the first pole of the fifth transistor. The fifth transistor may supply a signal input to a first pole thereof to the second node when it is in a turned-on state under control of a signal input to the signal terminal.
The timing charts of the shift register shown in fig. 11 may be those shown in fig. 5 and 6. Compared with the shift register shown in fig. 4, the shift register shown in fig. 11 only differs in the operation process: the signal terminal of the fourth transistor connected to the control electrode of the fifth transistor is replaced, so that turning on and off of the fourth transistor in fig. 11 can be referred to the turning on and off of the fifth transistor of the shift register in the first and second embodiments. Turning on and off the fifth transistor in fig. 11 can be seen from the turning on and off processes of the fourth transistor of the shift register in the first and second embodiments. In addition, the rest of the working processes of the shift register shown in fig. 11 may refer to the specific implementation of the working processes in the first embodiment and the second embodiment, which are not described herein again.
Example eight,
Fig. 12 shows a structure diagram of a shift register according to this embodiment, which is a modification of the connection manner between the seventh transistor M7 and the third capacitor C3 in the third control module 5 of fig. 4 in the first embodiment, so as to implement the function of the third control module 5 in another manner. The connection manner of the other transistors is the same as that of fig. 4 in the first embodiment, and is not described herein again.
In a specific implementation manner, in the shift register provided in the embodiment of the invention, as shown in fig. 12, in the third control module 5, the control electrode and the first electrode of the seventh transistor M7 are both connected to the first node N1, the second electrode of the seventh transistor M7 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 is connected to the third clock signal terminal CK 3.
In a specific implementation, when the seventh transistor is in a conducting state under the control of the signal of the first node, the third capacitor may be conducted with the first node. When the third capacitor is disconnected from the first node, the signal influence of the third clock signal end on the first node through the coupling of the third capacitor can be avoided; when the third capacitor is conducted with the first node, the signal of the first node can be kept stable, and when the first node is in a floating state, the voltage difference between the first node and the third clock signal end can be kept stable. When the third capacitor is turned on with the first node and the signal at the third clock signal end is changed from a high potential to a low potential, the potential of the first node can be further pulled down due to the coupling effect of the third capacitor, so that the influence of the threshold loss of the eighth transistor in the transmission of the low potential signal at the first reference signal end on the transmission of the low potential signal is avoided.
The timing charts of the shift register shown in fig. 12 may be those shown in fig. 5 and 6. Compared with the shift register shown in fig. 4, the shift register shown in fig. 12 only differs in the operation process: when the potential of the first node is high, the seventh transistor is turned off, so that the first node and the third capacitor can be disconnected. The first node may be maintained at a high potential when the first node is floated and no external signal is input to the first node to discharge the first node. When the potential of the first node is a low potential, the seventh transistor is turned on, so that the first node and the third capacitor can be turned on. In addition, the rest of the working processes of the shift register shown in fig. 12 may refer to the specific implementation of the working processes in the first embodiment and the second embodiment, which are not described herein again.
Examples nine,
As can be seen from the first and second embodiments, the first node has a floating state during a period in which the signal output terminal OUT outputs an active pulse signal of a high potential. In order to avoid the influence of the floating state of the first node on the output of the shift register, in a specific implementation, as shown in fig. 13 and 14, the shift register may further include: a node stabilizing module 7; the node stabilizing module 7 is respectively connected to the third clock signal terminal CK3, the second reference signal terminal VREF2, the first node N1 and the third node N3, and is configured to provide a signal of the second reference signal terminal VREF2 to the first node N1 under the control of the third clock signal terminal CK3 and the third node N3.
In specific implementation, as shown in fig. 13 and 14, the node stabilizing module 7 may include: a twelfth transistor M12 and a thirteenth transistor M13. As shown in fig. 13, a control electrode of the twelfth transistor M12 is connected to the third node N3, a first electrode of the twelfth transistor M12 is connected to the second reference signal terminal VREF2, a second electrode of the twelfth transistor M12 is connected to a first electrode of the thirteenth transistor M13, a control electrode of the thirteenth transistor M13 is connected to the third clock signal terminal CK3, and a second electrode of the thirteenth transistor M13 is connected to the first node N1. In a specific implementation, when the twelfth transistor M12 is in a turned-on state under the control of the signal of the third node N3, the signal of the second reference signal terminal VREF2 may be provided to the first pole of the thirteenth transistor M13. The thirteenth transistor M13 may provide a signal input to its first pole to the first node N1 when it is in a turned-on state under the control of the third clock signal terminal CK 3.
Alternatively, as shown in fig. 14, a control electrode of the twelfth transistor M12 is connected to the third clock signal terminal CK3, a first electrode of the twelfth transistor M12 is connected to the second reference signal terminal VREF2, a second electrode of the twelfth transistor M12 is connected to a first electrode of the thirteenth transistor M13, a control electrode of the thirteenth transistor M13 is connected to the third node N3, and a second electrode of the thirteenth transistor M13 is connected to the first node N1. In a specific implementation, when the twelfth transistor M12 is in a turned-on state under the control of the signal of the third clock signal terminal CK3, the signal of the second reference signal terminal VREF2 may be provided to the first pole of the thirteenth transistor M13. The thirteenth transistor M13 may provide a signal input to a first pole thereof to the first node N1 when it is in a turn-on state under the control of the signal of the third node N3.
The operation of the circuit will be described with reference to a timing chart of the circuit, taking fig. 13 as an example. In the following description, 1 denotes a high potential, and 0 denotes a low potential. It should be noted that 1 and 0 are logic potentials, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values.
Fig. 5 shows a timing chart of a shift register circuit shown in fig. 13. Specifically, seven stages of T1, T2, T3, T4, T5, T6, and T7 in the circuit timing chart shown in fig. 5 are mainly selected. The signal of the first reference signal terminal VREF1 is at a low potential, and the signal of the second reference signal terminal VREF2 is at a high potential.
IN stage T1, IN is 1, CK1 is 0, CK2 is 1, and CK3 is 1. Since CK3 is equal to 1, the thirteenth transistor M13 is turned off. The rest of the working process at this stage is substantially the same as the working process at stage T1 in the first embodiment, and is not described herein again.
IN stage T2, IN is 1, CK1 is 1, CK2 is 0, and CK3 is 1. Since CK3 is equal to 1, the thirteenth transistor M13 is turned off. The rest of the working process at this stage is substantially the same as the working process at stage T2 in the first embodiment, and is not described herein again.
IN stage T3, IN is 1, CK1 is 1, CK2 is 1, and CK3 is 0. Since CK3 is equal to 0, the thirteenth transistor M13 is turned on. Since the potential of the third node N3 is low, the twelfth transistor M12 is turned on. The high signal of the second reference signal terminal VREF2 can be transmitted to the first node N1 through the turned-on thirteenth transistor M13 and twelfth transistor M12, so that the potential of the first node N1 is high, thereby preventing the first node N1 from floating. The rest of the working process at this stage is substantially the same as the working process at stage T3 in the first embodiment, and is not described herein again.
IN stage T4, IN is 1, CK1 is 0, CK2 is 1, and CK3 is 1. Since CK3 is equal to 1, the thirteenth transistor M13 is turned off. The rest of the working process at this stage is substantially the same as the working process at stage T4 in the first embodiment, and is not described herein again.
IN stage T5, IN is 0, CK1 is 1, CK2 is 0, and CK3 is 1. Since CK3 is equal to 1, the thirteenth transistor M13 is turned off. The rest of the working process at this stage is substantially the same as the working process at stage T5 in the first embodiment, and is not described herein again.
IN stage T6, IN is 0, CK1 is 1, CK2 is 1, and CK3 is 0. Since CK3 is equal to 0, the thirteenth transistor M13 is turned on. Since the potential of the third node N3 is low, the twelfth transistor M12 is turned on. The high signal of the second reference signal terminal VREF2 can be transmitted to the first node N1 through the turned-on thirteenth transistor M13 and twelfth transistor M12, so that the potential of the first node N1 is high, thereby preventing the first node N1 from floating. The rest of the working process at this stage is substantially the same as the working process at stage T6 in the first embodiment, and is not described herein again.
IN stage T7, IN is 0, CK1 is 0, CK2 is 1, and CK3 is 1. Since CK3 is equal to 1, the thirteenth transistor M13 is turned off. The rest of the working process at this stage is substantially the same as the working process at stage T7 in the first embodiment, and is not described herein again.
After the stage T7, the method may further include: stages T8 and T9. IN stage T8, IN is 0, CK1 is 1, CK2 is 0, and CK3 is 1. Since CK3 is equal to 1, the thirteenth transistor M13 is turned off. The rest of the working process at this stage is substantially the same as the working process at stage T8 in the first embodiment, and is not described herein again.
IN stage T9, IN is 0, CK1 is 1, CK2 is 1, and CK3 is 0. Since CK3 is equal to 0, the thirteenth transistor M13 is turned on. However, since the potential of the third node N3 is high, the twelfth transistor M12 is turned off. The rest of the working process at this stage is substantially the same as the working process at stage T9 in the first embodiment, and is not described herein again.
After the stage T9, the operation process of the stages T7 to T9 is repeated until the signal at the input signal terminal is the high potential signal again.
In the shift register provided by the embodiment of the present invention, the twelfth transistor and the thirteenth transistor are arranged to reduce the floating state of the first node, so that the stable output of the output waveform can be further maintained, and the circuit operation of the shift register is further stabilized.
In the ninth embodiment, based on the signal input to the signal terminal, the duration of the effective pulse signal of the signal terminal is extended by M clock cycles, and the effective pulse signal output by the signal output terminal can be correspondingly extended by M clock cycles.
Based on the same inventive concept, an embodiment of the present invention further provides a method for driving any one of the shift registers, as shown in fig. 15, including: a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage and a seventh stage;
s1301, in the first stage, a first potential signal is respectively provided for an input signal end, a second clock signal end and a third clock signal end, a second potential signal is provided for the first clock signal end, and a signal output end outputs the second potential signal;
s1302, at the second stage, providing a first potential signal to the input signal terminal, the first clock signal terminal and the third clock signal terminal, providing a second potential signal to the second clock signal terminal, and outputting the second potential signal from the signal output terminal;
s1303, in the third stage, providing a first potential signal to the input signal terminal, the first clock signal terminal, and the second clock signal terminal, providing a second potential signal to the third clock signal terminal, and outputting the first potential signal from the signal output terminal;
s1304, in the fourth stage, providing the first potential signal to the input signal terminal, the second clock signal terminal, and the third clock signal terminal, providing the second potential signal to the first clock signal terminal, and outputting the first potential signal from the signal output terminal;
s1305, in the fifth stage, providing a first potential signal to the first clock signal terminal and the third clock signal terminal, respectively, providing a second potential signal to the input signal terminal and the second clock signal terminal, respectively, and outputting a potential signal from the signal output terminal;
s1306, in the sixth stage, providing the first potential signal to the first clock signal terminal and the second clock signal terminal, providing the second potential signal to the input signal terminal and the third clock signal terminal, and outputting the first potential signal from the signal output terminal;
s1307, in the seventh stage, the first potential signal is provided to the second clock signal terminal and the third clock signal terminal, the second potential signal is provided to the input signal terminal and the first clock signal terminal, and the signal output terminal outputs the second potential signal.
The driving method provided by the embodiment of the invention can avoid the output competition relationship of the shift register, so that the shift register can stably shift output signals.
In a specific implementation, in the driving method provided in the embodiment of the present invention, the first potential signal may be a high potential signal, and correspondingly, the second potential signal is a low potential signal; or conversely, the first potential signal may be a low potential signal, and correspondingly, the second potential signal is a high potential signal, which is determined according to whether the transistor in the shift register is an N-type transistor or a P-type transistor. Specifically, fig. 5 and fig. 6 show the timing diagrams of the circuits in which the transistors in the shift register are P-type transistors, and the first potential signal is a high potential signal and the second potential signal is a low potential signal.
In practical implementation, in the driving method provided in the embodiment of the present invention, after the fourth stage and before the fifth stage, the method further includes: at least one insertion phase; wherein the insertion phase comprises: a first insertion sub-stage, a second insertion sub-stage and a third insertion sub-stage;
in the first inserting sub-stage, a first potential signal is respectively provided for an input signal end, a first clock signal end and a third clock signal end, a second potential signal is provided for a second clock signal end, and a signal output end outputs the first potential signal;
in the second insertion sub-stage, a first potential signal is respectively provided for the input signal end, the first clock signal end and the second clock signal end, a second potential signal is provided for the third clock signal end, and the signal output end outputs the first potential signal;
in the third insertion sub-stage, the first potential signal is provided to the input signal terminal, the second clock signal terminal and the third clock signal terminal, the second potential signal is provided to the first clock signal terminal, and the first potential signal is output by the signal output terminal.
In specific implementation, an insertion stage is inserted between the fourth stage and the fifth stage, that is, the duration of the effective pulse signal of the input signal end is prolonged by one clock cycle, and the effective pulse signal of the signal output by the output signal end is correspondingly prolonged by one clock cycle. Two insertion stages are inserted between the fourth stage and the fifth stage, namely, the duration of the effective pulse signal of the input signal end is prolonged by two clock cycles, and the effective pulse signal of the signal output by the output signal end is correspondingly prolonged by two clock cycles. In the case of a valid pulse signal on the input signal side that is extended by three, four, five … clock cycles, and so on. Therefore, the extension of the effective pulse signal output by the signal output end can be realized only by prolonging the duration of the effective pulse signal of the input signal end without changing the signal of the clock signal end and changing the circuit and the process, so that the difficulty of the preparation process can be reduced.
Based on the same inventive concept, an embodiment of the present invention further provides a driving control circuit, as shown in fig. 16, including: a plurality of cascaded shift registers according to embodiments of the present invention as described above: SR (1), SR (2) … SR (N-1), SR (N) … SR (N) (N shift registers, N is more than or equal to 1 and less than or equal to N);
an input signal end IN of the first-stage shift register SR (1) is connected with an initial signal end STV;
except for the first stage of shift register SR (1), the input signal terminals IN of the shift registers SR (n) of the other stages are respectively connected with the signal output terminal OUT _ n-1 of the shift register SR (n-1) of the previous stage adjacent to the input signal terminal IN of the shift register SR (n).
In concrete implementation, as shown in fig. 16, in the driving control circuit, a first clock signal terminal CK1 of the 3k-2 th stage shift register, a second clock signal terminal CK2 of the 3k-1 th stage shift register, and a third clock signal terminal CK3 of the 3 k-3 th stage shift register are connected to a first clock terminal CK 1; the second clock signal terminal CK2 of the 3k-2 stage shift register, the third clock signal terminal CK3 of the 3k-1 stage shift register, and the first clock signal terminal CK1 of the 3k stage shift register are all connected to the second clock terminal CK 2; the third clock signal terminal CK3 of the 3k-2 stage shift register, the first clock signal terminal CK1 of the 3k-1 stage shift register, and the second clock signal terminal CK2 of the 3k stage shift register are all connected to the third clock terminal CK 3; wherein k is a positive integer.
In specific implementation, the first reference signal end of each stage of shift register is connected with the same signal end, namely the first reference end; the second reference signal end of each stage of shift register is connected with the same signal end, namely the second reference end.
Specifically, the specific structure of each shift register in the driving control circuit is the same as that of the shift register of the present invention in function and structure, and repeated descriptions are omitted.
In specific implementation, the driving control circuit provided by the embodiment of the invention can be used as a gate driving circuit and applied to providing a gate scanning signal of the scanning control transistor.
Alternatively, the driving control circuit provided in the embodiment of the present invention may be used as a light emitting driving circuit, and is applied to provide a light emitting control signal of the light emitting control transistor, which is not limited herein.
Based on the same inventive concept, the embodiment of the present invention further provides a display panel, including any one of the above-mentioned driving control circuits provided by the embodiment of the present invention. The principle of the display panel to solve the problem is similar to that of the shift register, so the implementation of the display panel can refer to the implementation of the shift register, and repeated details are not repeated herein.
In specific implementation, the driving control circuit may be a gate driving circuit, and the display panel further includes a plurality of gate lines; the signal output end of each shift register in the grid driving circuit is respectively and correspondingly connected with at least one grid line.
In a specific implementation, the display panel provided in the embodiment of the present invention may be an organic light emitting display panel, or may also be a liquid crystal display panel, which is not limited herein. In general, a liquid crystal display device includes a plurality of pixel electrodes and switching transistors connected to the pixel electrodes. In a specific implementation, when the display panel provided by the embodiment of the present invention is a liquid crystal display panel, the driving control circuit provided by the embodiment of the present invention can be used as a gate driving circuit, and provide a gate scanning signal to the switching transistor through a gate line in the display panel.
In an organic light emitting display device, a plurality of organic light emitting diodes and a pixel compensation circuit connected to each organic light emitting diode are generally provided. A light emission control transistor for controlling light emission of the organic light emitting diode and a scan control transistor for controlling input of a data signal are provided in a general pixel compensation circuit. When the display panel provided by the embodiment of the invention is an organic light emitting display panel, the driving control circuit can be used as a gate driving circuit, and provides a gate scanning signal to the scanning control transistor through a gate line in the display panel.
In specific implementation, the driving control circuit is a light-emitting control circuit, and the display panel further comprises a plurality of light-emitting control signal lines; the signal output end of each shift register in the light-emitting control circuit is respectively and correspondingly connected with at least one light-emitting control signal line. When the display panel provided by the embodiment of the invention is an organic light emitting display panel, the driving control circuit can be used as a light emitting driving circuit, and provides a light emitting control signal to the light emitting control transistor through a light emitting control signal line in the display panel.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The implementation of the display device can refer to the above-mentioned embodiments of the shift register, and repeated descriptions are omitted.
In specific implementation, the display device provided in the embodiment of the present invention may be a full-screen mobile phone shown in fig. 17. Of course, the display device provided in the embodiment of the present invention may also be any product or component having a display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
The shift register, the driving method thereof, the driving control circuit, the display panel and the display device provided by the embodiment of the invention comprise the following steps: the system comprises an input module, a transmission control module, a first control module, a second control module, a third control module and an output module; the input module is used for providing a signal of an input signal end to a first node under the control of a first clock signal end and providing a signal of a first reference signal end to a second node; the first control module is used for providing a signal of a second reference signal end to a second node under the control of the input signal end and a second clock signal end; the second control module is used for providing a signal of a second reference signal end to a third node under the control of the signal of the first node; the third control module is used for keeping the signal of the first node stable under the control of the signal of the first node and coupling the signal of the third clock signal end to the first node when the first node is floated; the transmission control module is at least used for enabling the potential of the signal of the second node to be the same as the potential of the signal of the third node under the control of the signal of the second node; the output module is used for providing the signal of the first reference signal end to the signal output end under the control of the signal of the first node, and providing the signal of the second reference signal end to the signal output end under the control of the signal of the third node. Therefore, by arranging the third control module to keep the signal of the first node stable under the control of the signal of the first node and coupling the signal of the third clock signal terminal to the first node when the first node is floating, it is possible to keep the signal of the first node unaffected by the signal of the third clock signal terminal and avoid the signal of the third node from being affected by the second control module when the signal output terminal outputs the valid pulse signal. And the transmission control module is arranged to enable the potential of the signal of the second node to be the same as the potential of the signal of the third node at least under the control of the signal of the second node, so that the signal can be directly and quickly output to the third node, the risk of signal transmission competition can be avoided, the output competition relationship of the shift register can be avoided, and the shift register can stably output the signal in a shifting way.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (19)

1. A shift register, comprising: the system comprises an input module, a transmission control module, a first control module, a second control module, a third control module and an output module;
the input module is respectively connected with an input signal end, a first clock signal end, a first reference signal end, a first node and a second node, and is used for providing a signal of the input signal end to the first node and providing a signal of the first reference signal end to the second node under the control of the first clock signal end;
the first control module is respectively connected with the input signal end, the second clock signal end, the second reference signal end and the second node, and is used for providing a signal of the second reference signal end to the second node under the control of the input signal end and the second clock signal end;
the second control module is respectively connected with a second reference signal terminal, the first node and a third node, and is configured to provide a signal of the second reference signal terminal to the third node under the control of the signal of the first node;
the third control module is respectively connected with a third clock signal terminal and the first node, and is used for keeping the signal of the first node stable under the control of the signal of the first node and coupling the signal of the third clock signal terminal to the first node when the first node is floated;
the transmission control module is respectively connected with a third clock signal end, the second node and the third node, and is at least used for enabling the potential of the signal of the second node to be the same as the potential of the signal of the third node under the control of the signal of the second node;
the output module is respectively connected to the first reference signal terminal, the second reference signal terminal, the first node, the third node and the signal output terminal, and is configured to provide the signal of the first reference signal terminal to the signal output terminal under the control of the signal of the first node, and provide the signal of the second reference signal terminal to the signal output terminal under the control of the signal of the third node.
2. The shift register of claim 1, wherein the transmission control module comprises: a first transistor and a second transistor;
a control electrode of the first transistor is connected with the second node, a first electrode of the first transistor is connected with the first reference signal end, a second electrode of the first transistor is connected with a first electrode of the second transistor, a control electrode of the second transistor is connected with the third clock signal end, and a second electrode of the second transistor is connected with the third node; alternatively, the first and second electrodes may be,
a control electrode of the first transistor is connected with the third clock signal end, a first electrode of the first transistor is connected with the first reference signal end, a second electrode of the first transistor is connected with a first electrode of the second transistor, a control electrode of the second transistor is connected with the second node, and a second electrode of the second transistor is connected with the third node; alternatively, the first and second electrodes may be,
a control electrode of the first transistor is connected with the second node, a first electrode of the first transistor is connected with the third clock signal end, a second electrode of the first transistor is connected with a first electrode of the second transistor, a control electrode of the second transistor is connected with the third clock signal end, and a second electrode of the second transistor is connected with the third node; alternatively, the first and second electrodes may be,
the control electrode and the first electrode of the first transistor are connected with the third clock signal end, the second electrode of the first transistor is connected with the first electrode of the second transistor, the control electrode of the second transistor is connected with the second node, and the second electrode of the second transistor is connected with the third node.
3. The shift register of claim 1, wherein the transmission control module comprises: a third transistor;
a control electrode of the third transistor is connected to the second node, a first electrode of the third transistor is connected to the third clock signal terminal, and a second electrode of the third transistor is connected to the third node.
4. The shift register of claim 1, wherein the first control module comprises: a fourth transistor, a fifth transistor, and a first capacitor; a first end of the first capacitor is connected with the second node, and a second end of the first capacitor is connected with the second reference signal end;
a control electrode of the fourth transistor is connected with the input signal end, a first electrode of the fourth transistor is connected with the second reference signal end, a second electrode of the fourth transistor is connected with a first electrode of the fifth transistor, a control electrode of the fifth transistor is connected with the second clock signal end, and a second electrode of the fifth transistor is connected with the second node; alternatively, the first and second electrodes may be,
a control electrode of the fourth transistor is connected with the second clock signal end, a first electrode of the fourth transistor is connected with the second reference signal end, a second electrode of the fourth transistor is connected with a first electrode of the fifth transistor, a control electrode of the fifth transistor is connected with the input signal end, and a second electrode of the fifth transistor is connected with the second node.
5. The shift register of claim 1, wherein the second control module comprises: a sixth transistor and a second capacitor;
a control electrode of the sixth transistor is connected with the first node, a first electrode of the sixth transistor is connected with the second reference signal end, and a second electrode of the sixth transistor is connected with the third node;
and the first end of the second capacitor is connected with the third node, and the second end of the second capacitor is connected with the second reference signal end.
6. The shift register of claim 1, wherein the third control module comprises: a seventh transistor and a third capacitor;
a first end of the third capacitor is connected with the first node, a second end of the third capacitor is connected with a first pole of the seventh transistor, a second pole of the seventh transistor is connected with the third clock signal end, and a control pole of the seventh transistor is connected with the first node; alternatively, the first and second electrodes may be,
a control electrode and a first electrode of the seventh transistor are both connected with the first node, a second electrode of the seventh transistor is connected with a first end of the third capacitor, and a second end of the third capacitor is connected with the third clock signal end.
7. The shift register of claim 1, wherein the output module comprises: an eighth transistor and a ninth transistor;
a control electrode of the eighth transistor is connected with the first node, a first electrode of the eighth transistor is connected with the first reference signal end, and a second electrode of the eighth transistor is connected with the signal output end;
and a control electrode of the ninth transistor is connected with the third node, a first electrode of the ninth transistor is connected with the second reference signal end, and a second electrode of the ninth transistor is connected with the signal output end.
8. The shift register of claim 1, wherein the input module comprises: a tenth transistor and an eleventh transistor;
a control electrode of the tenth transistor is connected to the first clock signal terminal, a first electrode of the tenth transistor is connected to the first reference signal terminal, and a second electrode of the tenth transistor is connected to the second node;
a control electrode of the eleventh transistor is connected to the first clock signal terminal, a first electrode of the eleventh transistor is connected to the input signal terminal, and a second electrode of the eleventh transistor is connected to the first node.
9. The shift register of any one of claims 1-8, further comprising: a node stabilizing module;
the node stabilizing module is respectively connected to the third clock signal terminal, the second reference signal terminal, the first node and the third node, and configured to provide a signal of the second reference signal terminal to the first node under the control of the third clock signal terminal and the third node.
10. The shift register of claim 9, wherein the node stabilization module comprises: a twelfth transistor and a thirteenth transistor;
a control electrode of the twelfth transistor is connected with the third node, a first electrode of the twelfth transistor is connected with the second reference signal terminal, a second electrode of the twelfth transistor is connected with a first electrode of the thirteenth transistor, a control electrode of the thirteenth transistor is connected with the third clock signal terminal, and a second electrode of the thirteenth transistor is connected with the first node; alternatively, the first and second electrodes may be,
a control electrode of the twelfth transistor is connected to the third clock signal terminal, a first electrode of the twelfth transistor is connected to the second reference signal terminal, a second electrode of the twelfth transistor is connected to a first electrode of the thirteenth transistor, a control electrode of the thirteenth transistor is connected to the third node, and a second electrode of the thirteenth transistor is connected to the first node.
11. A drive control circuit, comprising: a plurality of shift registers according to any one of claims 1 to 10 in cascade;
the input signal end of the first-stage shift register is connected with the initial signal end;
except the first stage of shift register, the input signal ends of the other shift registers are respectively connected with the signal output end of the adjacent shift register of the previous stage.
12. The drive control circuit according to claim 11, wherein in the drive control circuit, a first clock signal terminal of a 3k-2 th stage shift register, a second clock signal terminal of a 3k-1 th stage shift register, and a third clock signal terminal of a 3 k-3 th stage shift register are connected to the first clock terminal; wherein k is a positive integer;
the second clock signal end of the 3k-2 stage shift register, the third clock signal end of the 3k-1 stage shift register and the first clock signal end of the 3k stage shift register are connected with the second clock end;
and the third clock signal end of the 3k-2 stage shift register, the first clock signal end of the 3k-1 stage shift register and the second clock signal end of the 3k stage shift register are connected with the third clock end.
13. The drive control circuit according to claim 11 or 12, wherein the drive control circuit is a gate drive circuit; alternatively, the drive control circuit is a light emission control circuit.
14. A display panel, comprising: a drive control circuit according to any one of claims 11 to 13.
15. The display panel according to claim 14, wherein the driving control circuit is a gate driving circuit, the display panel further comprising a plurality of gate lines;
and the signal output end of each shift register in the grid driving circuit is respectively and correspondingly connected with at least one grid line.
16. The display panel according to claim 14, wherein the drive control circuit is a light emission control circuit, the display panel further comprising a plurality of light emission control signal lines;
and the signal output end of each shift register in the light-emitting control circuit is respectively and correspondingly connected with at least one light-emitting control signal line.
17. A display device characterized by comprising the display panel according to any one of claims 14 to 16.
18. A driving method of a shift register according to any one of claims 1 to 10, comprising: a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage and a seventh stage;
in the first stage, a first potential signal is provided to the input signal end, the second clock signal end and the third clock signal end respectively, a second potential signal is provided to the first clock signal end, and the signal output end outputs the second potential signal;
in the second stage, a first potential signal is provided to the input signal end, the first clock signal end and the third clock signal end respectively, a second potential signal is provided to the second clock signal end, and the signal output end outputs the second potential signal;
in the third stage, a first potential signal is provided to the input signal terminal, the first clock signal terminal and the second clock signal terminal, a second potential signal is provided to the third clock signal terminal, and the signal output terminal outputs the first potential signal;
in the fourth stage, a first potential signal is provided to the input signal end, the second clock signal end and the third clock signal end respectively, a second potential signal is provided to the first clock signal end, and the signal output end outputs the first potential signal;
in the fifth stage, a first potential signal is provided to the first clock signal end and the third clock signal end respectively, a second potential signal is provided to the input signal end and the second clock signal end respectively, and the signal output end outputs a potential signal;
in the sixth stage, a first potential signal is provided to the first clock signal end and the second clock signal end respectively, a second potential signal is provided to the input signal end and the third clock signal end respectively, and the signal output end outputs the first potential signal;
in the seventh stage, a first potential signal is provided to the second clock signal terminal and the third clock signal terminal, a second potential signal is provided to the input signal terminal and the first clock signal terminal, and the signal output terminal outputs the second potential signal.
19. The driving method according to claim 18, further comprising, after the fourth stage and before the fifth stage: at least one insertion phase; wherein the insertion phase comprises: a first insertion sub-stage, a second insertion sub-stage and a third insertion sub-stage;
in the first insertion sub-stage, a first potential signal is provided to the input signal terminal, the first clock signal terminal and the third clock signal terminal, a second potential signal is provided to the second clock signal terminal, and the signal output terminal outputs the first potential signal;
in the second insertion sub-stage, a first potential signal is provided to the input signal terminal, the first clock signal terminal and the second clock signal terminal, a second potential signal is provided to the third clock signal terminal, and the signal output terminal outputs the first potential signal;
in the third insertion sub-stage, a first potential signal is provided to the input signal terminal, the second clock signal terminal and the third clock signal terminal, a second potential signal is provided to the first clock signal terminal, and the signal output terminal outputs the first potential signal.
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