CN103021321B - Shift register and liquid crystal indicator - Google Patents
Shift register and liquid crystal indicator Download PDFInfo
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- CN103021321B CN103021321B CN201210589418.1A CN201210589418A CN103021321B CN 103021321 B CN103021321 B CN 103021321B CN 201210589418 A CN201210589418 A CN 201210589418A CN 103021321 B CN103021321 B CN 103021321B
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Abstract
The present invention relates to a kind of shift register and the liquid crystal indicator using this shift register.This liquid crystal indicator includes a liquid crystal panel and at least scan driving circuit.This scan drive circuit all includes a shift register.Each shift register includes multiple shifting deposit unit, each shifting deposit unit all receives from two clock signals receiving external circuit, and two the clock signal that received of adjacent shifting deposit unit contrary, the output signal of previous shifting deposit unit be after the input signal of a shifting deposit unit.Each shifting deposit unit all includes start-up circuit, signal input circuit, signal output apparatus and control circuit.The electronegative potential of this shift register output signal is all consistent, uses the liquid crystal indicator picture of this shift register to show relatively sharp and accurate.
Description
Technical field
The present invention relates to a kind of shift register and the liquid crystal indicator using this shift register.
Background technology
Current thin film transistor (ThinFilmTransistor, TFT) liquid crystal indicator has been increasingly becoming the standard output device of various digital product, but, it needs to design suitable drive circuit to ensure its steady operation.
Generally, liquid crystal display device drive circuit includes at least scan driving circuit.Scan drive circuit is then used for controlling conducting and the cut-off of thin film transistor (TFT), and scan drive circuit all uses shift register as core circuit unit.Generally, shift register is to be in series by multiple shifting deposit units, and the input signal that the output signal of previous shifting deposit unit is a rear shifting deposit unit.The plurality of shifting deposit unit exports a high potential to wherein scan line according to sequential, and to open the thin film transistor (TFT) in this scan line, and end is both needed to be maintained at low-potential state when other.If the low-potential state of each shifting deposit unit can not keep consistent, then opening by mistake of thin film transistor (TFT) can be caused to open so that the picture that display panels cannot be the most to be shown, the phenomenons such as ghost image occur.
Summary of the invention
The problem inconsistent in order to solve the electronegative potential of prior art shift register output signal, it is necessary to the shift register that the electronegative potential of a kind of output signal is consistent is provided.
May inconsistent cause showing the inaccurate problem of picture because of the electronegative potential of its shift register output signal to solve prior art liquid crystal indicator, be also necessary to provide a kind of display picture clearly, liquid crystal indicator accurately.
A kind of shift register, it includes multiple shifting deposit unit, it is characterized in that: two clock signal phases that two adjacent shifting deposit units are received are contrary, contrary the first clock signal of each shifting deposit unit receiving phase and second clock signal, and each shifting deposit unit all includes enabling signal input, start-up circuit, signal input circuit, signal output apparatus, control circuit, reference voltage end and outfan, this start-up circuit is for receiving an enabling signal, it includes the first transistor, this the first transistor receives this enabling signal from this enabling signal input, and export to this reference voltage end, the voltage of this reference voltage end is used for starting this signal input circuit；This signal input circuit receives this first clock signal, it includes transistor seconds and the first electric capacity, this transistor seconds receives this first clock signal, and exports this first clock signal to this outfan, and this first electric capacity is electrically connected between this reference voltage end and this outfan；nullThis signal output apparatus includes third transistor and the 4th transistor，This third transistor is on or off under the control of this control circuit，4th transistor on or off under the control of this second clock signal，This third transistor and the 4th transistor export low-potential signal to this outfan when conducting state，The signal of this outfan output is as this enabling signal of a rear shifting deposit unit，This control circuit is for controlling the on or off of this third transistor，Including the 5th transistor、Second electric capacity、Primary nodal point、Secondary nodal point and boosted switch，This second electric capacity one end receives this first clock signal，The other end is electrically connected at this secondary nodal point，5th transistor on or off under the control of this reference voltage end，5th transistor one end is electrically connected at this secondary nodal point，The other end receives a low voltage signal，This boosted switch exports high potential signal or low-potential signal respectively to this primary nodal point under the voltage of this secondary nodal point and the control of second clock signal，When this secondary nodal point is high potential，The output of this boosted switch is higher than the high potential signal of this secondary nodal point voltage to this primary nodal point，When this primary nodal point is electronegative potential，This boosted switch exports a low-potential signal to this primary nodal point.
A kind of liquid crystal indicator, it includes a liquid crystal panel and at least scan driving circuit, and this scan drive circuit includes aforesaid shift LD,.
Compared to prior art, from the work schedule and circuit structure of this shift register, this boosted switch is under the voltage of secondary nodal point and the control of second clock signal, ensure that primary nodal point is high and low with secondary nodal point current potential consistent, simultaneously when secondary nodal point is high potential, make primary nodal point export higher high potential signal, thus more accurately with the third transistor opening signal output apparatus fully so that now the first signal of electronegative potential is consistent with the electronegative potential in other moment.
Accompanying drawing explanation
Fig. 1 is the circuit structure block diagram of shift register one better embodiment of the present invention.
Fig. 2 is the circuit diagram of this first shifting deposit unit shown in Fig. 1.
Fig. 3 is the circuit diagram of this first shifting deposit unit shown in Fig. 1 and this second shifting deposit unit.
Fig. 4 is the working timing figure of this first shifting deposit unit shown in Fig. 2 and this second shifting deposit unit.
Fig. 5 is the structural representation of the liquid crystal indicator of shift register shown in application drawing 1.
Main element symbol description
Shift register 20
First shifting deposit unit 21
Second shifting deposit unit 22
3rd shifting deposit unit 23
Enabling signal STV
Enabling signal input VIN
Outfan GOUT
First signal G1
Secondary signal G2
First controls end Vc1
Second controls end Vc2
Primary nodal point Vb1
Secondary nodal point Vb2
Reference voltage end Va
First reference signal Ra1
Second reference signal Ra2
Start-up circuit 211
Signal input circuit 212
Signal output apparatus 213
Control circuit 214
Boosted switch 215
Clock signal clk 1
Inverting clock signal CLK2
The first transistor T1, P1
Transistor seconds T2, P2
Third transistor T3, P3
4th transistor T4, P4
5th transistor T5, P5
6th transistor T6, P6
7th transistor T7, P7
8th transistor T8, P8
9th transistor T9, P9
Tenth transistor T10, P10
11st transistor T11, P11
Tenth two-transistor T12, P12
First electric capacity C1
Second electric capacity C2
Low-potential signal VEE
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
Refer to Fig. 1, be the circuit structure block diagram of shift register one better embodiment of the present invention.This shift register 20 includes multiple shifting deposit unit with same circuits structure, the plurality of shifting deposit unit is sequentially connected in series, each shifting deposit unit all receives clock signal clk 1 and the inverting clock signal CLK2 that external circuit provides, and the clock signal that two adjacent shifting deposit units are received is anti-phase.The internal circuit configuration of each shifting deposit unit is identical, and it is formed by multiple nmos type transistors.Each nmos type transistor all includes a grid, a source electrode and a drain electrode.Present embodiment is only with the first shifting deposit unit 21 and the second shifting deposit unit 22 of being adjacent, and the annexation of this shift register 20 is described as a example by the 3rd shifting deposit unit 23 adjacent with the second shifting deposit unit 22.
Each shifting deposit unit, the first shifting deposit unit the 21, second shifting deposit unit 22 and the 3rd shifting deposit unit 23 as shown in Figure 1, all include enabling signal input VIN, outfan GOUT, the first control end Vc1, the second control end Vc2 and reference voltage end Va.The signal that this first to three shifting deposit unit 21-23 exports respectively, if the first signal G1 and secondary signal G2 (see Fig. 4) are as the displacement signal of this shift register output.
For the first shifting deposit unit 21, its enabling signal input VIN accepts enabling signal STV (referring to Fig. 4) that an external circuit provides, first signal G1 of its outfan GOUT output is as the first displacement signal of this displacement bit register 20, simultaneously, this outfan GOUT is also electrically connected with the enabling signal input VIN of the second shifting deposit unit 22, so that this first signal G1 is as enabling signal STV of this second shifting deposit unit 22.The first outfan GOUT controlling end Vc1 and the second shifting deposit unit 22 is electrically connected with, and secondary signal G2 that the outfan GOUT receiving the second shifting deposit unit 22 exports is as control signal, second reference voltage end Va controlling end Vc2 and the second shifting deposit unit 22 is electrically connected with, and accepting the second reference signal Ra2 of reference voltage end Va output in the second shifting deposit unit 22, this second reference signal Ra2 is a voltage signal.Its reference voltage end Va exports the first reference signal Ra1.
In like manner, for the second shifting deposit unit 22, its enabling signal input VIN receives this first signal G1 as its enabling signal；Its first control end Vc1 is electrically connected at the outfan GOUT of the 3rd shifting deposit unit 23, and receives the signal (sign) of the 3rd shifting deposit unit 23 outfan GOUT output as control signal；Its second reference voltage end Va controlling end Vc2 and the 3rd shifting deposit unit 23 is electrically connected with, and accepts the reference signal (sign) of reference voltage end Va output in the 3rd shifting deposit unit 23.
It is appreciated that other displacement deposit units of this shift register 20 are similar with the connected mode of above-mentioned displacement deposit unit 21,22, is not repeated.
See also Fig. 2 and Fig. 3, be the electrical block diagram of this first shifting deposit unit 21 respectively, and the electrical block diagram that the first shifting deposit unit 21 electrically connects with this second shifting deposit unit 22.This first shifting deposit unit 21 includes start-up circuit 211, signal input circuit 212, signal output apparatus 213, control circuit 214.In present embodiment, this start-up circuit 211, signal input circuit 212, signal output apparatus 213 and control circuit 214 include the first to the tenth two-transistor T1-T12.
Start-up circuit 211 includes the first transistor T1 and the 8th transistor T8.The grid of this first transistor T1 is electrically connected with the source electrode, and is electrically connected to enabling signal input VIN, and to receive this enabling signal STV, its drain electrode is electrically connected with the drain electrode of the 8th transistor T8, and is connected to reference voltage end Va.The grid of the 8th transistor T8 is electrically connected at this first control end Vc1, and source electrode accepts the low-potential signal VEE that external circuit provides.
Signal input circuit 212 includes transistor seconds T2, the 9th transistor T9 and the first electric capacity C1.The grid of transistor seconds T2 is connected to reference voltage end Va, and source electrode accepts the clock signal clk 1 from external circuit, and drain electrode is electrically connected with the drain electrode of the 9th transistor T9, and is electrically connected to outfan GOUT.The grid of the 9th transistor T9 is electrically connected at the second control end Vc2, and source electrode receives the clock signal clk 1 that external circuit provides.First electric capacity C1 is electrically connected between reference voltage end Va and outfan GOUT.
Signal output apparatus 213 includes third transistor T3, the 4th transistor T4, the tenth transistor T10 and the 11st transistor T11.The grid of this third transistor T3 and the grid of the tenth transistor T10 are electrically connected with, and are connected to this control circuit 214, and the drain electrode of third transistor T3 is connected to outfan GOUT, and source electrode receives the low-potential signal VEE that external circuit provides.The drain electrode of the tenth transistor T10 is connected to reference voltage end Va, and source electrode receives the low-potential signal VEE that external circuit provides.The grid of the 4th transistor T4 and the grid of the 11st transistor T11 are electrically connected with, and receive the inverting clock signal CLK2 that external circuit provides, and the drain electrode of the 4th transistor T4 is connected to outfan GOUT, and source electrode receives the low-potential signal VEE that external circuit provides.The drain electrode of the 11st transistor T11 is connected to reference voltage end Va, and source electrode receives this enabling signal STV.
Control circuit 214 includes boosted switch the 215, the 5th transistor T5, the tenth two-transistor T12 and the second electric capacity C2, and wherein, one end of this second electric capacity C2 connects this clock signal clk 1, and the other end defines a secondary nodal point Vb2.This boosted switch 215 includes the 6th transistor T6 and the 7th transistor T7 being connected in series, wherein, the drain electrode of the 6th transistor T6 is connected with the drain electrode of the 7th transistor T10, thus the primary nodal point Vb1 defined, the source electrode of the 6th transistor T6 receives this clock signal clk 1, and grid electrically connects this secondary nodal point Vb2.The grid of the 7th transistor T7 receives this inverting clock signal CLK2, and source electrode receives the low-potential signal VEE that external circuit provides.
The grid of the 5th transistor T5 is electrically connected at reference voltage end Va, and drain electrode is electrically connected at secondary nodal point Vb2, the low-potential signal VEE outside source electrode acceptance.
The grid of the tenth two-transistor T12 is electrically connected with reference voltage end Va, and drain electrode is electrically connected at primary nodal point Vb1, and source electrode receives the low-potential signal VEE that external circuit provides.
nullThe internal circuit configuration of this second shifting deposit unit 22 is identical with the circuit structure of this first shifting deposit unit 21，It includes 12 transistor P1-P12 and two electric capacity C1-C2 the most accordingly，Difference is: the clock signal that in the second shifting deposit unit 22, each transistor receives is anti-phase with the clock signal that the transistor of relevant position in the first shifting deposit unit 21 is received，As: the source electrode of the transistor seconds P2 of the second shifting deposit unit 22 receives this inverting clock signal CLK2，The source electrode of the 9th transistor P9 receives this inverting clock signal CLK2，The grid of the 4th transistor P4 and the 11st transistor P11 receives this clock signal clk 1，Second electric capacity C2 one end relative to secondary nodal point Vb2 receives this inverting clock signal CLK2，The source electrode of the 6th transistor P6 receives this inverting clock signal CLK2，7th transistor P7 grid receives this clock signal clk 1.And accordingly, the transistor seconds T2 of the first displacement deposit unit 21, the 9th transistor T9, the 6th transistor T6 and the second electric capacity C2 receive clock signal clk 1, the four, the 11 and seven transistor T4, T7, T11 receive inverting clock signal CLK2.
It is appreciated that follow-up adjacent pair the 3rd shifting deposit unit and the 4th shifting deposit unit (not shown) are identical with the connected mode of the first shifting deposit unit 21 and the second shifting deposit unit 22, repeats no more.
Refer to Fig. 4, be the working timing figure of this first shifting deposit unit 21 and this second shifting deposit unit 22.
Within the t1 period, enabling signal STV that external circuit provides and inverting clock signal CLK2 are high potential, and clock signal clk 1 is low-potential signal.Enabling signal STV of this high potential drives the first transistor T1 conducting, reference voltage end Va (reference signal) is high potential, transistor seconds T2 turns on, clock signal clk 1 exports the first signal G1 of electronegative potential from the source electrode input of transistor seconds T2 to outfan GOUT, outfan GOUT according to clock signal clk 1.
Owing to first electric capacity C1 one end is connected to reference voltage end Va of high potential, other end is connected to the outfan GOUT of electronegative potential, and now this first electric capacity C1 starts to charge up.After charging complete, this first reference signal Ra1 becomes high potential, now the 5th transistor T5 conducting in control circuit 214, and the secondary nodal point Vb2 being connected with the 5th transistor T5 drain electrode is pulled down to electronegative potential.Now, the 6th transistor T6 grid due to and be connected with secondary nodal point Vb2 and also become electronegative potential, therefore the 6th transistor T6 cut-off.Owing to this first reference signal Ra1 is high potential, the tenth two-transistor T12 conducting, the low-potential signal output of its drain electrode to primary nodal point Vb1 so that primary nodal point Vb1 is electronegative potential.Meanwhile, the 7th transistor T7 turns under the high potential of inverting clock signal CLK2 drives, then the low-potential signal of its drain electrode also exports to primary nodal point Vb1, ensures that this primary nodal point Vb1 is in electronegative potential simultaneously.Second electric capacity C2 two ends are electronegative potential, are not charged or discharge.
Owing to primary nodal point Vb1 is the cut-off of electronegative potential, then third transistor T3 and the tenth transistor T10.4th transistor T4 and the 11st transistor T11 turns under the driving of inverting clock signal CLK2 high potential, the low-potential signal of the 4th transistor T4 drain electrode also exports to outfan GOUT, it is further ensured that the first signal G1 is electronegative potential, enabling signal STV that 11st transistor T11 source terminal receives also exports to reference voltage end Va being connected with its source electrode, is further ensured that the first reference signal Ra1 of reference voltage end Va is in high potential.
Owing to now the second shifting deposit unit 22 is not opened, first controls end Vc1 and second control end Vc2 does not receive control signal, then the 8th transistor T8 and the 9th transistor T9 is in cut-off state.
Within the t2 period, enabling signal STV is electronegative potential by high potential saltus step, and clock signal clk 1 saltus step is high potential, and inverting clock signal CLK2 saltus step is electronegative potential.The first transistor T1 ends, and owing to the voltage at the first electric capacity C1 two ends will not suddenly change, the first reference signal Ra1 keeps high potential.When the t2 period starts, the second shifting deposit unit 22 is not actuated, and the grid of the 8th transistor T8 controls secondary signal G2 that end Vc1 receives the electronegative potential of the second shifting deposit unit 22 outfan GOUT output, then the 8th transistor T8 cut-off from first.First reference signal Ra1 remains as high potential, and the second electric capacity C2 continues charging under the high potential of clock signal clk 1 so that the high potential of the first reference signal Ra1 raises further.
Owing to the first reference signal Ra1 is high potential, transistor seconds T2 turns on, and its source electrode receives the clock signal clk 1 of high potential, and exports to drain electrode, then the first signal G1 saltus step of outfan GOUT output is high potential.The enabling signal input VIN of the first signal G1 output to the second shifting deposit unit 22 of this high potential, enabling signal as this second shifting deposit unit 22, start this second shifting deposit unit 22, the first transistor P1 making this second displacement deposit unit 22 turns on, second reference signal Ra2 of reference voltage end Va is high potential, transistor seconds P2 turns on, then the inverting clock signal CLK2 of electronegative potential exports to signal output part GOUT, making secondary signal 2 is electronegative potential, and to the first electric capacity C1 charging.Owing to the first reference signal Ra2 is high potential, then the 9th transistor T9 conducting of the first displacement deposit unit 21, the clock signal clk 1 of the high potential that its source terminal receives exports to outfan GOUT, is further ensured that the first signal G1 is high potential.
For control circuit 214 with signal output apparatus 213, owing to the first reference signal Ra1 remains as high potential, then the 5th transistor T5, the tenth two-transistor T12 conducting, primary nodal point Vb1 and secondary nodal point Vb2 is electronegative potential, 6th transistor T6 cut-off, the 7th transistor T7 ends under the inverting clock signal CLK2 of electronegative potential controls.It is to say, now, this boosted switch 215 is not activated.
Owing to secondary nodal point Vb2 is high potential still in electronegative potential and the first reference voltage Ra1, boosted switch 215 is not actuated.Tenth two-transistor T12 conducting, then the primary nodal point Vb1 being electrically connected with the tenth two-transistor T12 drain electrode is electronegative potential, and third transistor T3 and the tenth transistor T10 are still within cut-off state.It is the cut-off of electronegative potential, then the 4th transistor T4 and the 11st transistor T11 due to inverting clock signal CLK2 again, thus prevents the low-potential signal of its source terminal from the high potential of the first signal G1 is produced interference.
Additionally, after the outfan of the first shifting deposit unit 21 exports the first signal G1 of high potential, second shifting deposit unit 22 starts under the first signal G1 of high potential drives, but now receive inverting clock signal CLK2 due to the transistor seconds P2 of the second shifting deposit unit 22, then its outfan GOUT still exports secondary signal G2 of electronegative potential.
Within the t3 period, enabling signal STV keeps electronegative potential, and clock signal clk 1 saltus step is electronegative potential, and inverting clock signal CLK2 saltus step is high potential.The first transistor T1 ends.
It is appreciated that, after second shifting deposit unit 22 starts under the first signal G1 of this high potential drives, making the second reference signal Ra2 is high potential, then transistor seconds P2 conducting, the inverting clock signal CLK2 of the high potential that its source electrode receives exports to outfan GOUT, so that secondary signal G2 is high potential.
The first transistor T1 is still within cut-off state, the grid of the 8th transistor T8 controls end Vc1 from first and receives secondary signal G2 of high potential, 8th transistor T8 conducting, source electrode exports to reference voltage end Va being electrically connected with that drains with it from the low-potential signal VEE that external circuit receives, and the first reference signal Ra1 saltus step of reference voltage end Va output is electronegative potential.
First reference signal Ra1 saltus step is electronegative potential, transistor seconds T2 ends, the grid of the 9th transistor T9 controls, from second, the second reference signal Ra2 that end Vc2 receives the high potential of the second shifting deposit unit 22 output, 9th transistor T9 conducting, the first signal G1 saltus step that the low-potential signal VEE output that its source terminal receives from external circuit exports to outfan GOUT, outfan GOUT is electronegative potential.The first equal saltus step in electric capacity C1 two ends is electronegative potential, the first electric capacity C1 electric discharge.
Owing to the first reference signal Ra1 saltus step is electronegative potential, then the 5th transistor T5 and the tenth two-transistor T12 cut-off in control circuit 214, secondary nodal point Vb2 suspension joint, and due to the control of the second electric capacity C2 subject clock signal CLK1 electronegative potential, secondary nodal point Vb2 is clamped to electronegative potential.Secondary nodal point Vb2 is electronegative potential, the 6th transistor T6 cut-off.The grid of the 7th transistor T7 receives the inverting clock signal CLK2 of high potential, the 7th transistor T7 conducting, its source electrode from the low-potential signal VEE that external circuit receives export to primary nodal point Vb1, primary nodal point Vb1 be electronegative potential.
For signal output apparatus 213, owing to primary nodal point Vb1 is the cut-off of electronegative potential, then third transistor T3 and the tenth transistor T10.Owing to now inverting clock signal CLK2 is high potential, 4th transistor T4 and the 11st transistor T11 conducting, the source electrode of the 4th transistor T4 exports to outfan GOUT from the low-potential signal VEE that external circuit receives, and then ensure that the first signal G1 is in electronegative potential, enabling signal STV that 8th transistor T8 source electrode receives is now electronegative potential, and then ensures that the first reference signal Ra1 is in electronegative potential.
Within the t4 period, enabling signal STV keeps electronegative potential, and clock signal clk 1 saltus step is high potential, and inverting clock signal CLK2 saltus step is electronegative potential.The first transistor T1 ends.
It is appreciated that, time period, in second shifting deposit unit 22, the first transistor P1 ends under the control of the first signal G1 of electronegative potential, turn under the signal (infer to understand and export for high potential) that 8th transistor P8 is exported at a rear shifting deposit unit outfan, then the second reference signal Ra2 saltus step of reference voltage end Va is electronegative potential, 9th transistor P9 and the 4th transistor P4 is both turned on, then the secondary signal G2 saltus step of outfan GOUT output is electronegative potential.
Receiving secondary signal G2 of the second shifting deposit unit 22 output owing to the grid of the 8th transistor T8 controls end Vc1 from first, now, secondary signal G2 is electronegative potential, then transistor seconds T2 cut-off, and the second reference signal Ra2 is maintained at electronegative potential.
In signal input circuit 212, the first reference signal Ra1 is electronegative potential, and transistor seconds T2 ends.Owing to the grid of the 9th transistor T9 controls the second reference signal Ra2 that end Vc2 receives the electronegative potential of the second shifting deposit unit 22, then the 9th transistor T9 cut-off from second.
Owing to the first reference signal Ra1 is the cut-off of electronegative potential, then the 5th transistor T5 and the tenth two-transistor T12.Owing to clock signal clk 1 is high potential, second electric capacity C2 is charged, the voltage of secondary nodal point Vb2 raises, but voltage difference when charging in there remains the t2 time due to the second electric capacity C2, then the current potential of secondary nodal point Vb2 is less than the high potential of clock signal clk 1, the 1/2 of for example, CLK1 voltage.Owing to secondary nodal point Vb2 is high potential, the 6th transistor T6 conducting, its source electrode receives clock signal clk 1, and clock signal clk 1 is high potential this moment, then the primary nodal point Vb1 being connected that drains with it is also for high potential.The now voltage of the primary nodal point Vb1 voltage more than secondary nodal point Vb2.Inverting clock signal CLK2 is electronegative potential, then the 7th transistor T7 cut-off, thus prevents the low-potential signal VEE of external circuit from the voltage of primary nodal point Vb1 is produced interference.Visible, in boosted switch 215, the 6th transistor T6 and the 7th transistor T7 is under the high potential of secondary nodal point Vb2 controls, and in primary nodal point Vb1 output higher than the high potential of secondary nodal point Vb2 voltage, is raised by the voltage of secondary nodal point Vb2.Subsequent time period, clock signal clk 1 is electronegative potential, and when inverting clock signal CLK2 is high potential, primary nodal point Vb1 is electronegative potential, then boosted switch 215 exports identical electronegative potential at secondary nodal point Vb2.
In signal output apparatus 213, owing to primary nodal point Vb1 is the conducting of high potential, then third transistor T3 and the tenth transistor T10.The low-potential signal VEE output of third transistor T3 source electrode is electronegative potential to outfan GOUT, the first signal G1.The low-potential signal VEE of the tenth transistor T10 source electrode exports to reference voltage end Va, is further ensured that the first reference signal Ra1 is electronegative potential.The grid of the 4th transistor T4 and the 11st transistor T11 all receives inverting clock signal CLK2, owing to now inverting clock signal CLK2 is electronegative potential, and the 4th transistor T4 and the 11st transistor T11 cut-off.
In being appreciated that the time period thereafter, owing to enabling signal STV will maintain low-potential signal, clock signal clk 1 and inverting clock signal CLK2 alternately saltus step are high and low current potential, then the first shifting deposit unit 21 alternately presents the duty of t3 Yu t4 period.
Specifically, enabling signal STV is continuously electronegative potential, then the first transistor T1, the 8th transistor T8, transistor seconds T2 and the 9th transistor T9 are turned off, and the first reference signal Ra1 remains electronegative potential, then the 5th transistor T5 and the tenth two-transistor T12 will persistently end.
When clock signal CLK1 is electronegative potential, and when inverting clock signal CLK2 is high potential, the second electric capacity C2 clamper secondary nodal point Vb2 is electronegative potential, the 6th transistor T6 cut-off；7th transistor T7 conducting, primary nodal point Vb1 is electronegative potential, third transistor T3 and the tenth transistor T10 cut-off, the 4th transistor T4 and the 11st transistor T11 conducting, the first signal G1 of outfan GOUT output electronegative potential；
When clock signal CLK1 is high potential, and inverting clock signal CLK2 is when being electronegative potential, second electric capacity C2 charging, secondary nodal point Vb2 is high potential, the 6th transistor T6 conducting, and primary nodal point Vb1 is high potential, third transistor T3 and the tenth transistor T10 conducting, first signal G1, the 4th transistor T4 and the 11st transistor T11 cut-off of outfan GOUT output electronegative potential, prevents low-potential signal from the first signal G1 is produced interference.
It addition, the working method of the second shifting deposit unit 22 and sequential are all identical with the first shifting deposit unit 21, present embodiment repeats no more.
Compared to prior art, from work schedule and circuit structure, within the t4 period, owing to secondary nodal point Vb2 is connected to primary nodal point Vb1 by the 6th transistor T6 in boosted switch 215 and the 7th transistor T7, when secondary nodal point Vb2 is electronegative potential, 6th transistor T6 cut-off, the 7th transistor T7 conducting so that primary nodal point Vb1 is also electronegative potential；When secondary nodal point Vb2 is high potential, 6th transistor T6 conducting, 7th transistor T7 ends under the control of inverting clock signal CLK2, making primary nodal point Vb1 is the ratio secondary nodal point higher high potential of Vb2 voltage, thus more accurately with open third transistor T3 and the tenth transistor T10 fully, make the first signal G1 of now electronegative potential consistent with the electronegative potential in other moment, such as consistent with the electronegative potential that transistor seconds T2 and the 4th transistor T4 exports.
Separately, the tenth two-transistor T12 and the 5th transistor T5 synchronizes conducting and cut-off, is further ensured that the voltage of primary nodal point Vb1 and secondary nodal point Vb2 is simultaneously for electronegative potential.
Separately, owing to being provided with the 9th transistor T9, and grid receives the voltage of next adjacent shifting deposit unit reference edge, thus ensures that the first signal G1 is stable at high potential in the t2 period；In the t3 period, it is ensured that the first signal G1 is stable at electronegative potential, thus effectively assists the first signal G1 of output to export the more stable signal of telecommunication.
Changing ground, the 8th transistor T8, the 9th transistor T9, the tenth transistor T10, the 11st transistor T11 and the tenth two-transistor T12 all can omit.
Refer to Fig. 5, be the structural representation of the liquid crystal indicator applying this shift register 20.This liquid crystal indicator 30 includes display panels 31, data drive circuit 32 and scan drive circuit 33.This display panels 31 includes the liquid crystal layer (not shown) that a upper substrate (not shown), an infrabasal plate (not shown) and are clamped between upper substrate and infrabasal plate, and is provided with one for controlling the thin film transistor (TFT) array (not shown) of liquid crystal molecule torquing condition at this infrabasal plate adjacent to liquid crystal layer side.This scan drive circuit 33 output scanning signal is to control conducting and the cut-off state of the thin film transistor (TFT) array of this display panels 31, and this data drive circuit 32 outputting data signals controls this display panels 31 display variation.This scan drive circuit 33 utilizes this shift register 20 to control the output timing of scanning signal, thus controls the display of this display panels 31.This shift register 20 can be formed under same manufacturing process with the thin film transistor (TFT) array of this liquid crystal indicator 30.
Claims (10)
1. a shift register, it includes multiple shifting deposit unit, it is characterized in that: two clock signal phases that two adjacent shifting deposit units are received are contrary, contrary the first clock signal of each shifting deposit unit receiving phase and second clock signal, and each shifting deposit unit all includes enabling signal input, start-up circuit, signal input circuit, signal output apparatus, control circuit, reference voltage end and outfan, this start-up circuit is for receiving an enabling signal, it includes the first transistor, this the first transistor receives this enabling signal from this enabling signal input, and export to this reference voltage end, the voltage of this reference voltage end is used for starting this signal input circuit；This signal input circuit receives this first clock signal, it includes transistor seconds and the first electric capacity, this transistor seconds receives this first clock signal, and exports this first clock signal to this outfan, and this first electric capacity is electrically connected between this reference voltage end and this outfan；nullThis signal output apparatus includes third transistor and the 4th transistor，This third transistor is on or off under the control of this control circuit，4th transistor on or off under the control of this second clock signal，This third transistor and the 4th transistor export low-potential signal to this outfan when conducting state，The signal of this outfan output is as the enabling signal of a rear shifting deposit unit，This control circuit is for controlling the on or off of this third transistor，Including the 5th transistor、Second electric capacity、Primary nodal point、Secondary nodal point and boosted switch，This second electric capacity one end receives this first clock signal，The other end is electrically connected at this secondary nodal point，5th transistor on or off under the control of this reference voltage end，5th transistor one end is electrically connected at this secondary nodal point，The other end receives a low-potential signal，This boosted switch exports high potential signal or low-potential signal respectively to this primary nodal point under the voltage of this secondary nodal point and the control of second clock signal，This signal output apparatus also includes the tenth transistor，The grid of the tenth transistor and the grid of this third transistor are electrically connected with and are connected to this primary nodal point，Drain electrode is electrically connected at this reference voltage end，Source electrode receives the low-potential signal of external circuit output，When this secondary nodal point is high potential，The output of this boosted switch is higher than the high potential signal of this secondary nodal point voltage to this primary nodal point，When this secondary nodal point is electronegative potential，This boosted switch exports a low-potential signal to this primary nodal point.
2. shift register as claimed in claim 1, it is characterized in that, this boosted switch includes the 6th transistor AND gate the 7th transistor, the grid of the 6th transistor is electrically connected at this secondary nodal point, source electrode receives this first clock signal, and drain electrode is electrically connected at this primary nodal point, and the grid of the 7th transistor receives this second clock signal, source electrode receives the low-potential signal that external circuit provides, and drain electrode is electrically connected at this primary nodal point.
3. shift register as claimed in claim 2, it is characterised in that each shifting deposit unit is to be made up of multiple transistors.
4. shift register as claimed in claim 3, it is characterised in that this transistor is nmos type transistor.
5. shift register as claimed in claim 3, it is characterized in that, this start-up circuit also includes the 8th transistor, 8th this first transistor of transistor AND gate series connection, its drain electrode is electrically connected at this reference voltage end, source electrode receives the low-potential signal of external circuit output, and grid is electrically connected at this rear shifting deposit unit outfan, and the 8th transistor is on or off under the control of the signal of this rear shifting deposit unit outfan output.
6. shift register as claimed in claim 3, it is characterized in that, this signal input circuit also includes the 9th transistor, 9th this transistor seconds of transistor AND gate series connection, drain electrode is electrically connected at this outfan, source electrode receives this first clock signal, and grid is electrically connected at the reference voltage end of this rear shifting deposit unit, and on or off under the Control of Voltage of this rear shifting deposit unit reference voltage end.
7. shift register as claimed in claim 3, it is characterized in that, this signal output apparatus also includes the 11st transistor, the drain electrode of the 11st transistor is electrically connected at this reference voltage end, source electrode receives this enabling signal that external circuit provides, grid receives this second clock signal, and on or off under the control of this second clock signal.
8. shift register as claimed in claim 1, it is characterized in that, this signal output apparatus also includes the 11st transistor, the drain electrode of the 11st transistor is electrically connected at this reference voltage end, source electrode receives this enabling signal that external circuit provides, grid receives this second clock signal, and on or off under the control of this second clock signal.
9. shift register as claimed in claim 3, it is characterized in that, this control circuit also includes the tenth two-transistor, the grid of the tenth two-transistor is electrically connected with the grid of the 5th transistor, and it is connected to this reference voltage end, the drain electrode of the tenth two-transistor is electrically connected at this primary nodal point, and source electrode receives the low-potential signal of external circuit output.
10. a liquid crystal indicator, it includes a liquid crystal panel and at least scan driving circuit, and this scan drive circuit includes a shift register, it is characterised in that: this shift register is the shift register in claim 1 to 9 described in any one.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210589418.1A CN103021321B (en) | 2012-12-29 | 2012-12-29 | Shift register and liquid crystal indicator |
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| CN201210589418.1A CN103021321B (en) | 2012-12-29 | 2012-12-29 | Shift register and liquid crystal indicator |
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| CN103021321B true CN103021321B (en) | 2016-08-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104123918B (en) * | 2013-06-11 | 2016-06-29 | 深超光电（深圳）有限公司 | Shift register and liquid crystal indicator |
| CN104575354B (en) * | 2014-12-31 | 2017-02-22 | 上海天马微电子有限公司 | Grid driving circuit and driving method thereof |
| CN105489245B (en) * | 2015-11-24 | 2019-05-24 | 上海天马有机发光显示技术有限公司 | Shifting deposit unit, shift register and its driving method and display device |
| CN107863057B (en) * | 2017-10-31 | 2020-12-18 | 上海天马微电子有限公司 | Shift register, driving method thereof, driving control circuit and related device |
| CN111583880B (en) * | 2019-02-18 | 2021-08-24 | 合肥京东方光电科技有限公司 | Shift register unit circuit, driving method, gate driver and display device |
| WO2021000272A1 (en) * | 2019-07-02 | 2021-01-07 | 京东方科技集团股份有限公司 | Shift register unit, driving method therefor, and apparatus |
| CN111508433B (en) | 2020-05-28 | 2021-08-31 | 京东方科技集团股份有限公司 | Signal generation circuit, signal generation method, signal generation module and display device |
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| CN103021321A (en) | 2013-04-03 |
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