CN110364121A - Scanning circuit, display panel and display device - Google Patents
Scanning circuit, display panel and display device Download PDFInfo
- Publication number
- CN110364121A CN110364121A CN201910569536.8A CN201910569536A CN110364121A CN 110364121 A CN110364121 A CN 110364121A CN 201910569536 A CN201910569536 A CN 201910569536A CN 110364121 A CN110364121 A CN 110364121A
- Authority
- CN
- China
- Prior art keywords
- transistor
- node
- electrically connected
- signal input
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of scanning circuit, display panel and display devices.The scanning circuit includes input module, the first output module, the second output module, the first output control module, the second output control module, first node, second node, the first clock signal input terminal, second clock signal input part, the first electric potential signal input terminal, the second electric potential signal input terminal, shift signal input terminal and scanning signal output end.Input module is used to control the current potential of first node；First node controls the on state of the first output module；Second node controls the on state of the second output module；The on state of first output module and the second output module determines the output state of the scanning signal of scanning signal output end.The embodiment of the invention provides a kind of structure of new scanning circuit, the shift function of the shift signal to the input of shift signal input terminal is realized, and exports stable scanning signal in scanning signal output end.
Description
Technical field
The present embodiments relate to display technology more particularly to a kind of scanning circuits, display panel and display device.
Background technique
The display panel of numerous types is had developed both at home and abroad, for example, organic light emitting display panel (Organic Light-
Emitting Diode, OLED) and liquid crystal display panel (Liquid Crystal Display, LCD) etc..Display panel packet
It includes: pixel, the scan line being connect with every row pixel and the scanning circuit that driving signal is sent to scan line.Therefore, scanning circuit
The stability of the scanning signal of output has direct influence to the display of pixel.Since stability of the people to scanning circuit needs
Ask higher and higher, scanning circuit is designed to developer's one of main research tendency now.
Summary of the invention
The present invention provides a kind of scanning circuit, display panel and display device, so that scanning circuit exports stable scanning
Signal.
To realize the above-mentioned technical purpose, the embodiment of the invention provides following technical solutions:
A kind of scanning circuit, including input module, the first output module, the second output module, the first output control module,
Second output control module, first node, second node, the first clock signal input terminal, second clock signal input part, first
Electric potential signal input terminal, the second electric potential signal input terminal, shift signal input terminal and scanning signal output end；
The input module and the first node, first clock signal input terminal and the shift signal input terminal
Electrical connection, the input module are used to control the current potential of the first node；
First output control module and the first node, second node, the first electric potential signal input terminal and second
Clock signal input terminal electrical connection；First output control module is used to control the current potential of the first node, and described first
The on state of first output module described in node control；
Second output control module and the first node, second node, the second electric potential signal input terminal and first
Clock signal input terminal electrical connection；Second output control module is used to control the current potential of the second node, and described second
The on state of second output module described in node control；
First output module and the first node, the second clock signal input part and the scanning signal are defeated
Outlet electrical connection；During the first output module conducting, the signal of the second clock signal input part input is transmitted to institute
State scanning signal output end；
Second output module and the second node, the first electric potential signal input terminal and the scanning signal are defeated
Outlet electrical connection；During the second output module conducting, the signal of the first electric potential signal input terminal input is transmitted to institute
State scanning signal output end.
It can be seen from the above technical proposal that the embodiment of the present invention is by providing a kind of structure of new scanning circuit, it is real
The shift function of the shift signal to the input of shift signal input terminal is showed.And due to during the driving of scanning circuit,
Input module, the first output module, the second output module, the first output control module and the second output control module conducting shape
State and off state are stablized, and the current potential of first node and second node is stablized, and therefore, scanning signal output end exports stable sweep
Retouch signal.
Optionally, the input module includes the first transistor, when the control terminal of the first transistor is with described first
The electrical connection of clock signal input part, the first end of the first transistor are electrically connected with the shift signal input terminal, and described first
The second end of transistor is electrically connected with the first node.
Wherein, the structure of transistor is simple, and manufacture craft is simple.It, can when the scanning circuit is applied to display panel
To be made, the transistor in scanning circuit to save in same process flow with the transistor on display panel
Process flow, reduces costs.Therefore, setting of embodiment of the present invention input module includes the first transistor, is advantageously reduced
The cost of manufacture of display panel.
Optionally, the first transistor is double-gated transistor.Wherein, the first transistor can be equivalent to two transistors
Cascaded structure, have stronger electric leakage rejection ability.The first transistor is set double-gated transistor by the embodiment of the present invention can
To reduce the leakage current of input module, the current potential of first node is maintained to stablize.
Optionally, first output control module includes second transistor and third transistor；
The control terminal of the second transistor is electrically connected with the second node, the first end of the second transistor and institute
The electrical connection of the first electric potential signal input terminal is stated, the second end of the second transistor and the first end of the third transistor are electrically connected
It connects；
The control terminal of the third transistor is electrically connected with the second clock signal input part, the third transistor
Second end is electrically connected with the first node.
Wherein, the structure of transistor is simple, and manufacture craft is simple.It, can when the scanning circuit is applied to display panel
To be made, the transistor in scanning circuit to save in same process flow with the transistor on display panel
Process flow, reduces costs.Therefore, it includes second transistor and that the first output control module, which is arranged, in the embodiment of the present invention
Three transistors advantageously reduce the cost of manufacture of display panel.
Optionally, second output control module includes the 4th transistor and the 5th transistor；
The control terminal of 4th transistor is electrically connected with the first node, the first end of the 4th transistor and institute
The electrical connection of the first clock signal input terminal is stated, the second end of the 4th transistor is electrically connected with the second node；
The control terminal of 5th transistor is electrically connected with first clock signal input terminal, the 5th transistor
First end is electrically connected with the second electric potential signal input terminal, and the second end of the 5th transistor is electrically connected with the second node
It connects.
Wherein, the structure of transistor is simple, and manufacture craft is simple.It, can when the scanning circuit is applied to display panel
To be made, the transistor in scanning circuit to save in same process flow with the transistor on display panel
Process flow, reduces costs.Therefore, it includes the 4th transistor and that the second output control module, which is arranged, in the embodiment of the present invention
Five transistors advantageously reduce the cost of manufacture of display panel.
Optionally, first output module includes:
The control terminal of 6th transistor, the 6th transistor is electrically connected with the first node, the 6th transistor
First end be electrically connected with the second clock signal input part, the second end and the scanning signal of the 6th transistor are defeated
Outlet electrical connection；
First capacitor, the first end of the first capacitor are electrically connected with the control terminal of the 6th transistor, and described first
The second end of capacitor is electrically connected with the second end of the 6th transistor.
Wherein, the structure of transistor is simple, and manufacture craft is simple.It, can when the scanning circuit is applied to display panel
To be made, the transistor in scanning circuit to save in same process flow with the transistor on display panel
Process flow, reduces costs.The pole plate that capacitor is oppositely arranged by two is constituted, since display panel generally comprises multiple films
Layer, two pole plates of capacitor can be respectively arranged in two film layers, manufacture craft is simple, and cost is relatively low.Therefore, of the invention
It includes the 6th transistor and first capacitor that the first output module, which is arranged, in embodiment, advantageously reduces the cost of manufacture of display panel.
Optionally, second output module includes:
The control terminal of 7th transistor, the 7th transistor is electrically connected with the second node, the 7th transistor
First end be electrically connected with the first electric potential signal input terminal, the second end and the scanning signal of the 7th transistor are defeated
Outlet electrical connection；
Second capacitor, the first end of second capacitor are electrically connected with the control terminal of the 7th transistor, and described second
The second end of capacitor is electrically connected with the second end of the 7th transistor.
Wherein, the structure of transistor is simple, and manufacture craft is simple.It, can when the scanning circuit is applied to display panel
To be made, the transistor in scanning circuit to save in same process flow with the transistor on display panel
Process flow, reduces costs.The pole plate that capacitor is oppositely arranged by two is constituted, since display panel generally comprises multiple films
Layer, two pole plates of capacitor can be respectively arranged in two film layers, manufacture craft is simple, and cost is relatively low.Therefore, of the invention
It includes the 7th transistor and the second capacitor that the second output module, which is arranged, in embodiment, advantageously reduces the cost of manufacture of display panel.
It optionally, further include the 8th transistor, the control terminal of the 8th transistor and second electric potential signal input
End electrical connection, the first end of the 8th transistor is electrically connected with the first node, the second end of the 8th transistor and
The first output module electrical connection.Wherein, the 8th transistor is set between first node and the first output module, is played point
Pressure effect, to reduce leakage current of the first node to the first output module.In addition, the 8th transistor can also obstruct low potential by
One output module is transmitted in the first output control module and input module, is prevented in the first output control module and input module
Transistor damage.
Optionally, scanning circuit further include the 6th transistor described in the 8th transistor by the 8th transistor with it is described
First node electrical connection, wherein the control terminal of the 8th transistor is electrically connected with the second electric potential signal input terminal, described
The first end of 8th transistor is electrically connected with the first node, the second end of the 8th transistor and the 6th transistor
Control terminal electrical connection.Wherein, the 8th transistor is set between first node and the 6th transistor, plays the role of partial pressure, with
Reduce control terminal leakage current of the first node to the 6th transistor.
Correspondingly, the embodiment of the invention also provides a kind of display panel, which includes at least two such as this hair
Scanning circuit described in bright any embodiment, the first clock cable, second clock signal wire, the first electric potential signal line, second
Electric potential signal line and enabling signal line；
First clock signal input terminal of the scanning circuit is electrically connected with first clock cable, when described second
Clock signal input part is electrically connected with the second clock signal wire, and the first electric potential signal input terminal and first current potential are believed
The electrical connection of number line, the second electric potential signal input terminal are electrically connected with the second electric potential signal line；
At least two scanning circuit cascade connections, the shift signal input terminal of scanning circuit described in the first order with it is described
The electrical connection of enabling signal line；The displacement of scanning circuit described in the scanning signal output end and rear stage of scanning circuit described in previous stage
Signal input part electrical connection.
Wherein, first order scanning circuit shifts the enabling signal on enabling signal line, and is exported by its scanning signal
End output.The scanning signal that rear stage scanning circuit exports previous stage scanning circuit shifts, and exports.For example, the second level is swept
The shift signal input terminal of scanning circuit is electrically connected with the scanning signal output end of first order scanning circuit, by first order scanning circuit
The scanning signal of output is shifted and is exported.Therefore, display panel provided in an embodiment of the present invention realizes output scanning letter line by line
Number function, and scanning circuit at different levels exports stable scanning signal.
Correspondingly, the embodiment of the invention also provides a kind of display device, which includes as the present invention is any real
Apply display panel described in example.
The embodiment of the invention provides a kind of scanning circuit, display panel and display device, which includes input
Module, the first output module, the second output module, the first output control module, the second output control module, first node,
Two nodes, the first clock signal input terminal, second clock signal input part, the first electric potential signal input terminal, the second electric potential signal
Input terminal, shift signal input terminal and scanning signal output end are realized to the shift signal of shift signal input terminal input
Shift function.And due to during the driving of scanning circuit, input module, the first output module, the second output module,
The on state and off state of first output control module and the second output control module are stablized, first node and second node
Current potential stablize, therefore, scanning signal output end exports stable scanning signal.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of scanning circuit provided in an embodiment of the present invention；
Fig. 2 is a kind of driver' s timing figure of scanning circuit provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；
Fig. 6 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；
Fig. 7 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；
Fig. 8 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；
Fig. 9 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；
Figure 10 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention；
Figure 11 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Fig. 1 is a kind of structural schematic diagram of scanning circuit provided in an embodiment of the present invention.Referring to Fig. 1, the scanning circuit packet
It includes: input module 100, the first output module 200, the second output module 300, the output control of the first output control module 400, second
Molding block 500, first node N1, second node N2, the first clock signal input terminal 101, second clock signal input part 102,
First electric potential signal input terminal 201, the second electric potential signal input terminal 202, shift signal input terminal 301 and scanning signal output end
401。
Input module 100 and first node N1, the first clock signal input terminal 101 and shift signal input terminal 301 are electrically connected
It connects, input module 100 is used to control the current potential of first node N1.
First output control module 400 and first node N1, second node N2, the first electric potential signal input terminal 201 and the
The electrical connection of two clock signal input terminals 102；First output control module 400 is used to control the current potential of first node N1, first segment
Point N1 controls the on state of the first output module 200.
Second output control module 500 and first node N1, second node N2, the second electric potential signal input terminal 202 and the
The electrical connection of one clock signal input terminal 101；Second output control module 500 is used to control the current potential of second node N2, the second section
Point N2 controls the on state of the second output module 300.
First output module 200 and first node N1, second clock signal input part 102 and scanning signal output end 401
Electrical connection；During first output module 200 is connected, the signal that second clock signal input part 102 inputs is transmitted to scanning signal
Output end 401.
Second output module 300 and second node N2, the first electric potential signal input terminal 201 and scanning signal output end 401
Electrical connection；During second output module 300 is connected, the signal of the first electric potential signal input terminal 201 input is transmitted to scanning signal
Output end 401.
Wherein, input module 100 and the first output control module 400 control the by controlling the current potential of first node N1
The on state of one output module 200.Second output control module 500 controls second by controlling the current potential of second node N2
The on state of output module 300.The on state of first output module 200 and the second output module 300 determines scanning letter
The current potential for the scanning signal that number output end 401 exports.
Fig. 2 is a kind of driver' s timing figure of scanning circuit provided in an embodiment of the present invention.It can be used for driving shown in FIG. 1 sweep
Scanning circuit, referring to Fig. 1 and Fig. 2, illustratively, the first clock signal input terminal 101 input the first clock signal SCK1, when second
Clock signal input part 102 inputs second clock signal SCK2, and the first electric potential signal input terminal 201 inputs the first electric potential signal VGH,
Second electric potential signal input terminal 202 inputs the second electric potential signal VGL, and shift signal input terminal 301 inputs shift signal SIN.For
Show clearly that the signal type of each signal input part input, Fig. 1 is by the signal type table of the corresponding input of each signal input part
Show in bracket.Using the first electric potential signal VGH as high potential, it is example that the second electric potential signal VGL, which is low potential,.The scanning circuit
Driving method include following several stages, respectively first stage T1, second stage T2, phase III T3, fourth stage T4,
5th stage T5, the 6th stage T6, the 7th stage T7, the 8th stage T8 and the 9th stage T9.
First stage T1, the first clock signal SCK1 of the first clock signal input terminal 101 input are low potential, displacement letter
The shift signal SIN that number input terminal 301 inputs is low potential, the second clock signal that second clock signal input part 102 inputs
SCK2 is high potential.Input module 100 responds the low potential of the first clock signal SCK1 and is connected, by the low of shift signal SIN
Current potential is transmitted to first node N1, and the current potential of first node N1 is low potential.Second output control module 500 responds first node
The low potential of N1 and be connected, the second electric potential signal VGL is transmitted to second node N2, the current potential of second node N2 is low potential.
First output module 200 is stored and is connected in response to the low potential of first node N1, by the high potential of second clock signal SCK2
It is transmitted to scanning signal output end 401.Second output module 300 is stored and is connected in response to the low potential of second node N2, will
First electric potential signal VGH is transmitted to scanning signal output end 401.Scanning signal output end 401 export scanning signal Scan with
First electric potential signal VGH is consistent, while scanning signal Scan is also consistent with second clock signal SCK2, exports high level.
Second stage T2, the first clock signal SCK1 and shift signal SIN are high potential.The response of input module 100 the
The high potential of one clock signal SCK1 and turn off.Since the first output module 200 stores low potential, the first output module 200
Under the control of the low potential, continue to be connected in second stage T2, second clock signal SCK2 is transmitted to scanning signal output
End 401.And first output module 200 to maintain first node N1 simultaneously be low potential.Second output control module 500 response first
The low potential of node N1 and be connected, the high potential of the first clock signal is transmitted to second node N2, second node N2 is high electricity
Position.Second output module 300 is stored and is turned off in response to the high potential of second node N2.What scanning signal output end 401 exported
Scanning signal Scan is consistent with second clock signal SCK2.When second clock signal SCK2 exports low level, scanning signal Scan
It also is low level；When second clock signal SCK2 exports high level, scanning signal Scan is also high level.
Phase III T3, the first clock signal SCK1 are low potential, and second clock signal SCK2 and shift signal SIN are height
Current potential.Input module 100 responds the low potential of the first clock signal SCK1 and is connected, and the high potential of shift signal SIN is transmitted
It is high potential to first node N1, first node N1.First output module 200 storage and in response to the high potential of first node N1 and
Shutdown.Second output control module 500 responds the low potential of the first clock signal SCK1 and is connected, by the second electric potential signal VGL
It is transmitted to second node N2, the current potential of second node N2 is low potential.Second output module 300 stores and responds second node N2
Low potential and be connected, the first electric potential signal VGH is transmitted to scanning signal output end 401.Scanning signal output end 401 exports
Scanning signal Scan it is consistent with the first electric potential signal VGH, export high level.
Fourth stage T4, the first clock signal SCK1, second clock signal SCK2 and shift signal SIN are high potential.
Since the first output module 200 stores high potential, the first output module 200 is under the control of the high potential, in fourth stage
T4 is persistently turned off.Since the second output module 300 stores low potential, the second output module 300 under the control of the low potential,
In fourth stage T4 constant conduction, the first electric potential signal VGH is transmitted to scanning signal output end 401.Scanning signal output end
The scanning signal Scan of 401 outputs is consistent with the first electric potential signal VGH, exports high level.
5th stage T5, the first clock signal SCK1 and shift signal SIN are high potential, and second clock signal SCK2 is
Low potential.Since the second output module 300 stores low potential, the second output module 300 continues to be connected in the 5th stage T5, and
First output control module 400 is connected in response to the low potential of second clock signal SCK2 and the low potential of second node N2, will
First electric potential signal VGH is transmitted to first node N1.First output module 200 is held off.First output module 200 persistently closes
It is disconnected, 300 constant conduction of the second output module, the scanning signal Scan and the first electric potential signal that scanning signal output end 401 exports
VGH is consistent, exports high level.
The state of 6th stage T6, each input signal are identical as fourth stage T4, therefore, the state and fourth order of each module
Section T4 is identical, and the scanning signal Scan that scanning signal output end 401 exports is consistent with the first electric potential signal VGH, exports high level.
The state of 7th stage T7, each input signal are identical as phase III T3, therefore, the state of each module and third rank
Section T3 is identical, and the scanning signal Scan that scanning signal output end 401 exports is consistent with the first electric potential signal VGH, exports high level.
The state of 8th stage T8, each input signal are identical as fourth stage T4, therefore, the state and fourth order of each module
Section T4 is identical, and the scanning signal Scan that scanning signal output end 401 exports is consistent with the first electric potential signal VGH, exports high level.
9th stage T9 and its stage later, circulating repetition phase III T3, fourth stage T4, the 5th stage T5,
Six stage T6, the 7th stage T7 and the 8th stage T8.
The embodiment of the present invention is realized by providing a kind of structure of new scanning circuit to shift signal input terminal 301
The shift function of the shift signal SIN of input.And due to during the driving of scanning circuit, input module 100, first
Output module 200, the second output module 300, the first output control module 400 and the second output control module 500 conducting shape
State and off state are stablized, and the current potential of first node N1 and second node N2 are stablized, and therefore, scanning signal output end 401 exports
Stable scanning signal Scan.
It should be noted that in the above-described embodiments, schematically illustrating the first electric potential signal is high potential, the second electricity
Position signal is low potential, and the first clock signal, second clock signal and shift signal are that low potential is effective, not to of the invention
It limits.In other embodiments, can also be arranged the first electric potential signal be low potential, the second electric potential signal be high potential, first
Clock signal, second clock signal and shift signal are that high potential is effective.It can according to need and set in practical applications.
Fig. 3 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 3, in above-mentioned each reality
On the basis of applying example, optionally, input module includes the first transistor M1, and the control terminal of the first transistor M1 and the first clock are believed
Number input terminal 101 is electrically connected, and the first end of the first transistor M1 is electrically connected with shift signal input terminal 301, the first transistor M1
Second end be electrically connected with first node N1.The first transistor M1 responds the current potential of the first clock signal SCK1 and is connected or closes
It is disconnected, and in conducting, shift signal SIN is transmitted to first node N1.The first transistor M1 for example can be P-type transistor or
N-type transistor.Illustratively, the first transistor M1 is P-type transistor, and the first transistor M1 responds the first clock signal SCK1's
Low potential and be connected, shift signal SIN is transmitted to first node N1.
Wherein, the structure of transistor is simple, and manufacture craft is simple.It, can when the scanning circuit is applied to display panel
To be made, the transistor in scanning circuit to save in same process flow with the transistor on display panel
Process flow, reduces costs.Therefore, setting of embodiment of the present invention input module includes the first transistor M1, is conducive to drop
The cost of manufacture of low display panel.
With continued reference to Fig. 3, on the basis of the various embodiments described above, optionally, the first transistor M1 is double-gated transistor.Its
In, the first transistor M1 can be equivalent to the cascaded structure of transistor M1a and transistor M1b, have stronger electric leakage rejection ability.
The first transistor M1 is set double-gated transistor by the embodiment of the present invention can reduce the leakage current of input module, maintain first segment
The current potential of point N1 is stablized.
Fig. 4 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to fig. 4, in above-mentioned each reality
On the basis of applying example, optionally, the first output control module 400 includes second transistor M2 and third transistor M3.Second is brilliant
The control terminal of body pipe M2 is electrically connected with second node N2, the first end of second transistor M2 and the first electric potential signal input terminal 201
Electrical connection, the second end of second transistor M2 are electrically connected with the first end of third transistor M3.The control terminal of third transistor M3
It is electrically connected with second clock signal input part 102, the second end of third transistor M3 is electrically connected with first node N1.
Wherein, second transistor M2 in response to second node N2 current potential and be connected or turn off, third transistor M3 response
The current potential of second clock signal SCK2 and be connected or turn off.And when second transistor M2 and third transistor M3 are both turned on,
First electric potential signal VGH is transmitted to first node N1.Illustratively, second transistor M2 and third transistor M3 is p-type
Transistor, second transistor M2 in response to second node N2 low potential and be connected, third transistor M3 respond second clock signal
The low potential of SCK2 and be connected, shift signal SIN is transmitted to first node N1.It is similar with previous embodiment principle, the present invention
It includes second transistor M2 and third transistor M3 that the first output control module 400, which is arranged, in embodiment, advantageously reduces display surface
The cost of manufacture of plate.
Fig. 5 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 5, in above-mentioned each reality
On the basis of applying example, optionally, the second output control module 500 includes the 4th transistor M4 and the 5th transistor M5.4th is brilliant
The control terminal of body pipe M4 is electrically connected with first node N1, the first end of the 4th transistor M4 and the first clock signal input terminal 101
Electrical connection, the second end of the 4th transistor M4 are electrically connected with second node N2.The control terminal and the first clock of 5th transistor M5
Signal input part 101 is electrically connected, and the first end of the 5th transistor M5 is electrically connected with the second electric potential signal input terminal 202, and the 5th is brilliant
The second end of body pipe M5 is electrically connected with second node N2.Wherein, the 4th transistor M4 in response to first node N1 current potential and be connected
Or shutdown, and in conducting, the first clock signal SCK1 is transmitted to second node N2.Alternatively, the 5th transistor M5 is responded
The current potential of first clock signal SCK1 and be connected or turn off, and conducting when, the second electric potential signal VGL is transmitted to the second section
Point N2.Similar with previous embodiment principle, it includes the 4th transistor M4 that the second output control module 500, which is arranged, in the embodiment of the present invention
With the 5th transistor M5, the cost of manufacture of display panel is advantageously reduced.
Fig. 6 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 6, in above-mentioned each reality
On the basis of applying example, optionally, the first output module 200 includes: the 6th transistor M6 and first capacitor C1.6th transistor M6
Control terminal be electrically connected with first node N1, the first end of the 6th transistor M6 is electrically connected with second clock signal input part 102,
The second end of 6th transistor M6 is electrically connected with scanning signal output end 401.The first end of first capacitor C1 and the 6th transistor
The control terminal of M6 is electrically connected, and the second end of first capacitor C1 is electrically connected with the second end of the 6th transistor M6.
Wherein, the 6th transistor M6 in response to first node N1 current potential and be connected or turn off, and conducting when, by second
Clock signal SCK2 is transmitted to scanning signal output end 401.First capacitor C1 has store function, in the current potential of first node N1
There is the first electric potential signal VGH to store the first electric potential signal VGH or the first clock letter when perhaps the first clock signal SCK1 is inputted
The current potential of number SCK1；When the current potential of first node N1 does not have signal input, maintain first node N1 current potential on last stage
Current potential it is identical.
The structure of transistor is simple, and manufacture craft is simple.When the scanning circuit is applied to display panel, it can will sweep
Transistor in scanning circuit is made, to save technique in same process flow with the transistor on display panel
Process reduces costs.The pole plate that capacitor is oppositely arranged by two is constituted, can since display panel generally comprises multiple film layers
The two of capacitor pole plate to be respectively arranged in two film layers, manufacture craft is simple, and cost is relatively low.Therefore, the present invention is implemented
Example the first output module 200 of setting includes the 6th transistor M6 and first capacitor C1, advantageously reduces being fabricated to for display panel
This.
Fig. 7 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 7, in above-mentioned each reality
On the basis of applying example, optionally, scanning circuit further includes the 8th transistor M8, the control terminal and the second current potential of the 8th transistor M8
Signal input part 202 is electrically connected, and the first end of the 8th transistor M8 is electrically connected with first node N1, and the second of the 8th transistor M8
End is electrically connected with the first output module 200.The 8th transistor M8, which is arranged, in the embodiment of the present invention can reduce first node N1 to the
The control terminal leakage current of six transistor M6.It is transmitted in addition, the 8th transistor M8 can also obstruct low potential by the first output module 200
Into the first output control module 400 and input module 100, prevent in the first output control module 400 and input module 100
Transistor damage.
With continued reference to Fig. 7, on the basis of the various embodiments described above, optionally, the 8th transistor M8 is set to first node
Between N1 and the 6th transistor M6.That is, the 6th transistor M6 is electrically connected by the 8th transistor M8 with first node N1, wherein
The control terminal of 8th transistor M8 is electrically connected with the second electric potential signal input terminal 202, the first end and first of the 8th transistor M8
Node N1 electrical connection, the second end of the 8th transistor M8 are electrically connected with the control terminal of the 6th transistor M6.Wherein, the 8th transistor
M8 is set between first node N1 and the 6th transistor M6, plays the role of partial pressure, to reduce first node N1 to the 6th crystal
The control terminal leakage current of pipe M6.In addition, the grid of the 6th transistor M6 is in some cases due to the needs of the 6th transistor M6 conducting
It is lower to be pulled down to very low current potential (such as -15V or less), in the case, if the grid of the 6th transistor M6 directly connects
It is connected to the first transistor M1 and third transistor M3, the damage of the first transistor M1 and third transistor M3 may be caused, is led to
The 8th transistor M8 of setting is crossed, low potential can be obstructed and be transmitted to the first transistor M1 and third transistor M3, prevent transistor
Damage.
Fig. 8 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 8, in above-mentioned each reality
On the basis of applying example, optionally, the second output module 300 includes: the 7th transistor M7 and the second capacitor C2.7th transistor M7
Control terminal be electrically connected with second node N2, the first end of the 7th transistor M7 is electrically connected with the first electric potential signal input terminal 201,
The second end of 7th transistor M7 is electrically connected with scanning signal output end 401.The first end and the 7th transistor of second capacitor C2
The control terminal of M7 is electrically connected, and the second end of the second capacitor C2 is electrically connected with the second end of the 7th transistor M7.
Wherein, the 7th transistor M7 in response to second node N2 current potential and be connected or turn off, and conducting when, by first
Electric potential signal VGH is transmitted to scanning signal output end 401.Second capacitor C2 has store function, in the current potential of second node N2
There is the first clock signal SCK1 to store the first clock signal SCK1 or the second current potential when perhaps the second electric potential signal VGL is inputted
The current potential of signal VGL；When the current potential of second node N2 does not have signal input, maintain second node N2 current potential on last stage
Current potential it is identical.Similar with previous embodiment principle, it includes the 7th transistor that the second output module 300, which is arranged, in the embodiment of the present invention
M7 and the second capacitor C2, advantageously reduces the cost of manufacture of display panel.
Fig. 9 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 9, optionally, input
Module includes the first transistor M1, and the first output control module 400 includes second transistor M2 and third transistor M3, and second is defeated
Out control module 500 include the 4th transistor M4 and the 5th transistor M5, the first output module 200 include the 6th transistor M6 and
First capacitor C1, the second output module 300 include the 7th transistor M7 and the second capacitor C2, and scanning circuit further includes the 8th crystal
Pipe M8.
The control terminal of the first transistor M1 is electrically connected with the first clock signal input terminal 101, and the first of the first transistor M1
End is electrically connected with shift signal input terminal 301, and the second end of the first transistor M1 is electrically connected with first node N1, the first crystal
Pipe M1 constitutes the input module of scanning circuit.
The control terminal of second transistor M2 is electrically connected with second node N2, the first end of second transistor M2 and the first current potential
Signal input part 201 is electrically connected, and the second end of second transistor M2 is electrically connected with the first end of third transistor M3.Third crystal
The control terminal of pipe M3 is electrically connected with second clock signal input part 102, second end and first node the N1 electricity of third transistor M3
Connection.Second transistor M2 and third transistor M3 constitutes the first output control module of scanning circuit.
The control terminal of 4th transistor M4 is electrically connected with first node N1, the first end and the first clock of the 4th transistor M4
Signal input part 101 is electrically connected, and the second end of the 4th transistor M4 is electrically connected with second node N2.The control of 5th transistor M5
End is electrically connected with the first clock signal input terminal 101,202 electricity of first end and the second electric potential signal input terminal of the 5th transistor M5
Connection, the second end of the 5th transistor M5 are electrically connected with second node N2.4th transistor M4 and the 5th transistor M5 are constituted
Second output control module of scanning circuit.
The control terminal of 8th transistor M8 is electrically connected with the second electric potential signal input terminal 202, and the first of the 8th transistor M8
End is electrically connected with first node N1, and the second end of the 8th transistor M8 is electrically connected with the control terminal of the 6th transistor M6.8th is brilliant
Body pipe M8 constitutes the leakproof flow module of scanning circuit.
The first end of 6th transistor M6 is electrically connected with second clock signal input part 102, and the second of the 6th transistor M6
End is electrically connected with scanning signal output end 401.The first end of first capacitor C1 is electrically connected with the control terminal of the 6th transistor M6, the
The second end of one capacitor C1 is electrically connected with the second end of the 6th transistor M6.6th transistor M6 and first capacitor C1 are constituted and are swept
First output module of scanning circuit.
The control terminal of 7th transistor M7 is electrically connected with second node N2, the first end and the first current potential of the 7th transistor M7
Signal input part 201 is electrically connected, and the second end of the 7th transistor M7 is electrically connected with scanning signal output end 401.Second capacitor C2
First end be electrically connected with the control terminal of the 7th transistor M7, the second end of the second end of the second capacitor C2 and the 7th transistor M7
Electrical connection.7th transistor M7 and the second capacitor C2 constitute the second output module of scanning circuit.
It is P-type transistor, the first electric potential signal VGH as high potential and the second current potential using each transistor in scanning circuit
Signal VGL is for low potential, a kind of driver' s timing of the scanning circuit is as shown in Figure 2.Illustratively, the drive of the scanning circuit
Dynamic method include first stage T1, second stage T2, phase III T3, fourth stage T4, the 5th stage T5, the 6th stage T6,
7th stage T7, the 8th stage T8 and the 9th stage T9.
Wherein, since the control terminal of the 8th transistor M8 connects the second electric potential signal input terminal 202, and the second electric potential signal
VGL remains low potential, therefore, in each stage in, the 8th transistor M8 respond the second electric potential signal VGL low potential and lead
It is logical, so that first node N1 is consistent with the current potential of control terminal of the 6th transistor M6.In addition, due to the 6th transistor M6 conducting
It needs, the grid of the 6th transistor M6 can be pulled down to very low current potential (such as -15V or less) in some cases, in this feelings
Under condition, if the grid of the 6th transistor M6 is directly connected to the first transistor M1 and third transistor M3, may be caused
The damage of one transistor M1 and third transistor M3 can obstruct low potential and be transmitted to first by the way that the 8th transistor M8 is arranged
Transistor M1 and third transistor M3, prevents transistor from damaging.
First stage T1, the first clock signal SCK1 are low potential, and shift signal SIN is low potential, second clock signal
SCK2 is high potential.The first transistor M1 responds the low potential of the first clock signal SCK1 and is connected, by the low of shift signal SIN
Current potential is transmitted to first node N1, and the current potential of first node N1 is low potential.4th transistor M4 responds the low of first node N1
Current potential and be connected, the low potential of the first clock signal SCK1 is transmitted to second node N2, second node N2 is low potential.And the
Five transistor M5 respond the low potential of the first clock signal SCK1 and are connected, and the second electric potential signal VGL is transmitted to second node
N2.First capacitor C1 store first node N1 low potential, and the 6th transistor M6 in response to first node N1 low potential and lead
It is logical, the high potential of second clock signal SCK2 is transmitted to scanning signal output end 401.Second capacitor C2 stores second node N2
Low potential, and the 7th transistor M7 in response to second node N2 low potential and be connected, the first electric potential signal VGH is transmitted to and is swept
Retouch signal output end 401.The scanning signal Scan that scanning signal output end 401 exports is consistent with the first electric potential signal VGH, simultaneously
Scanning signal Scan is also consistent with second clock signal SCK2, exports high level.
Second stage T2, the first clock signal SCK1 and shift signal SIN are high potential.The first transistor M1 response the
The high potential of one clock signal SCK1 and turn off.Since first capacitor C1 is to the maintenance effect of current potential, first node N1 maintains the
The low potential of one stage T1, the 6th transistor M6 in response to first node N1 low potential and be connected, by second clock signal SCK2
It is transmitted to scanning signal output end 401.4th transistor M4 in response to first node N1 low potential and be connected, by the first clock believe
The high potential of number SCK1 is transmitted to second node N2, and second node N2 is high potential.Second capacitor C2 stores high potential, and the 7th
Transistor M7 in response to second node N2 high potential and turn off.Second transistor M2 in response to second node N2 high potential and close
It is disconnected, even if the first electric potential signal VGH is not yet when third transistor M3 is connected in response to the low potential of second clock signal SCK2
It can be transmitted to first node N1 by second transistor M2 and third transistor M3, so that first node N1, which stablizes, keeps low electricity
Position.The scanning signal Scan that scanning signal output end 401 exports is consistent with second clock signal SCK2.Second clock signal SCK2
When exporting low level, scanning signal Scan is also low level；When second clock signal SCK2 exports high level, scanning signal Scan
It also is high level.
Phase III T3, the first clock signal SCK1 are low potential, and second clock signal SCK2 and shift signal SIN are height
Current potential.The first transistor M1 responds the low potential of the first clock signal SCK1 and is connected, and the high potential of shift signal SIN is transmitted
It is high potential to first node N1, first node N1.6th transistor M6 in response to first node N1 high potential and turn off.5th
Transistor M5 responds the low potential of the first clock signal SCK1 and is connected, and the second electric potential signal VGL is transmitted to second node N2,
The current potential of second node N2 is low potential.Second capacitor C2 stores the low potential of second node N2, and the 7th transistor M7 is responded
The low potential of second node N2 and be connected, the first electric potential signal VGH is transmitted to scanning signal output end 401.Scanning signal is defeated
The scanning signal Scan that outlet 401 exports is consistent with the first electric potential signal VGH, exports high level.
Fourth stage T4, the first clock signal SCK1, second clock signal SCK2 and shift signal SIN are high potential.
Since first capacitor C1 is to the maintenance effect of current potential, first node N1 maintains high potential on last stage, and the 6th transistor M6 is held
Continuous shutdown.Since the second capacitor C2 is to the maintenance effect of current potential, second node N2 maintains low potential on last stage, the 7th crystal
First electric potential signal VGH is transmitted to scanning signal output end 401 by pipe M7 constant conduction.What scanning signal output end 401 exported
Scanning signal Scan is consistent with the first electric potential signal VGH, exports high level.
5th stage T5, the first clock signal SCK1 and shift signal SIN are high potential, and second clock signal SCK2 is
Low potential.Since the second capacitor C2 is to the maintenance effect of current potential, second node N2 maintains low potential on last stage, the second crystal
Pipe M2 in response to second node N2 low potential and be connected, and third transistor M3 in response to second clock signal SCK2 low potential and
First electric potential signal VGH is transmitted to first node N1 by conducting, second transistor M2 and third transistor M3.6th transistor M6
Lasting shutdown, the 7th transistor M7 constant conduction, the scanning signal Scan and the first current potential that scanning signal output end 401 exports believe
Number VGH is consistent, exports high level.
The state of 6th stage T6, each input signal are identical as fourth stage T4, therefore, the state of each transistor and the 4th
Stage, T4 was identical, and the scanning signal Scan that scanning signal output end 401 exports is consistent with the first electric potential signal VGH, exported high electricity
It is flat.
The state of 7th stage T7, each input signal are identical as phase III T3, therefore, the state and third of each transistor
Stage, T3 was identical, and the scanning signal Scan that scanning signal output end 401 exports is consistent with the first electric potential signal VGH, exported high electricity
It is flat.
The state of 8th stage T8, each input signal are identical as fourth stage T4, therefore, the state of each transistor and the 4th
Stage, T4 was identical, and the scanning signal Scan that scanning signal output end 401 exports is consistent with the first electric potential signal VGH, exported high electricity
It is flat.
9th stage T9 and its stage later, circulating repetition phase III T3, fourth stage T4, the 5th stage T5,
Six stage T6, the 7th stage T7 and the 8th stage T8.
It can be seen that scanning circuit provided in an embodiment of the present invention realizes the shifting inputted to shift signal input terminal 301
The shift function of position signal SIN, scanning signal output end 401 export stable scanning signal.And the embodiment of the present invention is adopted
The negligible amounts of transistor, therefore power consumption is lower.
It should be noted that in the above embodiments, the type of each transistor can be P-type transistor, it is also possible to N
Transistor npn npn, the present invention without limitation, can according to need set in practical applications.
The embodiment of the invention also provides a kind of display panels.Figure 10 is a kind of display panel provided in an embodiment of the present invention
Structural schematic diagram.Referring to Figure 10, which includes at least two such as scanning electricity provided by any embodiment of the invention
It road 10, the first clock cable 20, second clock signal wire 30, the first electric potential signal line 40, the second electric potential signal line 50 and opens
Dynamic signal wire 60.First clock signal input terminal of scanning circuit 10 is electrically connected with the first clock cable 20, second clock letter
Number input terminal is electrically connected with second clock signal wire 30, and the first electric potential signal input terminal is electrically connected with the first electric potential signal line 40,
Second electric potential signal input terminal is electrically connected with the second electric potential signal line 50.At least two scanning circuits, 10 cascade connection, the first order
The shift signal input terminal of scanning circuit 10 is electrically connected with enabling signal line 60；The scanning signal of previous stage scanning circuit 10 exports
End is electrically connected with the shift signal input terminal of rear stage scanning circuit 10.
Wherein, which for example can be organic LED display panel, liquid crystal display panel or Electronic Paper
Display panel etc..Every level-one scanning circuit 10 is electrically connected with the scan line 70 on display panel, is transmitted and is scanned to each scan line 70
Signal.First order scanning circuit 10 shifts the enabling signal on enabling signal line 60, and defeated by its scanning signal output end
Out.The scanning signal that rear stage scanning circuit 10 exports previous stage scanning circuit 10 shifts, and exports.Therefore, the present invention is real
The display panel for applying example offer realizes the function of exporting scanning signal line by line, and the scanning signal that scanning circuit at different levels 10 exports
It has good stability.
With continued reference to Figure 10, on the basis of the various embodiments described above, optionally, scanning circuit 10 is set to display panel
Two sides.Illustratively, 10 cascade connection of scanning circuit on the left of display panel successively sends to odd number scan line and scans
Signal.10 cascade connection of scanning circuit on the right side of display panel successively sends scanning signal to even number scan line.This hair
Bright embodiment is provided with the frame for being conducive to reduce the side that scanning circuit 10 occupies display panel in this way, to be conducive to reduce aobvious
Show the border width of panel.
The embodiment of the invention also provides a kind of display devices.Figure 11 is a kind of display device provided in an embodiment of the present invention
Structural schematic diagram.Referring to Figure 11, which includes such as display panel 1 provided by any embodiment of the invention.This is aobvious
Showing device for example can be mobile phone, tablet computer, intelligent wearable device, the information enquiry machine in public place hall etc..The display
Device includes display panel 1 provided by any embodiment of the invention, and technical principle is similar with the technical effect of generation, here
It repeats no more.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (11)
1. a kind of scanning circuit, which is characterized in that including input module, the first output module, the second output module, the first output
Control module, the second output control module, first node, second node, the first clock signal input terminal, second clock signal are defeated
Enter end, the first electric potential signal input terminal, the second electric potential signal input terminal, shift signal input terminal and scanning signal output end；
The input module is electrically connected with the first node, first clock signal input terminal and the shift signal input terminal
It connects, the input module is used to control the current potential of the first node；
First output control module and the first node, second node, the first electric potential signal input terminal and second clock
Signal input part electrical connection；First output control module is used to control the current potential of the first node, the first node
Control the on state of first output module；
Second output control module and the first node, second node, the second electric potential signal input terminal and the first clock
Signal input part electrical connection；Second output control module is used to control the current potential of the second node, the second node
Control the on state of second output module；
First output module and the first node, the second clock signal input part and the scanning signal output end
Electrical connection；During the first output module conducting, the signal of the second clock signal input part input is transmitted to described sweep
Retouch signal output end；
Second output module and the second node, the first electric potential signal input terminal and the scanning signal output end
Electrical connection；During the second output module conducting, the signal of the first electric potential signal input terminal input is transmitted to described sweep
Retouch signal output end.
2. scanning circuit according to claim 1, which is characterized in that the input module includes the first transistor, described
The control terminal of the first transistor is electrically connected with first clock signal input terminal, the first end of the first transistor with it is described
The electrical connection of shift signal input terminal, the second end of the first transistor are electrically connected with the first node.
3. scanning circuit according to claim 2, which is characterized in that the first transistor is double-gated transistor.
4. scanning circuit according to claim 1, which is characterized in that first output control module includes the second crystal
Pipe and third transistor；
The control terminal of the second transistor is electrically connected with the second node, the first end of the second transistor and described the
The electrical connection of one electric potential signal input terminal, the second end of the second transistor are electrically connected with the first end of the third transistor；
The control terminal of the third transistor is electrically connected with the second clock signal input part, and the second of the third transistor
End is electrically connected with the first node.
5. scanning circuit according to claim 1, which is characterized in that second output control module includes the 4th crystal
Pipe and the 5th transistor；
The control terminal of 4th transistor is electrically connected with the first node, the first end of the 4th transistor and described the
The electrical connection of one clock signal input terminal, the second end of the 4th transistor are electrically connected with the second node；
The control terminal of 5th transistor is electrically connected with first clock signal input terminal, and the first of the 5th transistor
End is electrically connected with the second electric potential signal input terminal, and the second end of the 5th transistor is electrically connected with the second node.
6. scanning circuit according to claim 1, which is characterized in that first output module includes:
The control terminal of 6th transistor, the 6th transistor is electrically connected with the first node, and the of the 6th transistor
One end is electrically connected with the second clock signal input part, the second end of the 6th transistor and the scanning signal output end
Electrical connection；
First capacitor, the first end of the first capacitor are electrically connected with the control terminal of the 6th transistor, the first capacitor
Second end be electrically connected with the second end of the 6th transistor.
7. scanning circuit according to claim 1, which is characterized in that second output module includes:
The control terminal of 7th transistor, the 7th transistor is electrically connected with the second node, and the of the 7th transistor
One end is electrically connected with the first electric potential signal input terminal, the second end of the 7th transistor and the scanning signal output end
Electrical connection；
Second capacitor, the first end of second capacitor are electrically connected with the control terminal of the 7th transistor, second capacitor
Second end be electrically connected with the second end of the 7th transistor.
8. scanning circuit according to claim 1, which is characterized in that it further include the 8th transistor, the 8th transistor
Control terminal be electrically connected with the second electric potential signal input terminal, the first end of the 8th transistor and first node electricity
Connection, the second end of the 8th transistor are electrically connected with first output module.
9. scanning circuit according to claim 6, which is characterized in that it further include the 8th transistor, the 6th transistor
It is electrically connected by the 8th transistor with the first node, wherein the control terminal and described second of the 8th transistor
The electrical connection of electric potential signal input terminal, the first end of the 8th transistor are electrically connected with the first node, the 8th crystal
The second end of pipe is electrically connected with the control terminal of the 6th transistor.
10. a kind of display panel, which is characterized in that including at least two as the described in any item scanning circuits of claim 1-9,
First clock cable, second clock signal wire, the first electric potential signal line, the second electric potential signal line and enabling signal line；
First clock signal input terminal of the scanning circuit is electrically connected with first clock cable, the second clock letter
Number input terminal is electrically connected with the second clock signal wire, the first electric potential signal input terminal and the first electric potential signal line
Electrical connection, the second electric potential signal input terminal are electrically connected with the second electric potential signal line；
At least two scanning circuit cascade connections, the shift signal input terminal of scanning circuit described in the first order and the starting
Signal wire electrical connection；The shift signal of scanning circuit described in the scanning signal output end and rear stage of scanning circuit described in previous stage
Input terminal electrical connection.
11. a kind of display device, which is characterized in that including display panel as claimed in claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910569536.8A CN110364121A (en) | 2019-06-27 | 2019-06-27 | Scanning circuit, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910569536.8A CN110364121A (en) | 2019-06-27 | 2019-06-27 | Scanning circuit, display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110364121A true CN110364121A (en) | 2019-10-22 |
Family
ID=68217217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910569536.8A Pending CN110364121A (en) | 2019-06-27 | 2019-06-27 | Scanning circuit, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110364121A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111739475A (en) * | 2020-06-16 | 2020-10-02 | 昆山国显光电有限公司 | Shift register and display panel |
| CN111916016A (en) * | 2020-07-27 | 2020-11-10 | 昆山国显光电有限公司 | Scanning driving circuit, display panel and display device |
| CN112002280A (en) * | 2020-08-31 | 2020-11-27 | 昆山国显光电有限公司 | Light emission control circuit and light emission control driver |
| CN112164364A (en) * | 2020-10-26 | 2021-01-01 | 合肥维信诺科技有限公司 | Driving circuit of display panel, display panel and driving method thereof |
| CN113192454A (en) * | 2021-05-14 | 2021-07-30 | 上海天马有机发光显示技术有限公司 | Scanning driving circuit, method, display panel and display device |
| CN114155803A (en) * | 2020-09-07 | 2022-03-08 | 深圳市柔宇科技股份有限公司 | Scanning drive circuit and display panel |
| CN116030747A (en) * | 2023-03-02 | 2023-04-28 | 昆山国显光电有限公司 | Scanning circuit and display panel |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007102162A (en) * | 2005-09-30 | 2007-04-19 | Samsung Sdi Co Ltd | Scan driving circuit and organic electroluminescence device using same |
| CN102592539A (en) * | 2011-01-06 | 2012-07-18 | 三星移动显示器株式会社 | Emission control line driver and organic light emitting display using the same |
| CN102831860A (en) * | 2012-09-05 | 2012-12-19 | 京东方科技集团股份有限公司 | Shifting register, drive method thereof, gate driver and display device |
| CN104409102A (en) * | 2014-10-31 | 2015-03-11 | 友达光电股份有限公司 | Shift register |
| CN105632561A (en) * | 2016-01-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Shift register, driving method, grid driving circuit and display device |
| CN107424649A (en) * | 2017-05-25 | 2017-12-01 | 上海天马有机发光显示技术有限公司 | A kind of shift register, its driving method, emission control circuit and display device |
| US20180018921A1 (en) * | 2016-07-13 | 2018-01-18 | Samsung Display Co., Ltd. | Stage and display device using the same |
| KR20180039196A (en) * | 2016-10-07 | 2018-04-18 | 엘지디스플레이 주식회사 | Gate driving circuit and display device using the same |
| CN107978276A (en) * | 2018-01-19 | 2018-05-01 | 昆山国显光电有限公司 | Level circuit, scanner driver and display device |
| CN108447448A (en) * | 2018-01-19 | 2018-08-24 | 昆山国显光电有限公司 | A kind of scan drive circuit, scanner driver and display device |
| CN108665837A (en) * | 2017-03-27 | 2018-10-16 | 昆山工研院新型平板显示技术中心有限公司 | Scan drive circuit and its driving method and panel display apparatus |
| CN108898988A (en) * | 2018-08-23 | 2018-11-27 | 京东方科技集团股份有限公司 | Shift register cell, driving method, shift register and display device |
-
2019
- 2019-06-27 CN CN201910569536.8A patent/CN110364121A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007102162A (en) * | 2005-09-30 | 2007-04-19 | Samsung Sdi Co Ltd | Scan driving circuit and organic electroluminescence device using same |
| CN102592539A (en) * | 2011-01-06 | 2012-07-18 | 三星移动显示器株式会社 | Emission control line driver and organic light emitting display using the same |
| CN102831860A (en) * | 2012-09-05 | 2012-12-19 | 京东方科技集团股份有限公司 | Shifting register, drive method thereof, gate driver and display device |
| CN104409102A (en) * | 2014-10-31 | 2015-03-11 | 友达光电股份有限公司 | Shift register |
| CN105632561A (en) * | 2016-01-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Shift register, driving method, grid driving circuit and display device |
| US20180018921A1 (en) * | 2016-07-13 | 2018-01-18 | Samsung Display Co., Ltd. | Stage and display device using the same |
| KR20180039196A (en) * | 2016-10-07 | 2018-04-18 | 엘지디스플레이 주식회사 | Gate driving circuit and display device using the same |
| CN108665837A (en) * | 2017-03-27 | 2018-10-16 | 昆山工研院新型平板显示技术中心有限公司 | Scan drive circuit and its driving method and panel display apparatus |
| CN107424649A (en) * | 2017-05-25 | 2017-12-01 | 上海天马有机发光显示技术有限公司 | A kind of shift register, its driving method, emission control circuit and display device |
| CN107978276A (en) * | 2018-01-19 | 2018-05-01 | 昆山国显光电有限公司 | Level circuit, scanner driver and display device |
| CN108447448A (en) * | 2018-01-19 | 2018-08-24 | 昆山国显光电有限公司 | A kind of scan drive circuit, scanner driver and display device |
| CN108898988A (en) * | 2018-08-23 | 2018-11-27 | 京东方科技集团股份有限公司 | Shift register cell, driving method, shift register and display device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111739475A (en) * | 2020-06-16 | 2020-10-02 | 昆山国显光电有限公司 | Shift register and display panel |
| CN111916016A (en) * | 2020-07-27 | 2020-11-10 | 昆山国显光电有限公司 | Scanning driving circuit, display panel and display device |
| CN112002280A (en) * | 2020-08-31 | 2020-11-27 | 昆山国显光电有限公司 | Light emission control circuit and light emission control driver |
| CN114155803A (en) * | 2020-09-07 | 2022-03-08 | 深圳市柔宇科技股份有限公司 | Scanning drive circuit and display panel |
| CN112164364A (en) * | 2020-10-26 | 2021-01-01 | 合肥维信诺科技有限公司 | Driving circuit of display panel, display panel and driving method thereof |
| CN113192454A (en) * | 2021-05-14 | 2021-07-30 | 上海天马有机发光显示技术有限公司 | Scanning driving circuit, method, display panel and display device |
| US20210366358A1 (en) * | 2021-05-14 | 2021-11-25 | Shanghai Tianma AM-OLED Co., Ltd. | Scanning drive circuit, driving method, display panel, and display apparatus |
| US11521539B2 (en) * | 2021-05-14 | 2022-12-06 | Shanghai Tianma AM-OLED Co., Ltd. | Scanning drive circuit including n shift registers each having independent output terminals, driving method, display panel, and display apparatus |
| CN113192454B (en) * | 2021-05-14 | 2023-08-01 | 武汉天马微电子有限公司 | Scan driving circuit, method, display panel and display device |
| CN116030747A (en) * | 2023-03-02 | 2023-04-28 | 昆山国显光电有限公司 | Scanning circuit and display panel |
| WO2024178908A1 (en) * | 2023-03-02 | 2024-09-06 | 昆山国显光电有限公司 | Scanning circuit and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110364121A (en) | Scanning circuit, display panel and display device | |
| CN106601190B (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN106910468B (en) | The driving method of display panel, display device and pixel circuit | |
| CN105609058B (en) | Backlight and display device | |
| CN104900192B (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN108564916A (en) | A kind of display panel and display device | |
| WO2021057067A1 (en) | Scanning circuit, display panel and display device | |
| CN105139801B (en) | Array base palte horizontal drive circuit, shift register, array base palte and display | |
| CN109697966A (en) | Array substrate, display panel and driving method thereof | |
| CN110178174A (en) | A kind of gate driving circuit and its control method, mobile terminal | |
| CN109509433A (en) | Pixel circuit, display device and image element driving method | |
| CN110047431A (en) | Pixel-driving circuit and its driving method | |
| CN107316599A (en) | Shifting deposit unit, its driving method and display panel | |
| CN107705757B (en) | Shift register and its Time-sharing control method, display panel and device | |
| CN108648690A (en) | A kind of display panel and display device | |
| CN107978276B (en) | Grade circuit, scanner driver and display device | |
| CN209374036U (en) | A kind of display panel and display device | |
| CN107481676A (en) | A kind of driving method of image element circuit, display panel and display device | |
| CN107919091A (en) | A kind of OLED pixel drive circuit and driving method, OLED display | |
| CN108288451A (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN109801594A (en) | A kind of display panel and display device | |
| CN107680536B (en) | Pixel circuit, its driving method and organic light emitting display panel, display device | |
| CN108877671A (en) | A kind of pixel circuit and its driving method, display device | |
| CN110503913A (en) | A kind of driving method of scanning circuit, display panel and display panel | |
| CN110322851A (en) | Scanning drive circuit and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191022 |
|
| RJ01 | Rejection of invention patent application after publication |