CN114155803A

CN114155803A - Scanning drive circuit and display panel

Info

Publication number: CN114155803A
Application number: CN202010928017.9A
Authority: CN
Inventors: 颜尧
Original assignee: Shenzhen Royole Technologies Co Ltd
Current assignee: Shenzhen Royole Technologies Co Ltd
Priority date: 2020-09-07
Filing date: 2020-09-07
Publication date: 2022-03-08

Abstract

The application provides a scanning driving circuit and a display panel, and relates to the technical field of display. The scanning driving circuit comprises a first output control module, a first output module, a second output control module and a second output module, wherein the first output control module is electrically connected with the first output module; the second output module is further connected with the first clock signal line, when the scanning driving circuit is in the reset stage, the first output module is cut off, the second output control module controls the second output module to be conducted, and the first clock signal line outputs a low potential signal, so that the second output module outputs the low potential signal to the output port when the scanning driving circuit is in the reset stage. The pixel circuit has the effect of reducing the power consumption of the pixel circuit.

Description

Scanning drive circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a scanning driving circuit and a display panel.

Background

With the development of optical technology and semiconductor technology, flat panel displays represented by liquid crystal displays and organic light emitting diode displays have the characteristics of lightness, thinness, low energy consumption, high reaction speed, good color purity, high contrast ratio and the like, and occupy a leading position in the display field.

In the current panel driving design, the scan driving circuit needs to include two circuits, namely, a Gate Driver on Array (GOA) circuit for providing scan signals to the real panel and an Emission circuit on Array (EOA) circuit for providing light emitting signals to the display panel.

In the current EOA scan driving circuit, each frame of output data only includes a falling edge, and in the reset stage, the output signal is a high-potential signal, which results in high power consumption in the pixel circuit and is not favorable for normal operation of the pixel circuit.

Disclosure of Invention

An object of the present application is to provide a scan driving circuit and a display panel, so as to solve the problem in the prior art that the loss in a pixel circuit is high due to the fact that an EOA scan driving circuit outputs a high-level signal when the EOA scan driving circuit is in a reset stage.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in one aspect, an embodiment of the present application provides a scan driving circuit, where the scan driving circuit includes a first output control module, a first output module, a second output control module, and a second output module, the first output control module is electrically connected to the first output module, the second output control module is electrically connected to the second output module, the first output control module, and the first output module, and both the first output module and the second output module are electrically connected to an output port; when the first output control module transmits a high potential to the first output module, the first output module is conducted, and when the first output module is conducted, the first output module outputs a high potential signal to the output port; when the second output control module transmits high potential to the second output module, the second output module is conducted; the first output module and the second output module are selected to be conducted; the second output module is further connected with a first clock signal line, when the scan driving circuit is in a reset stage, the first output module is turned off, the second output control module controls the second output module to be turned on, and the first clock signal line outputs a low potential signal, so that the second output module outputs the low potential signal to the output port when the scan driving circuit is in the reset stage.

On the other hand, the application also provides a display panel which comprises the scanning driving circuit.

Compared with the prior art, the method has the following beneficial effects:

the application provides a scanning driving circuit and a display panel, wherein the scanning driving circuit comprises a first output control module, a first output module, a second output control module and a second output module, the first output control module is electrically connected with the first output module, the second output control module is respectively electrically connected with the second output module, the first output control module and the first output module, and the first output module and the second output module are both electrically connected with an output port; the second output module is further connected with the first clock signal line, when the scanning driving circuit is in the reset stage, the first output module is cut off, the second output control module controls the second output module to be conducted, and the first clock signal line outputs a low potential signal, so that the second output module outputs the low potential signal to the output port when the scanning driving circuit is in the reset stage. When the time sequence is set, the second output module is conducted when the scanning driving circuit is in the reset stage, and the first clock signal line outputs the low-potential signal at the moment, so that the output port of the scanning driving circuit can output the low-potential signal in the stage, the pixel circuit can not be conducted when the pixel circuit is in the reset stage, and the power consumption of the pixel circuit is reduced.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a circuit schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

Fig. 2 is a block diagram of a scan driving circuit according to an embodiment of the present disclosure.

Fig. 3 is a first circuit diagram of a scan driving circuit according to an embodiment of the present disclosure.

Fig. 4 is a timing diagram of a scan driving circuit according to an embodiment of the present application.

Fig. 5 is a driving timing diagram according to an embodiment of the present application.

Fig. 6 is a second circuit schematic diagram of a scan driving circuit according to an embodiment of the present disclosure.

Fig. 7 is a third circuit schematic diagram of a scan driving circuit according to an embodiment of the present application.

Fig. 8 is a fourth circuit schematic diagram of a scan driving circuit according to an embodiment of the present application.

Fig. 9 is another timing diagram of a scan driving circuit according to an embodiment of the present application.

In the figure: 100-scan driving circuit; 110-a first output control module; 120-a first output module; 130-a second output control module; 140-a second output module; 150-output port; m1-first switch tube; m2-second switch tube; m3-third switch tube; m4-a fourth switching tube; m5-fifth switch tube; m6-sixth switching tube; m7-seventh switching tube; m8-eighth switch tube; m31-third main switching tube; m32-third auxiliary switch tube; m41-fourth main switching tube; m42-fourth auxiliary switching tube; m71-seventh main switching tube; m72-seventh auxiliary switching tube; m81-eighth main switching tube; m82-eighth auxiliary switch tube.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

First embodiment

As described in the background art, in the current panel driving design, two circuits, i.e., the GOA circuit and the EOA circuit, are required, and each frame of data output by the scanning driving circuit of the front EOA only includes one falling edge, and during the reset stage, the output signal is a high-level signal, which results in high power consumption in the pixel circuit and is not favorable for normal operation of the pixel circuit.

Referring to fig. 1, fig. 1 shows a circuit schematic diagram of a pixel circuit in the prior art, it can be understood that, when the pixel circuit is in a reset stage, if an output signal is a high-level signal, the T1, T2, T3 and T4 switch tubes in the pixel circuit are all in a conducting state, and at this time, because a voltage difference exists between the ELVDD signal and the Vinitial signal, a path is formed between the ELVDD signal and the Vinitial signal, which further causes an increase in power consumption of the pixel circuit, and may also affect an Anode potential, which further affects normal operation of the pixel circuit.

In view of this, the present application provides a scan driving circuit, which outputs a low potential signal when the scan driving circuit is in a reset stage by optimizing the scan driving circuit and a corresponding control timing sequence in the prior art, so that a circuit for driving a panel to emit light in a pixel circuit does not form a path, thereby reducing power consumption of the pixel circuit and not affecting normal operation of the pixel circuit.

The following is an exemplary description of the scan driving circuit 100 provided in the present application:

as an optional implementation manner, referring to fig. 2, the scan driving circuit 100 includes a first output control module 110, a first output module 120, a second output control module 130, and a second output module 140, where the first output control module 110 is electrically connected to the first output module 120, the second output control module 130 is electrically connected to the second output module 140, the first output control module 110, and the first output module 120, and both the first output module 120 and the second output module 140 are electrically connected to an output port 150.

When the first output control module 110 transmits a high voltage to the first output module 120, the first output module 120 is controlled to be turned on, and when the first output module 120 is turned on, the first output module 120 outputs a high voltage signal to the output port 150; when the second output control module 130 transmits a high voltage to the second output module 140, the second output module 140 is controlled to be turned on. It should be noted that the first output module 120 and the second output module 140 are alternatively turned on, that is, when the first output module 120 is turned on, the second output module 140 is turned off; when the second output module 140 is turned on, the first output module 120 is turned off.

The second output module 140 is further connected to the first clock signal line ECLKBm, where m is 1, 2, 3, or 4 as an implementation manner, and certainly, in some other embodiments, the value of m may be more, which depends on the driving period of the first clock signal line, which is not limited in this application. When the scan driving circuit 100 is in the reset stage, the first output module 120 is in the off state, and the second output control module 130 controls the second output module 140 to be turned on, so that the second output module 140 outputs the signal corresponding to the first clock signal line ECLKBm in the reset stage.

Moreover, the present application realizes that, through improvement of the control timing, when the scan driving circuit 100 is in the reset stage, the first clock signal line ECLKBm outputs a low potential signal, so that, at this stage, the second output control module 130 controls the second output module 140 to be turned on, and transmits a signal corresponding to the first clock signal line ECLKBm at this time to the output port 150, and if the signal corresponding to the first clock signal line ECLKBm at this time is a low potential, the second output module 140 outputs a low potential signal to the output port 150 at the reset stage. It can be understood that, referring to fig. 1, since the signal output from the output port 150 is a low-potential signal, the circuit for driving the panel to emit light in the pixel circuit is not turned on at this stage, and thus the power consumption of the pixel circuit at this stage can be reduced.

Referring to fig. 3, as an alternative implementation manner, the second output control module 130 includes a first switch tube M1 and a second switch tube M2, a first end and a second end of the first switch tube M1 are both electrically connected to a first signal line GN, where N is an integer greater than 0, a first end and a second end of the second switch tube M2 are both electrically connected to a second signal line GN-1, third ends of the first switch tube M1 and the second switch tube M2 are both electrically connected to the second output module 140, and the first switch tube M1 and the second switch tube M2 are used for controlling conduction of the second output module 140. In other words, when the first switch tube M1 and/or the second switch tube M2 are turned on to output a high-level signal, the second output module 140 can be driven to be turned on to output a signal corresponding to the first clock signal line.

The switching Transistor (including the switching Transistor described later) provided in the present application may be a TFT (Thin Film Transistor) or a Transistor. When the switching tube is a TFT, the first end of the switching tube is a grid electrode, and the second end and the third end of the switching tube are respectively a source electrode or a drain electrode; when the switching tube is a triode, the first end of the switching tube refers to a base electrode, and the second end and the third end of the switching tube refer to a collector electrode and an emitter electrode respectively. Meanwhile, when the switching tube is a TFT, the switching tube may be an N-type TFT tube or a P-type TFT tube, in the examples described in this application, the switching tube is an N-type TFT tube for example, and it can be understood that when the TFT in the scan driving circuit 100 is replaced by a P-type TFT, the driving signal is a low potential signal.

In addition, the first signal line GN outputs the Nth column signal, the second signal line GN-1 outputs the Nth-1 column signal, and N is an integer greater than 0. The first signal line GN and the second signal line GN-1 may be scanning lines. When the scan driving circuit 100 scans the rising edge of the N-1 th column signal and/or the nth column signal, the second output module 140 is controlled to be turned on, so that the second output module 140 outputs a low-potential signal to the output port 150 when the scan driving circuit 100 is in the reset phase. Since the actual operation principle of the pixel circuit is row-column scanning, when the scanning driving circuit 100 scans the rising edge of the N-1 th column signal and/or the nth column signal, the second switching tube M2 and/or the first switching tube M1 are controlled to be turned on, so as to control the second output module 140 to be turned on, and output a signal corresponding to the first clock signal line.

For convenience of illustration, the scan driving circuit 100 further includes a first node PU and a second node PD, wherein the first output control module 110 is electrically connected to the first output module 120 through the first node PU, and the second output control module 130 is electrically connected to the second output module 140 through the second node PD, and it can be understood that the first node PU and the second node PD are nodes with opposite potentials, that is, when the first node PU is at a high potential, the second node PD is at a low potential; when the first node PU is at a low potential, the second node PD is at a high potential. When the scanning circuit scans the rising edge of the N-1 th column signal, the second switching tube M2 is turned on, and the potential of the second node PD rises, so as to drive the second output module 140 to be turned on.

When the second node PD is at a high potential, the third switching tube M3 is turned on, and the low potential power end EVGL transmits a low potential to the first node PU through the third switching tube M3, so as to pull down the potential of the first node PU and turn off the first output module 120. Meanwhile, the second node PD is at a high potential to turn on the fifth switch M5, i.e., turn on the second output module 140, and the first clock signal line ECLKBm outputs the potential to the output port 150 through the fifth switch M5.

Referring to fig. 4, fig. 4 shows a timing diagram of the scan driving circuit 100 provided in the present application, where the output En of the scan driving circuit 100 includes Eout1-Eout1920, that is, the pixel driving circuit provided in the present application can drive a display panel including 1920 columns of pixels to work, and certainly, in some other embodiments, the number of columns of pixels may be more or less, which is not limited in this application.

Taking the example of outputting the Eout1 signal as an example, when the Eout1 needs to be outputted, the scan driving circuit 100 controls the second switch tube M2 to be turned on and output a high-potential signal when the scan driving circuit scans the rising edge of the signal Gn-1 (i.e., the G0 signal) outputted from the second signal line. In the present application, when the rising edge of the STV _ L signal is scanned by the G0 signal, i.e., the STV _ L signal shown in the figure, the second switch M2 is turned on, and the potential of the second node PD is high, so as to drive the second output module 140 to be turned on, and enable the output port 150 to output the signal corresponding to the first clock signal line ECLKBm. When the Eout1 signal is outputted, the signal outputted by the corresponding first clock line is ECKB 2. As can be seen from fig. 4, when the rising edge of the STV _ L signal is scanned, the signal output from the first clock signal line ECLKBm is ECKB2, i.e. the low-potential signal is output first and then the high-potential signal is output, and therefore the output port 150 also outputs the low-potential signal first and then the high-potential signal, i.e. Eout1 is low-potential and then high-potential. Referring to fig. 4, at the next time, G1 (i.e., Gout1) outputs high voltage, the first signal line and the second signal line output high voltage simultaneously, the first switch M1 and the second switch M2 are turned on simultaneously, and the output port 150 still outputs the signal corresponding to the first clock line ECLKBm. After a period of time, the STV _ L signal falls and is converted into a low potential, at this time, the second switch tube M2 is not turned on, the first switch tube M1 is turned on, and the output port 150 still outputs the signal corresponding to the first clock signal line ECLKBm. After a period of time, when the G1 signal has a falling edge, the first switch tube M1 and the second switch tube M2 are not turned on, and at this time, the driving signal ECK2 of the first output signal control module has a rising edge, the second clock signal line output corresponds to the ECK2 in fig. 4, so that the seventh switch tube M7 is turned on, the first node PU is at a high potential, the first output module 120 is turned on, the high potential power source end EVGH outputs the high potential to the output port 150 through the eighth switch tube M8, and the Eout1 is at the high potential before the first switch tube M1 and the second switch tube M2 are turned on again in the next frame.

For more convenience, referring to fig. 5, fig. 5 is a driving timing diagram of the circuit shown in fig. 3, it can be seen that when the scan driving circuit 100 is in the reset stage, the output signal En is a low-potential signal, and the circuit for driving the panel to emit light in the pixel circuit does not form a path, so as to reduce the power consumption of the pixel circuit and not affect the operation of the pixel circuit.

It should be noted that when the pixel circuit needs to be controlled to display one frame of image, 4 stages are generally required, namely, a reset stage (Initial), a compensation stage (Com), a gray Data voltage writing stage (Data), and a light emitting stage (Emission). As shown in fig. 5, in the timing sequence of the improved scan driving circuit, when the scan driving circuit is in the reset phase, the signal output from the output port 150 is at the low level (i.e., En in the figure), and with reference to fig. 1, T3 in fig. 1 is in the off state, so that no path is formed between the ELVDD signal and the Vinitial signal, and the power consumption of the pixel circuit in this phase is reduced. Meanwhile, in order to ensure the normal operation of the pixel circuit, the present application only improves the signal of the scan driving circuit 100 in the reset phase, and does not change the signal of the scan driving circuit 100 in the compensation phase, the data writing phase, and the light emitting phase. It can be understood that the first clock signal line also outputs the low potential signal in the data writing phase, and since the duration of the low potential signal output in the data writing phase is less than the duration of the low potential signal output in the reset phase, when the second output module 140 outputs a signal to the output port 150, two low potential signals with unequal durations are output, thereby further reducing the power consumption of the pixel circuit.

Referring to fig. 3 again, the operation principle of the scan driving circuit 100 provided in the present application is explained in more detail as follows:

as can be understood from the above description, when the first switch M1 and/or the second switch M2 are turned on, the second output module 140 is also turned on and outputs a signal corresponding to the first clock signal line to the output port 150. Also, the potentials of the first node PU and the second node PD must be opposite. Therefore, in order to prevent the circuit signal from being disturbed, for example, when the first node PU is at a high potential and the second node PD is also at a high potential, the present application designs a corresponding clamp switch, which includes the third switch M3 and the fourth switch M4.

A first end of the third switch tube M3 is electrically connected to the first switch tube M1, the second switch tube M2 and the second output module 140, a second end of the third switch tube M3 is electrically connected to a low-potential power source terminal, and a third end of the third switch tube M3 is electrically connected to the first output control module 110. A first end of the fourth switching tube M4 is electrically connected to the first output control module 110 and the first output module 120, respectively, a second end of the fourth switching tube M4 is electrically connected to a low-potential power source terminal, and a third end of the fourth switching tube M4 is electrically connected to the second output module 140.

By providing the third switch tube M3, when the first switch tube M1 and/or the second switch tube M2 are turned on, so that the second node PD is at a high potential, the second output module 140 can be controlled to be turned on, and the third switch tube M3 can be turned on. When the third switch tube M3 is turned on, since the second end of the third switch tube M3 is connected to the low potential voltage source, the third switch tube M3 will always pull the first node PU to the low potential, so as to implement the clamping function, and on this basis, it can be ensured that the driving signal of the first output module 120 is pulled to the low potential, thereby ensuring that the first output module 120 is in a stable cut-off state when the second output module 140 is in a turned-on state, and therefore ensuring that the signal is not disturbed when the second output module 140 is turned on.

Similarly, by providing the fourth switching tube M4, when the first output module 120 is controlled by the first output control module 110 to be turned on, the first node PU is at a high potential, at this time, the fourth switching tube M4 is also turned on due to the high potential driving of the first node PU, and since the second end of the fourth switching tube M4 is connected to the low potential voltage source, the fourth switching tube M4 will pull the second node PD to a low potential all the time, so as to implement the clamping function, on this basis, it is ensured that the second output module 140 is in a stable off state when the first output module 120 is turned on, and therefore it is ensured that the signal is not disturbed when the first output module 120 is turned on.

On the basis of the above implementation, the second output module 140 includes a fifth switch M5, a first end of the fifth switch M5 is electrically connected to the second output control module 130, a second end of the fifth switch M5 is electrically connected to the first clock signal line, and a third end of the fifth switch M5 is electrically connected to the output port 150.

Meanwhile, in actual operation, when the first node PU is at a high potential, the fourth switch tube M4 is always in a conducting state, so the fourth switch tube M4 is substantially in a long-time conducting state when the scan driving circuit 100 outputs each frame of data. Meanwhile, when the first node PU is at a high potential, the voltage of the first node PU is generally high, which may reach about 20V, so that the fourth switch tube M4 may drift during use, and finally the clamping capability of the fourth switch is weak.

In view of the above, referring to fig. 6, in order to improve the above problem, the second output module 140 further includes a sixth switch M6, a first terminal of the sixth switch M6 is electrically connected to the second clock signal line, a second terminal of the sixth switch M6 is electrically connected to a low-potential power source terminal, a third terminal of the sixth switch M6 is electrically connected to the second output module 140, and when the sixth switch M6 is turned on, the second output module 140 is in an off state.

In other words, when the first node PU is at a high potential, the sixth switch transistor M6 is also turned on, and the sixth switch transistor M6 is also electrically connected to the low potential power source terminal, so that the clamping function of the fifth switch transistor M5 can be realized. Therefore, when the first node PU is at a high potential, the first output module 120 is turned on to output a high potential signal to the output port 150, and the fourth switching tube M4 and the sixth switching tube M6 are also turned on, and at the same time, the voltage clamp on the fifth switching tube M5 is implemented, so that the fifth switching tube is in a stable off state.

As an implementation manner, in order to prevent the timing sequence of the on and off of the sixth switching tube M6 from being disordered, the second clock signal line is further electrically connected to the first output control module 110 to control the on and off of the first output control module 110, and by this arrangement manner, the timing sequence of the on and off of the sixth switching tube M6 can be ensured to be the same as the timing sequence of the first node PU. That is, when the second clock signal line outputs a high voltage, the sixth switch M6 is turned on, and the first output control module 110 is in a conducting state, and the first node PU is at a high voltage, so that the timing sequence of the sixth switch M6 is consistent with the timing sequence of the first node PU during this period.

As an implementation manner, the first output control module 110 includes a seventh switch tube M7, a first end and a second end of the seventh switch tube M7 are electrically connected to the second clock signal line, and a third end of the seventh switch tube M7 is electrically connected to the third switch tube M3 and the first output module 120, respectively.

It should be noted that, the signals of the first ends of the seventh switch M7 and the sixth switch M6 are ECLKn, please refer to fig. 4, which outputs an ECK2 corresponding to the signal Eout1, when the rising edge of the ECK2 is scanned, the scan driving circuit 100 controls the first output control module 110 to be turned on, so that the first node PU is at a high potential, and the second node PD is at a low potential, so as to continuously output a high potential signal to the output port 150.

As an implementation manner, the first output module 120 provided in the present application includes an eighth switch M8, a first terminal of the eighth switch M8 is electrically connected to a third terminal of the seventh switch M7, a second terminal of the eighth switch M8 is electrically connected to a high-potential power source terminal, and a third terminal of the eighth switch M8 is electrically connected to the output port 150. In addition, in order to protect the eighth switching tube M8, a capacitor is further disposed between the first terminal and the third terminal of the eighth switching tube M8.

In order to improve the stability of the switching tube, when the switching tube is a TFT tube, a back gate is provided at a position of a part or all of the gate of the switching tube. In other words, referring to fig. 7, the back gates are disposed at the positions of some or all of the gates of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, and the eighth switch tube, for example, the first transistor is taken as an example, the first transistor is provided with a back gate, and the back gate is also electrically connected to the first signal line. The back gate arranged on the switch tube can be used for connecting compensation voltage to compensate threshold voltage drift of the TFT tube, and therefore stability of the TFT tube is improved.

In addition, the voltage of the first terminal of the eighth switch tube M8 is equal to the voltage of the first node PU, and the voltage of the second terminal is equal to the voltage of the high voltage power source terminal EVGH, and in practical applications, the voltage of the first node PU is different from the voltage of the high voltage power source terminal EVGH, for example, when the voltage of the first node PU is 20V, the voltage of the high voltage power source terminal EVGH is only 15V, and thus a voltage difference exists between the first terminal and the second terminal of the eighth switch tube M8. Therefore, during the operation of the eighth switch transistor M8, a certain damage may be caused to the eighth switch transistor M8, and although the damage is reversible and can be repaired by the self-recovery of the eighth switch transistor M8, according to the above description, in outputting one frame signal by the scan driving current, the eighth switch transistor M8 is actually in a long-time conducting state and therefore in a long-time conducting state, so that the eighth switch transistor M8 cannot be recovered by the self-recovery.

In view of the above, referring to fig. 8, in order to solve the above problem, the first output control module 110 includes a main output control module and an auxiliary output control module, the first output module 120 includes a main output module and an auxiliary output module, the main output control module is electrically connected to the main output module, the main output module is further electrically connected to the output port 150, the auxiliary output control module is electrically connected to the auxiliary output module, and the auxiliary output module is further electrically connected to the output port 150; the main output control module is used for controlling the conduction of the main output module, the auxiliary output control module is used for controlling the conduction of the auxiliary output module, and when the first output module 120 is conducted, the main output module and the auxiliary output module are selected to be conducted.

In other words, the seventh switch tube M7 may be divided into a seventh main switch tube M71 and a seventh auxiliary switch tube M72, and an eighth main switch tube M81 and an eighth auxiliary switch tube M82 into which the eighth switch tube M8 may be divided, wherein the first ends of the seventh main switch tube M71 and the seventh auxiliary switch tube M72 are electrically connected to the second clock signal line ECLKn, the second end of the seventh main switch tube M71 is electrically connected to the eighth main switch tube M81, and the third end of the seventh main switch tube M71 is electrically connected to the high voltage supply terminal VDDO; a second terminal of the seventh sub-switch M72 is electrically connected to the eighth sub-switch M82, and a third terminal of the seventh sub-switch M72 is electrically connected to the high voltage power supply terminal VDDE. Certainly, in order to protect the eighth main switch tube M81 and the eighth sub switch tube M82, a capacitor is connected between the first end and the second end of the eighth main switch tube M81 and the eighth sub switch tube M82.

Through this setting mode, can realize utilizing eighth main switch pipe M81 or eighth auxiliary switch pipe M82 to output high potential signal, and then make eighth main switch pipe M81 and eighth auxiliary switch pipe M82 have certain time to realize self-resuming.

For example, when the scan driving circuit 100 outputs one frame signal, when the rising edge of ECLKn is scanned, the seventh main switch M71 and the seventh sub-switch M72 are both turned on, and meanwhile, if the high voltage power supply terminal VDDO outputs a high voltage signal and the high voltage power supply terminal VDDE does not output a high voltage signal, the eighth main switch M81 is driven to be turned on, and the eighth sub-switch M82 is still in a turned-off state, so that the effect of outputting a high voltage to the output port 150 is achieved, and the eighth sub-switch M82 is enabled to achieve self-recovery.

Similarly, when the rising edge of ECLKn is scanned, the seventh main switch M71 and the seventh auxiliary switch M72 are both turned on, and meanwhile, if the high voltage power supply terminal VDDO does not output a high voltage signal and the high voltage power supply terminal VDDE outputs a high voltage signal, the eighth auxiliary switch M82 is driven to be turned on, and the eighth main switch M81 is still in a cut-off state, so that the effect of outputting a high voltage to the output port 150 is realized, and the eighth main switch M81 is enabled to realize self-recovery.

Optionally, the eighth main switch M81 and the eighth sub-switch M82 may be turned on periodically, or may be turned on according to other ratios, for example, the eighth main switch M81 is turned on for two consecutive frames, and the eighth sub-switch M82 is turned on for only one frame, which is not limited in this application.

In the present application, the eighth main switch tube M81 and the eighth auxiliary switch tube M82 output signals in a periodic conduction manner. For example, during odd frames, the high voltage supply terminal VDDO outputs a high voltage signal, the high voltage supply terminal VDDE does not output a high voltage signal, so that the eighth main switch M81 is turned on, and the eighth sub-switch M82 is turned off; in odd frames, the high voltage power supply terminal VDDO does not output the high voltage signal, the high voltage power supply terminal VDDE outputs the high voltage signal, so that the eighth sub-switch M82 is turned on, and the eighth main switch M81 is turned off, and accordingly, the control timing of the scan driving circuit 100 is as shown in fig. 9.

It should be noted that, since the first output control module 110 and the first output control module 120 both include the main module and the sub-module, the third switch transistor M3 and the fourth switch transistor M4 in the second output control module 130 also include corresponding main switch transistors and switch transistors, so as to better implement the clamping function.

Specifically, the third switching tube M3 may be divided into a third main switching tube M31 and a third auxiliary switching tube M32, a first end of the third main switching tube M31 is electrically connected to the second output module 140, a second end of the third main switching tube M31 is electrically connected to a low-potential power source terminal, and a third end of the third main switching tube M31 is electrically connected to the main output control module; a first end of the third auxiliary switch tube M32 is electrically connected to the second output module 140, a second end of the third main switch tube M31 is electrically connected to a low-potential power source terminal, and a third end of the third auxiliary switch tube M32 is electrically connected to the auxiliary output control module.

The fourth switching tube M4 may be divided into a fourth main switching tube M41 and a fourth auxiliary switching tube M42, a first end of the fourth main switching tube M41 is electrically connected to the main output control module and the main output module, a second end of the fourth main switching tube M41 is electrically connected to a low-potential power supply terminal, and a third end of the fourth switching tube M4 is electrically connected to the second output module 140; a first end of the fourth sub-switch M42 is electrically connected to the sub-output control module and the sub-output module, a second end of the fourth sub-switch M42 is electrically connected to a low potential power source terminal, and a third end of the fourth sub-switch M42 is electrically connected to the second output module 140.

Through the arrangement mode, the self-recovery time of the eighth main switch tube M81 and the eighth auxiliary switch tube M82 can be ensured, and the performance of the device is further ensured.

Second embodiment

The embodiment of the present application further provides a display panel, which includes the scan driving circuit 100 according to the first embodiment, and the scan driving circuit 100 has been described in detail in the first embodiment, so that the detailed description of this embodiment is omitted.

It can be understood that the display panel further includes a GOA circuit and a pixel circuit, wherein the GOA circuit and the scan driving circuit are both electrically connected to the pixel circuit to drive the operation of the pixel circuit.

In summary, the present application provides a scan driving circuit and a display panel, where the scan driving circuit includes a first output control module, a first output module, a second output control module, and a second output module, the first output control module is electrically connected to the first output module, the second output control module is electrically connected to the second output module, the first output control module, and the first output module, and the second output module are electrically connected to an output port; the second output module is further connected with the first clock signal line, when the scanning driving circuit is in the reset stage, the first output module is cut off, the second output control module controls the second output module to be conducted, and the first clock signal line outputs a low potential signal, so that the second output module outputs the low potential signal to the output port when the scanning driving circuit is in the reset stage. When the time sequence is set, the second output module is conducted when the scanning driving circuit is in the reset stage, and the first clock signal line outputs the low-potential signal at the moment, so that the output port of the scanning driving circuit can output the low-potential signal in the stage, the pixel circuit can not be conducted when the pixel circuit is in the reset stage, and the power consumption of the pixel circuit is reduced.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A scanning driving circuit is characterized by comprising a first output control module, a first output module, a second output control module and a second output module, wherein the first output control module is electrically connected with the first output module, the second output control module is respectively electrically connected with the second output module, the first output control module and the first output module, and the first output module and the second output module are both electrically connected with an output port;

when the first output control module transmits a high potential to the first output module, the first output module is conducted, and when the first output module is conducted, the first output module outputs a high potential signal to the output port;

when the second output control module transmits high potential to the second output module, the second output module is conducted; the first output module and the second output module are selected to be conducted;

the second output module is further connected with a first clock signal line, when the scan driving circuit is in a reset stage, the first output module is turned off, the second output control module controls the second output module to be turned on, and the first clock signal line outputs a low potential signal, so that the second output module outputs the low potential signal to the output port when the scan driving circuit is in the reset stage.

2. The scan driving circuit of claim 1, wherein the second output control module comprises a first switch tube and a second switch tube, the first end and the second end of the first switch tube are electrically connected to a first signal line, the first end and the second end of the second switch tube are electrically connected to a second signal line, the third ends of the first switch tube and the second switch tube are electrically connected to the second output module, and the first switch tube and the second switch tube are used for controlling the conduction of the second output module, wherein,

the first signal line outputs an Nth column of signals, the second signal line outputs an N-1 th column of signals, and N is an integer greater than 0; when the scanning driving circuit scans the rising edge of the N-1 th column signal or the Nth column signal, the second output module is controlled to be conducted, so that the second output module outputs a low-potential signal to the output port when the scanning driving circuit is in a reset stage.

3. The scan driving circuit according to claim 2, wherein the second output control module further includes a third switching tube, a first end of the third switching tube is electrically connected to the first switching tube, the second switching tube and the second output module, respectively, a second end of the third switching tube is electrically connected to a low potential power source terminal, and a third end of the third switching tube is electrically connected to the first output module.

4. The scan driving circuit according to claim 2, wherein the first switching transistor and the second switching transistor are TFT transistors or triodes, and when the first switching transistor and the second switching transistor are TFT transistors, a back gate is disposed at a gate of the TFT transistor.

5. The scan driving circuit according to claim 1, wherein the second output control module further includes a fourth switching tube, a first end of the fourth switching tube is electrically connected to the first output control module and the first output module, a second end of the fourth switching tube is electrically connected to a low-potential power source terminal, and a third end of the fourth switching tube is electrically connected to the second output module.

6. The scan driving circuit according to claim 1, wherein the second output module includes a fifth switching tube, a first end of the fifth switching tube is electrically connected to the second output control module, a second end of the fifth switching tube is electrically connected to the first clock signal line, and a third end of the fifth switching tube is electrically connected to the output port; wherein the content of the first and second substances,

the first clock signal line also outputs a low-potential signal in a data writing stage, and the duration of the low-potential signal output in the data writing stage is less than that of the low-potential signal output in the resetting stage, so that the second output module outputs two low-potential signals with unequal durations when being conducted.

7. The scan driving circuit according to claim 1, wherein the second output control module further includes a sixth switching tube, a first end of the sixth switching tube is electrically connected to the second clock signal line, a second end of the sixth switching tube is electrically connected to a low-potential power source terminal, and a third end of the sixth switching tube is electrically connected to the second output module; wherein the content of the first and second substances,

when the sixth switching tube is conducted, the second output module is in a cut-off state.

8. The scan driving circuit according to claim 7, wherein the second clock signal line is further electrically connected to the first output control module to control conduction of the first output control module.

9. The scan driving circuit according to claim 1, wherein the first output control module includes a main output control module and a sub output control module, the first output module includes a main output module and a sub output module, the main output control module is electrically connected to the main output module, the main output module is further electrically connected to the output port, the sub output control module is electrically connected to the sub output module, the sub output module is further electrically connected to the output port; wherein the content of the first and second substances,

the main output control module is used for controlling the conduction of the main output module, the auxiliary output control module is used for controlling the conduction of the auxiliary output module, and when the first output module is conducted, the main output module and the auxiliary output module are selected to be conducted.

10. The scan driving circuit according to claim 9, wherein the second output control module further includes a third main switching tube and a third auxiliary switching tube, a first end of the third main switching tube is electrically connected to the second output module, a second end of the third main switching tube is electrically connected to a low-potential power supply terminal, and a third end of the third main switching tube is electrically connected to the main output control module;

the first end of the third auxiliary switching tube is electrically connected with the second output module, the second end of the third main switching tube is electrically connected with a low potential power supply end, and the third end of the third auxiliary switching tube is electrically connected with the auxiliary output control module.

11. The scan driving circuit according to claim 9, wherein the second output control module further includes a fourth main switching tube and a fourth auxiliary switching tube, a first end of the fourth main switching tube is electrically connected to the main output control module and the main output module, a second end of the fourth main switching tube is electrically connected to a low-potential power source terminal, and a third end of the fourth main switching tube is electrically connected to the second output module;

the first end of the fourth auxiliary switching tube is electrically connected with the auxiliary output control module and the auxiliary output module, the second end of the fourth auxiliary switching tube is electrically connected with a low potential power supply end, and the third end of the fourth auxiliary switching tube is electrically connected with the second output module.

12. A display panel comprising the scan driver circuit according to any one of claims 1 to 11.