CN105139801B - Array base palte horizontal drive circuit, shift register, array base palte and display - Google Patents

Array base palte horizontal drive circuit, shift register, array base palte and display Download PDF

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Publication number
CN105139801B
CN105139801B CN201510542621.7A CN201510542621A CN105139801B CN 105139801 B CN105139801 B CN 105139801B CN 201510542621 A CN201510542621 A CN 201510542621A CN 105139801 B CN105139801 B CN 105139801B
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China
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transistor
signal input
connects
clock signal
array base
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CN201510542621.7A
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Chinese (zh)
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CN105139801A (en
Inventor
田超
吴锦坤
田栋协
谢志生
胡君文
苏君海
李建华
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信利(惠州)智能显示有限公司
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Abstract

The present invention relates to display actuation techniques field, more particularly to a kind of array base palte horizontal drive circuit, shift register, array base palte and display, wherein, array base palte horizontal drive circuit includes:The first transistor is to the 9th transistor, the first electric capacity to the 3rd electric capacity, the first clock signal input terminal to the 3rd clock signal input terminal, high level input, low-level input, the first output end, the second output end and driving signal input.Above-mentioned array base palte horizontal drive circuit and shift register, by the first output end and the second output end.To cause to export two kinds of array base palte horizontal-drive signals in an array base palte horizontal drive circuit at the same time, so as to reduce the quantity of transistor, circuit design cost is reduced, the reliability and stability of circuit are improved, while being also beneficial to the design of narrow frame panel.

Description

Array base palte horizontal drive circuit, shift register, array base palte and display

Technical field

The present invention relates to display actuation techniques field, more particularly to a kind of array base palte horizontal drive circuit, displacement are posted Storage, array base palte and display.

Background technology

Either liquid crystal panel or AMOLED (Active Matrix/Organic Light Emitting Diode, Active matrix organic light-emitting diode) panel, it is required for horizontal-drive signal to provide image element circuit scanning, to show complete picture Face.

Array base palte row drives (Gate Driver on Array, GOA) circuit, by the design to circuit, by row Drive circuit is directly produced on array base palte, stably the horizontal-drive signal for needed for image element circuit is provided.Compared to traditional Horizontal-drive signal drives IC to produce by going, and GOA circuits reduce IC costs, while decreasing the width of panel border, add Portable product is booming in recent years, has good practical value and application prospect in actual production.

However, in traditional GOA circuits, complex circuit designs, the use multiport output of control signal, number of transistors Numerous and diverse, circuit reliability is low.

The content of the invention

Based on this, it is necessary to for how to reduce circuit design cost, how to improve circuit stability problem, there is provided A kind of array base palte horizontal drive circuit, shift register, array base palte and display.

A kind of array base palte horizontal drive circuit, including:The first transistor to the 9th transistor, the first electric capacity to the 3rd electricity Appearance, the first clock signal input terminal to the 3rd clock signal input terminal, high level input, low-level input, the first output End, the second output end and driving signal input;

The grid of the first transistor connects first clock signal input terminal, and the drain electrode connection drive signal is defeated Enter end;

The grid of the transistor seconds connects the source electrode of the first transistor, and source electrode connects the 3rd clock signal Input, drain electrode connection first output end;

The grid of the third transistor connects second output end or connects the drain electrode of the 7th transistor, source Pole connects the drain electrode of the transistor seconds, the drain electrode connection high level input;

The grid of the 4th transistor connects first clock signal input terminal, and it is defeated that source electrode connects the drive signal Enter end;

The grid of the 5th transistor connects the second clock signal input part, the drain electrode connection low level input End;

The grid of the 6th transistor connects the source electrode of the 5th transistor, and source electrode connects the high level input End, the drain electrode of drain electrode connection the 4th transistor;

The grid of the 7th transistor connects the drain electrode of the 6th transistor, and source electrode connects the high level input End, the grid of drain electrode connection the 6th transistor;

The grid of the 8th transistor connects the grid of the 7th transistor, and source electrode connects the high level input End, drain electrode connection second output end;

The grid of the 9th transistor connects the drain electrode of the 7th transistor, and source electrode connects second output end, The drain electrode connection low-level input;

One end of first electric capacity connects the drain electrode of the transistor seconds, and the other end connects the transistor seconds Grid;

One end of second electric capacity connects the high level input, and the other end connects the grid of the 8th transistor Pole;

One end of 3rd electric capacity connects the source electrode of the 9th thin film transistor (TFT), and the other end connects the 9th transistor Grid.

Wherein in one embodiment, also including the tenth transistor, its grid connects the grid of third transistor, and source electrode connects Connect the high level input, the grid of the drain electrode connection transistor seconds.

Wherein in one embodiment, the 7th transistor includes double-gate structure thin film transistor (TFT).

Wherein in one embodiment, the first transistor to the 9th transistor is thin film transistor (TFT).

Wherein in one embodiment, the first transistor is the thin film transistor (TFT) of p-type to the 9th transistor.

Wherein in one embodiment, the first transistor is the metal oxide of p-type to the 9th transistor Semiconductor field effect transistor.

Wherein in one embodiment, the first transistor to the 9th transistor is p-type bipolar junction transistor Pipe.

A kind of shift register, including the first clock signal input connection end is to the 3rd clock signal connection end, Yi Jiduo Individual cycling element, each cycling element includes three-level array base palte horizontal drive circuit, and the three-level array base palte row drives Circuit includes first order array base palte horizontal drive circuit to third level array base palte horizontal drive circuit;Wherein, per one-level array base Plate horizontal drive circuit is array base palte horizontal drive circuit as described above;

First clock signal input terminal of the first order array base palte horizontal drive circuit connects first clock signal Input connection end, second clock signal input part connects the second clock signal input connection end, the 3rd clock signal input End connection the 3rd clock signal input connection end;

First clock signal input terminal of the second level array base palte horizontal drive circuit connects the 3rd clock signal Input connection end, second clock signal input part connects the first clock signal input connection end, the 3rd clock signal input The end connection second clock signal input connection end;

First clock signal input terminal of the third level array base palte horizontal drive circuit connects the second clock signal Input connection end, second clock signal input part connects the 3rd clock signal input connection end, the 3rd clock signal input End connection the first clock signal input connection end;

First output end of the first order array base palte horizontal drive circuit connects the second level array base palte row and drives The driving signal input of circuit, the first output end of the second level array base palte horizontal drive circuit connects the third level battle array The driving signal input of row substrate horizontal drive circuit, wherein,

Only first driving signal input of the first order array base palte horizontal drive circuit of cycling element is used for receiving frame Open signal.

A kind of array base palte, it includes shift register as described above.

A kind of display, it includes array base palte as described above.

Above-mentioned array base palte horizontal drive circuit and shift register, by the first output end and the second output end.To cause Two kinds of array base palte horizontal-drive signals are exported in an array base palte horizontal drive circuit at the same time, so as to reduce the number of transistor Amount, reduces circuit design cost, the reliability and stability of circuit is improved, while being also beneficial to the design of narrow frame panel.

Brief description of the drawings

Fig. 1 is the structural representation of one embodiment of the invention array base palte horizontal drive circuit;

Fig. 2 is the timing diagram of embodiment illustrated in fig. 1;

Fig. 3 divides schematic diagram for the functional module of embodiment illustrated in fig. 1;

Fig. 4 is the structural representation of another embodiment of the present invention array base palte horizontal drive circuit;

Fig. 5 is the timing diagram of embodiment illustrated in fig. 4;

Fig. 6 divides schematic diagram for the functional module of embodiment illustrated in fig. 4;

Fig. 7 is the structural representation of one embodiment of the invention shift register;

Fig. 8 is the structural representation of one embodiment of the invention array base palte;

Fig. 9 is the structural representation of one embodiment of the invention display.

Specific embodiment

To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.Elaborate many details in order to fully understand this hair in the following description It is bright.But the present invention can be implemented with being much different from its mode described here, and those skilled in the art can not disobey Similar improvement is done in the case of back of the body intension of the present invention, therefore the present invention is not limited by following public specific embodiment.

It should be noted that GOA:Gate Driver on Array, i.e. array base palte row drive, and are by raster data model electricity Road is fabricated directly on array (Array) substrate, such that it is able to save grid-driving integrated circuit part, with from material cost and The aspect reduces cost of manufacture craft two, gate driving circuit of this utilization GOA Integration ofTechnologies on array base palte is also referred to as GOA Circuit.

It should be noted that P-type TFT:PTFT, refers to n-type substrate, p-channel, and the flowing by hole produces electric current Thin film transistor (TFT), its have low level turn on high level cut-off characteristic.

It should be noted that double-gate structure thin film transistor (TFT):Refer to and connected using two thin film transistor (TFT)s, and its grid is connected Be connected together the thin film transistor (TFT) of the special construction for using.

Fig. 1 is referred to, array base palte horizontal drive circuit includes:The first transistor T1, transistor seconds T2, third transistor T3, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6, the 7th transistor T7, the 8th transistor T8, the 9th crystal Pipe T9, the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the first clock signal input terminal CK1, second clock signal input End CK2, the 3rd clock signal input terminal CK3, high level input VGH, low-level input VGL, the first output end SN, second Output end EM and driving signal input IN.

The grid of the first transistor T1 connects the first clock signal input terminal CK1, drain electrode connection driving signal input IN.

The source electrode of the grid connection the first transistor T1 of transistor seconds T2, source electrode connects the 3rd clock signal input terminal CK3, the first output end SN of drain electrode connection.

The grid of third transistor T3 connects the drain electrode of seven transistors of the second output end EM or connection, source electrode connection second The drain electrode of transistor T2, drain electrode connection high level input VGH.

The grid of the 4th transistor T4 connects the first clock signal input terminal CK1, source electrode connection driving signal input IN.

The grid connection second clock signal input part CK2 of the 5th transistor T5, drain electrode connection low-level input VGL.

The grid of the 6th transistor T6 connects the source electrode of the 5th transistor T5, source electrode connection high level input VGH, drain electrode Connect the drain electrode of the 4th transistor T4.

The grid of the 7th transistor T7 connects the drain electrode of the 6th transistor T6, source electrode connection high level input VGH, drain electrode Connect the grid of the 6th transistor T6.

The grid of the 8th transistor T8 connects the grid of the 7th transistor T7, source electrode connection high level input VGH, drain electrode Connect the second output end EM.

The grid of the 9th transistor T9 connects the drain electrode of the 7th transistor T7, and source electrode connects the second output end EM, and drain electrode connects Meet low-level input VGL.

One end of first electric capacity C1 connects the drain electrode of transistor seconds T2, the grid of other end connection transistor seconds T2.

One end connection high level input VGH of the second electric capacity C2, the other end connects the grid of the 8th transistor T8.

One end of 3rd electric capacity C3 connects the source electrode of the 9th thin film transistor (TFT), and the other end connects the grid of the 9th transistor T9 Pole.

For example, the first clock signal input terminal CK1, second clock signal input part CK2 and the 3rd clock signal input terminal CK3 is respectively used to receive the first clock signal, second clock signal and the 3rd clock signal.For example, wherein described first clock Signal, the second clock signal and the 3rd clock signal have the high level part of part overlapping, it is preferred that such as Fig. 2 Shown, first clock signal, the second clock signal and the 3rd clock signal have and only two at any time Individual clock signal is in high level state, for example, it has sequential as shown in Figure 2.

For example, high level input VGH and low-level input VGL are respectively used to high level and low electricity outside connection It is flat.

For example, the first output end SN and the second output end EM are respectively used to externally export the first output signal, the second output Signal, wherein, first output signal is SN signals, and the second output signal is EM signals.It should be noted that SN signals are Refer to scanning signal or reset signal.EM signals are to refer to luminous signal.

For example, the driving signal input IN of each array base palte horizontal drive circuit is used to be connected as an array base First output end SN of plate horizontal drive circuit, also, the only first driving signal input IN of array base palte horizontal drive circuit For receiving STV signals.It should be noted that, the STV signals are frame open signal.

Fig. 2 is referred to, for example, the time interval of continuous uniform is provided with, for example, when being provided with the t1~t6 of continuous uniform Between be spaced, also, in each time interval, the first clock signal input terminal CK1, second clock signal input part CK2, the 3rd The level signal that an at least input is received in clock signal input terminal CK3 is different with other two inputs, so that the One output end SN and the second output end EM exports relative GOA drive signals.

For example, during t1, the first clock signal input terminal CK1 receives low level signal, second clock signal input part CK2, the 3rd clock signal input terminal CK3 receive high level signal, the first transistor T1, the 4th transistor T4, transistor seconds T2, the 7th transistor T7 and the 8th transistor T8 are turned on, the first output end SN output high level signals, the second output end EM outputs High level signal.

For example, during t2, the 3rd clock signal input terminal CK3 receives low level signal, the first clock signal input terminal CK1, second clock signal input part CK2 and driving signal input IN receive high level signal, the 7th transistor T7, the 8th crystalline substance Body pipe T8 and transistor seconds T2 is turned on, the second output end EM output high level signals, the first output end SN output low level letters Number.

For example, during t3, second clock signal input part CK2 receives low level signal, the first clock signal input terminal CK1, the 3rd clock signal input terminal CK3 and driving signal input IN receive high level signal, the 5th transistor T5, the 6th crystalline substance Body pipe T6, third transistor T3, the 9th transistor T9 conductings, the second output end EM output low level signals, the first output end SN Output high level signal.

For example, during t4, the first clock signal input terminal CK1 receives low level signal, second clock signal input part CK2 and the 3rd clock signal input terminal CK3 receives high level signal, and the first transistor T1 and the 4th transistor T4 is turned on, and first Output end SN exports high level signal, the second output end EM output low level signals.

For example, during t5, the 3rd clock signal input terminal CK3 receives low level signal, the first clock signal input terminal CK1, second clock signal input part CK2 and driving signal input IN receive high level signal, and the first output end SN outputs are high Level signal, the second output end EM output low level signals.

For example, during t6, second clock signal input part CK2 receives low level signal, the first clock signal input terminal CK1, the 3rd clock signal input terminal CK3 and driving signal input IN receive high level signal, and the 5th transistor T5 is turned on, the One output end SN exports high level signal, the second output end EM output low level signals.

Also referring to Fig. 1 and Fig. 2, the course of work to the array base palte horizontal drive circuit in the present embodiment is derived It is as follows:

During t1, CK1 and STV is low level, and CK2 and CK3 is high level, so, T1 and T4 is turned on, and B points and C points are low Level, T2, T7, T8 conducting, A points are high level, so SN output high level, EM output high level;

During t2, CK3 is low level, and CK1, CK2 and STV are high level, so, due to the maintenance effect of electric capacity C2, B points Low level is maintained at, so T7, T8 are turned on, A points are still high level, and EM output high level, C points keep low level, T2 conductings, SN Output low level, simultaneously because the coupling of electric capacity C1, the voltage of C points becomes lower.It should be noted that the coupling of electric capacity C1 Cooperation is with being specially:Electric capacity has the characteristic that its interior electric charge is not mutated, and the voltage difference for showing as electric capacity two ends will not be mutated, i.e. C1 Two ends, the voltage difference of SN and C points will not be mutated, so during t2, SN is changed into low level, voltage reduction, C points from high level The voltage of SN can be followed to be reduced.

During t3, CK2 is low level, and CK1, CK3 and STV are high level, so, T5 conductings, A points are low level, so T6, T9 are turned on, and B points are high level, and EM output low levels, EM causes that T3 is turned on for low level, and C points are low level, so SN is defeated Go out high level;

During t4, CK1 is low level, and CK2, CK3 and STV are high level, so, T1 and T4 is turned on, and B points and C points are height Level, A points maintain low level, so SN output high level, EM output low levels;

During t5, CK3 is low level, and CK1, CK2 and STV are high level, so, A points maintain low level, B points and C points High level, SN is maintained to continue to output high level, EM output low levels;

During t6, CK2 is low level, and CK1, CK3 and STV are high level, so, T5 conductings, A points are low level, B points and C points maintain high level, SN output high level, EM output low levels;

T7 and later time, circuit then repeat the action during t4~t6, until the low level of next STV is reached, Action during repeating t1, to complete the output of SN and EM.

Also referring to Fig. 1, Fig. 2 and Fig. 3, for the ease of understanding the work(of each component in array base palte horizontal drive circuit Can, now by above-mentioned array base palte horizontal drive circuit be divided into three functional modules, including GOA control modules, SN output modules with And EM output modules.

For example, GOA control modules include the first transistor T1, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6 and the 7th transistor T7.The first transistor T1 is SN signal low level output control units, the low electricity for controlling SN signals Flat output.4th transistor T4 is EM signal high level output control units, the high level output for controlling EM signals.5th Transistor T5 is EM signal low level output control units, the low level output for controlling EM signals.6th transistor T6 and 7th transistor T7 is pull-up unit, drop-down for the control in the first transistor T1, the 4th transistor T4, the 5th transistor T5 The level of high correspondence output unit.

For example, SN output modules include transistor seconds T2 and third transistor T3.Transistor seconds T2 is that SN signals are low Level output unit, for exporting low level SN signals.Third transistor T3 is SN signal high level output units, for defeated Go out the SN signals of high level.

For example, EM output modules include the 8th transistor T8 and the 9th transistor T9.8th transistor T8 is that EM signals are high Level output unit, the EM signals for exporting high level.9th transistor T9 is EM signal low level output units, for defeated Go out low level EM signals.Meanwhile, the 8th transistor T8 and the 9th transistor T9 collectively constitutes the control of SN signals high level output Unit, the high level output for controlling SN signals.

Fig. 4 is referred to, for example, array base palte horizontal drive circuit also includes the tenth transistor T10, its grid connection the 3rd is brilliant The grid of body pipe T3, source electrode connection high level input VGH, the grid of drain electrode connection transistor seconds T2.

For example, the 7th transistor T7 includes double-gate structure thin film transistor (TFT), for example, the double-gate structure thin film transistor (TFT) includes First double-gate structure thin film transistor (TFT) T7_1 and the second double-gate structure thin film transistor (TFT) T7_2.

In this way, brilliant by the tenth transistor T10, the first double-gate structure thin film transistor (TFT) T7_1 and the second double-gate structure film Body pipe T7_2, can cause that the stability of A and C nodes is increased substantially, and be more beneficial for the stabilization output of GOA signals, the GOA Signal includes SN signals and EM signals.

Also referring to Fig. 4 and Fig. 5, the course of work to the array base palte horizontal drive circuit in the present embodiment is derived It is as follows:

During t1, CK1 and STV is low level, and CK2 and CK3 is high level, so, T1 and T4 is turned on, and B points and C points are low Level, so T2, T7 (T7_1 and T7_2), T8 conductings, A points are high level, and T3, T9 and T10 cut-off, SN export CK3 high level, EM exports VGH high level;

During t2, CK3 is low level, and CK1, CK2 and STV are high level, so, due to the maintenance effect of electric capacity C2, B points Low level is maintained at, so T7 (T7_1 and T7_2), T8 are turned on, A points are still high level, T3, T9 and T10 cut-off, EM outputs VGH High level, due to the maintenance effect of electric capacity C1, C points keep low level, T2 conductings, SN output CK3 low levels, simultaneously because electric capacity The coupling of C1, the voltage of C points becomes lower;

During t3, CK2 is low level, and CK1, CK3 and STV are high level, so, T5 conductings, A points are low level, so T3, T6, T9 and T10 are turned on, and B points are high level, and T7 (T7_1 and T7_2), T8 cut-off, C points are high level, T2 cut-offs, so SN Output VGH high level EM output VGL low levels;

During t4, CK1 is low level, and CK2, CK3 and STV are high level, so, T1 and T4 is turned on, and B points and C points are height Level, T2, T7 (T7_1 and T7_2) and T8 end, and A points maintain low level, T3, T9 and T10 conducting, so SN outputs VGH is high Level, EM output VGL low levels;

During t5, CK3 is low level, and CK1, CK2 and STV are high level, so, A points maintain low level, B points and C points High level, SN is maintained to continue to output VGH high level, EM output VGL low levels;

During t6, CK2 is low level, and CK1, CK3 and STV are high level, so, T5 conductings, A points are low level, B points and C points maintain high level, SN output VGH high level, EM output VGL low levels;

T7 and later time, circuit then repeat the action during t4~t6, until the low level of next STV is reached, Action during repeating t1 completes the output of SN and EM.

Also referring to Fig. 4, Fig. 5 and Fig. 6, for the ease of understanding the work(of each component in array base palte horizontal drive circuit Can, now by above-mentioned array base palte horizontal drive circuit be divided into three functional modules, including GOA control modules, SN output modules with And EM output modules.

For example, GOA control modules include the first transistor T1, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6, the first double-gate structure thin film transistor (TFT) T7_1 and the second double-gate structure thin film transistor (TFT) T7_2.The first transistor T1 believes for SN Number low level output control unit, the low level output for controlling SN signals.4th transistor T4 is that EM signal high level is defeated Go out control unit, the high level output for controlling EM signals.5th transistor T5 is EM signal low level output control units, Low level output for controlling EM signals.6th transistor T6, the first double-gate structure thin film transistor (TFT) T7_1, the second double grid knot Structure thin film transistor (TFT) T7_2 and the tenth transistor T10 be pull-up unit, for the first transistor T1, the 4th transistor T4, The level of correspondence output unit is drawn high under the control of the 5th transistor T5.Meanwhile, the 5th transistor T5, the first double-gate structure film Transistor T7_1 and the second double-gate structure thin film transistor (TFT) T7_2 collectively constitute SN signal high level output control units, for controlling The high level output of SN signals processed.

For example, SN output modules include transistor seconds T2 and third transistor T3.Transistor seconds T2 is that SN signals are low Level output unit, for exporting low level SN signals.Third transistor T3 is SN signal high level output units, for defeated Go out the SN signals of high level.

For example, EM output modules include the 8th transistor T8 and the 9th transistor T9.8th transistor T8 is that EM signals are high Level output unit, the EM signals for exporting high level.9th transistor T9 is EM signal low level output units, for defeated Go out low level EM signals.

For example, the transistor T9 of the first transistor T1 to the 9th are thin film transistor (TFT).And for example, the first transistor T1 to the 9th Transistor T9 is the thin film transistor (TFT) of p-type.

For example, the transistor T9 of the first transistor T1 to the 9th are the mos field effect transistor of p-type.

For example, the transistor T9 of the first transistor T1 to the 9th are p-type bipolar junction transistor.

Fig. 7 is referred to, shift register includes that the first clock signal input connection end 210, second clock signal input connect End 220, the 3rd clock signal connection end 230 and multiple cycling elements 240 are connect, each cycling element 240 includes three-level Array base palte horizontal drive circuit.For example, three-level array base palte horizontal drive circuit include first order array base palte horizontal drive circuit G1, Second level array base palte horizontal drive circuit G2 and third level array base palte horizontal drive circuit G3.For example, next cycling element 240 Since fourth stage array base palte horizontal drive circuit G4, by that analogy.

For example, the first clock signal input terminal CK1 connections described the of the first order array base palte horizontal drive circuit G1 One clock signal input connection end 210, second clock signal input part CK2 connects the second clock signal input connection end, 3rd clock signal input terminal CK3 connects the 3rd clock signal input connection end.

For example, the first clock signal input terminal CK1 connections described the of the second level array base palte horizontal drive circuit G2 Three clock signal input connection ends, second clock signal input part CK2 connects the first clock signal input connection end 210, 3rd clock signal input terminal CK3 connects the second clock signal input connection end.

For example, the first clock signal input terminal CK1 connections described the of the third level array base palte horizontal drive circuit G3 Two clock signal input connection ends, second clock signal input part CK2 connects the 3rd clock signal input connection end, the 3rd Clock signal input terminal CK3 connects the first clock signal input connection end 210.

For example, the first output end SN of the first order array base palte horizontal drive circuit G1 connects the second level array base The driving signal input IN, the first output end SN of the second level array base palte horizontal drive circuit G2 of plate horizontal drive circuit G2 The driving signal input IN of the third level array base palte horizontal drive circuit G3 is connected, wherein, only first cycling element 240 First order array base palte horizontal drive circuit G1 driving signal input IN be used for connect outside frame open signal.

Fig. 8 is referred to, array base palte is provided with shift register.Shift register provides drive signal for pixelated array. For example, shift register is directly produced on array base palte, to cause that the row stably for needed for pixelated array is provided drives letter Number.

Fig. 9 is referred to, display includes array base palte.For example, array base palte using above-mentioned with shift register Array base palte is made, and the scanning of image element circuit is carried out to cause it to receive horizontal-drive signal, to show complete picture.Example Such as, the display includes that (Active Matrix/Organic Light Emitting Diode, have for liquid crystal panel and AMOLED Source matrix Organic Light Emitting Diode) panel.Liquid crystal panel and AMOLED panel are using above-mentioned array base palte and by above-mentioned driving Circuit drives.

Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited In contradiction, the scope of this specification record is all considered to be.

Embodiment described above only expresses several embodiments of the invention, and description is more specific and detailed, but not Can therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, Without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection model of the invention Enclose.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.

Claims (10)

1. a kind of array base palte horizontal drive circuit, it is characterised in that including:The first transistor is to the 9th transistor, the first electric capacity To the 3rd electric capacity, the first clock signal input terminal to the 3rd clock signal input terminal, high level input, low-level input, First output end, the second output end and driving signal input;
The grid of the first transistor connects first clock signal input terminal, the drain electrode connection drive signal input End;
The grid of the transistor seconds connects the source electrode of the first transistor, and source electrode connects the 3rd clock signal input End, drain electrode connection first output end;
The grid of the third transistor connects second output end or connects the drain electrode of the 7th transistor, and source electrode connects Connect the drain electrode of the transistor seconds, the drain electrode connection high level input;
The grid of the 4th transistor connects first clock signal input terminal, and source electrode connects the drive signal input End;
The grid of the 5th transistor connects the second clock signal input part, the drain electrode connection low-level input;
The grid of the 6th transistor connects the source electrode of the 5th transistor, and source electrode connects the high level input, leakage Pole connects the drain electrode of the 4th transistor;
The grid of the 7th transistor connects the drain electrode of the 6th transistor, and source electrode connects the high level input, leakage Pole connects the grid of the 6th transistor;
The grid of the 8th transistor connects the grid of the 7th transistor, and source electrode connects the high level input, leakage Pole connects second output end;
The grid of the 9th transistor connects the drain electrode of the 7th transistor, and source electrode connects second output end, drain electrode Connect the low-level input;
One end of first electric capacity connects the drain electrode of the transistor seconds, and the other end connects the grid of the transistor seconds Pole;
One end of second electric capacity connects the high level input, and the other end connects the grid of the 8th transistor;
One end of 3rd electric capacity connects the source electrode of the 9th thin film transistor (TFT), and the other end connects the grid of the 9th transistor Pole.
2. array base palte horizontal drive circuit according to claim 1, is characterised by, also including the tenth transistor, its grid The grid of third transistor is connected, source electrode connects the high level input, the grid of the drain electrode connection transistor seconds.
3. array base palte horizontal drive circuit according to claim 1, is characterised by, the 7th transistor includes double grid knot Structure thin film transistor (TFT).
4. array base palte horizontal drive circuit according to claim 1, is characterised by, the first transistor to the described 9th Transistor is thin film transistor (TFT).
5. array base palte horizontal drive circuit according to claim 4, is characterised by, the first transistor to the described 9th Transistor is the thin film transistor (TFT) of p-type.
6. array base palte horizontal drive circuit according to claim 1, is characterised by, the first transistor to the described 9th Transistor is the mos field effect transistor of p-type.
7. array base palte horizontal drive circuit according to claim 1, is characterised by, the first transistor to the described 9th Transistor is p-type bipolar junction transistor.
8. a kind of shift register, is characterised by, including the first clock signal input connection end to the 3rd clock signal connection end, And multiple cycling elements, each cycling element includes three-level array base palte horizontal drive circuit, the three-level array base palte Horizontal drive circuit includes first order array base palte horizontal drive circuit to third level array base palte horizontal drive circuit;Wherein, per one-level Array base palte horizontal drive circuit is the array base palte horizontal drive circuit as described in claim 1 to 7 is any;
First clock signal input terminal of the first order array base palte horizontal drive circuit connects first clock signal input Connection end, second clock signal input part connects the second clock signal input connection end, and the 3rd clock signal input terminal connects Connect the 3rd clock signal input connection end;
First clock signal input terminal of the second level array base palte horizontal drive circuit connects the 3rd clock signal input Connection end, second clock signal input part connects the first clock signal input connection end, and the 3rd clock signal input terminal connects Connect the second clock signal input connection end;
First clock signal input terminal of the third level array base palte horizontal drive circuit connects the second clock signal input Connection end, second clock signal input part connects the 3rd clock signal input connection end, and the 3rd clock signal input terminal connects Connect the first clock signal input connection end;
First output end of the first order array base palte horizontal drive circuit connects the second level array base palte horizontal drive circuit Driving signal input, the first output end of the second level array base palte horizontal drive circuit connects the third level array base The driving signal input of plate horizontal drive circuit, wherein,
Only first driving signal input of the first order array base palte horizontal drive circuit of cycling element is opened for receiving frame Signal.
9. a kind of array base palte, it is characterised in that it includes shift register as claimed in claim 8.
10. a kind of display, it is characterised in that it includes array base palte as claimed in claim 9.
CN201510542621.7A 2015-08-27 2015-08-27 Array base palte horizontal drive circuit, shift register, array base palte and display CN105139801B (en)

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