CN116030747A - Scanning circuit and display panel - Google Patents
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Abstract
The invention discloses a scanning circuit and a display panel. The scanning circuit comprises a first control module, a second control module and an output module; the first control module is connected with the first control end of the output module and is used for outputting a first control signal to the first control end according to the input signal, the first clock signal and the first power supply; the second control module is connected with the second control end of the output module and is used for outputting a second control signal to the second control end according to the input signal, the first clock signal, the first control signal, the first power supply and the second clock signal; wherein the first control signal and the second control signal are opposite in level; the output module is used for outputting a first power supply or a second clock signal according to the first control signal and the second control signal. The intermediate state of the set clock signal can be avoided, so that the pulse width of the scan signal output by the scan circuit can be increased.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a scanning circuit and a display panel.
Background
The display panel is provided with a scanning circuit which provides scanning signals for the pixel units and controls the pixel units in the display panel to be driven row by row. In the prior art, a clock signal provided for a scan circuit needs to be set to an intermediate state to ensure that the scan circuit normally outputs a scan signal. At this time, the intermediate state of the clock signal takes a certain time, which results in a smaller pulse time of the scan signal, which is unfavorable for the display of the display panel.
Disclosure of Invention
The invention provides a scanning circuit and a display panel, which are beneficial to improving the resolution and refresh rate of the display panel by increasing the pulse width of a scanning signal.
In a first aspect, an embodiment of the present invention provides a scan circuit, including a first control module, a second control module, and an output module;
the first control module is connected with a first control end of the output module and is used for outputting a first control signal to the first control end according to an input signal, a first clock signal and a first power supply; the second control module is connected with a second control end of the output module, and is used for outputting a second control signal to the second control end according to the input signal, the first clock signal, the first control signal, the first power supply and the second clock signal; wherein the first control signal and the second control signal are opposite in level; the output module is used for outputting the first power supply according to the first control signal and outputting the second clock signal according to the second control signal.
Optionally, the first control module includes an input inversion unit and a clock following unit; the working phases of the input inverting unit and the clock following unit are different;
The control end of the input inversion unit is used for inputting the input signal, the input end of the input inversion unit is connected with the first power supply input end, the output end of the input inversion unit is connected with the first control end, and the input inversion unit is used for inverting the input signal when the input signal is valid;
the control end of the clock following unit is connected with the input signal end, the first input end of the clock following unit is connected with the first power input end, the second input end of the clock following unit is connected with the first clock signal input end, the output end of the clock following unit is connected with the first control end, and the clock following unit is used for outputting the first clock signal when the first clock signal is effective.
Optionally, the input inverting unit includes a first transistor, and the clock following unit includes a second transistor, a third transistor, and a first capacitor;
the grid electrode of the first transistor and the grid electrode of the second transistor are used for inputting the input signal, the first electrode of the first transistor and the first electrode of the second transistor are connected with the first power input end, the second electrode of the first transistor and the second electrode of the third transistor are connected with the first control end, the second electrode of the second transistor is connected with the grid electrode of the third transistor and the first electrode of the first capacitor, and the first electrode of the third transistor and the second electrode of the first capacitor are connected with the first clock signal input end.
Optionally, the second control module includes an input following unit and a node control unit;
the control end of the input following unit is connected with the first clock signal input end, the input end of the input following unit is connected with the input signal end, the output end of the input following unit is connected with the second control end, and the input following unit is used for outputting the input signal when the first clock signal is effective;
the third control end of the node control unit is connected with the first control end, the fourth control end of the node control unit is connected with the second clock signal input end, the input end of the node control unit is connected with the first power input end, the output end of the node control unit is connected with the second control end, and the node control unit is used for controlling the potential of the second control end according to the first control signal and the second clock signal.
Optionally, the input following unit includes a fourth transistor, and the node control unit includes a fifth transistor and a sixth transistor;
the grid electrode of the fourth transistor is connected with the first clock signal input end, the first electrode of the fourth transistor is connected with the input signal end, and the second electrode of the fourth transistor and the second electrode of the sixth transistor are connected with the second control end; the grid electrode of the fifth transistor is connected with the first control end, the first electrode of the fifth transistor is connected with the first power input end, the second electrode of the fifth transistor is connected with the first electrode of the sixth transistor, and the grid electrode of the sixth transistor is connected with the second clock signal input end.
Optionally, a gate of the first transistor is connected to the input signal terminal or a second pole of the fourth transistor.
Optionally, the output module includes a first output unit and a second output unit;
the control end of the first output unit is used as the first control end, the input end of the first output unit is connected with the first power input end, and the output end of the first output unit is connected with the output end of the second output unit and used as the output end of the scanning circuit; the control end of the second output unit is used as the second control end, and the input end of the second output unit is connected with the second clock signal input end.
Optionally, the first output unit includes a seventh transistor and a second capacitor; the grid electrode of the seventh transistor is connected with the first electrode of the second capacitor and used as the first control end, the first electrode of the seventh transistor and the second electrode of the second capacitor are connected with the first power input end, and the second electrode of the seventh transistor is used as the output end of the scanning circuit;
the second output unit includes an eighth transistor and a third capacitor; the grid electrode of the eighth transistor is connected with the first electrode of the third capacitor and used as the second control end, the first electrode of the eighth transistor is connected with the second clock signal input end, and the second electrode of the eighth transistor is connected with the second electrode of the third capacitor and used as the output end of the scanning circuit; or alternatively, the first and second heat exchangers may be,
The second output unit includes an eighth transistor, a ninth transistor, and a third capacitor; the gate of the eighth transistor and the gate of the ninth transistor are connected to the first pole of the third capacitor, and serve as the second control end, the first pole of the eighth transistor and the first pole of the ninth transistor are both connected to the second clock signal input end, the second pole of the ninth transistor is connected to the second pole of the third capacitor, and the second pole of the eighth transistor serves as the output end of the scanning circuit.
Optionally, the scanning circuit further includes a tenth transistor; the grid electrode of the tenth transistor is connected with a second power input end, and the second control module is connected with the second control end through the tenth transistor.
In a second aspect, an embodiment of the present invention further provides a display panel, including a pixel driving circuit and any one of the scanning circuits in the first aspect; the scanning circuit is connected with the pixel driving circuit and is used for providing scanning signals for the pixel driving circuit.
According to the technical scheme, the first control signal and the second control signal are set to be signals with opposite levels, when the output module outputs the second clock signal according to the second control signal, when the second clock signal jumps from high level to low level, the output module can be ensured to stop outputting the first power supply according to the first control signal, the intermediate state of the clock signal is prevented from being set, the output module can be ensured to output the first power supply by mistake when the second clock signal jumps from high level to low level, and therefore the pulse width of the scanning signal output by the scanning circuit can be increased. When the scanning circuit is used for the display panel, the display effect of the display panel is improved.
Drawings
FIG. 1 is a schematic diagram of a part of a scan circuit according to the prior art;
fig. 2 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of another scan circuit according to an embodiment of the present invention;
FIG. 12 is a timing diagram of signals corresponding to the scan circuit shown in FIG. 11;
fig. 13 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic diagram of a part of a scan circuit according to the prior art. As shown in fig. 1, the scan circuit includes a first output transistor M1, a second output transistor M2, and a first control transistor M3, where a gate of the first output transistor M1 is connected to a second pole of the first control transistor M3, a first pole of the first output transistor M1 is connected to the high-level power supply input terminal VGH, a second pole of the first output transistor M1 is connected to a second pole of the second output transistor M2 as an output terminal OUT of the scan circuit, a gate of the second output transistor M2 is connected to a gate of the first control transistor M3, a first pole of the second output transistor M2 is connected to the second clock signal input terminal CK2, and a first pole of the first control transistor M3 is connected to the first clock signal input terminal CK1, and a gate of the first control transistor M3 and a gate of the second output transistor M2 are used for inputting a start signal. The operation of the pixel driving circuit is described by taking as an example the driving of the pixel driving circuit when the scanning signal outputted from the output terminal OUT of the scanning circuit is at a low level. In the first stage, the start signal is at a low level, the first clock signal provided by the first clock signal input terminal CK1 is at a low level, the second clock signal provided by the second clock signal input terminal CK2 is at a high level, the first output transistor M1, the second output transistor M2 and the first control transistor M3 are turned on, and the output terminal OUT of the scan circuit outputs a high level. Before the next stage arrives, the first clock signal is in preference to the second clock jump, that is, the first clock jumps from low level to high level, at this time, the first clock signal and the second clock signal are both high level, so that the first output transistor M1 is turned off under the action of the first clock signal, and then the second clock signal jumps from high level to low level, so that the second output transistor M2 outputs low level, thereby realizing the shift of the input signal. In the above process, the first clock signal is in preference to the second clock signal, so that the state that the first clock signal and the second clock signal are at high level simultaneously is the intermediate state of the clock signal, and a certain time is required to be occupied, so that the time of the scanning signal output by the scanning circuit is one intermediate state time less than the line time, which is not beneficial to the display of the display panel. The line time is the display period of the display panel divided by the number of lines of pixel units in the display panel, and the display period of the display panel is the reciprocal of the refresh rate of the display panel.
Aiming at the technical problems, the embodiment of the invention provides a scanning circuit. Fig. 2 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention. As shown in fig. 2, the scanning circuit includes a first control module 110, a second control module 120, and an output module 130; the first control module 110 is connected to the first control end CTRL1 of the output module 130, and the first control module 110 is configured to output a first control signal to the first control end CTRL1 according to the input signal, the first clock signal, and the first power supply; the second control module 120 is connected to the second control end CTRL2 of the output module 130, and the second control module 120 is configured to output a second control signal to the second control end CTRL2 according to the input signal, the first clock signal, the first control signal, the first power supply, and the second clock signal; wherein the first control signal and the second control signal are opposite in level; the output module 130 is configured to output a second clock signal according to the first control signal and the second control signal.
Specifically, the input signal terminal SIN is used for providing an input signal, the first clock signal input terminal CLK1 is used for providing a first clock signal, the second clock signal input terminal CLK2 is used for providing a second clock signal, the first power supply input terminal VH is used for providing a first power supply, the second clock signal input terminal CLK2 is used for providing a second clock signal, and the output terminal SOUT of the scan circuit is used for outputting a scan signal. Taking the first control terminal CTRL1 of the output module 130 as the low level, the output module 130 outputs the first power, and the second control terminal CTRL2 as the low level, the output module 130 outputs the second clock signal as an example. The first power supply may be high and the first and second clock signals may be opposite-level signals. During the operation of the scan circuit, when the second control signal provided by the second control module 120 is at a low level, the output module 130 may output the second clock signal according to the second control signal. At this time, the level of the first control signal is opposite to the level of the second control signal, i.e. the first control signal is at a high level, and the output module 130 stops outputting the first power according to the first control signal. Therefore, when the scanning circuit outputs the second clock signal, the second control signal is low level, and the first control signal is high level. When the second clock signal transitions from high level to low level, the output module 130 can be ensured to stop outputting the first power supply according to the first control signal, and the intermediate state of the clock signal is avoided to ensure that the output module 130 outputs the first power supply by mistake when the second clock signal transitions from high level to low level, so that the pulse width of the scanning signal output by the scanning circuit can be increased. When the scanning circuit is used for the display panel, the display effect of the display panel is improved.
Illustratively, in the first phase, the input signal is low, the first clock signal is low, and the second clock signal is high. The second control module 120 outputs an input signal, i.e., the second control signal is low, according to the input signal and the first clock signal. At this time, the first control module 110 outputs the first power according to the input signal and the first clock signal, i.e. the first control signal is at a high level, so as to ensure that the levels of the second control signal and the first control signal are opposite. The output module 130 outputs the second clock signal according to the second control signal while stopping outputting the first power according to the first control signal. At this time, the scanning signal outputted from the scanning circuit is at a high level. Since the first control signal is at a high level, when the second clock signal transitions from a high level to a low level, the output module 130 can be ensured to stop outputting the first power according to the first control signal, and the setting of the intermediate state of the clock signal is avoided to ensure that the output module 130 outputs the first power by mistake when the second clock signal transitions from a high level to a low level, thereby increasing the pulse width of the scan signal output by the scan circuit.
According to the technical scheme, through setting the first control signal and the second control signal to be signals with opposite levels, when the output module outputs the second clock signal according to the second control signal, when the second clock signal jumps from high level to low level, the output module can be ensured to stop outputting the first power supply according to the first control signal, the intermediate state of the clock signal is prevented from being set, the first power supply is ensured to be output by mistake when the second clock signal jumps from high level to low level, and therefore the pulse width of the scanning signal output by the scanning circuit can be increased. When the scanning circuit is used for the display panel, the display effect of the display panel is improved.
Fig. 3 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 3, the first control module 110 includes an input inversion unit 111 and a clock following unit 112; the operation phases of the input inverting unit 111 and the clock following unit 112 are different; the control end of the input inversion unit 111 is used for inputting an input signal, the input end of the input inversion unit 111 is connected with the first power input end VH, the output end of the input inversion unit 111 is connected with the first control end CTRL1, and the input inversion unit 111 is used for inverting the input signal when the input signal is valid; the control terminal of the clock follower unit 112 is connected to the input signal terminal SIN, the first input terminal of the clock follower unit 112 is connected to the first power input terminal VH, the second input terminal of the clock follower unit 112 is connected to the first clock signal input terminal CLK1, the output terminal of the clock follower unit 112 is connected to the first control terminal CTRL1, and the clock follower unit 112 is configured to output the first clock signal when the first clock signal is active.
Specifically, fig. 3 exemplarily shows that the control terminal of the input inverting unit 111 is connected to the input signal terminal SIN for inputting an input signal. The input signal and the first clock signal are active when they are low. In the first stage, the input signal is low, the first clock signal is low, and the second clock signal is high. The input inversion unit 111 sets a path according to an input signal, and outputs a first power to the first control terminal CTRL1, so that the first control signal is at a high level, and the inversion of the input signal is achieved. The output module 130 stops outputting the first power according to the first control signal. Since the first control signal is at a high level, when the second clock signal transitions from a high level to a low level, the output module 130 can be ensured to stop outputting the first power according to the first control signal, and the setting of the intermediate state of the clock signal is avoided to ensure that the output module 130 outputs the first power by mistake when the second clock signal transitions from a high level to a low level, thereby increasing the pulse width of the scan signal output by the scan circuit. The operation phases of the input inverting unit 111 and the clock following unit 112 are different. When the input inverting unit 111 inverts the input signal, the clock following unit 112 stops outputting the first clock signal.
In the second stage, the input signal is high, the first clock signal is high, and the second clock signal is low, and the first clock signal is not valid. The input inversion unit 111 is set to be off according to an input signal, and the clock following unit 112 is set to be off according to a first clock signal, so that the first control terminal CTRL1 is in a floating state. The potential maintaining function of the output module 130 maintains the potential of the first control terminal CTRL1 at a high level. In the third stage, the input signal is high, the first clock signal is low, and the second clock signal is high, and the first clock signal is inactive. The input inverting unit 111 is set to be off according to the input signal, while the clock following unit 112 is set to be on according to the first clock signal, and the clock following unit 112 follows and outputs the first clock signal to the first control terminal CTRL1, i.e., the first control signal is at a low level. The output module 130 outputs the first power source according to the first control signal, i.e. the scan signal output by the scan circuit is at a high level. Similarly, the operation phases of the input inverting unit 111 and the clock following unit 112 are different. When the clock follower unit 112 outputs the first clock signal, the input inverting unit 111 stops inverting the output input signal.
Fig. 4 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 4, the input inverting unit 111 includes a first transistor T1, and the clock following unit 112 includes a second transistor T2, a third transistor T3, and a first capacitor C1; the gate of the first transistor T1 and the gate of the second transistor T2 are both used for inputting an input signal, the first pole of the first transistor T1 and the first pole of the second transistor T2 are both connected to the first power input terminal VH, the second pole of the first transistor T1 and the second pole of the third transistor T3 are both connected to the first control terminal CTRL1, the second pole of the second transistor T2 is connected to the gate of the third transistor T3 and the first pole of the first capacitor C1, and the first pole of the third transistor T3 and the second pole of the first capacitor C1 are both connected to the first clock signal input terminal CLK 1.
Specifically, fig. 4 exemplarily shows that the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors, and the gate of the first transistor T1 and the gate of the second transistor T2 are connected to the input signal terminal SIN for inputting an input signal. When the input signal is at a low level, the first transistor T1 is turned on according to the input signal, and outputs the first power provided by the first power input terminal VH to the first control terminal CTRL1, so as to realize inversion of the input signal. At this time, the second transistor T2 is turned on, the second transistor T2 transmits the first power supplied from the first power input terminal VH to the gate of the third transistor T3, and controls the third transistor T3 to be turned off, i.e., the clock follower unit 112 stops outputting the first clock signal. When the input signal is at a high level, the first transistor T1 and the second transistor T2 are turned off, i.e., the input inversion unit 111 stops inverting the output input signal. If the first clock signal provided by the first clock signal input terminal CLK1 transitions from a high level to a low level, the first capacitor C1 couples the first clock signal to the gate of the third transistor T3, so that the gate of the third transistor T3 is at a low level, and the third transistor T3 is controlled to be turned on, and the third transistor T3 outputs the first clock signal to the first control terminal CTRL1, i.e., the first control signal is at a low level. The output module 130 outputs the first power according to the first control signal, and the scan signal output by the scan circuit is at a high level.
It should be noted that, in other embodiments, the first transistor T1, the second transistor T2, and the third transistor T3 may also be N-type transistors, where the high and low levels of the signals are inverted.
Fig. 5 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 5, the second control module 120 includes an input following unit 121 and a node control unit 122; the control end of the input follower unit 121 is connected with the first clock signal input end CLK1, the input end of the input follower unit 121 is connected with the input signal end SIN, the output end of the input follower unit 121 is connected with the second control end CTRL2, and the input follower unit 121 is used for outputting an input signal when the first clock signal is valid; the third control end of the node control unit 122 is connected to the first control end CTRL1, the fourth control end of the node control unit 122 is connected to the second clock signal input end CLK2, the input end of the node control unit 122 is connected to the first power input end VH, the output end of the node control unit 122 is connected to the second control end CTRL2, and the node control unit 122 is configured to control the potential of the second control end CTRL2 according to the first control signal and the second clock signal.
Specifically, the description will be given taking as an example that the input signal and the first clock signal are active when they are low. In the first stage, the input signal is low, the first clock signal is low, and the second clock signal is high. The input follower unit 121 sets a path according to the first clock signal, and outputs an input signal to the second control terminal CTRL2 such that the second control signal is at a low level. The output module 130 outputs the second clock signal to be high level according to the second control signal. While the first control signal is high, the control node control unit 122 is open. In the second stage, the input signal is high, the first clock signal is high, the second clock signal is low, and the input follower unit 121 is set to be off according to the first clock signal. The first control signal is maintained at a high level, and the node control unit 122 is continuously controlled to be opened, so that the second control terminal CTRL2 is in a floating state. The potential maintaining function of the output module 130 maintains the potential of the second control terminal CTRL2 to be low, and the output module 130 outputs the second clock signal according to the second control signal, that is, the scan signal is low, so as to realize the shift output of the input signal. In the third stage, the input signal is high, the first clock signal is low, the second clock signal is high, and the input follower unit 121 is set to the path according to the first clock signal. The input follower unit 121 transmits the input signal to the second control terminal CTRL2, i.e. the second control signal is at a high level, and the output module 130 stops outputting the second clock signal according to the second control signal. The first control signal is low, the second clock signal is high, and the node control unit 122 is set to be off according to the second clock signal. In the fourth stage, the input signal is high, the first clock signal is high, the second clock signal is low, and the input follower unit 121 is set to be off according to the first clock signal. Meanwhile, the first control module 110 is set to be turned off according to the input signal and the first clock signal, the potential maintaining function of the output module 130 maintains the potential of the first control terminal CTRL1 to be at a low level, the node control unit 122 is set to be at a path according to the first control signal and the second clock signal, the node control unit 122 transmits the first power to the second control terminal CTRL2, that is, the second control signal is at a high level, and the output module 130 stops outputting the second clock signal according to the second control signal.
Fig. 6 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 6, the input follower unit 121 includes a fourth transistor T4, and the node control unit 122 includes a fifth transistor T5 and a sixth transistor T6; the gate of the fourth transistor T4 is connected to the first clock signal input terminal CLK1, the first pole of the fourth transistor T4 is connected to the input signal terminal SIN, and the second pole of the fourth transistor T4 and the second pole of the sixth transistor T6 are connected to the second control terminal CTRL 2; the gate of the fifth transistor T5 is connected to the first control terminal CTRL1, the first pole of the fifth transistor T5 is connected to the first power input terminal VH, the second pole of the fifth transistor T5 is connected to the first pole of the sixth transistor T6, and the gate of the sixth transistor T6 is connected to the second clock signal input terminal CLK 2.
Specifically, fig. 6 exemplarily shows that the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type transistors. The first power supply is high, the input signal is low, the first clock signal is low, and the second clock signal is high in the first stage. The fourth transistor T4 is turned on, the sixth transistor T6 is turned off, and the fourth transistor T4 transmits the input signal to the second control terminal CTRL2 such that the second control signal is at a low level. The output module 130 outputs the second clock signal to be high level according to the second control signal. At the same time, the first control signal is high, and the fifth transistor T5 is controlled to be turned off. In the second stage, the input signal is high, the first clock signal is high, the second clock signal is low, the fourth transistor T4 is turned off, and the sixth transistor T6 is turned on. The first control signal is maintained at a high level, and the fifth transistor T5 is turned off, so that the second control terminal CTRL2 is in a floating state. The potential maintaining function of the output module 130 maintains the potential of the second control terminal CTRL2 to be low, and the output module 130 outputs the second clock signal according to the second control signal, that is, the scan signal is low, so as to realize the shift output of the input signal. In the third stage, the input signal is high, the first clock signal is low, the second clock signal is high, the fourth transistor T4 is turned on, and the sixth transistor T6 is turned off. The fourth transistor T4 outputs a high level to the second control terminal CTRL2, i.e. the second control signal is high level, and the output module 130 stops outputting the second clock signal according to the second control signal. The first control signal is low, and the fifth transistor T5 is turned on. In the fourth stage, the input signal is high, the first clock signal is high, the second clock signal is low, the fourth transistor T4 is turned off, and the sixth transistor T6 is turned on. Meanwhile, the potential of the first control terminal CTRL1 is maintained at a low level, the fifth transistor T5 is turned on, the first power is transmitted to the second control terminal CTRL2 through the fifth transistor T5 and the sixth transistor T6, that is, the second control signal is at a high level, and the output module 130 stops outputting the second clock signal according to the second control signal.
Optionally, the gate of the first transistor T1 is connected to the input signal terminal SIN.
Specifically, referring to fig. 6, the input signal terminal SIN is used to provide an input signal, and the gate of the first transistor T1 may be directly connected to the input signal terminal SIN, so that the gate of the first transistor T1 is connected to the input signal.
Fig. 7 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 7, the gate of the first transistor T1 is connected to the second pole of the fourth transistor T4.
Specifically, referring to fig. 7, the fourth transistor T4 serves as an input follower unit, and may output an input signal when the first clock signal is at a low level, and at this time, the gate of the first transistor T1 is connected to the second pole of the fourth transistor T4, and may acquire the input signal when the fourth transistor T4 outputs the input signal.
Fig. 8 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 8, the output module 130 includes a first output unit 131 and a second output unit 132; the control end of the first output unit 131 is used as a first control end CTRL1, the input end of the first output unit 131 is connected with the first power input end VH, and the output end of the first output unit 131 is connected with the output end of the second output unit 132 to be used as an output end SOUT of the scanning circuit; the control terminal of the second output unit 132 serves as a second control terminal CTRL2, and the input terminal of the second output unit 132 is connected to the second clock signal input terminal CLK 2.
Specifically, the potential of the first control terminal CTRL1 controls the state of the first output unit 131, and the potential of the second control terminal CTRL2 controls the state of the second output unit 132. The first control signal and the second control signal are active low as an example. When the first control signal is at a low level, the first output unit 131 is in a pass state, and at this time, the first output unit 131 may output the first power provided by the first power input terminal VH to the output terminal SOUT as a scan signal of the scan circuit. When the second control signal is at a low level, the second output unit 132 is in a pass state, and at this time, the second output unit 132 may output the second clock signal provided by the second clock signal input terminal CLK2 to the output terminal SOUT as the scan signal of the scan circuit. In addition, the first output unit 131 and the second output unit 132 have a control terminal potential maintaining function, so that the potentials of the first control terminal CTRL1 and the second control terminal CTRL2 can be maintained when the first control terminal CTRL1 and the second control terminal CTRL2 are in a floating state.
Fig. 9 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 9, the first output unit 131 includes a seventh transistor T7 and a second capacitor C2; the gate of the seventh transistor T7 is connected to the first pole of the second capacitor C2 as the first control terminal CTRL1, the first pole of the seventh transistor T7 and the second pole of the second capacitor C2 are connected to the first power input terminal VH, and the second pole of the seventh transistor T7 is used as the output terminal SOUT of the scan circuit; the second output unit 132 includes an eighth transistor T8 and a third capacitor C3; the gate of the eighth transistor T8 is connected to the first pole of the third capacitor C3 as the second control terminal CTRL2, the first pole of the eighth transistor T8 is connected to the second clock signal input terminal CLK2, and the second pole of the eighth transistor T8 is connected to the second pole of the third capacitor C3 as the output terminal SOUT of the scan circuit.
Specifically, the seventh transistor T7 and the eighth transistor T8 are exemplarily shown as P-type transistors in fig. 9. When the first control signal is at a low level, the potential of the first control terminal CTRL1 is at a low level, the seventh transistor T7 is turned on, and the first power is output to the output terminal SOUT through the seventh transistor T7 as a scan signal of the scan circuit. When the first control module 110 is set to be off, the potential of the first control terminal CTRL1 is in a floating state, and the potential of the first control terminal CTRL1 can be maintained by the second capacitor C2. When the second control signal is at a low level, the potential of the second control terminal CTRL2 is at a low level, the eighth transistor T8 is turned on, and the second clock signal is output to the output terminal SOUT through the eighth transistor T8 as a scan signal of the scan circuit. When the second control module 120 is set to be off, the potential of the second control terminal CTRL2 is in a floating state, and the potential of the second control terminal CTRL2 can be maintained by the third capacitor C3. In addition, the third capacitor C3 has a coupling effect. When the second clock signal jumps from high level to low level, the scanning signal output by the output end SOUT of the scanning circuit jumps from high level to low level, the coupling action of the third capacitor C3 makes the gate potential of the eighth transistor T8 lower than the low level potential of the second clock signal, so that the on state of the eighth transistor T8 can be ensured, and meanwhile, the threshold voltage loss when the eighth transistor T8 transmits the second clock signal can be eliminated, the level of the second clock signal output by the output end SOUT is ensured to be lower, and the reliability of the scanning signal output by the scanning circuit is ensured.
Fig. 10 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 10, the first output unit 131 includes a seventh transistor T7 and a second capacitor C2; the gate of the seventh transistor T7 is connected to the first pole of the second capacitor C2 as the first control terminal CTRL1, the first pole of the seventh transistor T7 and the second pole of the second capacitor C2 are connected to the first power input terminal VH, and the second pole of the seventh transistor T7 is used as the output terminal SOUT of the scan circuit; the second output unit includes an eighth transistor T8, a ninth transistor T9, and a third capacitor C3; the gate of the eighth transistor T8 and the gate of the ninth transistor T9 are connected to the first pole of the third capacitor C3 as the second control terminal CTRL2, the first pole of the eighth transistor T8 and the first pole of the ninth transistor T9 are both connected to the second clock signal input terminal CLK2, the second pole of the ninth transistor T9 is connected to the second pole of the third capacitor C3, and the second pole of the eighth transistor T8 is used as the output terminal SOUT of the scan circuit.
Specifically, fig. 10 is different from fig. 9 in the structure and connection relationship of the second output unit 132. When the second control signal is at a low level, the eighth transistor T8 and the ninth transistor T9 are turned on simultaneously, the eighth transistor T8 outputs the second clock signal to the output terminal SOUT, and the ninth transistor T9 outputs the second clock signal to the second pole of the third capacitor C3. When the second clock signal jumps from high level to low level, the third capacitor C3 can directly couple the second clock signal to the gate of the eighth transistor T8, thereby improving the coupling speed and being beneficial to further improving the reliability of the scanning circuit for outputting the scanning signal.
Fig. 11 is a schematic diagram of another scan circuit according to an embodiment of the present invention. As shown in fig. 11, the scanning circuit further includes a tenth transistor T10; the gate of the tenth transistor T10 is connected to the second power input terminal VL, and the second control module 120 is connected to the second control terminal CTRL2 through the tenth transistor T10.
Specifically, fig. 11 exemplarily shows that the tenth transistor T10 is a P-type transistor, and the second power supplied from the second power input terminal VL is at a low level. When the second control signal is at a high level, the tenth transistor T10 is in an on state. When the second control signal is at a low level, the tenth transistor T10 is in a near-off state. When the second clock signal jumps from high level to low level, the potential of the second control terminal CTRL2 is less than the low level potential due to the coupling effect, so that the low potential is prevented from being transmitted to the second control module 120, and damage to devices in the second control module 120 is prevented. For example, when the second control module 120 includes the fourth transistor T4 and the sixth transistor T6, the device damage caused by too low second-pole potential of the fourth transistor T4 and the sixth transistor T6 and too large difference between the gate potential and the second-pole potential of the fourth transistor T4 and the sixth transistor T6 can be avoided.
Fig. 12 is a signal timing diagram corresponding to the scan circuit provided in fig. 11. Referring to fig. 11 and 12, the first power supply is at a high level, and the second power supply is at a low level. Wherein SIN is the timing of the input signal provided by the input signal terminal SIN, CLK1 is the timing of the first clock signal provided by the first clock signal input terminal CLK1, CLK2 is the timing of the second clock signal provided by the second clock signal input terminal CLK2, and SOUT is the timing of the scan signal output by the output terminal SOUT of the scan circuit. The operation principle of the scanning circuit is explained below with reference to fig. 11 and 12.
In the first phase t1, the input signal is low, the first clock signal is low, and the second clock signal is high. The first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, and the sixth transistor T6 is turned off. The first power is transmitted to the first control terminal CTRL1 through the first transistor T1, and controls the fifth transistor T5 and the seventh transistor T7 to be turned off. While the first power is transferred to the gate of the third transistor T3 through the second transistor T2, controlling the third transistor T3 to be turned off. The input signal is output to the second control terminal CTRL2 through the fourth transistor T4, controlling the eighth transistor T8 and the ninth transistor T9 to be turned on, and the eighth transistor T8 outputs the second clock signal to the output terminal SOUT, and the scan signal is at a high level. In addition, the ninth transistor T9 directly outputs the second clock signal to the third capacitor C3, which can increase the coupling speed, and is beneficial to further improving the reliability of the scan circuit outputting the scan signal.
In the second phase t2, the input signal is high, the first clock signal is high, and the second clock signal is low. The first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off, and the sixth transistor T6 is turned on. When the first clock signal jumps from low level to high level, the gate of the third transistor T3 is at high level under the coupling action of the first capacitor C1, the third transistor T3 is turned off, at this time, the first control terminal CTRL1 is in a floating state, and the potential of the first control terminal CTRL1 is maintained at the potential of the first stage T1 and is at high level by the maintaining action of the second capacitor C2, so that the fifth transistor T5 and the seventh transistor T7 are continuously turned off. The second control terminal CTRL2 is in a floating state. When the second clock signal jumps from high level to low level, the coupling effect of the third capacitor C3 maintains the potential of the second control terminal CTRL2 smaller than low level, and the eighth transistor T8 and the ninth transistor T9 are continuously turned on, so that the threshold voltage loss of the eighth transistor T8 when transmitting the second clock signal can be eliminated, the level of the second clock signal output by the output terminal SOUT is ensured to be relatively low, and the reliability of the scanning signal output by the scanning circuit is ensured. Since the potential of the first control terminal CTRL1 is at the high level in the first stage t1, the potential of the first control terminal CTRL1 is maintained at the high level in the second stage t 2. When the second clock signal jumps from high level to low level, the seventh transistor T7 can be ensured to be in a cut-off state all the time, so that the setting of the intermediate state of the clock signal can be avoided to ensure that the seventh transistor T7 outputs the first power supply by mistake when the second clock signal jumps from high level to low level, and the pulse width of the scanning signal output by the scanning circuit is increased. When the scanning circuit is used for the display panel, the display effect of the display panel is improved.
In the third phase t3, the input signal is high, the first clock signal is low, and the second clock signal is high. The first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off, the fourth transistor T4 is turned on, the fourth transistor T4 transmits an input signal to the second control terminal CTRL2, and the eighth transistor T8 and the ninth transistor T9 are controlled to be turned off. When the first clock signal transitions from high level to low level, the first capacitor C1 couples the first clock signal to the gate of the third transistor T3, so that the gate of the third transistor T3 is at low level, and the third transistor T3 is controlled to be turned on, and the third transistor T3 outputs the first clock signal to the first control terminal CTRL1, i.e. the first control signal is at low level. The seventh transistor T7 and the fifth transistor T5 are controlled to be turned on, and the first power is output to the output terminal SOUT through the seventh transistor T7, and the scan signal is at a high level.
In the fourth phase t4, the input signal is high, the first clock signal is high, and the second clock signal is low. The first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off, and the sixth transistor T6 is turned on. When the first clock signal jumps from low level to high level, the gate of the third transistor T3 is at high level under the coupling action of the first capacitor C1, the third transistor T3 is turned off, at this time, the first control terminal CTRL1 is in a floating state, the potential of the first control terminal CTRL1 is maintained at the potential of the third stage T3 by the maintaining action of the second capacitor C2 to be at low level, the seventh transistor T7 and the fifth transistor T5 are controlled to be turned on, and the first power supply is output to the output terminal SOUT through the seventh transistor T7, at this time, the scanning signal is at high level. Meanwhile, the first power is transmitted to the second control terminal CTRL2 through the fifth transistor T5 and the sixth transistor T6, i.e. the second control signal is at a high level, and controls the eighth transistor T8 and the ninth transistor T9 to be turned off.
The embodiment of the invention also provides a display panel. Fig. 13 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 13, the display panel includes a pixel driving circuit 10 and a scanning circuit 20 provided in any embodiment of the present invention; the scanning circuit 20 is connected to the pixel driving circuit 10, and the scanning circuit 20 is configured to provide a scanning signal to the pixel driving circuit 10.
Specifically, the display panel may be, for example, an organic light emitting diode display panel, a liquid crystal display panel, or an electronic paper display panel. The display panel may include a plurality of rows of pixel driving circuits 10, a plurality of scanning circuits 20, and input signal lines 30. The multi-row scanning circuits 20 are cascaded, and an input signal end of the first-stage scanning circuit 20 is connected to the input signal line 30, and shifts and outputs an input signal provided by the input signal line 30. The input signal end of the next stage scan circuit 20 is connected to the output end of the previous stage scan circuit 20, so that the progressive output of the input signal can be realized. Each scanning circuit 20 is connected to a row of pixel driving circuits 10 for providing scanning signals to a row of pixel driving circuits 10. When the cascade scan circuit 20 outputs the scan signal step by step, the scan signal can be output to the pixel driving circuit 10 row by row, and the pixel driving circuit 10 is controlled to operate normally.
The embodiment of the invention also provides a display device. Fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 14, the display device includes a display panel 1 provided in any embodiment of the present invention. The display device can be, for example, a mobile phone, a tablet computer, intelligent wearable equipment, an information inquiry machine of a public place hall and the like. The display device includes the display panel 1 provided in any embodiment of the present invention, and its technical principle is similar to that of the produced technical effect, and will not be described herein again.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. The scanning circuit is characterized by comprising a first control module, a second control module and an output module;
the first control module is connected with a first control end of the output module and is used for outputting a first control signal to the first control end according to an input signal, a first clock signal and a first power supply; the second control module is connected with a second control end of the output module, and is used for outputting a second control signal to the second control end according to the input signal, the first clock signal, the first control signal, the first power supply and the second clock signal; wherein the first control signal and the second control signal are opposite in level; the output module is used for outputting the first power supply according to the first control signal and outputting the second clock signal according to the second control signal.
2. The scan circuit of claim 1, wherein the first control module comprises an input inversion unit and a clock follower unit; the working phases of the input inverting unit and the clock following unit are different;
the control end of the input inversion unit is used for inputting the input signal, the input end of the input inversion unit is connected with the first power supply input end, the output end of the input inversion unit is connected with the first control end, and the input inversion unit is used for inverting the input signal when the input signal is valid;
The control end of the clock following unit is connected with the input signal end, the first input end of the clock following unit is connected with the first power input end, the second input end of the clock following unit is connected with the first clock signal input end, the output end of the clock following unit is connected with the first control end, and the clock following unit is used for outputting the first clock signal when the first clock signal is effective.
3. The scan circuit of claim 2, wherein the input inversion unit comprises a first transistor, and the clock following unit comprises a second transistor, a third transistor, and a first capacitor;
the grid electrode of the first transistor and the grid electrode of the second transistor are used for inputting the input signal, the first electrode of the first transistor and the first electrode of the second transistor are connected with the first power input end, the second electrode of the first transistor and the second electrode of the third transistor are connected with the first control end, the second electrode of the second transistor is connected with the grid electrode of the third transistor and the first electrode of the first capacitor, and the first electrode of the third transistor and the second electrode of the first capacitor are connected with the first clock signal input end.
4. A scanning circuit according to claim 3, wherein the second control module comprises an input follower unit and a node control unit;
the control end of the input following unit is connected with the first clock signal input end, the input end of the input following unit is connected with the input signal end, the output end of the input following unit is connected with the second control end, and the input following unit is used for outputting the input signal when the first clock signal is effective;
the third control end of the node control unit is connected with the first control end, the fourth control end of the node control unit is connected with the second clock signal input end, the input end of the node control unit is connected with the first power input end, the output end of the node control unit is connected with the second control end, and the node control unit is used for controlling the potential of the second control end according to the first control signal and the second clock signal.
5. The scanning circuit according to claim 4, wherein the input following unit includes a fourth transistor, and the node control unit includes a fifth transistor and a sixth transistor;
The grid electrode of the fourth transistor is connected with the first clock signal input end, the first electrode of the fourth transistor is connected with the input signal end, and the second electrode of the fourth transistor and the second electrode of the sixth transistor are connected with the second control end; the grid electrode of the fifth transistor is connected with the first control end, the first electrode of the fifth transistor is connected with the first power input end, the second electrode of the fifth transistor is connected with the first electrode of the sixth transistor, and the grid electrode of the sixth transistor is connected with the second clock signal input end.
6. The scan circuit of claim 5, wherein a gate of the first transistor is connected to the input signal terminal or a second pole of the fourth transistor.
7. The scan circuit of any one of claims 1 to 6, wherein the output module comprises a first output unit and a second output unit;
the control end of the first output unit is used as the first control end, the input end of the first output unit is connected with the first power input end, and the output end of the first output unit is connected with the output end of the second output unit and used as the output end of the scanning circuit; the control end of the second output unit is used as the second control end, and the input end of the second output unit is connected with the second clock signal input end.
8. The scan circuit of claim 7, wherein the first output unit comprises a seventh transistor and a second capacitor; the grid electrode of the seventh transistor is connected with the first electrode of the second capacitor and used as the first control end, the first electrode of the seventh transistor and the second electrode of the second capacitor are connected with the first power input end, and the second electrode of the seventh transistor is used as the output end of the scanning circuit;
the second output unit includes an eighth transistor and a third capacitor; the grid electrode of the eighth transistor is connected with the first electrode of the third capacitor and used as the second control end, the first electrode of the eighth transistor is connected with the second clock signal input end, and the second electrode of the eighth transistor is connected with the second electrode of the third capacitor and used as the output end of the scanning circuit; or alternatively, the first and second heat exchangers may be,
the second output unit includes an eighth transistor, a ninth transistor, and a third capacitor; the gate of the eighth transistor and the gate of the ninth transistor are connected to the first pole of the third capacitor, and serve as the second control end, the first pole of the eighth transistor and the first pole of the ninth transistor are both connected to the second clock signal input end, the second pole of the ninth transistor is connected to the second pole of the third capacitor, and the second pole of the eighth transistor serves as the output end of the scanning circuit.
9. The scan circuit of claim 1, further comprising a tenth transistor; the grid electrode of the tenth transistor is connected with a second power input end, and the second control module is connected with the second control end through the tenth transistor.
10. A display panel comprising a pixel driving circuit and the scanning circuit according to any one of claims 1 to 9; the scanning circuit is connected with the pixel driving circuit and is used for providing scanning signals for the pixel driving circuit.
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| CN202310191390.4A CN116030747A (en) | 2023-03-02 | 2023-03-02 | Scanning circuit and display panel |
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| CN110364121A (en) * | 2019-06-27 | 2019-10-22 | 昆山国显光电有限公司 | Scanning circuit, display panel and display device |
| CN110675836A (en) * | 2019-10-18 | 2020-01-10 | 合肥维信诺科技有限公司 | Scanning circuit, driving method thereof and display panel |
| CN111696469A (en) * | 2020-06-18 | 2020-09-22 | 昆山国显光电有限公司 | Shift register, scanning circuit and display panel |
| CN112802422A (en) * | 2021-01-29 | 2021-05-14 | 云谷（固安）科技有限公司 | Shift register, grid drive circuit and display panel |
| CN112802424A (en) * | 2021-02-26 | 2021-05-14 | 合肥维信诺科技有限公司 | Shift register, display panel and display device |
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| CN110364121A (en) * | 2019-06-27 | 2019-10-22 | 昆山国显光电有限公司 | Scanning circuit, display panel and display device |
| CN110675836A (en) * | 2019-10-18 | 2020-01-10 | 合肥维信诺科技有限公司 | Scanning circuit, driving method thereof and display panel |
| CN111696469A (en) * | 2020-06-18 | 2020-09-22 | 昆山国显光电有限公司 | Shift register, scanning circuit and display panel |
| CN112802422A (en) * | 2021-01-29 | 2021-05-14 | 云谷（固安）科技有限公司 | Shift register, grid drive circuit and display panel |
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