CN107978276B - Grade circuit, scanner driver and display device - Google Patents
Grade circuit, scanner driver and display device Download PDFInfo
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- CN107978276B CN107978276B CN201810054349.1A CN201810054349A CN107978276B CN 107978276 B CN107978276 B CN 107978276B CN 201810054349 A CN201810054349 A CN 201810054349A CN 107978276 B CN107978276 B CN 107978276B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of grade of circuit, scanner driver and display device, the grade circuit has small number of transistor and can export the scanning signal of required waveform using only the first clock signal and second clock signal, and circuit is simple, and stability is high；And power consumption can be reduced to avoid the output of the second clock signal and the first supply voltage simultaneously with high level.Scanner driver and display device of the invention, power consumption is lower, and performance is higher.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of grade of circuit, scanner driver and display device.
Background technique
In recent years, the display device of numerous types, such as liquid crystal display device, plasma display dress are had developed both at home and abroad
It sets, electrowetting display device, electrophoretic display apparatus, organic light-emitting display device etc..Wherein organic light-emitting display device utilizes electricity
Sub- hole issues the light of specific wavelength to compound in certain material, to show image, has quick response, low in energy consumption, gently
It is thin, the advantages that colour gamut is wide.Organic light-emitting display device includes: pixel region, data driver, scanner driver, emission control drive
Dynamic device etc., wherein data driver is used to for data-signal to be supplied to a plurality of data line along column direction arrangement, scanner driver
For scanning signal to be supplied to a plurality of scan line along line direction arrangement, emission control driver according at least one for sweeping
Signal is retouched to generate an emissioning controling signal and be supplied to launch-control line, pixel region includes being connected to scan line, data line, hair
Multiple pixels of control line are penetrated, data-signal, scanning signal and emissioning controling signal realize phase to the pixel region based on the received
The pixel light emission answered is to show image.Wherein, scanner driver includes multiple grades of circuits for being connected to multi-strip scanning line, Duo Geji
Scanning signal is supplied to the multi-strip scanning line for being connected to the multiple grade circuit by circuit, is supplied to the multiple grade to correspond to
Signal.
It is found by the applicant that power consumption caused by current scanner driver considerably increases the overall power of display device.
Summary of the invention
The purpose of the present invention is to provide a kind of grade of circuit, scanner driver and display devices, can reduce power consumption.
In order to solve the above technical problems, the present invention provides a kind of grade of circuit, comprising:
Output module with first node, second node and signal output end, for according to be applied to first node and
The voltage of the voltage of first power supply or second clock signal is supplied to signal output end by the voltage of second node；
Input module with the first clock end, second clock end, the first power end and the first signal input part, it is described
First clock end is for receiving the first clock signal, and the second clock end is for receiving second clock signal, first electricity
For source for accessing the first power supply, first signal input part, which is used to receive, scans the defeated of commencing signal or previous stage circuit
Signal out；The input module be used for first clock signal, second clock signal control under by first signal
The write-in of input terminal received signal；
With second source end and connect the voltage control module of the input module, first node and second node, institute
Second source end is stated for accessing second source, the voltage control module is used under the control of first clock signal will
The voltage of first power supply or the voltage of second source are provided to the first node, and will under the control of the voltage of second source
The voltage of the first signal input part received signal is provided to second node.
Optionally, the input module include be sequentially arranged in first signal input part and first power end it
Between the first transistor, second transistor, third transistor, the grid of the first transistor is connected to first clock
End, the grid of the second transistor are connected to the second clock end, and the grid of the third transistor is connected to described the
One node.
Optionally, the voltage control module includes pull-up control unit, drop-down control unit and partial pressure control unit；
The pull-up control unit is connected between first power end and the first node, for inputting in first signal
It holds and the voltage of the first power supply is supplied to first node under the control of received signal；The drop-down control unit is connected to described
Between first node and second source end, and the control terminal of the drop-down control unit is connected to first clock end, is used for
The voltage of second source is supplied to first node under the control of first clock signal；The partial pressure control unit series connection
Between the input module and the output module, and the partial pressure control unit and the concatenated node of the input module are also
It is connected to the control terminal of the pull-up control unit, the control terminal of the partial pressure control unit is connected to the second source end,
The partial pressure control unit is used for the voltage of the first signal input part received signal under the control of the second source
It is provided to the second node, is also used to share between the pull-up control unit and the second node and the input mould
The voltage on circuit between block and the second node, to protect the pull-up control unit and the input module
Optionally, the pull-up control unit includes the 4th transistor, and the drop-down control unit includes the 5th transistor,
The partial pressure control unit includes the 8th transistor, wherein the grid of the 4th transistor is the pull-up control unit
Control terminal, is connected to the first pole of the 8th transistor, and the first pole of the 4th transistor is connected to first power supply
End, the second pole of the 4th transistor is connected to the first node；The grid of 5th transistor is as the drop-down
The control terminal of control unit, is connected to first clock end, and the first pole of the 5th transistor is connected to the first segment
Second pole of point, the 5th transistor is connected to the second source end；The grid of 8th transistor is the partial pressure
The control terminal of control unit, is connected to the second source end, and the first pole of the 8th transistor is additionally coupled to the input
Second pole of module, the 8th transistor is connected to the second node.
Optionally, the output module includes the first output unit and the second output unit, and first output unit connects
The first node, the first power end and signal output end are connect, for electric by described first under the control of the first node
The voltage output in source is to the signal output end；Second output unit connects the second node, second clock end and letter
Number output end, for exporting the second clock signal to the signal output end under the control of the second node.
Optionally, first output unit includes the first charging capacitor and the 6th transistor, the 6th transistor
One end of grid and first charging capacitor is connected to the first node, the first pole of the 6th transistor and described
The other end of first charging capacitor is connected to first power end, and the second pole of the 6th transistor is connected to the letter
Number output end；Second output unit include the second charging capacitor and the 7th transistor, the grid of the 7th transistor and
One end of second charging capacitor is connected to the second node, and the first pole of the 7th transistor and described first are filled
The other end of capacitor is connected to the signal output end, and the second pole of the 7th transistor is connected to the second clock
End.
Optionally, the output module further includes speed expanded unit and/or filter unit, the speed expanded unit with
Second output unit is in parallel, for improving the transmission speed for being transmitted to the signal of the signal output end；The filtering is single
First one end is connected at first output unit and the node of the second output unit connection, and one end is connected to the signal output
End is transmitted to the signal after being filtered for the signal to first output unit or the output of the second output unit signal
Output end.
Optionally, the speed expanded unit includes the extended transistor of at least one and the 7th coupled in parallel,
The grid of each extended transistor is connected to the second clock end, and the first pole of each extended transistor is connected to described
Second pole of signal output end, each extended transistor is connected to the second node；The filter unit includes filtered electrical
Hold and protective resistance, one end of the protective resistance and one end of the filter capacitor are connected to the signal output end, institute
The other end for stating protective resistance is connected at first output unit and the node of the second output unit connection, the filtered electrical
The other end of appearance is grounded.
Optionally, the input module further includes first control signal end, second control signal end, second signal input terminal
With bi-directional drive unit, the bi-directional drive unit includes the 9th transistor and the tenth transistor, the 9th transistor connection
Between the first signal input part and the second pole of the first transistor, the grid of the 9th transistor is connected to first control
Signal end processed, the 9th transistor are connected when the first control signal end provides first control signal, and the described tenth is brilliant
Body pipe is connected between second signal input terminal and the second pole of the first transistor, and the grid of the tenth transistor is connected to institute
Second control signal end is stated, the tenth transistor is connected when the second control signal end provides second control signal, institute
It states the first signal input part to receive the output signal of previous stage circuit or start scanning signal, second signal input terminal receives latter
The output signal of grade circuit starts scanning signal.
The present invention also provides a kind of scanner driver, including cascade multiple one of above-mentioned grade circuits, each grade of circuit
Signal output end be connected in corresponding scan line, and the grade circuit of the first order the first signal input part reception start to scan
Signal, the first signal input part of remaining grade of circuit receive the output signal of the signal output end of previous stage circuit.
The present invention also provides a kind of display devices, including above-mentioned scanner driver.
Compared with prior art, technical solution of the present invention has the advantages that
1, it can be realized the normal output of the output signal of required waveform；
2, the voltage of second clock signal and the first power supply is alternatively provided to signal output end, therefore when second
When the voltage of clock signal and the first power supply is high level, one of them can be only exported, power consumption is advantageously reduced；
3, only have drop-down control unit in voltage control module and be connected to the first clock end, advantageously reduce the first clock end
The load of itself.
Detailed description of the invention
Figure 1A is the structural schematic diagram of the grade circuit of one embodiment of the invention；
Figure 1B is the timing diagram of grade circuit shown in FIG. 1；
Fig. 2 is the structural schematic diagram of the scanner driver of one embodiment of the invention；
Fig. 3 is the structural schematic diagram of the display device of one embodiment of the invention；
Fig. 4 is the structural schematic diagram of the grade circuit of another embodiment of the present invention；
Fig. 5 is the structural schematic diagram of the scanner driver of another embodiment of the present invention.
Specific embodiment
Grade circuit proposed by the present invention, scanner driver and display device are made further specifically below in conjunction with attached drawing
It is bright.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to conveniently, lucidly
The purpose of the embodiment of the present invention is aided in illustrating, a part of corresponding construction is only indicated in each attached drawing, and actual product can
Need to make corresponding variation according to actual displayed.In addition, it will be further understood that being connected to another element when showing an element
When upper, which can be directly connected to another described element, or can connect indirectly via one or more add ons
It is connected to another described element.In the accompanying drawings, for brevity and clarity, it is convenient to omit some add ons.Entirely saying
In bright book, identical label indicates identical element.
Figure 1A is please referred to, the present invention provides a kind of grade of circuit, including input module 11, voltage control module 12 and output mould
Block 13.
Input module 11 has the first clock end SCK1, second clock end SCK2, the first power end VGH and the first signal
Input terminal SIN, the first clock end SCK1 are for receiving the first clock signal, and the second clock end SCK2 is for receiving the
Two clock signals, for accessing the first power supply (high level), the first signal input part SIN is used the first power end VGH
In the output signal for receiving scanning commencing signal or previous stage circuit.The input module 11 is used to believe in first clock
Number, the first signal input part SIN received signal is exported under the control of second clock signal.It, will in order to facilitate understanding
Port with and its transmission signal title it is unified, i.e. the first clock signal of the first clock end SCK1 transmission is denoted as SCK1, the
The second clock signal of two clock end SCK2 transmission is denoted as SCK2, and the signal of the first signal input part SIN transmission is denoted as SIN, institute
The voltage signal (or being high level signal) for stating the first power supply of the first power end VGH transmission is denoted as VGH.Institute in the present embodiment
Stating input module 11 includes first be sequentially arranged between the first signal input part SIN and the first power end VGH
Transistor M1, second transistor M2, third transistor M3, the grid of the first transistor M1 are connected to first clock end
The second pole (drain electrode) of the first pole (source electrode) connection second transistor M2 of SCK1, the first transistor M1, described first is brilliant
The second pole (drain electrode) of body pipe M1 connects the first signal input part SIN, under the control of the first clock signal SCK1
On or off the SIN signal of low level or high level is written, and then makes SIN signal be provided to the second of output module 13
Node N2, and the main function of the first transistor M1 is the low level for exporting SIN signal；The grid of the second transistor M2 connects
It is connected to the second clock end SCK2, the first pole of the first pole (source electrode) connection third transistor M3 of the second transistor M2
(source electrode) is controlled for the on or off under the control of second clock signal SCK2 with controlling third transistor M3 and voltage
The connection of the partial pressure control unit 123 (i.e. the first pole of the 8th transistor M8) of module 12, i.e. control third transistor M3 and the
The connection of two node N2；The grid of third transistor M3 is connected to the first node N1 of the output module 13, third transistor
The second pole (drain electrode) of M3 connects the first power end VGH, for controlling the first power supply according to the voltage of first node N1
Hold the connection of VGH and second transistor M2.Preferably, the first transistor M1 is double-gated transistor, to reduce transistor leakage.Institute
It states the first clock signal SCK1 and second clock signal SCK2 period having the same and there is nonoverlapping phase, it can be
It is provided in different leveled time sections as low level signal, i.e. the first clock signal SCK1, second clock signal SCK2
Waveform has the phase successively postponed.
The voltage control module 12 includes pull-up control unit 121, drop-down control unit 122 and partial pressure control unit
123.In the present embodiment, the pull-up control unit 121 includes being connected to the first power end VGH and the first node N1
Between the 4th transistor M4, the drop-down control unit include be connected to the first node N1 and second source end VGL it
Between the 5th transistor M5, the partial pressure control unit 123 include be connected on the input module 11 and the output module 13
Between the 8th transistor M8.Specifically, the grid of the 4th transistor M4 is the control of the pull-up control unit 121
End is connected to the first pole (source electrode) of described point of the 8th transistor M8, the first pole (source electrode) connection of the 4th transistor M4
To the first power end VGH, the second pole (drain electrode) of the 4th transistor M4 is connected to the first node N1, and described the
The voltage VGH of first power supply for being supplied to by four transistor M4 under the control for the SIN signal being written through the first transistor M1
First node N1；Control terminal of the grid of the 5th transistor M5 as the drop-down control unit 122 is connected to described
One clock end SCK1, the first pole (source electrode) of the 5th transistor M5 are connected to the first node N1, the 5th crystal
The second pole (drain electrode) of pipe M5 is connected to the second source end VGL, and the 5th transistor M5 is used in first clock
The voltage VGL of second source is supplied to first node N1 under the control of signal SCK1；The grid of the 8th transistor M8 is
The control terminal of the partial pressure control unit 123, is connected to the second source end VGL, the first pole of the 8th transistor M8
(source electrode) is connected to the connecting node of the first transistor M1 and second transistor M2 in the input module 11, i.e. first crystal
The position that the first pole of pipe M1 is connected with the second pole of second transistor M2, that is to say, that the first pole of the 8th transistor M8 can
To be connected to the first pole of the first transistor M1 and/or the second pole of second transistor M2, the second of the 8th transistor M8
Pole (drain electrode) is connected to the second node N2, and the 8th transistor M8 is used for the control in the voltage VGL of the second source
The voltage of the first signal input part SIN received signal SIN is provided to the second node N2 under system, is also used to point
High pressure (for for example negative 18.5V high pressure) is separated the 7th transistor in the second output unit 132 of output module 13 by pressure
In the area of grid of M7, the breakdown risk of the first transistor M1, the 4th transistor M4 is reduced, i.e. the 8th transistor M8 is also used to
Share between the grid (i.e. the control terminal of pull-up control unit 121) of the 4th transistor M4 and the second node N2 and
The voltage on circuit between the input module 11 and the second node N2, to protect 121 He of pull-up control unit
The input module 11.In the present embodiment, breadth length ratio (W/L) design of M2 to M5 is close, meets switching function, the width of M8
Length is more relatively large than (W/L) (i.e. bigger than M2 to M5), to meet the second charging capacitor quick charge in output module 13
It is required that.The first pole of M4 connects the first power end VGH, and is not connected to the first clock end SCK1, advantageously reduces the first clock end
The load of SCK1 itself, and then advantageously reduce the power consumption of circuit entirety.
Output module 13 has first node N1, second node N2 and signal output end OUT, is applied to first for basis
The voltage of the voltage VGH of first power supply or second clock signal SCK2 are supplied to letter by the voltage of node N1 and second node N2
Number output end OUT, the output module 13 include the first output unit 131, the second output unit 132, speed expanded unit 133
With filter unit 134, wherein first output unit 131 connects the first node N1 (being directly connected to), the first power end
VGH (being directly connected to) and signal output end OUT (being indirectly connected with), for will be described under the control of the voltage of the first node N1
The voltage VGH of first power supply is exported to the signal output end OUT；Second output unit 122 connects the second node
N2 (being directly connected to), second clock end SCK2 (being directly connected to) and signal output end OUT (being indirectly connected with), for described second
The second clock signal SCK2 is exported to the signal output end OUT under the control of node N2；The speed expanded unit
133 is in parallel with second output unit 132, for improving the transmission speed for being transmitted to the signal of the signal output end OUT；
Described 134 one end of filter unit is connected at first output unit 131 and the node of the second output unit 132 connection, and one
End is connected to the signal output end OUT, for exporting to first output unit 131 or 132 signal of the second output unit
Signal be filtered after be transmitted to the signal output end OUT.In the present embodiment, the speed expanded unit 133 includes protecting
Resistance R1 and filter capacitor C3 is protected, one end of the protective resistance R1 and one end of the filter capacitor C3 are connected to the letter
Number output end OUT, the other end of the protective resistance R1 are connected to first output unit 131 and the second output unit 132
At the node of connection, the other end of the filter capacitor C3 is grounded, and the protective resistance R1 is single for protecting first output
The output voltage of member 131 or the second output unit 132 avoids output voltage is excessive rear stage circuit is caused to burn in given threshold
It ruins, the filter capacitor can be filtered place to the output voltage of first output unit 131 or the second output unit 132
Reason, filtering interference signals guarantee the accuracy of output signal.First output unit 131 include the first charging capacitor C1 and
One end of 6th transistor M6, the grid of the 6th transistor M6 and the first charging capacitor C1 are connected to described first
The other end of node N1, the first pole (source electrode) of the 6th transistor M6 and the first charging capacitor C1 are connected to described
The second pole (drain electrode) of first power end VGH, the 6th transistor M6 is connected to the other end of the protective resistance R1, described
First output unit 131 be used for the first node N1 voltage control under by the voltage VGH of first power supply export to
The signal output end OUT；Second output unit 132 includes the second charging capacitor C2 and the 7th transistor M7, and described the
One end of the grid of seven transistor M7 and the second charging capacitor C2 are connected to the second node N2, the 7th crystal
The other end of the first pole (source electrode) of M7 pipe and the first charging capacitor C1 are connected to the signal output end OUT, described
The second pole (drain electrode) of 7th transistor M7 is connected to the second clock end SCK2, and second output unit 132 is used for
The voltage SCK2 of the second clock signal SCK2 is exported to the signal under the voltage control of the second node N2 and is exported
Hold OUT；The speed expanded unit 133 includes at least one extended transistor MDx in parallel with the 7th transistor M7, example
As shown in the MD1 to MD3 in Figure 1A, the grid of each extended transistor MDx is connected to the second clock end SCK2, each
The first pole (source electrode) of extended transistor MDx is connected to the first pole (source electrode) of the 7th transistor M7, and each extension is brilliant
The second pole of body pipe MDx is connected to the second node N2, and extended transistor MDx in parallel can extend breadth length ratio (W/L),
The charging rate of the second capacitor C2 is improved, and then improves signaling rate.
It should be noted that each transistor in above-described embodiment can be N-type switching transistor, it is also possible to p-type
Switching transistor, the conducting when its grid connects high level of N-type switching transistor, cut-off when connecing low level, the p-type switch crystal
Conducting when Guan Qi grid connects low level, cut-off when connecing high level, and each transistor can be thin film transistor (TFT) (TFT),
It can be metal oxide semiconductor field effect tube (MOS), be not limited thereto, the source electrode and drain electrode of these switching transistors can
With according to the difference of switching transistor type and input signal, function be can be interchanged, do not distinguish specifically herein.In addition, working as
When the breadth length ratio of 7th transistor M7 is sufficiently large, it is convenient to omit the setting of speed expanded unit 133, similarly, when the of input
The voltage of one clock signal SCK1, the voltage VGH of second clock signal SCK2, SIN signal and the first power supply and second source
When VGL is sufficiently stable, the setting of filter unit 134 also can be omitted.
The timing diagram of input and output shown in 1B with reference to the accompanying drawing carries out the course of work of grade circuit shown in figure 1A
Detailed description.Wherein, the voltage VGH of the first power supply of the first power end VGH access is high level, and second source end VGL connects
The voltage VGL of the second source entered is low level, and all transistors are p-type switching transistor.
Firstly, during the t1 period, output signal or beginning scanning signal SIN with low level previous stage circuit
It is supplied to the second pole (source electrode) of the first transistor M1, there is low level first clock signal SCK1 to be provided to first crystal
The grid of the grid of pipe M1 and the 5th transistor M5, the second clock signal SCK2 with high level are fed into second transistor
The second pole (drain electrode) of the grid of M2 and the 7th transistor M7, the voltage VGH of the first power supply with high level are provided to the
The second pole (drain electrode), the first pole (source electrode) of the 4th transistor M4 and the first pole of the 6th transistor M6 of three transistor M3
One end of (source electrode), the first charging capacitor C1, the voltage VGL with low level second source are provided to the 8th transistor M8
The second pole (drain electrode) of grid and the 5th transistor M5.Correspondingly, third transistor M2, third transistor M3 keep cut-off shape
The 8th transistor M8 is written by the first transistor M1 in state, the first transistor M1, the 5th transistor M5, low level SIN signal
The first pole (source electrode) and the 4th transistor M4 grid, the low level of SIN signal makes the 4th transistor M4, the 8th transistor
M8 conducting, the low level of SIN signal are written to the grid of the 7th transistor M7, the 7th transistor M7 conducting, second clock signal
SCK2 is exported by the 7th transistor M7 to signal output end OUT, i.e., signal output end OUT keeps output high during the t1 period
Level signal, and the high level signal is the second clock signal SCK2 with high level.At this point, the 7th crystal can be connected
The voltage of pipe M7 is stored (or charging) in the second charging capacitor C2.In addition, the 4th transistor M4's leads during the t1 period
Lead to so that the voltage VGH (high level) of the first power supply is supplied to first node N1, the 6th transistor M6 cut-off, therefore avoids
The output of the VGH signal of high level, advantageously reduces power consumption.
Next, during the t2 period, output signal or beginning scanning signal with low level previous stage circuit
SIN continues the second pole (source electrode) of supply the first transistor M1, and the first clock signal SCK1 with high level is provided to
There is the grid of the grid of the first transistor M1 and the 5th transistor M5 low level second clock signal SCK2 to be fed into the
The second pole (drain electrode) of the grid of two-transistor M2 and the 7th transistor M7, the voltage VGH quilt of the first power supply with high level
It is supplied to the second pole (drain electrode) of third transistor M3, the first pole (source electrode) of the 4th transistor M4 and the 6th transistor M6
First pole (source electrode), the first charging capacitor C1 one end, with low level second source voltage VGL be provided to the 8th crystalline substance
The second pole (drain electrode) of body pipe M8 grid and the 5th transistor M5.Because the voltage of the 7th transistor M7 can be connected previous
Stored during period t1 (or charging) in the second charging capacitor C2 (i.e. C2 can keep the t1 period during SIN signal it is low
Level), so the 7th transistor M7 is tended to remain on, there is low level second clock signal SCK2 to pass through the 7th transistor
M7 is exported to signal output end OUT, i.e., signal output end OUT keeps output low level signal, and the low electricity during the t2 period
Ordinary mail number is with low level second clock signal SCK2.In addition, the 8th transistor M8 is held on during the t2 period
State, low level second node N2 make the grid of the 4th transistor M4 be low level by the 8th transistor M8, therefore the
Four transistor M4 are tended to remain on, and the conducting of the 4th transistor M4 is so that the voltage VGH (high level) of the first power supply is supplied to
To first node N1, so that third transistor M3 and the 6th transistor M6 keeps off state, therefore high level is avoided
VGH signal output, advantageously reduce power consumption.In addition, the first clock signal SCK1 of high level make the first transistor M1,
Second transistor M2 is connected in 5th transistor M5 cut-off, low level second clock signal SCK2.
Next, during the t3 period, the output signal or beginning scanning signal of the previous stage circuit with high level
SIN is supplied to the second pole (source electrode) of the first transistor M1, and there is low level first clock signal SCK1 to be provided to first
The grid of the grid of transistor M1 and the 5th transistor M5, the second clock signal SCK2 with high level are fed into the second crystalline substance
The voltage VGH of the grid of body pipe M2 and the second pole (drain electrode) of the 7th transistor M7, the first power supply with high level is provided
To the first of the second pole (drain electrode) of third transistor M3, the first pole (source electrode) of the 4th transistor M4 and the 6th transistor M6
Pole (source electrode), the first charging capacitor C1 one end, be provided to the 8th transistor with the voltage VGL of low level second source
The second pole (drain electrode) of M8 grid and the 5th transistor M5.Correspondingly, second transistor M2 ends, the first transistor M1, the
The first pole (source electrode) of the 8th transistor M8 is written by the first transistor M1 for five transistor M5 conducting, the SIN signal of high level
And the 4th transistor M4 grid, the high level of SIN signal makes the 4th transistor M4 cut-off, the 8th transistor M8 conducting, high
The SIN signal of level is written by the 8th transistor M8 to the grid of the 7th transistor M7, and the 7th transistor M7 cut-off has height
The second clock signal SCK2 of level can not be exported to signal output end OUT.In addition, during the t3 period, the 5th transistor
The conducting of M5 so that be transmitted to first node N1 with the voltage VGL of low level second source so that third transistor M3 and
The grid of 6th transistor M6 has low level, so that third transistor M3 and the 6th transistor M6 conducting, has high electricity
The voltage VGH of flat second source is exported by the 6th transistor M6 to signal output end OUT, i.e., during the t3 period, signal
Output end OUT keeps output high level signal, and the high level signal is the voltage VGH of the second source with high level.
At this point, the voltage that the 6th transistor M6 can be connected is stored (or charging) in the first charging capacitor C1.
Next, during the t4 period, the output signal or beginning scanning signal of the previous stage circuit with high level
SIN continues the second pole (source electrode) of supply the first transistor M1, and the first clock signal SCK1 with high level is provided to
There is the grid of the grid of the first transistor M1 and the 5th transistor M5 low level second clock signal SCK2 to be fed into the
The second pole (drain electrode) of the grid of two-transistor M2 and the 7th transistor M7, the voltage VGH quilt of the first power supply with high level
It is supplied to the second pole (drain electrode) of third transistor M3, the first pole (source electrode) of the 4th transistor M4 and the 6th transistor M6
First pole (source electrode), the first charging capacitor C1 one end, with low level second source voltage VGL be provided to the 8th crystalline substance
The second pole (drain electrode) of body pipe M8 grid and the 5th transistor M5.Because the voltage of the 6th transistor M6 can be connected previous
Stored during period t3 (or charging) in the first charging capacitor C1 (i.e. C1 can keep the t3 period during VGL low electricity
It is flat), so third transistor M3 and the 6th transistor M6 are tended to remain on, the voltage VGH of the first power supply with high level
It is exported by the 6th transistor M6 to signal output end OUT, i.e., during the t4 period, signal output end OUT keeps the high electricity of output
Ordinary mail number, and the high level signal is the voltage VGH of the second source with high level.In addition, having during the t4 period
Second transistor M2 is connected in low level second clock signal SCK2, and the first clock signal SCK1 with high level makes
The first transistor M1 and the 5th transistor M5 cut-off, the 8th transistor M8 are tended to remain on, and the 4th transistor M4 keeps cut-off
State, so that the grid of the 7th transistor M7 keeps high level, the 7th transistor M7 keeps cut-off for the conducting of the 8th transistor M8
There is state low level second clock signal SCK2 can not export to signal output end OUT.
In the above-mentioned course of work, extended transistor MDx's (such as MD1, MD2, MD3) in speed expanded unit 133
On and off state is synchronous with the 7th transistor M7.T3 to the t4 period be the pixel light emission stage.When signal output end OUT is mentioned
The VGH signal of confession is transmitted to corresponding scan line as scanning signal, and with synchronize the data-signal for being filled with corresponding data line
Collective effect chooses the pixel of needs, so that the pixel chosen generates the light component with predetermined luminance component, to be used for
Show image.
According to the description of the above-mentioned course of work, it is seen that grade circuit of the invention can export the signal of required waveform.And
And in the t1 period, the voltage of the first power end input and the second clock signal of second clock end input are high level, but
Signal output end only outputs the second clock signal of high level, avoids the voltage output of the first power supply of high level, favorably
In reduction power consumption.
Based on the same inventive concept, the present embodiment also provides a kind of scanner driver, referring to FIG. 2, the turntable driving
Device include cascade multiple grades of circuit SG1, SG2 ..., SGn, the signal output end OUT of each grade of circuit is connected to be swept accordingly
It retouches on line, and according to the first clock signal SCK1, second clock signal SCK2, the voltage VGH of the first power supply and second source
Voltage VGL driving, such as the signal output end OUT of grade circuit SG1 of the first order are connected on first scan line S1, the second level
The signal output end OUT of grade circuit SG2 be connected on Article 2 scan line S2, the signal of the grade circuit SGn of afterbody is defeated
Outlet OUT is connected on the last item scan line Sn.Multiple grades of circuit SG1, SG2 ..., SGn circuit layout having the same,
Using grade circuit layout shown in figure 1A, each grade of circuit includes with flowering structure:
Output module 13 with first node N1, second node N2 and signal output end OUT, for according to being applied to the
The voltage of the voltage VGH of first power supply or second clock signal SCK2 are supplied to by the voltage of one node N1 and second node N2
Signal output end OUT；
With the first clock end SCK1, second clock end SCK2, the first power end VGH and the first signal input part SIN
Input module 11, the first clock end SCK1 uses for receiving the first clock signal SCK1, the second clock end SCK2
In receiving second clock signal SCK2, the first power end VGH is for accessing the first power supply VGH, the first signal input
End SIN is used to receive the output signal of scanning commencing signal or previous stage circuit；The input module 11 is used for described the
One clock signal SCK1, second clock signal SCK2 control under by the first signal input part SIN received signal be written；
With second source end VGL and connect the voltage control of the input module 11, first node N1 and second node N2
Molding block 12, for accessing second source VGL, the voltage control module 12 is used for described the second source end VGL
The voltage VGL of the voltage VGH of the first power supply or second source are provided to described first under the control of one clock signal SCK1
Node, and be provided to the voltage of the first signal input part SIN received signal under the voltage VGL of second source control
Second node N2.
In addition, multiple grades of circuit SG1, SG2 ..., the first signal input part SIN of the grade circuit SG1 of the first order in SGn
It receives and starts scanning signal, the first signal input part SIN of remaining grade of circuit receives the signal output end of previous stage circuit
Output signal, such as the first signal input part SIN of grade circuit SGi of i-stage (i be more than or equal to 2) receive (i-1)-th grade of grade electricity
The signal of the signal output end OUT output of road SGi-1.In addition, the first clock signal SCK1 and second clock signal SCK2 have
The identical period and have nonoverlapping phase.For example, when scanning signal is provided to the period quilt an of scan line
When referred to as 1 leveled time section 1H, clock signal SCK1 and SCK2 have the period of 2H and in different leveled time section quilts
It provides.In particular, although the time that the first clock signal SCK1 and second clock signal SCK2 are not provided can be overlapped (example
Such as, the first clock signal SCK1 and second clock signal SCK2 can have high level simultaneously), but the first clock signal SCK1 and
The time that second clock signal SCK2 is provided is (for example, the first clock signal SCK1 and second clock signal SCK2 has low electricity
The flat time) it is not overlapped.The signal of the signal output end OUT output of each grade of circuit is available to sweeping for corresponding scan line
Retouch signal, for choosing one-row pixels, correspondingly, multiple grades of circuit SG1, SG2 ..., SGn can sequentially by multiple scannings believe
Number it is supplied to multi-strip scanning line.
Based on the same inventive concept, the present embodiment also provides a kind of display device, including above-mentioned scanner driver.It please join
Fig. 3 is examined, display device of the invention can be organic light-emitting display device, and the organic light-emitting display device specifically includes pixel
Area 20, data driver 21, scanner driver 22 and emission control driver 23 further include the electricity of the first power supply VGH and second
Source VGL.
Pixel region 20 may include multi-strip scanning line S, multiple data lines D, a plurality of launch-control line E and multiple pixel P,
Multi-strip scanning line S is, for example, scan line S1, S2 ..., the Sn arranged along line direction；Multiple data lines D is, for example, along column direction cloth
Data line D1, D2 ..., the Dm set；A plurality of launch-control line E is, for example, the launch-control line E1 arranged along line direction,
E2 ..., En；Multiple pixel p-shapeds are at defining in multiple data lines D1, D2 ..., Dm and multi-strip scanning line S1, S2 ..., Sn
In region, and be connected respectively to corresponding scan line, data line, on launch-control line, can based on the received data-signal, sweep
It retouches signal and emissioning controling signal realizes corresponding shine to show image.Each pixel P may include pixel circuit and organic
Light emitting diode, the pixel circuit can produce the pixel current for flowing through pixel, and can be according to passing through multiple data lines
D1, D2 ..., Dm-1, the data-signal and pass through multi-strip scanning line S1, S2 ..., Sn-1, the scanning letter of Sn transmission that Dm is transmitted
Number the pixel current is supplied to Organic Light Emitting Diode, i.e. pixel circuit electricity that data-signal is received in response to scanning signal
Pressure, and then corresponding pixel current is generated, when the pixel current is flowed to from the anode electrode of Organic Light Emitting Diode (OLED)
When its cathode electrode, luminescent layer can shine, and the brightness of light is corresponding with the pixel current amount, and Organic Light Emitting Diode produces at this time
The raw light with predetermined luminance corresponding with the voltage of data-signal is to show image.The launch time section of pixel is (when shining
Between section) controlled by emissioning controling signal.
Data driver 21 may be coupled to multiple data lines D1, D2 ..., Dm.Data driver 21 can produce data
Signal, and data-signal is supplied to multiple data lines D1, D2 ..., Dm, the voltage of data-signal is applied to accordingly
On pixel P.
Scanner driver 22 may be coupled to multi-strip scanning line S1, S2 ..., Sn.Scanner driver 22 can produce scanning
Signal, and scanning signal is supplied to multi-strip scanning line S1, S2 ..., Sn, scanning signal is sequentially applied to corresponding picture
Element.Specific a line can be selected by scanning signal, and the data-signal of data driver 21 can be supplied to and be located at
Pixel P at selected particular row, the voltage of data-signal is received with addressed pixel P in response to scanning signal, and generation has
The light of predetermined luminance corresponding with the voltage of data-signal is to show image.The scanner driver 22 of the present embodiment is shown in Fig. 2
Scanner driver, that is, include cascade multiple grades of circuits SG1, SG2 ..., SGn, each grade of circuit can be using shown in Figure 1A
Circuit structure, and the signal output end OUT of the grade circuit SG1 of the first order is separately connected first scan line S1 and the second level
Grade circuit SG2 the first signal input part SIN, the signal output end OUT of the grade circuit SG2 of the second level is separately connected Article 2
The first signal input part SIN ... of scan line S2 and the grade circuit SG3 of the third level, the signal of the grade circuit SGn of afterbody
Output end OUT is separately connected the last item scan line Sn.Further, since the scanner driver 22 uses the first clock signal
Multiple scanning signals are output to multi-strip scanning line by SCK1 and second clock signal SCK2, that is, grade circuit according to the present invention is not
Receive other initializing signal, thus the width of scanning signal can be set to it is larger.
Emission control driver 23 may be coupled to a plurality of launch-control line E1, E2 ..., En.Emission control driver 23
Emissioning controling signal is generated in response to initial control signal, and emissioning controling signal is supplied to a plurality of launch-control line E1,
Emissioning controling signal is applied to corresponding pixel by E2 ..., En, to control the launch time section of the pixel.
First power supply VGH and second source VGL is each pixel circuit, the data driver 21, turntable driving of pixel region 20
Device 22 and mission controller 23 provide the first supply voltage and second source voltage.As shown in figure 3, pixel region 20, data are driven
Dynamic device 21, scanner driver 22, emission control driver 23, the first power supply and second source can be formed on one piece of substrate.
Fig. 4 shows the circuit diagram of the grade circuit of another embodiment of the present invention.In Fig. 4, will by identical label come
It indicates element identical with the element of Figure 1A, and detailed description thereof will not be repeated.
Referring to FIG. 4, the input module 11 further includes first control signal in the grade circuit of another embodiment of the present invention
Hold CS1, second control signal end CS2, second signal input terminal SIN ' and bi-directional drive unit 110.The bi-directional drive unit
110 include the 9th transistor M9 and the tenth transistor M10；The 9th transistor M9 be connected to the first signal input part SIN and
Between the second pole (drain electrode) of the first transistor M1, the grid of the 9th transistor M9 is connected to the first control signal end
CS1, the 9th transistor M9 are connected when the first control signal end CS1 provides first control signal.Described tenth is brilliant
Body pipe M10 is connected between the second pole (drain electrode) of second signal input terminal SIN ' and the first transistor M1, the tenth crystal
The grid of pipe M10 is connected to the second control signal end CS2, and the tenth transistor M10 is at the second control signal end
CS2 is connected when providing second control signal, and the first signal input part SIN receives the output signal or beginning of previous stage circuit
Scanning signal, second signal input terminal SIN ' receive the output signal of rear stage circuit or start scanning signal.Bi-directional drive list
Member 110 can make scanning signal can be along first direction (from first scan line S1 to nth scan line Sn) or along second party
It is provided to (the scan line S1 from nth scan line Sn to first), specifically, when first control signal CS1 is provided, the
Nine transistor M9 conducting, the letter that the grade circuit is exported according to the signal output end OUT for starting scanning signal or previous stage circuit
Number (i.e. scanning signal) driving, so that including that the scanner drivers of cascade multiple grade circuits can be along first direction
(from the first scan line S1 to the multiple scanning signals of the n-th scan line Sn) Sequential output；When second control signal CS2 is provided,
Tenth transistor M10 conducting, the grade circuit are exported according to the signal output end OUT for starting scanning signal or rear stage circuit
Signal (i.e. scanning signal) driving, so that the scanner driver including cascade multiple grade circuits can be along second party
To (the scan line S1 from nth scan line Sn to first) the multiple scanning signals of Sequential output.
Other driving processing of the grade circuit of the present embodiment are identical as the driving processing of grade circuit shown in figure 1A, so will
Its detailed description is not repeated.
Based on the same inventive concept, the present embodiment also provides a kind of scanner driver, referring to FIG. 5, the turntable driving
Device include cascade multiple grades of circuit SG1, SG2 ..., SGn, the signal output end OUT of each grade of circuit is connected to be swept accordingly
Retouch on line, and according to the first clock signal SCK1, second clock signal SCK2, the voltage VGH of the first power supply, second source electricity
Press VGL, first control signal CS1 and second control signal CS2 driving, such as the first order grade circuit SG1 signal output end
OUT is connected on first scan line S1, and the signal output end OUT of the grade circuit SG2 of the second level is connected to Article 2 scan line
On S2, the signal output end OUT of the grade circuit SGn of afterbody is connected on the last item scan line Sn.Multiple grades of circuits
SG1, SG2 ..., SGn circuit layout having the same, the circuit layout is as shown in Figure 4.The scanner driver of the present embodiment with
The main distinction of scanner driver shown in Fig. 2 has been driving signal mostly first control signal CS1 and second control signal
CS2, the input module of each grade of circuit further include that first control signal end CS1, second control signal end CS2, second signal are defeated
Enter to hold SIN ' and bi-directional drive unit, when first control signal CS1 is provided, the grade electricity of rear stage in the scanner driver
The first signal input part SIN on road receives the signal (i.e. scanning signal) of the signal output end OUT output of the grade circuit of previous stage,
The scanner driver root can be along first direction (from the first scan line S1 to the multiple scanning letters of the n-th scan line Sn) Sequential output
Number；When second control signal CS2 is provided, the second signal input terminal of the grade circuit of previous stage in the scanner driver
SIN ' receives the signal (i.e. scanning signal) of the signal output end OUT output of the grade circuit of rear stage, the scanner driver energy
Enough (the scan line S1 from nth scan line Sn to first) multiple scanning signals of Sequential output in a second direction.The scanning is driven
Dynamic device remaining circuit part and driving processing are identical as scanner driver shown in Fig. 2, retouch in detail so will not be repeated again it
It states.
Based on the same inventive concept, the present embodiment also provides a kind of display device including scanner driver shown in fig. 5.
In conclusion grade circuit of the invention has small number of transistor and the first clock signal and the is used only
Two clock signals can export the scanning signal of required waveform, and circuit is simple, and stability is high；And it can be to avoid there is height simultaneously
The output of the second clock signal and the first supply voltage of level, reduces power consumption, be conducive to high performance scanner driver and
The manufacture of display device.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (9)
1. a kind of grade of circuit characterized by comprising
Output module with first node, second node and signal output end is applied to first node and second for basis
The voltage of the voltage of first power supply or second clock signal is supplied to signal output end by the voltage of node；
Input module with the first clock end, second clock end, the first power end and the first signal input part, described first
Clock end is for receiving the first clock signal, and the second clock end is for receiving second clock signal, first power end
For accessing the first power supply, first signal input part is used to receive the output letter of scanning commencing signal or previous stage circuit
Number；The input module is for inputting first signal under the control of first clock signal, second clock signal
Hold received signal write-in；
With second source end and connect the voltage control module of the input module, first node and second node, described
Two power ends are used under the control of first clock signal for accessing second source, the voltage control module by first
The voltage of power supply or the voltage of second source are provided to the first node, and will be described under the control of the voltage of second source
The voltage of first signal input part received signal is provided to second node；
Wherein, the voltage control module includes pull-up control unit, drop-down control unit and partial pressure control unit；On described
Control unit is drawn to be connected between first power end and the first node, for receiving in first signal input part
Signal control under the voltage of the first power supply is supplied to first node；The drop-down control unit is connected to the first segment
Between point and second source end, and the control terminal of the drop-down control unit is connected to first clock end, for described
The voltage of second source is supplied to first node under the control of first clock signal；The partial pressure control unit is connected on described
Between input module and the output module, and the partial pressure control unit is additionally coupled to the concatenated node of the input module
The control terminal of the control terminal of the pull-up control unit, the partial pressure control unit is connected to the second source end, and described point
The voltage of the first signal input part received signal for being provided to by pressure control unit under the control of the second source
The second node, is also used to share between the pull-up control unit and the second node and the input module and institute
The voltage on the circuit between second node is stated, to protect the pull-up control unit and the input module；
The pull-up control unit includes the 4th transistor, and the drop-down control unit includes the 5th transistor, the partial pressure control
Unit processed includes the 8th transistor, wherein the grid of the 4th transistor is the control terminal of the pull-up control unit, connection
To the first pole of the 8th transistor, the first pole of the 4th transistor is connected to first power end, and the described 4th
Second pole of transistor is connected to the first node；Control of the grid of 5th transistor as the drop-down control unit
End processed is connected to first clock end, and the first pole of the 5th transistor is connected to the first node, and the described 5th is brilliant
Second pole of body pipe is connected to the second source end；The grid of 8th transistor is the control of the partial pressure control unit
End is connected to the second source end, and the first pole of the 8th transistor is additionally coupled to the input module, and the described 8th is brilliant
Second pole of body pipe is connected to the second node, and the breadth length ratio of the 8th transistor is greater than the 4th transistor and the 5th crystalline substance
The breadth length ratio of body pipe.
2. as described in claim 1 grade of circuit, which is characterized in that the input module includes being sequentially arranged in first letter
The first transistor, second transistor, third transistor number between input terminal and first power end, the first transistor
Grid be connected to first clock end, the grid of the second transistor is connected to the second clock end, the third
The grid of transistor is connected to the first node.
3. as described in claim 1 grade of circuit, which is characterized in that the output module includes that the first output unit and second are defeated
Unit out, first output unit connect the first node, the first power end and signal output end, for described first
By the voltage output of first power supply to the signal output end under the control of node；Described in the second output unit connection
Second node, second clock end and signal output end, under the control of the second node by the second clock signal
It exports to the signal output end.
4. as claimed in claim 3 grade of circuit, which is characterized in that first output unit includes the first charging capacitor and the
Six transistors, the grid of the 6th transistor and one end of first charging capacitor are connected to the first node, institute
The other end of the first pole and first charging capacitor of stating the 6th transistor is connected to first power end, and the described 6th
Second pole of transistor is connected to the signal output end；Second output unit includes the second charging capacitor and the 7th crystal
Pipe, the grid of the 7th transistor and one end of second charging capacitor are connected to the second node, and the described 7th
The other end of first pole of transistor and first charging capacitor is connected to the signal output end, the 7th transistor
The second pole be connected to the second clock end.
5. as claimed in claim 4 grade of circuit, which is characterized in that the output module further include speed expanded unit and/or
Filter unit, the speed expanded unit is in parallel with second output unit, is transmitted to the signal output end for improving
Signal transmission speed；Described filter unit one end is connected to the section of first output unit and the connection of the second output unit
At point, one end is connected to the signal output end, for what is exported to first output unit or the second output unit signal
Signal is transmitted to the signal output end after being filtered.
6. as claimed in claim 5 grade of circuit, which is characterized in that the speed expanded unit includes at least one and described
The extended transistor of seven coupled in parallel, the grid of each extended transistor are connected to the second clock end, each extension
First pole of transistor is connected to the signal output end, and the second pole of each extended transistor is connected to second section
Point；The filter unit includes filter capacitor and protective resistance, one end of one end of the protective resistance and the filter capacitor
It is connected to the signal output end, the other end of the protective resistance is connected to first output unit and the second output is single
At the node of member connection, the other end of the filter capacitor is grounded.
7. such as grade circuit described in any one of claims 1 to 6, which is characterized in that the input module further includes the first control
Signal end, second control signal end, second signal input terminal and bi-directional drive unit processed, the bi-directional drive unit include the 9th
Transistor and the tenth transistor, the 9th transistor be connected to the first signal input part and the first transistor the second pole it
Between, the grid of the 9th transistor is connected to the first control signal end, and the 9th transistor is in first control
Signal end is connected when providing first control signal, and the tenth transistor is connected to second signal input terminal and the first transistor
Between second pole, the grid of the tenth transistor is connected to the second control signal end, and the tenth transistor is described
Second control signal end is connected when providing second control signal, and first signal input part receives the output letter of previous stage circuit
Number or start scanning signal, second signal input terminal receive rear stage circuit output signal or start scanning signal.
8. a kind of scanner driver, which is characterized in that including the electricity of grade described in cascade multiple any one of claims 1 to 7
Road, the signal output end of each grade of circuit are connected in corresponding scan line, and the first signal input of the grade circuit of the first order
End, which receives, starts scanning signal, and the first signal input part of remaining grade of circuit receives the defeated of the signal output end of previous stage circuit
Signal out.
9. a kind of display device, which is characterized in that including scanner driver according to any one of claims 8.
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| CN201810054349.1A CN107978276B (en) | 2018-01-19 | 2018-01-19 | Grade circuit, scanner driver and display device |
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| CN201810054349.1A CN107978276B (en) | 2018-01-19 | 2018-01-19 | Grade circuit, scanner driver and display device |
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| KR20200061448A (en) * | 2018-11-23 | 2020-06-03 | 삼성디스플레이 주식회사 | Scan driver |
| CN110364121A (en) * | 2019-06-27 | 2019-10-22 | 昆山国显光电有限公司 | Scanning circuit, display panel and display device |
| CN110675793A (en) * | 2019-09-05 | 2020-01-10 | 深圳市华星光电半导体显示技术有限公司 | Display driving circuit |
| CN110767175A (en) * | 2019-10-08 | 2020-02-07 | 武汉华星光电半导体显示技术有限公司 | Drive circuit and display panel |
| CN111243513B (en) * | 2020-03-13 | 2021-07-20 | Oppo广东移动通信有限公司 | Control circuit and control method |
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| CN107978276A (en) | 2018-05-01 |
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