TWI493557B - Shift register circuit - Google Patents

Description

Shift register circuit

The present invention relates to a shift register circuit, and more particularly to a shift register circuit for providing a complex scan signal and a complex illumination signal.

Flat Panel Display is widely used in computer screens, mobile phones, personal digital assistants (PDAs), flat-panel TVs and other electronic products because of its advantages of thinness, power saving and no radiation. Among various flat display devices, Active Matrix Organic Light Emitting Display (AMOLED) has self-luminous, high brightness, high luminous efficiency, high contrast, fast response speed, wide viewing angle, and usable temperature. Further advantages such as a large range are therefore highly competitive in the market for flat panel display devices. In general, an active matrix organic light emitting display device includes a plurality of pixel units, a shift register circuit, and a data driver. The data driver is used to generate a complex data signal to a complex pixel unit. The shift register circuit is configured to generate a complex scan signal to feed the complex pixel unit to control the writing operation of the complex data signal. In addition, the shift register circuit is further configured to generate a plurality of illuminating signals, thereby providing illuminance enabling control of the plurality of pixel units, and each illuminating signal is inverted to a corresponding threshold voltage for performing a circuit operating voltage threshold voltage make up. The prior art uses an inverter designed by a complementary Metal Oxide Semiconductor (CMOS) circuit to provide mutually inverted scan signals and illuminating signals, that is, the conventional shift register circuit includes P-type transistors and N-type transistors require a more complex semiconductor process.

According to an embodiment of the invention, a shift register circuit for providing a complex scan signal and a complex illumination signal is disclosed. The shift register circuit comprises a plurality of shift register, each shift register comprises a first pull-down unit, an input unit, a first control unit, a first pull-up unit, and a second pull-up unit. a second pull down unit and a second control unit. The first pull-down unit is configured to correspond to the scan signal corresponding to the first clock according to the driving control voltage. The input unit electrically connected to the first pull-down unit is configured to output a driving control voltage according to the input signal and the second clock reversed to the first clock. A first control unit electrically coupled to the input unit is operative to provide a first control signal based on the drive control voltage. The first pull-up unit electrically connected to the first control unit, the input unit and the first pull-down unit is configured to pull the driving control voltage and the corresponding scanning signal according to the first control signal. The second pull-up unit electrically connected to the first pull-down unit is configured to pull the corresponding illuminating signal according to the corresponding scan signal. The second pull-down unit electrically connected to the second pull-up unit is configured to pull the corresponding illuminating signal according to the second control signal. The second control unit electrically connected to the second pull-down unit is configured to provide the second control signal according to the corresponding scan signal and the second clock.

The following is a detailed description of the preferred embodiment of the present invention in accordance with the present invention, but the embodiments are not intended to limit the scope of the present invention.

1 is a schematic diagram of a shift register circuit of a first embodiment of the present invention. As shown in FIG. 1, the shift register circuit 100 includes a plurality of shift register registers. For convenience of explanation, the shift register circuit 100 displays only the (N-1)th shift register 111, The Nth stage shift register 112 and the (N+1)th stage shift register 113, wherein only the Nth stage shift register 112 displays the internal functional unit architecture, and the remaining stage shift register Similar to the Nth stage shift register 112, no further details are provided. In the operation of the shift register circuit 100, the Nth stage shift register 112 is used to scan the signal SSn-1, (N+) generated by the (N-1)th stage shift register 111. 1) The scan signal SSn+1 generated by the stage shift register 113, the first clock CK1, and the second clock CK2 inverted to the first clock CK1 to generate the scan signal SSn and the illuminating signal EMn, and the remaining stages The shift register can be analogized by analogy.

The Nth stage shift register 112 includes a first pull down unit 120, an input unit 125, a first pull up unit 130, a first control unit 135, a second pull up unit 140, a second pull down unit 145, and a second control. The unit 150, the voltage stabilizing unit 155, and the third pull-up unit 160. The input unit 125 electrically connected to the (N-1)th stage shift register 111 is configured to output the drive control voltage VQn according to the scan signal SSn-1 and the second clock CK2. The first pull-down unit 120 electrically connected to the input unit 125 and the scan line LSn is configured to pull down the scan signal SSn according to the driving control voltage VQn and the first clock CK1, wherein the scan line LSn is used to transmit the scan signal SSn. The first control unit 135 electrically coupled to the input unit 125 is operative to provide the first control signal SC1 in accordance with the drive control voltage VQn. The first pull-up unit 130 electrically connected to the first control unit 135, the input unit 125 and the first pull-down unit 120 is configured to pull and drive the control voltage VQn and the scan signal SSn according to the first control signal SC1.

The second pull-up unit 140 electrically connected to the first pull-down unit 120 and the transmission line LEn is configured to pull the illuminating signal EMn according to the scanning signal SSn, wherein the transmission line LEn is used for transmitting the illuminating signal EMn. The second control unit 150 electrically connected to the first pull-down unit 120 is configured to provide the second control signal SC2 according to the scan signal SSn and the second clock CK2. The second pull-down unit 145 electrically connected to the transmission line LEn and the second control unit 150 is configured to pull down the illumination signal EMn according to the second control signal SC2. The third pull-up unit 160 electrically connected to the scan line LSn and the (N+1)th stage shift register 113 is configured to pull the scan signal SSn according to the scan signal SSn+1. The voltage stabilizing unit 155 electrically connected to the input unit 125 and the first pull-down unit 120 is configured to drive the control voltage VQn according to the scan signal SSn.

In the embodiment of FIG. 1, the first pull-down unit 120 includes a first transistor 121, the first pull-up unit 130 includes a second transistor 131 and a third transistor 132, and the first control unit 135 includes a fourth battery. The crystal 136 and the fifth transistor 137, the second pull-up unit 140 includes a sixth transistor 141, the second pull-down unit 145 includes a seventh transistor 146, and the second control unit 150 includes an eighth transistor 151 and a ninth transistor 152, the third pull-up unit 160 includes a tenth transistor 161, the input unit 125 includes an eleventh transistor 126 and a twelfth transistor 127, and the voltage stabilizing unit 155 includes a thirteenth transistor 156. Please note that each of the transistors described above or below may be a Thin Film Transistor (TFT) or a Field Effect Transistor (FET).

The first transistor 121 has a first terminal for receiving the first clock CK1, a gate terminal for receiving the driving control voltage VQn, and a second terminal for outputting the scanning signal SSn. The eleventh transistor 126 has a first terminal for receiving the scan signal SSn-1, a gate terminal for receiving the second clock CK2, and a second terminal electrically connected to the twelfth transistor 127. The twelfth transistor 127 has a first end electrically connected to the second end of the eleventh transistor 126, a gate terminal for receiving the second clock CK2, and a gate electrically connected to the first transistor 121. Extreme second end. The tenth transistor 161 has a first end electrically connected to the second end of the first transistor 121, a gate terminal for receiving the scanning signal SSn+1, and a second terminal for receiving the high reference voltage VGH. The second transistor 131 has a first end electrically connected to the second end of the first transistor 121, a gate terminal for receiving the first control signal SC1, and a second terminal for receiving the high reference voltage VGH. The third transistor 132 has a first end electrically connected to the second end of the twelfth transistor 127, a gate terminal for receiving the first control signal SC1, and a second terminal for receiving the high reference voltage VGH. .

The fourth transistor 136 includes a first end, a second end, and a gate terminal, wherein the first end and the gate terminal are used to receive the low reference voltage VGL, and the second end is used to output the first control signal SC1. The fifth transistor 137 has a first end electrically connected to the second end of the fourth transistor 136, a gate terminal for receiving the driving control voltage VQn, and a second terminal for receiving the high reference voltage VGH. The sixth transistor 141 has a first end for receiving the high reference voltage VGH, a gate terminal for receiving the scanning signal SSn, and a second terminal for outputting the illuminating signal EMn. The seventh transistor 146 has a first end electrically connected to the second end of the sixth transistor 141, a gate terminal for receiving the second control signal SC2, and a second terminal for receiving the low reference voltage VGL. The eighth transistor 151 has a first terminal for outputting the second control signal SC2, a gate terminal for receiving the second clock CK2, and a second terminal for receiving the low reference voltage VGL. The ninth transistor 152 has a first end electrically connected to the first end of the eighth transistor 151, a gate terminal for receiving the scan signal SSn, and a second end for receiving the high reference voltage VGH.

The thirteenth transistor 156 includes a first end, a second end, and a gate terminal, wherein the first end and the gate terminal are used to receive the scan signal SSn, and the second end is electrically connected to the first end of the twelfth transistor 127. The thirteenth transistor 156 can transmit the scan signal SSn having a low voltage level to the first end of the twelfth transistor 127 for reducing the source-to-source voltage difference of the twelfth transistor 127 to suppress leakage current. Further, the voltage stabilization effect of the drive control voltage VQn is achieved. In another embodiment, the thirteenth transistor 156 and the twelfth transistor 127 can be omitted, and the second end of the eleventh transistor 126 is directly coupled to the gate of the first transistor 121, The gate terminal of the fifth transistor 137 and the first terminal of the third transistor 132 and the eleventh transistor 126 having a low leakage current characteristic are used to achieve the voltage stabilizing effect of the driving control voltage VQn.

Fig. 2 is a schematic diagram showing the waveforms of the operation-related signals of the shift register circuit shown in Fig. 1, wherein the horizontal axis is the time axis. In the second figure, the signals from top to bottom are the first clock CK1, the second clock CK2, the scan signal SSn-1, the driving control voltage VQn, the scanning signal SSn, the illuminating signal EMn, and the scanning signal SSn+. 1. Referring to FIG. 2 and FIG. 1 , in the period T1, the scan signal SSn-1 and the second clock CK2 are both switched from the high level to the low level, so that the eleventh transistor 126 and the twelfth battery can be turned on. The crystal 127 pulls the driving control voltage VQn to the first low voltage level VL1. At this time, the driving control voltage VQn having the first low voltage level VL1 can turn on the fifth transistor 137 to pull the first control signal SC1 to the high reference voltage VGH, thereby turning off the second transistor 131 and the third transistor 132.

During the period T2, the second clock CK2 is switched from the low level to the high level, thereby turning off the eleventh transistor 126 and the twelfth transistor 127, so that the driving control voltage VQn becomes the floating voltage, and The first clock CK1 is switched from the high level to the low level, so that the driving control voltage VQn can be pulled down from the first low voltage level VL1 to the second low voltage level by capacitive coupling of the elements of the first transistor 121. Bit VL2, and according to the first transistor 121, the scan signal SSn is pulled from the high level to the low level. At this time, the scan signal SSn having a low level can turn on the sixth transistor 141, thereby pulling up the illuminating signal EMn from the low level to the high level. The scan signal SSn having a low level can further turn on the ninth transistor 152 to pull the second control signal SC2 to the high reference voltage VGH, thereby turning off the seventh transistor 146. In addition, the low voltage level of the scan signal SSn during the period T2 can turn on the thirteenth transistor 156, thereby pulling down the voltage of the first end of the twelfth transistor 127 to a low voltage level, thereby reducing the twelfth The voltage difference between the source and the cathode of the transistor 127 is to reduce the leakage current, so that the voltage regulation effect of the driving control voltage VQn can be achieved.

During the period T3, the scan signal SSn+1 having a low level can turn on the tenth transistor 161, thereby pulling up the scan signal SSn to the high reference voltage VGH, thereby turning off the sixth transistor 141 and the ninth transistor 152. At this time, since the second clock CK2 is switched from the high level to the low level, the eighth transistor 151 can be turned on to pull the second control signal SC2 to the low reference voltage VGL, and the second control signal having the low reference voltage VGL The SC2 is used to turn on the seventh transistor 146 to pull the illuminating signal EMn to the low reference voltage VGL.

Please note that as shown in FIG. 1, all of the transistors of the Nth stage shift register 112 are P-type transistors, that is, the Nth stage shift register 112 is based on a P-type transistor only. The circuit is similar to the scanning signal SSn and the illuminating signal EMn. The remaining stages of the shift register can also be based on a circuit including only a P-type transistor to provide mutually inverted scanning signals and illuminating signals. Therefore, the semiconductor process can be significantly simplified to reduce the production cost. In addition, those skilled in the art can easily complete the equivalent shift register circuit including only the N-type transistor according to the architecture disclosed by the N-th shift register 112, so based on only N The equivalent shift register circuit of the type of transistor does not depart from the spirit and scope of the present invention.

Figure 3 is a schematic diagram of a shift register circuit in accordance with a second embodiment of the present invention. As shown in FIG. 3, the shift register circuit 200 includes a plurality of shift register registers. For convenience of explanation, the shift register circuit 200 displays only the (N-1)th shift register 211, The Nth stage shift register 212 and the (N+1)th stage shift register 213, wherein only the Nth stage shift register 212 displays the internal functional unit architecture, and the remaining stage shift register Similar to the Nth stage shift register 212, it will not be described again. In the operation of the shift register circuit 200, the Nth stage shift register 212 is used to start the pulse signal STn-1, according to the (N-1)th stage shift register 211. The scan signal SSn+1 generated by the (N+1)-stage shift register 213, the first clock CK1, and the second clock CK2 inverted to the first clock CK1 to generate the scan signal SSn and the illuminating signal EMn And the start pulse signal STn, the rest of the shift register can be analogized analogously.

The Nth stage shift register 212 is similar to the Nth stage shift register 112 shown in FIG. 1, the main difference being that the input unit 125 is replaced with the input unit 225, and the third pull unit 160 is replaced with The third pull-up unit 260 further includes a carry unit 270. The input unit 225 electrically connected to the (N-1)th stage shift register 211 is configured to output the drive control voltage VQn according to the start pulse signal STn-1 and the second clock CK2. The carry unit 270 electrically connected to the input unit 225 is configured to output the start pulse signal STn according to the drive control voltage VQn and the first clock CK1. The third pull-up unit 260 electrically connected to the first pull-down unit 120, the carry unit 270, and the (N+1)th stage shift register 213 is configured to pull the scan signal SSn and the scan according to the scan signal SSn+1. The initial pulse signal STn.

In the embodiment of FIG. 3, the input unit 225 includes an eleventh transistor 226 and a twelfth transistor 227, the carry unit includes a fourteenth transistor 271, and the third pull-up unit 260 includes a tenth transistor 261 and The fifteenth transistor 262. The eleventh transistor 226 has a first end for receiving the start pulse signal STn-1, a gate terminal for receiving the second clock CK2, and a first electrode electrically connected to the twelfth transistor 227. Two ends. The twelfth transistor 227 has a first end electrically connected to the second end of the eleventh transistor 226, a gate terminal for receiving the second clock CK2, and a gate electrically connected to the first transistor 121. Extreme second end. The fourteenth transistor 271 has a first end for receiving the first clock CK1, a gate terminal for receiving the driving control voltage VQn, and a second terminal for outputting the start pulse signal STn. The tenth transistor 261 has a first end electrically connected to the second end of the first transistor 121, a gate terminal for receiving the scanning signal SSn+1, and a second terminal for receiving the high reference voltage VGH. The fifteenth transistor 262 has a first end electrically connected to the second end of the fourteenth transistor 271, a gate terminal electrically connected to the gate terminal of the tenth transistor 261, and one for receiving the high reference voltage VGH. The second end. In another embodiment, the gate terminal of the tenth transistor 261 is electrically connected to the (N+1)th stage shift register 213 to receive the start pulse signal STn+1.

Since the waveforms of the start pulse signal STn-1, the start pulse signal STn, and the start pulse signal STn+1 are substantially the same as the waveforms of the scan signal SSn-1, the scan signal SSn, and the scan signal SSn+1, respectively. Therefore, the circuit working principle of the Nth stage shift register 212 can be analogized according to the circuit working principle of the Nth stage shift register 112. In addition, as shown in FIG. 3, all of the transistors of the Nth stage shift register 212 are P-type transistors, that is, the Nth stage shift register 212 is also based on only the P-type transistor. The circuit provides the mutually inverted scan signal SSn and the illuminating signal EMn, and additionally provides the starting pulse signal STn for driving the (N+1)th stage shift register 213, so the semiconductor can be significantly simplified. Process to reduce production costs.

Figure 4 is a schematic diagram of a shift register circuit of a third embodiment of the present invention. As shown in FIG. 4, the shift register circuit 300 includes a plurality of stages of shift registers. For convenience of explanation, the shift register circuit 300 displays only the (N-1)th stage shift register 311, The Nth stage shift register 312 and the (N+1)th stage shift register 313, wherein only the Nth stage shift register 312 displays the internal functional unit architecture, and the remaining stage shift register Similar to the Nth stage shift register 312, it will not be described again. In the operation of the shift register circuit 300, the Nth stage shift register 312 is used to start the pulse signal STn-1, according to the (N-1)th stage shift register 311. The scan signal SSn+1 generated by the (N+1)-stage shift register 313, the first clock CK1, and the second clock CK2 inverted to the first clock CK1 to generate the scan signal SSn and the illuminating signal EMn And the start pulse signal STn, the rest of the shift register can be analogized analogously.

The Nth stage shift register 312 is similar to the Nth stage shift register 212 shown in FIG. 3, the main difference being that the first pull up unit 130 is replaced with the first pull up unit 330, and the first The three pull-up unit 260 is replaced with a third pull-up unit 360. The first pull-up unit 330 electrically connected to the first control unit 135, the input unit 225, the first pull-down unit 120 and the carry unit 270 is configured to pull and drive the control voltage VQn and the scan signal SSn according to the first control signal SC1. Start the pulse signal STn. The third pull-up unit 360 electrically connected to the input unit 225, the first pull-down unit 120, the carry unit 270, and the (N+1)th stage shift register 313 is configured to pull the drive according to the scan signal SSn+1. The control voltage VQn, the scan signal SSn, and the start pulse signal STn.

In the embodiment of FIG. 4, the first pull-up unit 330 includes a second transistor 331, a third transistor 332, and a sixteenth transistor 333. The third pull-up unit 360 includes a tenth transistor 361 and a tenth. Five transistors 362 and seventeenth transistor 363. The second transistor 331 has a first end electrically connected to the second end of the first transistor 121, a gate terminal for receiving the first control signal SC1, and a second terminal for receiving the high reference voltage VGH. The third transistor 332 has a first end electrically connected to the second end of the twelfth transistor 227, a gate terminal for receiving the first control signal SC1, and a second end for receiving the high reference voltage VGH. . The sixteenth transistor 333 has a first end electrically connected to the second end of the fourteenth transistor 271, a gate terminal for receiving the first control signal SC1, and a second terminal for receiving the high reference voltage VGH. end.

The tenth transistor 361 has a first end electrically connected to the second end of the first transistor 121, a gate terminal for receiving the scanning signal SSn+1, and a second terminal for receiving the high reference voltage VGH. The fifteenth transistor 362 has a first end electrically connected to the second end of the fourteenth transistor 271, a gate terminal electrically connected to the gate terminal of the tenth transistor 361, and one for receiving the high reference voltage VGH. The second end. The seventeenth transistor 363 has a first end electrically connected to the second end of the twelfth transistor 227, a gate terminal electrically connected to the gate terminal of the tenth transistor 361, and one for receiving the high reference voltage VGH. The second end. In another embodiment, the gate terminal of the tenth transistor 361 is electrically connected to the (N+1)th stage shift register 313 to receive the start pulse signal STn+1.

Basically, the circuit operation principle of the Nth stage shift register 312 is similar to the circuit operation principle of the Nth stage shift register 212 described above. In addition, as shown in FIG. 4, all of the transistors of the Nth stage shift register 312 are P-type transistors, so the Nth stage shift register 312 is also based on a circuit including only a P-type transistor. The mutually inverting scan signal SSn and the illuminating signal EMn are provided, and the starting pulse signal STn for driving the (N+1)th stage shift register 313 is additionally provided, so that the semiconductor process can be significantly simplified to reduce Cost of production.

In summary, the shift register of the present invention can be based on a circuit including only a P-type transistor or an N-type transistor to provide mutually inverted scan signals and illuminating signals to pixel units, so that the pixel units can be In order to perform the illumination control operation and the transistor threshold voltage compensation operation, the semiconductor process can be significantly simplified to reduce the production cost.

While the present invention has been described above by way of example, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 300. . . Shift register circuit

111, 211, 311. . . (N-1) stage shift register

112, 212, 312. . . Nth stage shift register

113, 213, 313. . . (N+1)th shift register

120. . . First pull down unit

121. . . First transistor

125, 225. . . Input unit

126, 226. . . Eleventh transistor

127, 227. . . Twelfth transistor

130, 330. . . First pull-up unit

131,331. . . Second transistor

132, 332. . . Third transistor

135. . . First control unit

136. . . Fourth transistor

137. . . Fifth transistor

140. . . Second pull-up unit

141. . . Sixth transistor

145. . . Second pull down unit

146. . . Seventh transistor

150. . . Second control unit

151. . . Eighth transistor

152. . . Ninth transistor

155. . . Voltage regulator unit

156. . . Thirteenth transistor

160, 260, 360. . . Third pull-up unit

161, 261, 361. . . Tenth transistor

262, 362. . . Fifteenth transistor

270. . . Carry unit

271. . . Fourteenth transistor

333. . . Sixteenth transistor

363. . . Seventeenth transistor

CK1. . . First clock

CK2. . . Second clock

EMn-1, EMn, EMn+1. . . Luminous signal

LEn-1, LEn, LEn+1. . . Transmission line

LSn-1, LSn, LSn+1. . . Scanning line

SC1. . . First control signal

SC2. . . Second control signal

SSn-2, SSn-1, SSn, SSn+1, SSn+2. . . Scanning signal

STn-2, STn-1, STn, STn+1. . . Start pulse signal

T1, T2, T3. . . Time slot

VGH. . . High reference voltage

VGL. . . Low reference voltage

VL1. . . First low voltage level

VL2. . . Second low voltage level

VQn. . . Drive control voltage

1 is a schematic diagram of a shift register circuit of a first embodiment of the present invention.

Fig. 2 is a schematic diagram showing the waveforms of the operation-related signals of the shift register circuit shown in Fig. 1, wherein the horizontal axis is the time axis.

Figure 3 is a schematic diagram of a shift register circuit in accordance with a second embodiment of the present invention.

Figure 4 is a schematic diagram of a shift register circuit of a third embodiment of the present invention.

100. . . Shift register circuit

111. . . (N-1) stage shift register

112. . . Nth stage shift register

113. . . (N+1)th shift register

120. . . First pull down unit

121. . . First transistor

125. . . Input unit

126. . . Eleventh transistor

127. . . Twelfth transistor

130. . . First pull-up unit

131. . . Second transistor

132. . . Third transistor

135. . . First control unit

136. . . Fourth transistor

137. . . Fifth transistor

140. . . Second pull-up unit

141. . . Sixth transistor

145. . . Second pull down unit

146. . . Seventh transistor

150. . . Second control unit

151. . . Eighth transistor

152. . . Ninth transistor

155. . . Voltage regulator unit

156. . . Thirteenth transistor

160. . . Third pull-up unit

161. . . Tenth transistor

CK1. . . First clock

CK2. . . Second clock

EMn-1, EMn, EMn+1. . . Luminous signal

LEn-1, LEn, LEn+1. . . Transmission line

LSn-1, LSn, LSn+1. . . Scanning line

SC1. . . First control signal

SC2. . . Second control signal

SSn-2, SSn-1, SSn, SSn+1, SSn+2. . . Scanning signal

VGH. . . High reference voltage

VGL. . . Low reference voltage

VQn. . . Drive control voltage

Claims (20)

A shift register circuit for providing a plurality of scan signals and a plurality of light-emitting signals, wherein the shift register circuit comprises a plurality of shift register registers, and one of the stages of the shift registers is shifted by an Nth stage The register includes: a first pull-down unit for pulling an Nth scan signal of the scan signals according to a driving control voltage and a first clock; an input unit electrically connected to the first pulldown a unit for outputting the driving control voltage according to a first input signal and a second clock inverted to the first clock; a first control unit electrically connected to the input unit, The first control unit is configured to provide a first control signal according to the driving control voltage; a first pull-up unit electrically connected to the first control unit, the input unit, and the first pull-down unit, the first The pull-up unit is configured to pull the driving control voltage and the Nth scan signal according to the first control signal; a second pull-up unit is electrically connected to the first pull-down unit, and the second pull-up unit is used To pull the above based on the Nth scan signal One of the illuminating signals, the Nth illuminating signal; a second pull-down unit electrically connected to the second pull-up unit, wherein the second pull-down unit is configured to pull the Nth illuminating signal according to a second control signal; The second control unit is electrically connected to the second pull-down unit, and the second control unit is configured to provide the second control signal according to the Nth scan signal and the second clock. The shift register circuit of claim 1, wherein the first pull-down unit comprises: a first transistor having a first end for receiving the first clock and a receiving end for receiving the driving a gate terminal for controlling the voltage, and a second terminal for outputting the Nth scan signal. The shift register circuit of claim 1, wherein the first pull-up unit comprises: a second transistor having a first end electrically connected to the first pull-down unit, and a receiving a gate terminal of the first control signal, and a second terminal for receiving a high reference voltage; and a third transistor having a first end electrically connected to the input unit and a receiving the first control The gate terminal of the signal and a second terminal for receiving the high reference voltage. The shift register circuit of claim 1, wherein the first control unit comprises: a fourth transistor having a first end for receiving a low reference voltage and an electrical connection to the first end a gate terminal, and a second terminal for outputting the first control signal; and a fifth transistor having a first end electrically connected to the second end of the fourth transistor, and a receiving terminal for receiving the driving A gate terminal for controlling the voltage and a second terminal for receiving a high reference voltage. The shift register circuit of claim 1, wherein the second pull-up unit comprises: a sixth transistor having a first end for receiving a high reference voltage and a receiving the Nth The gate terminal of the scan signal and a second end for outputting the Nth illumination signal. The shift register circuit of claim 1, wherein the second pull-down unit comprises: a seventh transistor having a first end electrically connected to the second pull-up unit and one for receiving the first The gate terminal of the second control signal and a second terminal for receiving a low reference voltage. The shift register circuit of claim 1, wherein the second control unit comprises: an eighth transistor having a first end for outputting the second control signal and a second receiving unit for receiving the second a gate terminal of the clock, and a second terminal for receiving a low reference voltage; and a ninth transistor having a first end electrically connected to the first end of the eighth transistor, and a receiving a gate terminal of the Nth scan signal and a second terminal for receiving a high reference voltage. The shift register circuit of claim 1, wherein the Nth stage shift register further comprises: a third pull-up unit electrically connected to the first pull-down unit, the third pull-up unit The system is configured to pull the Nth scan signal according to a second input signal. The shift register circuit of claim 8, wherein the third pull-up unit comprises: a tenth transistor having a first end electrically connected to the first pull-down unit, and one for receiving the a gate terminal of the second input signal and a second terminal for receiving a high reference voltage. The shift register circuit of claim 8, wherein the first input signal is one of the (N-1) scan signals of the scan signals, and the second input signal is one of the scan signals. The (N+1)th scan signal. The shift register circuit of claim 1, wherein the input unit comprises: an eleventh transistor having a first end for receiving the first input signal and a second receiving end for receiving the second input signal a gate terminal of the pulse and an electrical connection to the second end of the first pull down unit. The shift register circuit of claim 1, wherein the Nth stage shift register further comprises: a voltage stabilizing unit electrically connected to the input unit and the first pull down unit, the voltage stabilizing unit The system is configured to regulate the driving control voltage according to the Nth scan signal. The shift register circuit of claim 12, wherein the input unit comprises: an eleventh transistor having a first end for receiving the first input signal and one for receiving the second a gate terminal of the clock, and a second end; and a twelfth transistor having a first end electrically connected to the second end of the eleventh transistor and a gate for receiving the second clock Extremely, and electrically connected to the second end of the first pull-down unit; and the voltage stabilizing unit comprises: a thirteenth transistor having a first end for receiving the Nth scan signal, and a Receiving a gate terminal of the Nth scan signal and a second end electrically connected to the first end of the twelfth transistor. The shift register circuit of claim 1, wherein the Nth stage shift register further comprises: a carry unit electrically connected to the input unit, the carry unit is configured to control a voltage according to the drive The first clock outputs an Nth start pulse signal; and a third pull-up unit is electrically connected to the input unit, the first pull-down unit and the carry unit, and the third pull-up unit is used And driving the driving control voltage, the Nth scanning signal and the Nth starting pulse wave signal according to a second input signal. The shift register circuit of claim 14, wherein the first input signal is a (N-1) start pulse signal, and the second input signal is a (N+1) start The first pulse signal or one (N+1) scan signal of one of the scan signals. The shift register circuit of claim 14, wherein the carry unit comprises: a fourteenth transistor having a first end for receiving the first clock and a receiving control voltage a gate terminal and a second terminal for outputting the Nth start pulse signal. The shift register circuit of claim 14, wherein the third pull-up unit comprises: a tenth transistor having a first end electrically connected to the first pull-down unit, and one for receiving the a gate terminal of the second input signal, and a second terminal for receiving a high reference voltage; and a fifteenth transistor having a first end electrically connected to the carry unit and one for receiving the second The gate terminal of the input signal and a second terminal for receiving the high reference voltage. The shift register circuit of claim 17, wherein the third pull-up unit further comprises: a seventeenth transistor having a first end electrically connected to the input unit, and a receiving end a gate terminal of the two input signals and a second terminal for receiving the high reference voltage. The shift register circuit of claim 14, wherein the first pull-up unit is further configured to pull the Nth start pulse signal according to the first control signal. The shift register circuit of claim 19, wherein the first pull-up unit comprises: a second transistor having a first end electrically connected to the first pull-down unit, and a receiving a gate terminal of the first control signal and a second terminal for receiving a high reference voltage; a third transistor having a first end electrically connected to the input unit and a receiving the first control signal a gate terminal, and a second terminal for receiving the high reference voltage; and a sixteenth transistor having a first end electrically connected to the carry unit and a gate for receiving the first control signal Extreme, and a second end for receiving the high reference voltage.