CN102760407B - Emission control circuit, light-emitting control method and shift register - Google Patents
Emission control circuit, light-emitting control method and shift register Download PDFInfo
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- CN102760407B CN102760407B CN201210244370.0A CN201210244370A CN102760407B CN 102760407 B CN102760407 B CN 102760407B CN 201210244370 A CN201210244370 A CN 201210244370A CN 102760407 B CN102760407 B CN 102760407B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a kind of emission control circuit, light-emitting control method and shift register.Described emission control circuit comprises input end, input sample unit, output unit, reset unit and LED control signal output terminal; Input sample unit is sampled to input signal under the control of the first clock signal; Output unit, after input sample unit is sampled to input signal, produces LED control signal under the control of second clock signal; Reset unit, after described output unit produces LED control signal, resets to LED control signal under the control of the 3rd clock signal.The present invention can guarantee in the process of display data writing pixel cell, OLED is in closed condition, and after display data writing pixel cell, OLED is opened luminous, thus guarantee that display image can not glimmer due to the non-steady state of image element circuit in the write of data.
Description
Technical field
The present invention relates to organic light emitting display field, particularly relate to a kind of emission control circuit, light-emitting control method and shift register.
Background technology
Organic light emitting display diode (OLED), owing to having the advantage such as high brightness, wide viewing angle, faster response speed, is applied in high-performance display more and more.Traditional passive matrix organic light emitting display diode (PMOLED), along with the increase of display size, needs the driving time of shorter single pixel, thus needs to increase transient current, increases power consumption; The application of big current simultaneously can cause pressure drop on ITO line excessive, and makes OLED operating voltage too high, and then reduces its efficiency.And active matrix organic light-emitting display diode (AMOLED) to be lined by line scan input OLED electric current by switching tube, can address these problems well.
For AMOLED(active matrix organic light-emitting diode) display, not only need to produce row gating signal, control the open/close state with this grid line unconnected pixels, the open/close state for organic light emitting display diode is also needed to control, it is a positive level signal that the state control signal of this organic light emitting display diode shows backboard for the AMOLED that P-type crystal pipe is formed, guarantee in the process of display data writing pixel cell, OLED is in closed condition, and after display data writing pixel cell, OLED is opened luminous, guarantee that showing image can not glimmer due to the non-steady state of image element circuit when the write of data with this.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of emission control circuit, light-emitting control method and shift register, can guarantee in the process of display data writing pixel cell, OLED is in closed condition, and after display data writing pixel cell, OLED is opened luminous, thus guarantees that display image can not glimmer due to the non-steady state of image element circuit in the write of data.
In order to achieve the above object, the invention provides a kind of emission control circuit, for generation of the LED control signal of control OLED luminescence in AMOLED, described LED control signal and gate drive signal anti-phase;
Described emission control circuit comprises input end, input sample unit, output unit, reset unit and LED control signal output terminal, wherein,
Described input sample unit, be connected with described input end, the first clock signal input terminal and described LED control signal output terminal respectively, for sampling to input signal under the control of the first clock signal, and the signal obtained of sampling is sent to described LED control signal output terminal;
Described output unit, be connected with described input sample unit, second clock signal input part and described LED control signal output terminal respectively, for after described input sample unit is sampled to input signal, under the control of second clock signal, produce LED control signal, and this LED control signal is sent to described LED control signal output terminal;
Described reset unit, be connected with described output unit, the 3rd clock signal input terminal and described LED control signal output terminal respectively, for after described output unit produces LED control signal, under the control of the 3rd clock signal, described LED control signal is resetted.
During enforcement, described input sample unit comprises the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT) and the first electric capacity;
Described the first film transistor, grid is connected with the first clock signal input terminal, and source electrode is connected with described reset unit, and drain electrode is connected with described input end;
Described second thin film transistor (TFT), grid is connected with the first clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with described output unit;
Described 3rd thin film transistor (TFT), grid is connected with the first clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with described output unit;
Described 4th thin film transistor (TFT), grid is connected with the first clock signal input terminal, and source electrode is connected with reset unit, and drain electrode is connected with the low level output end of driving power;
Described first electric capacity, between the source electrode being connected to described 4th thin film transistor (TFT) and described LED control signal output terminal.
During enforcement, described output unit comprises the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT) and the second electric capacity;
Described 5th thin film transistor (TFT), grid is connected with the source electrode of described the first film transistor, and source electrode is connected with the drain electrode of described second thin film transistor (TFT) and the grid of described 6th thin film transistor (TFT) respectively, and drain electrode is connected with second clock signal input part;
Described 6th thin film transistor (TFT), source electrode be connected with the drain electrode of described 3rd thin film transistor (TFT) and the grid of described eight thin film transistor (TFT)s respectively, drain electrode be connected with the low level output end of driving power;
Described 7th thin film transistor (TFT), grid is connected with second clock signal input part, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the grid of the 13 thin film transistor (TFT);
Described 8th thin film transistor (TFT), source electrode is connected with the high level output end of driving power;
Between the grid that described second electric capacity is connected to described 5th thin film transistor (TFT) and source electrode.
During enforcement, described reset unit comprises the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11 thin film transistor (TFT), the 12 thin film transistor (TFT) and the 13 thin film transistor (TFT);
Described 9th thin film transistor (TFT), grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of the first film transistor;
Described tenth thin film transistor (TFT), grid is connected with the 3rd clock signal terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of described 5th thin film transistor (TFT);
Described 11 thin film transistor (TFT), grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of described 6th thin film transistor (TFT);
Described 12 thin film transistor (TFT), grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the grid of described 13 thin film transistor (TFT), and drain electrode is connected with the low level output end of driving power;
Described 13 thin film transistor (TFT), grid is connected with the source electrode of described 4th thin film transistor (TFT), and source electrode is connected with the drain electrode of described 8th thin film transistor (TFT), and drain electrode is connected with the low level output end of driving power;
The source electrode of described 13 thin film transistor (TFT) is connected with described LED control signal output terminal.
During enforcement, emission control circuit of the present invention also comprises reversed-phase output;
The grid of described 6th thin film transistor (TFT) is connected with described reversed-phase output;
The signal exported from described reversed-phase output and described LED control signal anti-phase.
During enforcement, described output unit also comprises the 3rd electric capacity, and described reset unit also comprises the 4th electric capacity;
Described 3rd electric capacity, between the source electrode being connected to described 6th thin film transistor (TFT) and the low level output end of driving power;
Described 4th electric capacity, between the source electrode being connected to described 13 thin film transistor (TFT) and the low level output end of driving power.
During enforcement, the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11 thin film transistor (TFT), the 12 thin film transistor (TFT) and the 13 thin film transistor (TFT) are p-type TFT.
Present invention also offers a kind of light-emitting control method, for generation of the LED control signal of control OLED luminescence in AMOLED, described LED control signal and gate drive signal anti-phase;
Described light-emitting control method comprises the following steps:
Input sample step: input sample unit is sampled to input signal, and the signal obtained of sampling is sent to LED control signal output terminal;
Export step: output unit produces LED control signal, and this LED control signal is sent to described LED control signal output terminal;
Reset process: reset unit resets to described LED control signal.
Present invention also offers a kind of shift register, comprise multistage above-mentioned emission control circuit;
Except first order emission control circuit and second level emission control circuit, the input signal of n-th grade of emission control circuit is the signal anti-phase with the LED control signal of (n-2) level emission control circuit;
The input signal of first order emission control circuit and the input signal of second level emission control circuit are start signal;
N is greater than the integer that 2 are less than or equal to N, and N is the progression of the emission control circuit that described shift register comprises.
Compared with prior art, emission control circuit of the present invention, light-emitting control method and shift register, the LED control signal anti-phase with producing gate drive signal, to make in the process of display data writing pixel cell, OLED is in closed condition, and after display data writing pixel cell, OLED is opened luminous, thus guarantee that display image can not glimmer due to the non-steady state of image element circuit in the write of data.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the emission control circuit described in first embodiment of the invention;
Fig. 2 is the circuit diagram of the emission control circuit described in second embodiment of the invention;
Fig. 3 is the circuit diagram of the shift register described in one embodiment of the invention;
Fig. 4 is the working timing figure in the emission control circuit described in second embodiment of the invention;
Fig. 5 is the working timing figure of shift register as shown in Figure 3.
Embodiment
In order to make the object of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with embodiment and accompanying drawing, embodiments of the invention are further described in detail.At this, illustrative examples of the present invention and illustrating for explaining the present invention, but not as a limitation of the invention.
For active matrix liquid crystal display (AMLCD), gate driver circuit controls for generation of the row gating of pixel circuit array.But for AMOLED(active matrix organic light-emitting diode) display, OLED is current driving apparatus, therefore controls the current path flowing into OLED, namely can control the luminescence of OLED.So in order at AMOLED(active matrix organic light-emitting diode) luminescence of OLED is controlled accurately in display, the invention provides a kind of emission control circuit, light-emitting control method and shift register.
Emission control circuit of the present invention and traditional gate driver circuit cooperating, for completing the control respectively of OLED and image element circuit duty.
As shown in Figure 1, the emission control circuit described in first embodiment of the invention, for generation of the LED control signal of control OLED luminescence in AMOLED, described LED control signal and gate drive signal anti-phase;
Described emission control circuit comprises input end Input, input sample unit 11, output unit 12, reset unit 13 and LED control signal output terminal EM [n], wherein,
Described input sample unit 11, be connected with described input end Input, the first clock signal input terminal and described LED control signal output terminal EM [n] respectively, for sampling to input signal under the control of the first clock signal C K1, and the signal obtained of sampling is sent to described LED control signal output terminal EM [n];
Described output unit 12, be connected with described input sample unit 11, second clock signal input part and described LED control signal output terminal EM [n] respectively, for after described input sample unit 11 pairs of input signals are sampled, under the control of second clock signal CK2, produce LED control signal, and this LED control signal is sent to described LED control signal output terminal EM [n];
Described reset unit 13; be connected with described output unit 12, the 3rd clock signal input terminal and described LED control signal output terminal EM [n] respectively; for after described output unit 12 produces LED control signal, under the control of the 3rd clock signal C K3, described LED control signal is resetted;
The first clock signal C K1 is inputted, from second clock signal input part input second clock signal CK2, from the 3rd clock signal input terminal input the 3rd clock signal C K3 from the first clock signal input terminal.
Emission control circuit described in first embodiment of the invention can produce the LED control signal of control OLED luminescence in AMOLED, described LED control signal and gate drive signal anti-phase, can at AMOLED(active matrix organic light-emitting diode) luminescence of OLED is controlled accurately in display, to make in the process of display data writing pixel cell, OLED is in closed condition, and after display data writing pixel cell, OLED is opened luminous, thus guarantee that display image can not glimmer due to the non-steady state of image element circuit in the write of data.
Fig. 2 is the circuit diagram of the emission control circuit described in second embodiment of the invention.As shown in Figure 2, the emission control circuit described in second embodiment of the invention is based on the emission control circuit described in first embodiment of the invention.In the emission control circuit described in second embodiment of the invention, described input sample unit 11 comprises the first film transistor T1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 and the first electric capacity C1;
Described output unit comprises the 5th thin film transistor (TFT) T5, the 6th thin film transistor (TFT) T6, the 7th thin film transistor (TFT) T7, the 8th thin film transistor (TFT) T8, the second electric capacity C2 and the 3rd electric capacity C3;
Described reset unit comprises the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11 thin film transistor (TFT) T11, the 12 thin film transistor (TFT) T12, the 13 thin film transistor (TFT) T13 and the 4th electric capacity C4;
Described emission control circuit also comprises reversed-phase output EM_Out;
Described the first film transistor T1, grid is connected with the first clock signal input terminal, and source electrode is connected with the drain electrode of described 9th thin film transistor (TFT) T9, and drain electrode is connected with described input end INPUT;
Described second thin film transistor (TFT) T2, grid is connected with the first clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of described 5th thin film transistor (TFT) T5;
Described 3rd thin film transistor (TFT) T3, grid is connected with the first clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of described 6th thin film transistor (TFT) T6;
Described 4th thin film transistor (TFT) T4, grid is connected with the first clock signal input terminal, and source electrode is connected with the grid of described 13 thin film transistor (TFT) T13, and drain electrode is connected with the low level output end of driving power;
Described 5th thin film transistor (TFT) T5, grid is connected with the source electrode of described the first film transistor T1, and source electrode is connected with the grid of described 6th thin film transistor (TFT) T6, and drain electrode is connected with second clock signal input part;
Described 6th thin film transistor (TFT) T6, source electrode is connected with the grid of described eight thin film transistor (TFT) T8, and drain electrode is connected with the low level output end of driving power;
Described 7th thin film transistor (TFT) T7, grid is connected with second clock signal input part, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the grid of the 13 thin film transistor (TFT) T13;
Described 8th thin film transistor (TFT) T8, source electrode is connected with the high level output end of driving power;
Described 9th thin film transistor (TFT) T9, grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the high level output end of driving power;
Described tenth thin film transistor (TFT) T10, grid is connected with the 3rd clock signal terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of described 5th thin film transistor (TFT) T5;
Described 11 thin film transistor (TFT) T11, grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of described 6th thin film transistor (TFT) T6;
Described 12 thin film transistor (TFT) T12, grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the grid of described 13 thin film transistor (TFT) T13, and drain electrode is connected with the low level output end of driving power;
Described 13 thin film transistor (TFT) T13, source electrode is connected with the drain electrode of described 8th thin film transistor (TFT) T8, and drain electrode is connected with the low level output end of driving power;
Described first electric capacity C1, between the grid being connected to described 13 thin film transistor (TFT) T13 and source electrode;
Between the grid that described second electric capacity C2 is connected to described 5th thin film transistor (TFT) T5 and source electrode;
Described 3rd electric capacity C3, between the source electrode being connected to described 6th thin film transistor (TFT) T6 and the low level output end of driving power;
Described 4th electric capacity C4, between the source electrode being connected to described 13 thin film transistor (TFT) T13 and the low level output end of driving power;
The source electrode of described 13 thin film transistor (TFT) T13 is connected with described LED control signal output terminal EM [n];
The grid of described 6th thin film transistor (TFT) T6 is connected with described reversed-phase output EM_Out;
The first clock signal C K1 is inputted, from second clock signal input part input second clock signal CK2, from the 3rd clock signal input terminal input the 3rd clock signal C K3 from the first clock signal input terminal;
The output voltage of the high level output end of driving power is VGH, and the output voltage of the low level output end of driving power is VGL;
N1 point is the node be connected with the grid of described 5th thin film transistor (TFT) T5;
N2 point is the node be connected with the grid of described 6th thin film transistor (TFT) T6;
N3 point is the node be connected with the grid of described 8th thin film transistor (TFT) T8;
N4 point is the node be connected with the grid of described 13 thin film transistor (TFT) T13;
N2 point (i.e. reversed-phase output EM_Out) is connected with next stage emission control circuit;
The signal exported from described reversed-phase output EM_Out and described LED control signal anti-phase;
Wherein, C1 and C2 is bootstrap capacitor, and C3 is for maintaining the level of N3 point, and C4 is for maintaining the level of described LED control signal output terminal EM [n];
The first film transistor T1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4, the 5th thin film transistor (TFT) T5, the 6th thin film transistor (TFT) T6, the 7th thin film transistor (TFT) T7, the 8th thin film transistor (TFT) T8, the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11 thin film transistor (TFT) T11, the 12 thin film transistor (TFT) T12 and the 13 thin film transistor (TFT) T13 are p-type TFT.
As shown in Figure 3, the shift register described in one embodiment of the invention comprises the emission control circuit described in multistage second embodiment of the invention;
Except first order emission control circuit and second level emission control circuit, the input end Input of n-th grade of emission control circuit is connected with the reversed-phase output EM_Out of (n-2) level emission control circuit;
The input end Input of first order emission control circuit is connected with start signal input end with the input end Input of second level emission control circuit;
From described start signal input end input start signal STV;
N is greater than the integer that 2 are less than or equal to N, and N is the progression of the emission control circuit that described shift register comprises;
In figure 3, STAGE_1, STAGE_2, STAGE_3, STAGE_4, STAGE_5, STAGE_6, STAGE_7, STAGE_8 instruction is first order emission control circuit, second level emission control circuit, first order emission control circuit, second level emission control circuit, third level emission control circuit, fourth stage emission control circuit, level V emission control circuit, the 6th grade of emission control circuit, the 7th grade of emission control circuit, the 8th grade of emission control circuit respectively;
Further, the first clock signal be connected with odd level emission control circuit, second clock signal, the 3rd clock signal are respectively: CLK1-1, CLK1-2, CLK1-3;
The first clock signal be connected with even level emission control circuit, second clock signal, the 3rd clock signal are respectively: CLK2-1, CLK2-2, CLK2-3.
Fig. 4 is the working timing figure in the emission control circuit described in second embodiment of the invention, and this emission control circuit is the first order emission control circuit in shift register;
The pulsewidth of STV is the twice of the pulsewidth of the pulsewidth of CK1, the pulsewidth of CK2 and CK3;
First negative edge of CK1 and the negative edge alignment of STV;
First negative edge of CK2 and first rising edge alignment of CK1;
First negative edge of CK3 and the rising edge alignment of STV;
The dutycycle of the dutycycle of CK1, the dutycycle of CK2 and CK3 is 1/3.
As shown in Figure 4, the t1 stage is the input sample stage: the start signal STV now inputted from input end Input is low level, first clock signal C K1 is low level simultaneously, the first film transistor T1 conducting, second clock signal CK2 is high level simultaneously, 9th thin film transistor (TFT) T9 closes, then now the level of N1 point is dragged down as VGL+ ∣ Vthp|; Simultaneously because the first clock signal C K1 is low level, second thin film transistor (TFT) T2 conducting, N2 point is high level, guarantee that the 6th thin film transistor (TFT) T6 closes, do not affect the level of N3 point, now due to the 3rd thin film transistor (TFT) T3 conducting, N3 point is high level, guarantee that the 8th thin film transistor (TFT) T8 closes, do not affect input EM [n]; 4th thin film transistor (TFT) T4 due to CK1 be low level conducting, the level of N4 point is dragged down as VGL+ ∣ Vthp ∣, the 13 thin film transistor (TFT) T13 conducting, and LED control signal is now low level; Wherein, Vthp is the threshold voltage of p-type thin film transistor;
The t2 stage is output stage: CK1, CK3 is high level, the first film transistor T1, second thin film transistor (TFT) T2, 5th thin film transistor (TFT) T5 and the tenth thin film transistor (TFT) T10 all closes, due to the boot strap of the second electric capacity C2, N1 level point will be dragged down by corresponding, 5th thin film transistor (TFT) T5 conducting, second clock signal CK2 signal is low level, now N2 level point is low, then the 6th thin film transistor (TFT) T6 conducting, N3 level point is dragged down, accordingly, 8th thin film transistor (TFT) T8 conducting, LED control signal is high level signal, for the drive TFT of OLED provides start signal,
The t3 stage is reseting stage: the 3rd clock signal C K3 signal is low, accordingly, 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11 thin film transistor (TFT) T11 and the 12 thin film transistor (TFT) T12 conducting, N1 point, N2 point and N3 level point are drawn high, N4 level point drags down.Now the 13 thin film transistor (TFT) T13 conducting, the 8th thin film transistor (TFT) T8 closes, and LED control signal is dragged down again, completes the reset to LED control signal.
Fig. 5 is the working timing figure of shift register as shown in Figure 3, in Figure 5, EM_out_1, EM_out_2, EM_out_n instruction is reversed-phase output, the reversed-phase output of second level emission control circuit, the reversed-phase output of n-th grade of emission control circuit of first order emission control circuit respectively;
What EM_1, EM_2, EM_n indicated is LED control signal, the LED control signal of second level emission control circuit output, the LED control signal of n-th grade of emission control circuit output that first order emission control circuit exports respectively;
N is the integer of the progression being less than or equal to the emission control circuit that shift register comprises;
The pulsewidth of the pulsewidth of CLK1-1, the pulsewidth of CLK1-2, CLK1-3, the pulsewidth of CLK2-1, the pulsewidth of CLK2-2 are identical with the pulsewidth of CLK2-3;
The pulsewidth of described start signal STV is the twice of the pulsewidth of the pulsewidth of CLK1-1, the pulsewidth of CLK1-2, the pulsewidth of CLK1-3, the pulsewidth of CLK2-1, the pulsewidth of CLK2-2 and CLK2-3 respectively;
First negative edge of CLK1-1 and the negative edge alignment of STV;
First negative edge of CLK1-2 and first rising edge alignment of CLK1-1;
First negative edge of CLK1-3 and the rising edge alignment of STV;
First negative edge of CLK2-1 is positioned at 1/4 place of STV pulsewidth, is namely positioned at 1/2 place of CLK1-1 self pulsewidth;
First negative edge of CLK2-2 and first rising edge alignment of CLK2-1;
First negative edge of CLK2-3 and first rising edge alignment of CLK2-2;
The dutycycle of the dutycycle of the dutycycle of CLK1-1, the dutycycle of CLK1-2, CLK1-3, the dutycycle of CLK2-1, the dutycycle of CLK2-2 and CLK2-3 is 1/3.
Present invention also offers a kind of light-emitting control method, for generation of the LED control signal of control OLED luminescence in AMOLED, described LED control signal and gate drive signal anti-phase;
Described light-emitting control method comprises the following steps:
Input sample step: input sample unit is sampled to input signal, and the signal obtained of sampling is sent to LED control signal output terminal;
Export step: output unit produces LED control signal, and this LED control signal is sent to described LED control signal output terminal;
Reset process: reset unit resets to described LED control signal.
Emission control circuit of the present invention, light-emitting control method and shift register, the LED control signal anti-phase with producing gate drive signal, to make in the process of display data writing pixel cell, OLED is in closed condition, and after display data writing pixel cell, OLED is opened luminous, thus guarantees that display image can not glimmer due to the non-steady state of image element circuit in the write of data.
More than illustrate just illustrative for the purpose of the present invention; and nonrestrictive, those of ordinary skill in the art understand, when not departing from the spirit and scope that claims limit; many amendments, change or equivalence can be made, but all will fall within the scope of protection of the present invention.
Claims (5)
1. an emission control circuit, for generation of the LED control signal of control OLED luminescence in AMOLED, is characterized in that, described LED control signal and gate drive signal anti-phase;
Described emission control circuit comprises input end, input sample unit, output unit, reset unit and LED control signal output terminal, wherein,
Described input sample unit, be connected with described input end, the first clock signal input terminal and described LED control signal output terminal respectively, for sampling to input signal under the control of the first clock signal, and the signal obtained of sampling is sent to described LED control signal output terminal;
Described output unit, be connected with described input sample unit, second clock signal input part and described LED control signal output terminal respectively, for after described input sample unit is sampled to input signal, under the control of second clock signal, produce LED control signal, and this LED control signal is sent to described LED control signal output terminal;
Described reset unit, be connected with described output unit, the 3rd clock signal input terminal and described LED control signal output terminal respectively, for after described output unit produces LED control signal, under the control of the 3rd clock signal, described LED control signal is resetted;
Described input sample unit comprises the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT) and the first electric capacity;
Described the first film transistor, grid is connected with the first clock signal input terminal, and source electrode is connected with described reset unit, and drain electrode is connected with described input end;
Described second thin film transistor (TFT), grid is connected with the first clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with described output unit;
Described 3rd thin film transistor (TFT), grid is connected with the first clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with described output unit;
Described 4th thin film transistor (TFT), grid is connected with the first clock signal input terminal, and source electrode is connected with reset unit, and drain electrode is connected with the low level output end of driving power;
Described first electric capacity, between the source electrode being connected to described 4th thin film transistor (TFT) and described LED control signal output terminal;
Described output unit comprises the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT) and the second electric capacity;
Described 5th thin film transistor (TFT), grid is connected with the source electrode of described the first film transistor, and source electrode is connected with the drain electrode of described second thin film transistor (TFT) and the grid of described 6th thin film transistor (TFT) respectively, and drain electrode is connected with second clock signal input part;
Described 6th thin film transistor (TFT), source electrode be connected with the drain electrode of described 3rd thin film transistor (TFT) and the grid of described eight thin film transistor (TFT)s respectively, drain electrode be connected with the low level output end of driving power;
Described 7th thin film transistor (TFT), grid is connected with second clock signal input part, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the grid of the 13 thin film transistor (TFT);
Described 8th thin film transistor (TFT), source electrode is connected with the high level output end of driving power;
Between the grid that described second electric capacity is connected to described 5th thin film transistor (TFT) and source electrode;
Described reset unit comprises the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11 thin film transistor (TFT), the 12 thin film transistor (TFT) and the 13 thin film transistor (TFT);
Described 9th thin film transistor (TFT), grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of the first film transistor;
Described tenth thin film transistor (TFT), grid is connected with the 3rd clock signal terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of described 5th thin film transistor (TFT);
Described 11 thin film transistor (TFT), grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the high level output end of driving power, and drain electrode is connected with the source electrode of described 6th thin film transistor (TFT);
Described 12 thin film transistor (TFT), grid is connected with the 3rd clock signal input terminal, and source electrode is connected with the grid of described 13 thin film transistor (TFT), and drain electrode is connected with the low level output end of driving power;
Described 13 thin film transistor (TFT), grid is connected with the source electrode of described 4th thin film transistor (TFT), and source electrode is connected with the drain electrode of described 8th thin film transistor (TFT), and drain electrode is connected with the low level output end of driving power;
The source electrode of described 13 thin film transistor (TFT) is connected with described LED control signal output terminal;
Described emission control circuit also comprises reversed-phase output;
The grid of described 6th thin film transistor (TFT) is connected with described reversed-phase output;
The signal exported from described reversed-phase output and described LED control signal anti-phase.
2. emission control circuit as claimed in claim 1, it is characterized in that, described output unit also comprises the 3rd electric capacity, and described reset unit also comprises the 4th electric capacity;
Described 3rd electric capacity, between the source electrode being connected to described 6th thin film transistor (TFT) and the low level output end of driving power;
Described 4th electric capacity, between the source electrode being connected to described 13 thin film transistor (TFT) and the low level output end of driving power.
3. emission control circuit as claimed in claim 1 or 2, it is characterized in that, the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11 thin film transistor (TFT), the 12 thin film transistor (TFT) and the 13 thin film transistor (TFT) are p-type TFT.
4. a light-emitting control method, be applied to the emission control circuit as described in claim arbitrary in claims 1 to 3, for generation of the LED control signal of control OLED luminescence in AMOLED, it is characterized in that, described LED control signal and gate drive signal anti-phase;
Described light-emitting control method comprises the following steps:
Input sample step: input sample unit is sampled to input signal, and the signal obtained of sampling is sent to LED control signal output terminal;
Export step: output unit produces LED control signal, and this LED control signal is sent to described LED control signal output terminal;
Reset process: reset unit resets to described LED control signal.
5. a shift register, is characterized in that, comprises multistage emission control circuit as described in claim arbitrary in claims 1 to 3;
Except first order emission control circuit and second level emission control circuit, the input signal of n-th grade of emission control circuit is the signal anti-phase with the LED control signal of (n-2) level emission control circuit;
The input signal of first order emission control circuit and the input signal of second level emission control circuit are start signal;
N is greater than the integer that 2 are less than or equal to N, and N is the progression of the emission control circuit that described shift register comprises.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210244370.0A CN102760407B (en) | 2012-07-13 | 2012-07-13 | Emission control circuit, light-emitting control method and shift register |
| PCT/CN2012/086611 WO2014008743A1 (en) | 2012-07-13 | 2012-12-14 | Light emitting control circuit, light emitting control method, and shift register |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210244370.0A CN102760407B (en) | 2012-07-13 | 2012-07-13 | Emission control circuit, light-emitting control method and shift register |
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| CN102760407A CN102760407A (en) | 2012-10-31 |
| CN102760407B true CN102760407B (en) | 2015-11-25 |
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| WO (1) | WO2014008743A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760407B (en) * | 2012-07-13 | 2015-11-25 | 京东方科技集团股份有限公司 | Emission control circuit, light-emitting control method and shift register |
| CN103000120B (en) * | 2012-12-13 | 2015-04-01 | 京东方科技集团股份有限公司 | Shifting register, gate drive circuit and display device |
| CN104599630B (en) * | 2014-12-16 | 2017-04-19 | 上海天马有机发光显示技术有限公司 | Driving circuit, lighting control circuit, display panel and display device |
| CN104464628B (en) * | 2014-12-18 | 2017-01-18 | 京东方科技集团股份有限公司 | Shifting register unit, driving method of shifting register unit, grid drive circuit and display device |
| CN108735150B (en) * | 2017-04-24 | 2020-11-03 | 昆山国显光电有限公司 | Light-emitting control circuit, light-emitting control method and shift register |
| CN108806590B (en) * | 2017-04-28 | 2023-11-24 | 昆山国显光电有限公司 | Emission control driver and display device thereof |
| CN107657918B (en) | 2017-09-29 | 2019-10-01 | 上海天马微电子有限公司 | Emission control signal generating circuit, its driving method and device |
| CN108039150B (en) * | 2017-11-16 | 2020-05-19 | 武汉华星光电半导体显示技术有限公司 | Shift register circuit and shift register unit |
| KR102470378B1 (en) * | 2017-11-30 | 2022-11-23 | 엘지디스플레이 주식회사 | Gate driving circuit and light emitting display apparatus comprising the same |
| CN108230999B (en) * | 2018-02-01 | 2019-11-19 | 武汉华星光电半导体显示技术有限公司 | GOA circuit and OLED display |
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| CN102760407A (en) | 2012-10-31 |
| WO2014008743A1 (en) | 2014-01-16 |
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