CN108806590B - Emission control driver and display device thereof - Google Patents
Emission control driver and display device thereof Download PDFInfo
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- CN108806590B CN108806590B CN201710297171.9A CN201710297171A CN108806590B CN 108806590 B CN108806590 B CN 108806590B CN 201710297171 A CN201710297171 A CN 201710297171A CN 108806590 B CN108806590 B CN 108806590B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
Abstract
The invention provides an emission control driver and a display device thereof, the emission control driver comprises: a plurality of emitter stages, each emitter stage comprising: a first signal processor receiving the first voltage and outputting a first signal and a second signal in response to the first control signal, the second control signal, and the third control signal; a second signal processor receiving the first voltage, the second voltage and outputting a third signal in response to the third control signal, the first signal and the second signal; and a third signal processor receiving the first voltage, the second voltage and outputting a transmission control signal in response to the third control signal, the second signal and the third signal. According to the emission control driver and the display device thereof, the three signal processors are used for receiving the first voltage and the second voltage and responding to the first control signal, the second control signal and the third control signal to finally output the emission control signal, so that the structure of the emission control driver is simplified, and stable emission control signals can be output.
Description
Technical Field
The invention relates to the field of flat panel display, in particular to an emission control driver and a display device thereof.
Background
In recent years, various types of display devices, such as liquid crystal display devices, plasma display devices, electrowetting display devices, electrophoretic display devices, organic light emitting display devices, and the like, have been developed at home and abroad. The organic light-emitting display device utilizes the recombination of electron hole pairs in a specific material to emit light with specific wavelength to display images, and has the advantages of quick response, low power consumption, light weight, wide color gamut and the like.
The organic light emitting display device includes a display panel and a panel driver. The display panel includes a plurality of pixels for displaying an image. The panel driver includes: a data driver for applying a data voltage to the pixels; a scan driver for sequentially applying scan signals to the pixels; an emission control driver for applying an emission control signal to the pixels. The pixels receive the data voltages in response to the scan signals, and the pixels generate light having a predetermined brightness corresponding to the data voltages to display an image. The emission period of the pixel is controlled by an emission control signal, and the emission control driver is initialized in response to the initial control signal and generates the emission control signal.
However, existing emission control drivers are relatively complex, and it is desirable to simplify the construction of the emission control drivers.
Disclosure of Invention
The invention aims to provide an emission control driver and a display device thereof, which simplify the structure of the emission control driver.
To achieve the above object, the present invention provides an emission control driver comprising: a plurality of emission stages sequentially outputting emission control signals through emission control lines, each of the emission stages including:
a first signal processor receiving the first voltage and outputting a first signal and a second signal in response to the first control signal, the second control signal, and the third control signal;
a second signal processor receiving the first voltage, the second voltage and outputting a third signal in response to the third control signal, the first signal and the second signal;
a third signal processor receiving the first voltage, the second voltage and outputting a transmission control signal in response to the third control signal, the second signal and the third signal;
wherein the level of the first voltage is higher than the level of the second voltage; the first signal processor of each of the plurality of transmitting stages except the first transmitting stage receives the transmission control signal output from the previous transmitting stage as a first control signal, and the first signal processor of the first transmitting stage of the plurality of transmitting stages receives a trigger signal as a first control signal.
Optionally, the second control signal is a first clock signal, and the third control signal is a second clock signal; the first clock signal and the second clock signal have the same frequency and are 180 degrees out of phase.
Optionally, the first signal processor comprises six transistors, wherein,
a grid electrode of the first transistor receives a first clock signal, a first electrode of the first transistor receives a trigger signal, and a second electrode of the first transistor, a first electrode of the second transistor, a grid electrode of the fourth transistor and a grid electrode of the fifth transistor are connected with a second node;
a grid electrode of the second transistor receives a second clock signal, and a second electrode of the second transistor is connected with a second electrode of the third transistor; a first electrode of the third transistor receives a first voltage, and a gate of the third transistor is connected with a first node;
the first electrode of the fourth transistor is connected with the second electrode of the fifth transistor, and the second electrode of the fourth transistor receives a first clock signal; a first electrode of the fifth transistor and a second electrode of the sixth transistor are connected with the first node; the grid electrode of the sixth transistor is connected with the first electrode of the sixth transistor and receives a first clock signal;
wherein the voltage of the first node is output as a first signal and the voltage of the second node is output as a second signal.
Optionally, the second signal processor comprises four transistors and a capacitor, wherein,
a grid electrode of the seventh transistor receives a second signal, a first electrode of the seventh transistor receives a first voltage, and a second electrode of the seventh transistor and a first electrode of the ninth transistor are connected with a third node;
a grid electrode of the eighth transistor is connected with a first electrode of the tenth transistor and receives a first signal, the first electrode of the eighth transistor receives a second clock signal, and a second electrode of the eighth transistor, a second electrode of the ninth transistor and one end of a first capacitor are connected; a gate of the ninth transistor receives a second clock signal; a grid electrode of the tenth transistor receives a second voltage, and a second electrode of the tenth transistor is connected with the other end of the first capacitor;
wherein the voltage of the third node is output as a third signal.
Optionally, the second signal processor further includes an eleventh transistor, a gate of the eleventh transistor receives the second voltage, a first electrode of the eleventh transistor is connected to the gate of the eighth transistor, and a second electrode of the eleventh transistor is connected to the first electrode of the fifth transistor and the second electrode of the sixth transistor.
Optionally, the third signal processor comprises two transistors and two capacitors, wherein,
a gate of the twelfth transistor receives the third signal, a first electrode of the twelfth transistor is connected with a second electrode of the thirteenth transistor, and outputs an emission control signal, and a second electrode of the twelfth transistor receives the first voltage; a gate of the thirteenth transistor receives a second signal, a first electrode of the thirteenth transistor receives a second voltage;
one end of the second capacitor receives the first voltage, and the other end of the second capacitor receives the third signal; one end of the third capacitor receives the second signal, and the other end of the third capacitor receives the second clock signal.
Optionally, the first transistor to the thirteenth transistor are P-type thin film transistors.
Optionally, the first electrode is a drain electrode, and the second electrode is a source electrode.
Correspondingly, the invention also provides a display device which comprises the emission control driver.
Optionally, the display device further includes:
a display panel including a plurality of scan lines, a plurality of data lines, a plurality of emission control lines, and a plurality of pixels;
a scan driver sequentially applying scan signals to the pixels through the scan lines; and
a data driver applying a data signal to the pixel through the data line;
and, the emission control driver applies an emission control signal to the pixel through an emission control line.
Compared with the prior art, the emission control driver and the display device thereof provided by the invention have the advantages that the three signal processors are used for receiving the first voltage and the second voltage and responding to the first control signal, the second control signal and the third control signal to finally output the emission control signal, the connection relation among the signal processors is simple, and the structure of the emission control driver is simplified;
furthermore, the emission control driver adopts a small amount of transistors and capacitors to realize the output of emission control signals, thereby being convenient for the realization of integration and improving the yield of the display device; and because of the arrangement of the tenth transistor and the eleventh transistor, the high voltage resistance of the circuit in the emission control driver can be improved, certain transistors of the circuit are prevented from being broken down under the condition of large voltage difference between the first voltage and the second voltage, the reliability of the emission control driver is improved, and the emission control driver can output stable emission control signals.
Drawings
FIG. 1 is a circuit diagram of a first transmit stage of a transmit control driver;
FIG. 2 is a block diagram of a transmit control driver according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a first transmission stage of a transmission control driver according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a first transmission stage of a transmission control driver according to an embodiment of the present invention;
FIG. 5 is a timing diagram of the operation of a first firing stage of the firing control driver shown in FIG. 3 or FIG. 4;
fig. 6 is a block diagram of a display device according to an embodiment of the invention.
Detailed Description
Fig. 1 is a circuit diagram of a first emission stage of an emission control driver, as shown in fig. 1, including: a first signal processor 1 receiving the first voltage VGH and outputting a first signal CS1 and a second signal CS2 in response to the trigger signal STP, the first clock signal CK1, and the second clock signal CK2; a second signal processor 2 receiving the first voltage VGH, the second voltage VGL and outputting a third signal CS3 in response to the second clock signal CK2, the first signal CS1, the second signal CS2; the third signal processor 3 receives the first voltage VGH, the second voltage VGL, and outputs the emission control signal EM in response to the second clock signal CK2, the second signal CS2, and the third signal CS3.
Specifically, the first signal processor 1 includes six transistors, where a gate of the first transistor M1 receives the first clock signal CK1, a first electrode of the first transistor M1 receives the trigger signal STP, and a second electrode of the first transistor M1, a first electrode of the second transistor M2, a gate of the fourth transistor M4, and a gate of the fifth transistor M5 are connected to the second node P2; a gate of the second transistor M2 receives the second clock signal CK2, and a second electrode of the second transistor M2 is connected to a second electrode of the third transistor M3; a first electrode of the third transistor M3 receives a first voltage VGH, and a gate of the third transistor M3 is connected to the first node P1; the first electrode of the fourth transistor M4 is connected to the second electrode of the fifth transistor M5, and the second electrode of the fourth transistor M4 receives the first clock signal CK1; the first electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6 are connected to the first node P1; the gate of the sixth transistor M6 is connected to the first electrode of the sixth transistor M6 and receives the first clock signal CK1. Wherein the voltage of the first node P1 is output as a first signal CS1 and the voltage of the second node P2 is output as a second signal CS2. The applicant has found that in this case, by connecting the first electrode of the sixth transistor M6 to the first clock signal CK1, routing can be greatly facilitated, simplifying the manufacturing process of the circuit.
The second signal processor 2 comprises three transistors and a capacitor, wherein,
a gate of the seventh transistor M7 receives the second signal CS2, a first electrode of the seventh transistor M7 receives the first voltage VGH, and a second electrode of the seventh transistor M7 and a first electrode of the ninth transistor M9 are connected to the third node P3; a gate of the eighth transistor M8 is connected to one end of the first capacitor C1, and receives the first signal CS1, a first electrode of the eighth transistor M8 receives the second clock signal CK2, and a second electrode of the eighth transistor M8 is connected to the other end of the first capacitor C1 and a second electrode of the ninth transistor M9; the gate of the ninth transistor M9 receives the second clock signal CK2. Wherein the voltage of the third node P3 is output as a third signal CS3.
The third signal processor 3 comprises two transistors and two capacitors, wherein,
a gate of the tenth transistor M10 receives the third signal CS3, a first electrode of the tenth transistor M10 is connected to a second electrode of the eleventh transistor M11, and outputs the emission control signal EM, and a second electrode of the tenth transistor M10 receives the first voltage VGH; a gate of the eleventh transistor M11 receives the second signal CS2, and a first electrode of the eleventh transistor M11 receives the second voltage VGL; one end of the second capacitor C2 receives the first voltage VGH, and the other end of the second capacitor C2 receives the third signal CS3; one end of the third capacitor C3 receives the second signal CS2, and the other end of the third capacitor C3 receives the second clock signal CK2.
The circuit diagram of the remaining emitters of the emission control driver, except for the first emitter, is similar to the circuit diagram of the first emitter, except that the trigger signal STP is taken as the emission control signal output by the previous emitter, for example, for the second emitter, the trigger signal STP in fig. 1 is the emission control signal output by the first emitter, and for the third emitter, the trigger signal STP in fig. 1 is the emission control signal output by the second emitter.
The structure of each emitter is simple, an emission control signal is sequentially output through an emission control line, and the emission control signal is sequentially supplied to a display panel including the emission control driver for controlling an emission period of a pixel, but the circuit shown in fig. 1 has a certain reliability problem. For example, at a certain moment, when the first clock signal CK1 is at a high level and the second clock signal CK2 is at a low level, the point P2 forms a high voltage (e.g. 7V) at the moment, the point P1 forms an ultra-low voltage (-17.3V) at the moment, the ultra-low voltage is applied to the gate of the third transistor M3, and a large voltage difference is formed between the ultra-low voltage and the 7V voltage of the source of the third transistor M3, so that the third transistor M3 is easily broken down. Similarly, the fifth transistor M5 and the sixth transistor M6 are also easily broken down.
In view of the above problems, the inventors have improved the circuit shown in fig. 1, and added one or more transistors to the circuit shown in fig. 1 to prevent breakdown due to excessive voltage difference of the transistors, thereby improving the high voltage resistance of each emitter.
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
In the following description, the present invention will be described in detail with reference to the drawings, which are not to be construed as limiting the invention, for the purpose of illustration and not as an actual scale.
Fig. 2 is a block diagram of an emission control driver according to an embodiment of the present invention, and as shown in fig. 2, the present invention provides an emission control driver including a plurality of emission stages sequentially connected, a first emission stage S1, second emission stages S2, … …, an n-1 emission stage Sn-1, and an n-1 emission stage Sn (where n is an integer greater than 1), and the plurality of emission stages sequentially output emission control signals through emission control lines. Hereinafter, the emission control signals output from the first to nth emission stages S1 to Sn are referred to as first to nth emission control signals EM1 to EMn.
Each of the plurality of transmitting stages receives the first voltage VGH, the second terminal voltage VGL, and outputs a transmitting control signal in response to the first control signal, the second control signal, and the third control signal. Wherein, the voltage level of the first voltage VGH is higher than the voltage level of the second voltage VGL. Each of the plurality of transmitting stages except the first transmitting stage S1 receives the transmission control signal output from a previous transmitting stage as a first control signal, and the first transmitting stage S1 of the plurality of transmitting stages receives a trigger signal STP as the first control signal. The second control signal CK1 is the first clock signal CK1, and the third control signal is the second clock signal CK2. The first clock signal CK1 and the second clock signal CK2 have the same frequency and are 180 degrees out of phase.
Specifically, the first emission stage S1 receives the first voltage VGH and the second voltage VGL and outputs the first emission signal EM1 in response to the trigger signal STP, the first clock signal CK1, and the second clock signal CK2. The second transmitting stage S2 receives the first voltage VGH and the second voltage VGL and outputs a second transmitting signal EM2 in response to the first transmitting signal EM1, the first clock signal CK1, and the second clock signal CK2. Similarly, the n-1 th transmission stage Sn-1 receives the first voltage VGH and the second voltage VGL and outputs the n-1 th transmission signal EMn-1 in response to the n-2 th transmission signal EMn-2, the first clock signal CK1 and the second clock signal CK2. The nth transmission stage Sn receives the first voltage VGH and the second voltage VGL and outputs an nth transmission signal EM in response to the nth-1 transmission signal EMn-1, the first clock signal CK1, and the second clock signal CK2.
Fig. 3 is a circuit diagram of a first emission stage of an emission control driver according to an embodiment of the present invention, where, as shown in fig. 3, the first emission stage includes: the first signal processor 10 receives the first voltage VGH and outputs a first signal CS1 and a second signal CS2 in response to the trigger signal STP, the first clock signal CK1, and the second clock signal CK2; a second signal processor 20 receiving the first voltage VGH, the second voltage VGL and outputting a third signal CS3 in response to the second clock signal CK2, the first signal CS1, the second signal CS2; the third signal processor 30 receives the first voltage VGH, the second voltage VGL, and outputs the emission control signal EM in response to the second clock signal CK2, the second signal CS2, and the third signal CS3.
Fig. 3 is a circuit diagram of an emitter by taking a first emitter as an example, and the circuit diagram of the remaining emitters is identical to the circuit diagram of the first emitter, except that the trigger signal STP in fig. 3 should be an emission control signal output from the previous emitter for the remaining emitters. For example, for the second emitter, the trigger signal STP in fig. 3 should be the emission control signal output by the first emitter; for the n-1 th emitter, the trigger signal STP in FIG. 3 should be the emission control signal output by the n-2 th emitter; for the n-th emitter, the trigger signal STP in FIG. 3 should be the emission control signal output by the n-1-th emitter.
With continued reference to fig. 3, in particular, the first signal processor 10 includes six transistors, wherein,
a gate of the first transistor M1 receives the first clock signal CK1, a first electrode of the first transistor M1 receives the trigger signal STP, and a second electrode of the first transistor M1, a first electrode of the second transistor M2, a gate of the fourth transistor M4, and a gate of the fifth transistor M5 are connected to the second node P2; a gate of the second transistor M2 receives the second clock signal CK2, and a second electrode of the second transistor M2 is connected to a second electrode of the third transistor M3; a first electrode of the third transistor M3 receives a first voltage VGH, and a gate of the third transistor M3 is connected to the first node P1; the first electrode of the fourth transistor M4 is connected to the second electrode of the fifth transistor M5, and the second electrode of the fourth transistor M4 receives the first clock signal CK1; the first electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6 are connected to the first node P1; the gate of the sixth transistor M6 is connected to the first electrode of the sixth transistor M6 and receives the first clock signal CK1. Wherein the voltage of the first node P1 is output as a first signal CS1 and the voltage of the second node P2 is output as a second signal CS2.
The second signal processor 20 comprises four transistors and a capacitor, wherein,
a gate of the seventh transistor M7 receives the second signal CS2, a first electrode of the seventh transistor M7 receives the first voltage VGH, and a second electrode of the seventh transistor M7 and a first electrode of the ninth transistor M9 are connected to the third node P3; a gate of the eighth transistor M8 is connected to the first electrode of the tenth transistor M10, and receives the first signal CS1, the first electrode of the eighth transistor M8 receives the second clock signal CK2, and the second electrode of the eighth transistor and the second electrode of the ninth transistor are connected to one end of the first capacitor; a gate of the ninth transistor M9 receives the second clock signal CK2; the gate of the tenth transistor M10 receives the second voltage VGL, and the second electrode of the tenth transistor M10 is connected to the other end of the first capacitor C1. Wherein the voltage of the third node P3 is output as a third signal CS3.
The tenth transistor M10 is used to prevent the voltage of the first node P1 from being too low, prevent the remaining transistors, particularly the third transistor M3, the fifth transistor M5 and the sixth transistor M6, from being broken down, and improve the high voltage resistance of the emitter. Specifically, for example, at a certain moment, the trigger signal STP is at a high level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level, the second node P2 forms a high voltage (e.g. 7V) at the moment, the first node P1 forms an ultra-low voltage (-17.3V) at the moment, the ultra-low voltage is applied to the gate of the third transistor M3, and a large voltage difference is formed between the ultra-low voltage and the 7V voltage of the source of the third transistor M3, so that the third transistor M3 is easily broken down. Similarly, the fifth transistor M5 and the sixth transistor M6 are also easily broken down. And due to the arrangement of the tenth transistor M10, the voltage at the first electrode of the tenth transistor M10 is not too low, and the first electrode of the tenth transistor M10, the gate of the eighth transistor M8, and the first node P1 are connected, i.e., the arrangement of the tenth transistor M10 makes the voltage at the first node P1 not too low, thereby avoiding the voltage difference between the gate and the source of the third transistor M3, the fifth transistor M5, the sixth transistor M6, or the rest of transistors from being too large, preventing the transistors from being broken down, thereby improving the reliability of the emission control driver, and enabling the emission control driver to output a stable emission control signal.
The third signal processor 30 comprises two transistors and two capacitors, wherein,
a gate of the twelfth transistor M12 receives the third signal CS3, a first electrode of the twelfth transistor M12 is connected to a second electrode of the thirteenth transistor M13, and outputs the emission control signal EM, and a second electrode of the twelfth transistor M12 receives the first voltage VGH; a gate of the thirteenth transistor M13 receives the second signal CS2, and a first electrode of the thirteenth transistor M13 receives the second voltage VGL; one end of the second capacitor C2 receives the first voltage VGH, and the other end of the second capacitor C2 receives the third signal CS3; one end of the third capacitor C3 receives the second signal CS2, and the other end of the third capacitor C3 receives the second clock signal CK2.
Preferably, the second signal processor 20 further includes an eleventh transistor M11, wherein the gate of the eleventh transistor M11 receives the second voltage VGL, the first electrode of the eleventh transistor M11 is connected to the gate of the eighth transistor M8, and the second electrode of the eleventh transistor M11 is connected to the first electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6, as shown in fig. 4. The eleventh transistor M11 and the tenth transistor M10 cooperate to prevent the voltage at the fifth node P5 from being too low, prevent the remaining transistors, particularly the third transistor M3, the fifth transistor M5, and the sixth transistor M6, from being broken down, and improve the high voltage resistance of the emitter.
Fig. 4 is a circuit diagram of a first emission stage of an emission control driver according to an embodiment of the present invention, compared with fig. 3, an eleventh transistor M11 is added, and due to the addition of the eleventh transistor M11, a voltage of a fourth node P4 at a connection point of a first electrode of the fifth transistor M5 and a second electrode of the sixth transistor M6 is different from a voltage of a fifth node P5 at a connection point of a gate of the eighth transistor M8 and a second electrode of the tenth transistor M10, so in fig. 4, the first signal processor 10 further outputs a fourth signal CS4 at the fourth node P4, the second signal processor 20 further inputs the fourth signal CS4, specifically, the first signal processor 10 receives a first voltage VGH and outputs the first signal CS1, the second signal CS2 and the fourth signal CS4 in response to the first control signal, the second control signal and the third control signal, and the second signal CS 20 receives the first voltage VGH and the third signal CS2 and outputs the fourth signal CS1 and the third signal CS4 in response to the first voltage VGL and the third signal CS 4.
Referring specifically to fig. 4, in the first signal processor 10, a first electrode of the fifth transistor M5 and a second electrode of the sixth transistor M6 are connected to the fourth node P4, a voltage of the fourth node P4 is output as a fourth signal CS4, a gate of the third transistor M3 is connected to the first node P1, and a voltage of the first node P1 is output as a first signal CS1; in the second signal processor 20, the second electrode of the eleventh transistor M11 receives the fourth signal CS4, the first electrode of the eleventh transistor M11 is connected to the gate of the eighth transistor M8, the second electrode of the tenth transistor M10, and one end of the first capacitor C1, the first electrode of the tenth transistor M10 receives the first signal CS1, and the gate of the eleventh transistor M11 receives the second voltage VGL. The connection manner of the remaining transistors or capacitors in fig. 4 is the same as that of fig. 3, so the remaining structures in fig. 4 are not described one by one, and refer to the description of fig. 3.
The transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. Preferably, the first to thirteenth transistors M1 to M13 are thin film transistors, and more preferably, the first to thirteenth transistors M1 to M13 may be low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
In this embodiment, the first electrode is a source electrode, and the second electrode is a drain electrode; alternatively, the first electrode is a drain electrode and the second electrode is a source electrode. Transistors can be classified into P-channel transistors (referred to as P-type transistors) and N-channel transistors (referred to as N-type transistors) according to the type of transistor channel. In this embodiment, the first transistor M1 to the thirteenth transistor M13 are P-type transistors, and are turned on at low level. In other embodiments, the first to thirteenth transistors M1 to M13 may be N-type transistors, and are turned on at a high level. It should be understood that the first to thirteenth transistors M1 to M13 may be different types of thin film transistors, for example, the first to fifth transistors M1 to M5 are P-type transistors, and the sixth to thirteenth transistors M6 to M13 are N-type transistors. When the first transistor T1 to the thirteenth transistor M13 are P-type transistors, the first electrode is a drain electrode and the second electrode is a source electrode.
Fig. 5 is an operation timing chart of the first transmission stage of the transmission control driver shown in fig. 3 or 4, and as shown in fig. 5, the first clock signal CK1 and the second clock signal CK2 have the same frequency and are 180 degrees out of phase, i.e., the first clock signal CK1 and the second clock signal CK2 have the same period, and when the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and when the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level.
When the first clock signal CK1 changes from a high level to a low level and the second clock signal CK2 changes from a low level to a high level, the trigger signal STP changes from a low level to a high level, and the duration of the high level of the trigger signal STP is preferably four times the duration of the high level of the first clock signal CK1 or the second clock signal CK2.
When the trigger signal STP changes from a high level to a low level, the first emitter outputs an emission control signal, that is, the first emission control signal EM1 changes from a low level to a high level, and the high level duration of the first emission control signal EM1 is preferably three times the high level duration of the first clock signal CK1 or the second clock signal CK2.
The first emission control signal EM1 is used as a first control signal of a second stage, and outputs a second emission control signal EM2, and the high levels of a part of the second emission control signal EM2 and the first emission control signal EM1 are overlapped with each other, and the high level overlapped with each other is preferably one third of the high level of the first emission control signal EM1. And so on, finally, the nth transmission control signal (not shown in the figure) is output.
In fig. 5, the first transistor M1 to the thirteenth transistor M13 are P-type transistors. When the first transistor M1 to the thirteenth transistor M13 are all N-type transistors, the timings of the signals in fig. 5 have opposite levels. When the first to thirteenth transistors M1 to M13 are different types of thin film transistors, the timing of each signal needs to be determined according to an actual connection relationship, which is not described in detail herein.
Correspondingly, the invention also provides a display device which comprises the emission control driver.
Fig. 6 is a block diagram of a display device according to an embodiment of the present invention, and as shown in fig. 6, the present invention provides a display device, including: a display panel 110, a scan driver 120, a data driver 130, and an emission control driver 140. The emission control driver 140 is the emission control driver described above.
The display panel 110 includes a plurality of scan lines S1 to Sn, a plurality of data lines D1 to Dm, a plurality of emission control lines E1 to En, and a plurality of pixels PX11 to PXnm arranged in a matrix form, each of the pixels PX11 to PXnm being connected to a corresponding one of the scan lines S1 to Sn extending in a row direction and to a corresponding one of the data lines D1 to Dm crossing the scan lines S1 to Sn. In addition, each of the pixels PX11 to PXnm is connected to a corresponding emission control line of the emission control lines E1 to En. Wherein the emission control lines E1 to En are substantially parallel to the scan lines S1 to Sn.
The scan lines S1 to Sn are connected to the scan driver 120 to receive scan signals. The data lines D1 to Dm are connected to the data driver 130 to receive data signals. The emission control lines E1 to En are connected to the emission control driver 140 to receive emission control signals. In the present exemplary embodiment, n and m are each integers greater than 1.
Specifically, each of the pixels PX11 to PXnm receives the data voltage through the corresponding one of the data lines D1 to Dm in response to the scan signal supplied through the corresponding one of the scan lines S1 to Sn, and the pixels PX11 to PXnm generate light having a predetermined brightness corresponding to the data voltage to display a graphic. Each of the pixels PX11 to PXnm determines a period of time for which each pixel emits light in response to an emission control signal supplied through a corresponding one of the emission control lines E1 to En.
In summary, according to the emission control driver and the display device thereof provided by the invention, the three signal processors receive the first voltage and the second voltage and respond to the first control signal, the second control signal and the third control signal to finally output the emission control signal, and the connection relationship among the signal processors is simple, so that the structure of the emission control driver is simplified.
Furthermore, the emission control driver adopts a small amount of transistors and capacitors to realize the output of emission control signals, thereby being convenient for the realization of integration and improving the yield of the display device; and because of the arrangement of the tenth transistor and the eleventh transistor, the high voltage resistance of the circuit in the emission control driver can be improved, certain transistors of the circuit are prevented from being broken down under the condition of large voltage difference between the first voltage and the second voltage, the reliability of the emission control driver is improved, and the emission control driver can output stable emission control signals.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. An emission control driver, comprising:
a plurality of emission stages sequentially outputting emission control signals through emission control lines, each of the emission stages including:
a first signal processor receiving the first voltage and outputting a first signal and a second signal in response to the first control signal, the second control signal, and the third control signal;
a second signal processor receiving the first voltage, the second voltage and outputting a third signal in response to the third control signal, the first signal and the second signal;
a third signal processor receiving the first voltage, the second voltage and outputting a transmission control signal in response to the third control signal, the second signal and the third signal;
wherein the level of the first voltage is higher than the level of the second voltage; the first signal processor of each of the plurality of transmitting stages except the first transmitting stage receives the transmission control signal output from the previous transmitting stage as a first control signal, and the first signal processor of the first transmitting stage of the plurality of transmitting stages receives a trigger signal as a first control signal.
2. The transmit control driver of claim 1, wherein the second control signal is a first clock signal and the third control signal is a second clock signal; the first clock signal and the second clock signal have the same frequency and are 180 degrees out of phase.
3. The emission control driver of claim 2, wherein the first signal processor comprises six transistors, wherein,
a grid electrode of the first transistor receives a first clock signal, a first electrode of the first transistor receives a trigger signal, and a second electrode of the first transistor, a first electrode of the second transistor, a grid electrode of the fourth transistor and a grid electrode of the fifth transistor are connected with a second node;
a grid electrode of the second transistor receives a second clock signal, and a second electrode of the second transistor is connected with a second electrode of the third transistor; a first electrode of the third transistor receives a first voltage, and a gate of the third transistor is connected with a first node;
the first electrode of the fourth transistor is connected with the second electrode of the fifth transistor, and the second electrode of the fourth transistor receives a first clock signal; a first electrode of the fifth transistor and a second electrode of the sixth transistor are connected with the first node; the grid electrode of the sixth transistor is connected with the first electrode of the sixth transistor and receives a first clock signal;
wherein the voltage of the first node is output as a first signal and the voltage of the second node is output as a second signal.
4. The emission control driver of claim 3, wherein the second signal processor comprises four transistors and a capacitor, wherein,
a grid electrode of the seventh transistor receives a second signal, a first electrode of the seventh transistor receives a first voltage, and a second electrode of the seventh transistor and a first electrode of the ninth transistor are connected with a third node;
a grid electrode of the eighth transistor is connected with a first electrode of the tenth transistor and receives a first signal, the first electrode of the eighth transistor receives a second clock signal, and a second electrode of the eighth transistor, a second electrode of the ninth transistor and one end of a first capacitor are connected; a gate of the ninth transistor receives a second clock signal; a grid electrode of the tenth transistor receives a second voltage, and a second electrode of the tenth transistor is connected with the other end of the first capacitor;
wherein the voltage of the third node is output as a third signal.
5. The emission control driver of claim 4, wherein the second signal processor further comprises an eleventh transistor having a gate receiving the second voltage, a first electrode coupled to the gate of the eighth transistor, and a second electrode coupled to the first electrode of the fifth transistor and the second electrode of the sixth transistor.
6. The emission control driver of claim 5, wherein the third signal processor comprises two transistors and two capacitors, wherein,
a gate of the twelfth transistor receives the third signal, a first electrode of the twelfth transistor is connected with a second electrode of the thirteenth transistor, and outputs an emission control signal, and a second electrode of the twelfth transistor receives the first voltage; a gate of the thirteenth transistor receives a second signal, a first electrode of the thirteenth transistor receives a second voltage;
one end of the second capacitor receives the first voltage, and the other end of the second capacitor receives the third signal; one end of the third capacitor receives the second signal, and the other end of the third capacitor receives the second clock signal.
7. The emission control driver of claim 6, wherein the first transistor through the thirteenth transistor are P-type thin film transistors.
8. The emission control driver of claim 7, wherein the first electrode is a drain and the second electrode is a source.
9. A display device comprising the emission control driver according to any one of claims 1 to 7.
10. The display device according to claim 9, wherein the display device further comprises:
a display panel including a plurality of scan lines, a plurality of data lines, a plurality of emission control lines, and a plurality of pixels;
a scan driver sequentially applying scan signals to the pixels through the scan lines; and
a data driver applying a data signal to the pixel through the data line;
and, the emission control driver applies an emission control signal to the pixel through an emission control line.
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