CN103000120B - Shifting register, gate drive circuit and display device - Google Patents
Shifting register, gate drive circuit and display device Download PDFInfo
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- CN103000120B CN103000120B CN201210540703.4A CN201210540703A CN103000120B CN 103000120 B CN103000120 B CN 103000120B CN 201210540703 A CN201210540703 A CN 201210540703A CN 103000120 B CN103000120 B CN 103000120B
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Abstract
The invention discloses a shifting register, a gate drive circuit and a liquid crystal display (LCD) and relates to the LCD field. The shifting register comprises a first clock circuit, a second clock circuit, a shutdown signal circuit, a start signal circuit, a third clock circuit and a reset switch. Before normal operation of the circuit of the shifting register, a reset stage is performed through the reset switch to enable potential of each suspended gate node in the circuit to reset, therefore written-in signals when the operation is started are not affected, and the problems of potential suspension, poor quality of output signals and the like during operation process are solved.
Description
Technical field
The present invention relates to field of liquid crystal, particularly a kind of shift register, gate driver circuit and display device.
Background technology
Along with the continuous maturation of lcd technology, and LCD(Liquid Crystal Display, liquid crystal display) the continuous decline of price, adopt LCDs as the display screen of various electronic or ornamental electronic display unit in life, become the developing direction of a kind of LCDs consumption gradually.The LCDs of prior art has been widely used in various electrical equipment, as LCD TV, mobile phone etc.
Multiple pixels that liquid crystal display is arranged by matrix form formed, and are specifically made up of the picture element matrix of horizontal and vertical directions.The driving of liquid crystal display mainly comprises data driver and grid level driver, wherein, timely for the display data of input clock signal timing order latches by data driver, the data line of display panels is input to after converting simulating signal to, the clock signal of input is changed through shift register by grid level driver, switch to conduction and cut-off voltage, be applied in turn on the grid level line of display panels.
Fig. 1 is a kind of electrical block diagram adopting the shift register of simple three clocks of P-type crystal pipe in prior art, and the feature of P-type crystal pipe is gate electrode input signal when being high pressure, transistor cutoff; During gate electrode input low pressure, transistor turns.Fig. 2 is its triphasic working timing figure, and the principle of work of this shift register is as follows:
During the first stage, after the first clock signal clk 1 and start signal STV become and open low ordinary mail number, transistor M3 conducting, STV signal is transferred to the gate terminal of transistor M1 by M3, and keeps conducting state by electric capacity C1.The transistor M5 conducting simultaneously controlled by STV signal, by the gate terminal that high-pressure stop signal Vgh is transferred to transistor M2, makes M2 close; During subordinate phase, after second clock signal CLK2 becomes the low ordinary mail of conducting number, the low ordinary mail number of CLK2 is transferred to the output terminal Output of shift register by the conducting state that transistor M1 is kept by C1; During the phase III, 3rd clock signal clk 3 becomes the low ordinary mail number of conducting, transistor M6 conducting, low pressure Continuity signal Vgl is transferred to the grid of transistor M2 and M4, make M2 and M4 all conductings, the conducting of M2 by Vgh Signal transmissions to the conducting of Output, M4 by the grid of Vgh Signal transmissions to M1, M1 grid potential is uprised, thus cut-off M1.
There is following defect in above-mentioned shift register, when subordinate phase, the signal end signal of M2 and M4 is unsettled, non-mandrel roller, causes its current potential unstable, causes M2 to export the signal of M1 and cause impact; When the first stage, now the signal output effect of shift register output end Output is only determined by M1, and now M1 fan-out capability affects by its grid potential size, and single output causes signal quality poor, have impact on the signal output effect of Output.
Summary of the invention
Embodiments provide a kind of shift register, gate driver circuit and display device, the problems such as the electric potential floating occurred in the course of the work in order to solution, the signal quality of output are poor.
The invention provides a kind of shift register, comprising:
First clock circuit, is connected with start signal circuit, and is connected to Controlling vertex A with second clock circuit, the 3rd clock circuit, reset circuit, under the control of the first clock signal, start signal is input to Controlling vertex A;
Second clock circuit, under the control of the first clock signal, exports to signal output part OUTPUT by second clock signal;
Shutdown signal circuit, is connected to Controlling vertex B with the 3rd clock circuit, receives the start signal that start signal circuit exports, exports the first level signal to signal output part OUTPUT;
Start signal circuit, under the control of the start signal of the first clock circuit output, exports to Controlling vertex B by the start signal of self;
3rd clock circuit, under the control of the 3rd clock signal, exports the first level signal to Controlling vertex A, exports second electrical level signal to Controlling vertex B.
Above-mentioned shift register, wherein, described first clock circuit comprises the first transistor M1, and the grid of described the first transistor connects described first clock signal input terminal, the source electrode of the first transistor connects start signal input end, the drain electrode connection control node A of the first transistor.
Above-mentioned shift register, wherein, described second clock circuit comprises third transistor M3 and the first electric capacity C1, the grid connection control node A of described third transistor, the source electrode of third transistor connects second clock signal, the drain electrode connection signal output terminal OUTPUT of third transistor, described first electric capacity C1 are connected between the grid of third transistor M3 and drain electrode.
Above-mentioned shift register, wherein, described shutdown signal circuit comprises the grid connection control Node B of the 4th transistor described in the 4th transistor M4 and the 9th transistor M9, the source electrode of the 4th transistor connects the first level signal, the drain electrode connection signal output terminal OUTPUT of the 4th transistor, the grid connection signal input end OUTPUT of described 9th transistor, the source electrode of the 9th transistor is connected with the source electrode of the 4th transistor, and the drain electrode of the 9th transistor is connected with the grid of the 4th transistor; The two ends of the second electric capacity C2 connect source electrode and the grid of the 4th transistor respectively.
Above-mentioned shift register, wherein, described start signal circuit comprises transistor seconds M2, the grid connection control node A of described transistor seconds, and the source electrode of transistor seconds connects start signal, the drain electrode connection control Node B of transistor seconds.
Above-mentioned shift register, wherein, described 3rd clock circuit comprises the 6th transistor M6 and the 5th transistor M5, the source electrode of described 5th transistor connects the first level signal, the drain electrode connection control node A of the 5th transistor, the source electrode of described 6th transistor connects second electrical level signal, the drain electrode connection control Node B of the 6th transistor, and the grid of the 6th transistor described in described 5th transistor AND gate connects the 3rd clock signal.
Further, above-mentioned shift register, wherein, also comprise reset circuit, described reset circuit and shutdown signal circuit and the 3rd clock circuit are connected to Controlling vertex B, under the control of reset signal, export the first level signal to Controlling vertex A, export second electrical level signal to Controlling vertex B.
Above-mentioned shift register, wherein, described reset circuit comprises the 7th transistor M7 and the 8th transistor M8, the source electrode of described 7th transistor connects second electrical level signal, the drain electrode connection control Node B of the 7th transistor, the source electrode of the 8th transistor connects the first level signal, the source electrode connection control node A of the 8th transistor, and the grid of the 8th transistor described in described 7th transistor AND gate connects reset signal.
Above-mentioned shift register, wherein, described the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and the 9th transistor are P-type crystal pipe, described first level signal is high level, and described second electrical level signal is low level.
Above-mentioned shift register, wherein, described the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and the 9th transistor are N-type transistor, described first level signal is low level, and described second electrical level signal is high level.
Present invention also offers a kind of gate driver circuit, comprise above-mentioned shift register.
Present invention also offers a kind of display device, comprise above-mentioned gate driver circuit.
The embodiment of the present invention, when per stage work, is all avoided occurring suspension node in the course of work by carrying out control to the grid of the 4th transistor and the 5th transistor, and do not have interference and impact when shift register signal exports, the output quality of signal is good; Be provided with reset switch, before the circuit of shift register normally works, the advanced horizontal reset stage makes the current potential of each suspended grid node in circuit reset, and does not impact the signal of write when starting working; When the first stage, shift register exports second clock signal and shutdown signal simultaneously, and only use the output one road signal of one-transistor compared to existing technology, signal is more stable.
Accompanying drawing explanation
The circuit structure diagram of a kind of shift register that Fig. 1 provides for prior art;
The working timing figure of a kind of shift register that Fig. 2 provides for prior art;
The circuit structure diagram of a kind of shift register that Fig. 3 provides for the embodiment of the present invention;
The working timing figure of a kind of shift register that Fig. 4 provides for the embodiment of the present invention.
Embodiment
Embodiments provide a kind of shift register, gate driver circuit and liquid crystal display, the problems such as the electric potential floating occurred in the course of the work in order to solution, the signal quality of output are poor.
Because the present invention mainly solves the problems referred to above by shift register, therefore carry out emphasis to it and describe, a kind of shift register of the embodiment of the present invention, this shift register comprises:
First clock circuit, is connected with start signal circuit, and is connected to Controlling vertex A with second clock circuit, the 3rd clock circuit, reset circuit, under the control of the first clock signal, start signal is input to Controlling vertex A;
Second clock circuit, under the control of the first clock signal, exports to signal output part OUTPUT by second clock signal;
Shutdown signal circuit, is connected to Controlling vertex B with the 3rd clock circuit, receives the start signal that start signal circuit exports, exports the first level signal to signal output part OUTPUT;
Start signal circuit, under the control of the start signal of the first clock circuit output, exports to Controlling vertex B by the start signal of self;
3rd clock circuit, under the control of the 3rd clock signal, exports the first level signal to Controlling vertex A, exports second electrical level signal to Controlling vertex B.
Described shift register also can comprise reset circuit, described reset circuit and shutdown signal circuit and the 3rd clock circuit are connected to Controlling vertex B, under the control of reset signal, export the first level signal to Controlling vertex A, export second electrical level signal to Controlling vertex B.
It is that the signal quality exported by the signal output part of shutdown signal circuit and these two output terminals of signal output part of second clock circuit is decided, so two sides' outputs are compared with the single output of prior art obviously more stable that the signal of the shift register described in the embodiment of the present invention exports.
And no matter exporting at each stage signal of shift register described in the embodiment of the present invention is by shutdown signal circuit or when being exported by second clock circuit, these two circuit all signal that can be subject to from other circuit control it, so it is can not be affected that the signal of this shift register exports.
Below by by above-mentioned each circuit refinement, coordinate Fig. 3, introduce the shift register that a kind of embodiment of the present invention provides in detail:
Described first clock circuit comprises the first transistor M1, and the grid of described the first transistor connects described first clock signal input terminal, and the source electrode of the first transistor connects start signal input end, the drain electrode connection control node A of the first transistor.
Described second clock circuit comprises third transistor M3 and the first electric capacity C1, the grid connection control node A of described third transistor, the source electrode of third transistor connects second clock signal, the drain electrode connection signal output terminal OUTPUT of third transistor, described first electric capacity C1 are connected between the grid of third transistor M3 and drain electrode.
Described shutdown signal circuit comprises the 4th transistor M4 and the 9th transistor M9, the grid connection control Node B of described 4th transistor, the source electrode of the 4th transistor connects the first level signal, the drain electrode connection signal output terminal OUTPUT of the 4th transistor, the grid connection signal input end OUTPUT of described 9th transistor, the source electrode of the 9th transistor is connected with the source electrode of the 4th transistor, and the drain electrode of the 9th transistor is connected with the grid of the 4th transistor.
In order to the current potential of better retentive control Node B, such as when TFT leakage current is larger, in order to keep B point current potential, Controlling vertex B do not occur current potential unsettled time, described shutdown signal circuit can also comprise the second electric capacity C2, and the two ends of the second electric capacity C2 connect source electrode and the grid of the 4th transistor respectively.
Described start signal circuit comprises transistor seconds M2, the grid connection control node A of described transistor seconds, and the source electrode of transistor seconds connects start signal, the drain electrode connection control Node B of transistor seconds.
Described 3rd clock circuit comprises the 6th transistor M6 and the 5th transistor M5, the source electrode of described 5th transistor connects the first level signal, the drain electrode connection control node A of the 5th transistor, the source electrode of described 6th transistor connects second electrical level signal, the drain electrode connection control Node B of the 6th transistor, the grid of the 6th transistor described in described 5th transistor AND gate connects the 3rd clock signal.
The embodiment of the present invention, when per stage work, is all avoided occurring suspension node in work by carrying out control to the grid of the 4th transistor and the 5th transistor, and do not have interference and impact when shift register signal exports, the output quality of signal is good.
It should be noted that in the embodiment of the present invention, source electrode and the drain electrode of each transistor do not do strict differences, and the pole that each transistor AND gate signal end is connected is called source electrode, and the non-pole be connected with signal end of each transistor is called drain electrode.
Because the circuit connection structure of the shift register described in the embodiment of the present invention can be applied to N-type transistor and P-type crystal pipe simultaneously, also can be made up of N-type transistor and mixed the taking of P-type crystal pipe.
Due to before signal charging, in circuit, the suspended grid node potential of each transistor is uncertain, when likely causing initially signal to write, causes interference to write signal, so the shift register described in the embodiment of the present invention can also comprise:
Reset circuit, for receiving reset signal, and controls conducting and the closedown of second clock circuit and closedown clock circuit under the control of reset signal.Described reset circuit comprises the 7th transistor M7 and the 8th transistor M8, the source electrode of described 7th transistor connects the first level signal, the drain electrode connection control Node B of the 7th transistor, the source electrode of the 8th transistor connects second electrical level signal, the source electrode connection control node A of the 8th transistor, the grid of the 8th transistor described in described 7th transistor AND gate connects reset signal.
The embodiment of the present invention before circuit life's work, has carried out current potential recovery to the 4th transistor and third transistor by reset signal, makes it can work with normal current potential when life's work.
As Fig. 3, technical scheme for a better understanding of the present invention, describes course of work when a kind of shift register of the present invention adopts P-type crystal pipe to coordinate Fig. 2 work schedule below in detail:
As shown in Figure 4, this circuit structure is divided into 4 stages when signal writes at first, and after normal work, be divided into 3 stages, these 3 stages are exactly 3 clock signal phase.When signal writes at first, what first carry out is reseting stage, the signal of the grid suspension point in all circuit structures is resetted, namely controlled by Reset reset signal, the gate terminal current potential of the 4th transistor M4 and third transistor M3 is resetted, makes the signal output part Output of shift register export the shutdown signal of high pressure Vgh.
Now the first level signal is high voltage signal VGH, and second electrical level signal is low-voltage VGL.
After reseting stage terminates, just start the three phases of the normal work of shift register.
First stage: CLK1 first clock signal and start signal STV become low flat Continuity signal, and transistor M1 opens, and the gate terminal that STV signal is transferred to transistor seconds M2 and third transistor M3 by M1 makes its conducting.After M3 conducting, the shutdown signal of the high level of second clock signal CLK2 is transferred to the output terminal Output of shift register.When after M2 conducting, start signal STV is transferred to Node B, and Node B controls the 4th transistor M4, makes M4 conducting, the shutdown signal of Vgh is transferred to Output end.
Subordinate phase: CLK1 and STV becomes high level, second clock signal CLK2 becomes low level Continuity signal, now CLK2 is transferred to Output by M3, and be transferred to the gate terminal of the 9th transistor M9, make M9 conducting, the accommodation of Vgh shutdown signal is crossed M9 and is drawn high to cut-off by B point current potential, and control M4 makes it not affect Output output.
Phase III: CLK2 becomes high level signal, the 3rd clock signal clk 3 becomes low level Continuity signal, and A point current potential is drawn high by the 5th transistor M5 by CLK3, becomes Vgh, so just makes M3 end completely, can not affect Output output signal.Also make the 6th transistor M6 conducting simultaneously, B point current potential is dragged down, by M4 conducting, make Vgh signal output to Output end.
By the circulation of these three working stages above-mentioned repeatedly, the function of shift register is achieved.
The embodiment of the present invention additionally provides a kind of gate driver circuit, comprises arbitrary described shift register in preceding claim technical scheme.
The embodiment of the present invention additionally provides a kind of display device, comprises above-mentioned gate driver circuit.
It should be noted that, the shift register described in the invention described above embodiment is not only applicable to liquid crystal display, is also applicable to AMOLED active matrix organic light-emitting diode (AMOLED) panel.
In sum, the embodiment of the present invention is when per stage work, all avoid occurring suspension node in the course of work by carrying out control to the grid of the 4th transistor and the 5th transistor, do not have interference and impact when shift register signal exports, the output quality of signal is good; Be provided with reset switch, before the circuit of shift register normally works, the advanced horizontal reset stage makes the current potential of each suspended grid node in circuit reset, and does not impact the signal of write when starting working; When the first stage, shift register exports second clock signal and shutdown signal simultaneously, and only use the output one road signal of one-transistor compared to existing technology, signal is more stable.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (12)
1. a shift register, is characterized in that, comprising:
First clock circuit, is connected with start signal circuit, and is connected to Controlling vertex A with second clock circuit, the 3rd clock circuit, reset circuit, under the control of the first clock signal, start signal is input to Controlling vertex A;
Second clock circuit, under the control of the first clock signal, exports to signal output part OUTPUT by second clock signal;
Shutdown signal circuit, is connected to Controlling vertex B with the 3rd clock circuit, receives the start signal that start signal circuit exports, exports the first level signal to signal output part OUTPUT;
Start signal circuit, under the control of the start signal of the first clock circuit output, exports to Controlling vertex B by the start signal of self;
3rd clock circuit, under the control of the 3rd clock signal, exports the first level signal to Controlling vertex A, exports second electrical level signal to Controlling vertex B.
2. a kind of shift register as claimed in claim 1, it is characterized in that, described first clock circuit comprises the first transistor M1, the grid of described the first transistor connects described first clock signal input terminal, the source electrode of the first transistor connects start signal input end, the drain electrode connection control node A of the first transistor.
3. a kind of shift register as claimed in claim 2, it is characterized in that, described second clock circuit comprises third transistor M3 and the first electric capacity C1, the grid connection control node A of described third transistor, the source electrode of third transistor connects second clock signal, the drain electrode connection signal output terminal OUTPUT of third transistor, described first electric capacity C1 are connected between the grid of third transistor M3 and drain electrode.
4. a kind of shift register as claimed in claim 3, it is characterized in that, described shutdown signal circuit comprises the 4th transistor M4 and the 9th transistor M9, the grid connection control Node B of described 4th transistor, the source electrode of the 4th transistor connects the first level signal, the drain electrode connection signal output terminal OUTPUT of the 4th transistor, the grid connection signal input end OUTPUT of described 9th transistor, the source electrode of the 9th transistor is connected with the source electrode of the 4th transistor, and the drain electrode of the 9th transistor is connected with the grid of the 4th transistor.
5. a kind of shift register as claimed in claim 4, it is characterized in that, described start signal circuit comprises transistor seconds M2, the grid connection control node A of described transistor seconds, the source electrode of transistor seconds connects start signal, the drain electrode connection control Node B of transistor seconds.
6. a kind of shift register as claimed in claim 5, it is characterized in that, described 3rd clock circuit comprises the 6th transistor M6 and the 5th transistor M5, the source electrode of described 5th transistor connects the first level signal, the drain electrode connection control node A of the 5th transistor, the source electrode of described 6th transistor connects second electrical level signal, the drain electrode connection control Node B of the 6th transistor, and the grid of the 6th transistor described in described 5th transistor AND gate connects the 3rd clock signal.
7. shift register as claimed in claim 6, it is characterized in that, also comprise reset circuit, described reset circuit and shutdown signal circuit and the 3rd clock circuit are connected to Controlling vertex B, under the control of reset signal, export the first level signal to Controlling vertex A, export second electrical level signal to Controlling vertex B.
8. shift register as claimed in claim 7, it is characterized in that, described reset circuit comprises the 7th transistor M7 and the 8th transistor M8, the source electrode of described 7th transistor connects second electrical level signal, the drain electrode connection control Node B of the 7th transistor, the source electrode of the 8th transistor connects the first level signal, the source electrode connection control node A of the 8th transistor, and the grid of the 8th transistor described in described 7th transistor AND gate connects reset signal.
9. shift register as claimed in claim 8, it is characterized in that, described the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and the 9th transistor are P-type crystal pipe, described first level signal is high level signal, and described second electrical level signal is low level signal.
10. a kind of shift register as claimed in claim 8, it is characterized in that, described the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and the 9th transistor are N-type transistor, described first level signal is low level signal, and described second electrical level signal is high level signal.
11. 1 kinds of gate driver circuits, is characterized in that, comprise arbitrary described shift register in claim 1-10.
12. 1 kinds of display device, is characterized in that, comprise gate driver circuit according to claim 11.
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| CN201210540703.4A CN103000120B (en) | 2012-12-13 | 2012-12-13 | Shifting register, gate drive circuit and display device |
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| CN201210540703.4A CN103000120B (en) | 2012-12-13 | 2012-12-13 | Shifting register, gate drive circuit and display device |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103280200B (en) | 2013-04-22 | 2015-01-21 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| CN103996367B (en) * | 2014-04-18 | 2017-01-25 | 京东方科技集团股份有限公司 | Shifting register, gate drive circuit and display device |
| CN104537980B (en) * | 2015-02-03 | 2017-03-29 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driver circuit, display device |
| CN106057143A (en) * | 2016-05-30 | 2016-10-26 | 京东方科技集团股份有限公司 | Shifting register and operation method thereof, grid driving circuit and display device |
| CN106782399A (en) * | 2017-01-11 | 2017-05-31 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driving circuit and display device |
| CN106782288B (en) * | 2017-03-10 | 2020-11-17 | 京东方科技集团股份有限公司 | Gate drive circuit, gate drive method and shift register |
| CN108831385B (en) * | 2018-06-25 | 2020-04-28 | 上海天马有机发光显示技术有限公司 | Scanning driving circuit, display device and driving method |
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| CN203134382U (en) * | 2012-12-13 | 2013-08-14 | 京东方科技集团股份有限公司 | Shifting register, gate driving circuit and display device |
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| KR100797522B1 (en) * | 2002-09-05 | 2008-01-24 | 삼성전자주식회사 | Shift register and liquid crystal display with the same |
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| CN1889190A (en) * | 2006-07-12 | 2007-01-03 | 友达光电股份有限公司 | Shift register |
| CN102760407A (en) * | 2012-07-13 | 2012-10-31 | 京东方科技集团股份有限公司 | Light-emitting control circuit, light-emitting control method and shift register |
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