CN104599630B - A driving circuit and a light emitting control circuit, a display panel, a display device - Google Patents

A driving circuit and a light emitting control circuit, a display panel, a display device Download PDF

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CN104599630B
CN104599630B CN201410784238.8A CN201410784238A CN104599630B CN 104599630 B CN104599630 B CN 104599630B CN 201410784238 A CN201410784238 A CN 201410784238A CN 104599630 B CN104599630 B CN 104599630B
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transistor
node
signal
turned
control
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CN104599630A (en
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王志良
钱栋
罗丽媛
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上海天马有机发光显示技术有限公司
天马微电子股份有限公司
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Abstract

本发明优选实施例提供一种驱动电路及其发光控制电路、显示面板、显示装置,发光控制电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管,第一电容、第二电容;第六晶体管以等效二极管形式连接,只能单向导通,第二电容保持输出端的电位稳定,使得输出端的信号不受时钟信号的影响,也即发光控制电路输出端输出的信号不会抖动。 Preferred embodiments of the present invention provides a driving circuit and a light emitting control circuit, a display panel, a display device, the light emission control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor, a second capacitor; equivalent sixth transistor connected in a diode form, only a single conduction, the output of the second holding capacitor stabilizing the potential of the terminal, so that the clock signal output from the influence of a signal, i.e., light emission control signal output terminal of the circuit does not jitter. 且发光控制电路整个工作过程中,输出端有第十晶体管传输第一电平信号或者第十一晶体管传输第二电平信号,使得输出端输出的信号不会悬空,输出更加稳定,提升显示效果。 And the light emitting control the entire operation of the circuit, the output terminal of the tenth transistor has a first transmission signal level or a second level of the eleventh transistor transmission signal, so that the signal output terminal is not floating, the output is more stable, enhance the display effect .

Description

一种驱动电路及发光控制电路、显示面板、显示装置 A driving circuit and a light emitting control circuit, a display panel, a display device

技术领域 FIELD

[0001] 本发明涉及显示技术领域,尤其涉及一种驱动电路及发光控制电路、显示面板、显示装置。 [0001] The present invention relates to display technology, and particularly relates to a driving circuit and a light emitting control circuit, a display panel, a display device.

背景技术 Background technique

[0002] 有机发光显示(Organic light Emitting Display),由于其具有不需背光源、对比度高、厚度薄、视角广、反应速度等技术优点,已经成为显示行业发展的重点方向之一。 [0002] The organic light emitting display (Organic light Emitting Display), since it has no need backlight, high contrast, thin, wide viewing angle, speed and other technical advantages of the reaction, has become the focus of development direction of display industry. 其利用有机发光材料作为像素的发光材料,利用像素驱动电路驱动发光,而为像素驱动电路提供驱动信号的电路设计是发展有机发光显示技术的重中之重。 Which uses an organic luminescent material as a light emitting material of the pixel, using the pixel drive circuit drives the light-emitting, and for the pixel driving circuit to provide the drive signal circuit design is the development of organic light emitting display priority technique.

发明内容 SUMMARY

[0003] 本发明优选实施例主要提供一种结构简单且输出信号更加稳定的发光控制电路。 [0003] Preferred embodiments of the present invention generally provides a simple and more stable output signal of the control circuit for the light emitting structure.

[0004] —方面,本发明优选实施例提供一种驱动电路,包括第一晶体管、第二晶体管、第三晶体管和第四晶体管,其中: [0004] - aspect, a preferred embodiment of the present invention provides a driving circuit comprising a first transistor, a second transistor, a third transistor and a fourth transistor, wherein:

[0005] 所述第一晶体管的栅极耦接用于接收起始信号的起始信号输入端,第一端耦接用于接收第二时钟信号的第二时钟信号输入端,第二端耦接第一节点; A gate coupled to [0005] of the first transistor coupled for receiving a start signal start signal input terminal, a first terminal of the second clock signal input terminal connected for receiving a second clock signal, a second terminal coupled to the first node;

[0006] 所述第二晶体管的栅极耦接所述第二时钟信号输入端,第一端耦接用于接收第二电平信号的第二电平信号输入端,第二端耦接所述第一节点; [0006] The gate contact of the second transistor coupled to a second clock signal input terminal, a first terminal coupled to the second level signal input terminal connected for receiving the second level signal, a second terminal coupled to the said first node;

[0007] 所述第三晶体管的栅极耦接所述第一节点,第一端耦接用于接收第一时钟信号的第一时钟信号输入端,第二端耦接第二节点; A gate [0007] of the third transistor is coupled to the first node, a first terminal coupled to a first clock signal input terminal for receiving a first clock signal, a second terminal coupled to the second node;

[0008] 所述第四晶体管的栅极耦接所述起始信号输入端,第一端耦接用于接收第一电平信号的第一电平信号输入端,第二端耦接所述第二节点。 [0008] The gate of the fourth transistor is coupled to the start signal input terminal, a first terminal coupled to a first level signal input terminal for receipt of a first signal level, a second terminal connected to the the second node.

[0009]另一方面,本发明另一优选实施例提供一种发光控制电路,包括输入单元和反向单元,其中输入单元包括上述驱动电路。 [0009] On the other hand, another preferred embodiment of the present invention provides a light emission control circuit, comprising an input unit and a reverse unit, wherein the input means comprises the drive circuit.

[0010] 进一步的,所述反向单元包括:第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第一电容和第二电容,其中,所述第五晶体管的栅极耦接所述第二节点,第一端耦接所述第一电平信号输入端,第二端耦接第四节点; [0010] Further, the reverse unit comprises: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor and a second capacitor, wherein the gate of the fifth transistor is coupled to the second node, a first terminal coupled to the first level signal input terminal, a second terminal coupled to the fourth node;

[0011] 所述第六晶体管的第一端通过所述第一电容与所述第一时钟信号输入端耦接,所述第六晶体管的栅极与第一端耦接,第二端耦接于所述第四节点; [0011] The first terminal of the sixth transistor through the first capacitor and the first clock signal input terminal coupled to the gate of the sixth transistor coupled to the first end, a second terminal coupled to the fourth node;

[0012] 所述第七晶体管的栅极耦接所述第四节点,第二端耦接所述第六晶体管的第一端,第一端耦接所述第二电平信号输入端; [0012] The gate of the seventh transistor is coupled to the fourth node, a second terminal coupled to the first terminal of the sixth transistor, a first terminal coupled to the second level signal input terminal;

[0013] 所述第八晶体管的栅极耦接所述第四节点,第一端耦接于所述第一电平信号输入端,第二端親接于第三节点; A gate [0013] of the eighth transistor is coupled to the fourth node, a first terminal coupled to the first level signal input terminal, a second terminal connected to a third parent node;

[0014] 所述第九晶体管的栅极耦接所述第二节点,第一端耦接于所述第二电平信号输入端,第二端耦接于所述第三节点; A gate [0014] of the ninth transistor is coupled to the second node, a first terminal coupled to the second level signal input terminal, a second terminal coupled to said third node;

[0015] 所述第十晶体管的栅极耦接所述第三节点,第一端耦接所述第一电平信号输入端,第二端耦接所述发光控制电路的输出端; [0015] The gate of the tenth transistor is coupled to the third node, a first terminal coupled to the first level signal input terminal, a second terminal coupled to the output of the control circuit of light emission;

[0016] 所述第十一晶体管的栅极耦接于所述第四节点,第一端耦接所述第二电平信号输入端,第二端耦接所述发光控制电路的输出端; A gate [0016] of the eleventh transistor is coupled to the fourth node, a first terminal coupled to the second level signal input terminal, a second terminal coupled to the output of the control circuit of light emission;

[0017] 所述第二电容耦接于所述第四节点和所述发光控制电路输出端之间。 [0017] The second capacitor coupled between the fourth node and the emission output of the control circuit.

[0018] 另一方面,本发明另一优选实施例还提供一种显示面板,包括N级上述发光控制电路。 [0018] On the other hand, another preferred embodiment of the present invention further provides a display panel including N stages the light emission control circuit.

[0019] 进一步的,所述第一级发光控制电路的起始信号输入端输入起始信号,所述第I级发光控制电路的起始信号输入端输入上一级发光控制电路的输出信号,1 = 2,3,…N。 [0019] Further, the first light emission start signal input terminal stage control start signal input circuit, a Class I emission start signal input of the control circuit on one input the output signal of the light emission control circuit, 1 = 2,3, ... N.

[0020] 另一方面,本发明优选实施例还提供一种显示装置,包括上述显示面板。 [0020] On the other hand, preferred embodiments of the present invention further provides a display apparatus comprising the display panel.

[0021] 本发明优选实施例提供的驱动电路及发光控制电路、显示面板、显示装置至少具有的有益效果:多级发光控制电路相互级联,只需一个高电平的触发信号;发光控制电路结构简单且输出的信号不会抖动,在工作期间不会出现输出悬空,使得输出更加稳定,提高显示效果。 [0021] The embodiment of the present invention is preferably provided in a driving circuit and a light emitting control circuit, a display panel, the display device has an advantageous effect of at least: a multi-stage cascade each light emission control circuit, a high-level trigger signal only; light emission control circuit a simple structure and does not dither signal output, the output does not occur during operation of floating, so that more stable output and improve the display effect.

附图说明 BRIEF DESCRIPTION

[0022]图1是现有技术的发光控制电路原理图; [0022] FIG. 1 is a schematic diagram of a light emitting control circuit of the prior art;

[0023]图2是图1中发光控制电路的各个信号时序图; [0023] Figure 2 is a timing chart of each signal of the light emission control circuit 1;

[0024]图3是本发明优选实施例一提供的驱动电路原理图; [0024] FIG. 3 is a schematic diagram of a driving circuit according to a first preferred embodiment of the present invention;

[0025]图4是图3中驱动电路的各个信号时序图; [0025] FIG. 3 FIG. 4 is a timing chart of each signal driving circuit;

[0026]图5a〜图5e是图4中驱动电路各个工作阶段对应的电路图; [0026] Figure 5e is 5a~ FIG various working phases corresponding to FIG. 4 a circuit diagram of a driving circuit;

[0027]图6是本发明优选实施例二提供的发光控制电路原理图; [0027] FIG. 6 is a light emitting control circuit according to the second principle of the present invention, FIG preferred embodiment;

[0028]图7是图6中发光控制电路的工作时序图; [0028] FIG. 7 is an emission control circuit in a timing chart of operation;

[0029]图8a〜图8h是图6中发光控制电路各个工作阶段对应的电路图; [0029] FIG 8a~ Fig 8h is the various working stages of FIG. 6 corresponding to the light emission control circuit diagram;

[0030]图9是本发明优选实施例三提供的显示面板截面示意图; [0030] FIG. 9 is a display panel according to a third cross-sectional schematic of a preferred embodiment of the present invention;

[0031]图10是图9中第二基板的结构示意图; [0031] FIG. 10 is a schematic view of a second substrate in FIG 9;

[0032]图11是图10中发射驱动电路的连接示意图; [0032] FIG. 11 is a connection diagram in FIG emission driving circuit 10;

[0033]图12是本发明优选实施例四提供的显示装置结构示意图。 [0033] FIG. 12 is a diagram showing the structure of a display device according to a fourth preferred embodiment of the present invention.

具体实施方式 Detailed ways

[0034]下面结合附图和实施例对本发明作进一步的详细说明。 Drawings and embodiments of the present invention will be further described in detail [0034] below in conjunction. 可以理解的是,此处所描述的具体实施例仅仅用于解释本发明,而非对本发明的限定。 It will be appreciated that the specific embodiments described herein are merely to illustrate the invention, not limitation of the invention. 另外还需要说明的是,为了便于描述,附图中仅示出了与本发明相关的部分而非全部。 Also to be noted also that, for convenience of description, the accompanying drawings illustrate only the part related to the present invention, but not all.

[0035]如背景技术所述,为像素驱动电路提供驱动信号的电路设计已是OLED显示的重要课题,像素驱动电路一般需要栅极驱动信号SCAN和发光控制信号Emit,一行的OLED像素可能需要多个的栅极驱动信号SCAN来驱动。 [0035] As described in the background, providing a driving signal to the pixel driving circuit has the circuit design is an important subject OLED display, the pixel driving circuits are generally required gate drive signals SCAN and the Emit light emission control signal, an OLED pixel row may require multiple a gate driving signal to drive the SCAN. 通常,发光控制信号由发光驱动电路产生。 Typically, the emission control signal generated by the light emission drive circuit. OLED显示面板有N行像素,则一般对应有N级发光驱动电路,一级发光驱动电路通常包括移位寄存电路VSR和反相器,移位寄存电路的输出端连接至反相器的输入端。 OLED display panel has N rows of pixels, there are N stages corresponding to the general light emission drive circuit, a light emission drive circuit typically includes an output shift register VSR and an inverter circuit, a shift register circuit is connected to the input terminal of inverter . 而每级发光驱动电路的移位寄存电路VSR以级联方式连接,如此逐级产生相应的发光控制信号Emit。 Each stage is displaced light emission drive circuit VSR register circuit are connected in cascade, thus progressively generates a corresponding light emission control signal Emit. 常用的像素驱动电路是PMOS结构,发光控制信号Emit在栅极驱动信号SCAN工作时应该为高电平,因此,发光驱动电路需输入低电平,然后经移位寄存电路VSR传输至反相器,也即,传统的发光驱动电路输入的是低电平信号。 Common pixel drive circuit is a PMOS structure, when the light emission control signal Emit gate drive signal SCAN working should be high so that the light emission drive circuit for an input low, then the transmission through the shift register circuit VSR to the inverter , i.e., the conventional light emission drive circuit signal input is low.

[0036] 上述发光驱动电路的结构过于复杂,因而相继出现了替代技术,如图1所示,是三星公司设计的发光控制电路的电路图(专利公开号:US20140055444A1),其采用10T3C的结构,整个发光控制电路不是采用移位寄存电路和反相器的结构,而是直接由10T3C的结构生成发光控制信号Emi t。 [0036] The driving circuit of the light emitting structure is too complicated, and therefore alternative technologies have emerged, as shown in FIG. 1 is a circuit diagram of a Samsung emission control circuit design (Patent Publication Number: US20140055444A1), which employs 10T3C structure, the whole light emission control circuit instead of using the circuit configuration of the shift register and an inverter, but is generated directly by the structure of the light emitting control signal 10T3C Emi t. 图2是图1中发光控制电路的工作时序图,由图2可知,此发光控制电路输入的是高电平起始信号,但其在t4-t5工作时段中,由于NI点的电位为高电平,MlO管关闭,因此输出端会出现悬空状态,也即输出信号处于不稳定状态。 FIG 2 is an operation timing diagram of the light emitting control circuit, can be seen from FIG 2, this light emission control circuit start signal input is high, but its work period t4-t5, since the potential is high NI point level, M1O tube closed, the output terminal will be suspended state, i.e., the output signal is in an unstable state. 另外,此发光控制电路输出时,由于NI点和N3点的电位没有保持功能,也会导致输出抖动现象发生。 Further, this light emission control circuit outputs, since the NI point and the potential of the point N3 no holding function, also causes the output jitter phenomenon. 因此上述输出悬空及输出抖动,会导致发光控制电路在工作过程中输出信号不稳定,影响面板的显示效果。 Thus the output becomes vacant and output jitter will cause the control circuit outputs a light emitting signal is unstable during operation, influence the effect of the display panel.

[0037] 实施例一 [0037] Example a

[0038] 本发明优选实施例一提供一种驱动电路,如图3所示,包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4,其中,第一晶体管Ml的栅极耦接用于接收起始信号的起始信号输入端IN,第一端耦接用于接收第二时钟信号的第二时钟信号输入端XCK,第二端耦接第一节点NI;第二晶体管M2的栅极耦接第二时钟信号输入端XCK,第一端耦接用于接收第二电平信号的第二电平信号输入端VGL,第二端耦接第一节点NI;第三晶体管M3的栅极耦接第一节点NI,第一端耦接用于接收第一时钟信号的第一时钟信号输入端CK,第二端耦接第二节点N2;第四晶体管M4的栅极耦接起始信号输入端IN,第一端耦接用于接收第一电平信号的第一电平信号输入端VGH,第二端耦接所述第二节点N2。 [0038] The preferred embodiment of the present invention, one embodiment provides a driving circuit, as shown, includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, which gate of the first transistor Ml 3 is coupled for receiving a start signal of the start signal input terminal iN, a first terminal coupled to a second clock signal input terminal receiving a second clock signal XCK, a second terminal coupled to the NI first node; a second gate of the transistor M2 is coupled to the second clock signal input terminal XCK, a first terminal coupled to the second level receives a second signal input terminal VGL level signal, a second terminal coupled to the first node the NI; third the gate of transistor M3 is coupled to node NI, a first terminal coupled to a first clock signal input terminal for receiving a first clock signal CK, a second terminal coupled to the second node N2 of; a gate of the fourth transistor M4 coupled to the start signal input terminal iN, a first terminal coupled to a first level of a signal input for receiving a first signal level VGH, a second terminal coupled to the second node N2.

[0039] 进一步的,实施例一提供的驱动电路中第一晶体管Ml、第二晶体管M2、第三晶体管M3和第四晶体管M4可以是PMOS管,也可以是NMOS管。 [0039] Further, the driving circuit according to a first embodiment of the first transistor Ml, the second transistor M2, a third transistor M3 and fourth transistor M4 may be PMOS transistor, it may be a NMOS transistor. 优选的,其中第一时钟信号输入端CK输入的第一时钟信号和第二时钟信号输入端XCK输入的第二时钟信号是脉冲信号,相位相差180度;当所述的第一晶体管Ml、第二晶体管M2、第三晶体管M3和第四晶体管M4均为PMOS管时,第一电平信号输入端VGH输入的第一电平信号为恒定的高电平,第二电平信号输入端VGL输入的第二电平信号为恒定的低电平;当第一晶体管Ml、第二晶体管M2、第三晶体管M3和第四晶体管M4均为WOS管时,第一电平信号输入端VGH输入的第一电平信号为恒定的低电平,第二电平信号输入端VGL输入的第二电平信号为恒定的高电平。 Preferably, wherein the second clock signal of a first clock signal input terminal CK of the first clock signal input and a second clock signal input terminal XCK is input pulse signal, the phase difference of 180 degrees; of Ml when said first transistor, a first second transistor M2, a third transistor M3 and fourth transistor M4 are both PMOS transistor, a first level of a first signal level of the input signal input terminal VGH constant high level, a second level of the input signal input terminal VGL a second constant level signal is low; the first transistor when the first of Ml, a second transistor M2, a third transistor M3 and fourth transistor M4 are both WOS tube, a first level of the input signal input terminal VGH a constant level signal is low level, the second level of the second signal level signal is input to input terminal VGL constant high level. 实际使用时,起始信号、输出信号、第一时钟信号和第二时钟信号的高电平值可以选10V,低电平值可以选-5V,也可以根据晶体管的设计类型和实际需要进行设定。 Actual use, high-level value of the start signal, the output signal of the first clock signal and second clock signals may be selected 10V, -5 V may be selected from a low value, can also be provided according to actual needs and design type transistor set. 需要说明书的是,对于PMOS来说,晶体管的第一端指的是源极,第二端指的是漏极。 Specification requires that, for a PMOS transistor first terminal is a source electrode means, the second means is a drain terminal. 而对于NMOS管来说,晶体管的第一端指的是漏极,第二端指的是源极。 For NMOS transistors, the first transistor is a drain terminal means, the second means is a source terminal.

[0040]图4所示为图3中驱动电路的一种优选工作时序图,其对应的是第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4均为PMOS管,第一电平信号输入端VGH输入的第一电平信号为恒定的高电平,第二电平信号输入端VGL输入的第二电平信号为恒定的低电平。 [0040] Figure 4 is a driving circuit in FIG. 3 a preferred operation timing diagram, which corresponds to the first transistor M1, a second transistor M2, a third transistor M3 and fourth transistor M4 are PMOS transistors, the first a first level signal power level input signal input terminal VGH constant high level, the second level of the second signal level signal is input to input terminal VGL constant low level.

[0041] 实施例一提供的驱动电路至少包括五个工作时段,图4中的Tl〜T5时刻对应实施例一驱动电路的五个工作阶段,分别如图5a〜5e所示。 [0041] The driving circuit according to a first embodiment includes at least five working periods, Tl~T5 time in FIG. 4 corresponds to five sessions a driving circuit according to embodiments shown in Figures 5a~5e FIG. 下面结合图4和图5a〜5e详细说明实施例一驱动电路的工作过程: The following working process of a driving circuit of the embodiment described in detail in conjunction with FIG. 4 and FIG 5a~5e:

[0042]图5a为实施例一中驱动电路工作的第一阶段电路图,即图4中Tl时段,起始信号IN输入高电平,控制第一晶体管Ml和第四晶体管M4关闭,第一时钟信号CK输入高电平,第二时钟信号XCK输入低电平,控制第二晶体管M2打开,第二电平信号VGL经第二晶体管M2传输至第一节点NI,使得第一节点的电位为低电平,然后控制第三晶体管M3打开,第三晶体管M3传输第一时钟信号CK至第二节点N2,使得第二节点的电位为高电平。 [0042] Figure 5a is a first embodiment of a circuit diagram of a driving phase, i.e., the period Tl in FIG. 4, the start signal IN is input a high level, the first control transistor Ml and turn off the fourth transistor M4, a first clock CK inputs a high level signal, a second input clock signal XCK low level, controls the second transistor M2 is turned on, a second level signal VGL via the second transistor M2 to the first node transmitting the NI, so that the low potential of the first node level, and controlling the third transistor M3 is turned on, the third transistor M3 transmits the first clock signal CK to the second node N2, such that a high level electric potential of the second node.

[0043]图5b为实施例一中驱动电路工作的第二阶段电路图,即图4中T2时段,起始信号IN输入高电平,控制第一晶体管Ml和第四晶体管M4关闭,第一时钟信号CK输入高电平,第二时钟信号XCK发生跳变,由低电平变为高电平,控制第二晶体管M2关闭,第一节点NI保持前一阶段电位,也即第一节点NI电位保持低电平,控制第三晶体管M3打开,第三晶体管M3传输第一时钟信号CK至第二节点N2,使得第二节点的电位为高电平;此阶段中主要由第三晶体管M3的寄生电容保持第一节点NI的电位,因此第三晶体管M3的宽长比要设计足够的大。 [0043] Figure 5b is a second embodiment of a circuit diagram of a driving circuit of the stage, i.e., a period T2 in FIG. 4, the start signal IN is input a high level, the first control transistor Ml and turn off the fourth transistor M4, a first clock high level input signal CK, a second clock signal XCK transition occurs from low to high, close control of the second transistor M2, the potential of the first node NI holding the previous stage, i.e., the potential of the first node NI remains low, the control to open the third transistor M3, the third transistor M3 transmits the first clock signal CK to the second node N2, such that a high level electric potential of the second node; this stage is mainly composed of a third parasitic transistor M3 NI capacitor holding the potential of the first node, the third transistor M3 is designed to be longer than a width large enough.

[0044]图5c为实施例一中驱动电路工作的第三阶段电路图,即图4中T3时段,起始信号IN输入高电平,控制第一晶体管Ml和第四晶体管M4关闭,第二时钟信号XCK输入高电平,控制第二晶体管M2关闭,第一节点NI保持前一阶段低电位,控制第三晶体管M3打开,第一时钟信号CK发生跳变,由高电平变为低电平,并经第三晶体管M3传输至第二节点N2,使得第二节点N2的电位为低电平。 [0044] FIG 5c a third stage is a circuit diagram of the drive circuit of the embodiment, i.e., a period T3 in FIG. 4, the start signal IN is input a high level, the first control transistor Ml and the fourth transistor M4 is turned off, the second clock XCK high level input signal, the control to close the second transistor M2, the previous stage node NI kept low, controlling the third transistor M3 turned on, the first clock signal CK transition occurs from high to low , and transmitted via the third transistor M3 to the second node N2, so that the potential of the second node N2 is low.

[0045]图5d为实施例一中驱动电路工作的第四阶段电路图,即图4中T4时段,起始信号IN输入高电平,控制第一晶体管Ml和第四晶体管M4关闭,第二时钟信号XCK输入高电平,控制第二晶体管M2关闭,第一节点NI保持前一阶段低电位,控制第三晶体管M3打开,第一时钟信号CK发生跳变,由低电平变为高电平,并经第三晶体管M3传输至第二节点N2,使得第二节点N2的电位为高电平。 [0045] Figure 5d is a fourth embodiment of a phase diagram of a drive circuit, i.e., the period T4 in FIG. 4, the start signal IN is input a high level, the first control transistor Ml and the fourth transistor M4 is turned off, the second clock XCK high level input signal, the control to close the second transistor M2, the previous stage node NI kept low, controlling the third transistor M3 turned on, the first clock signal CK transition occurs from low to high , and transmitted via the third transistor M3 to the second node N2, so that the potential of the second node N2 is high.

[0046]图5e为实施例一中驱动电路工作的第五阶段电路图,即图4中T5时段,第一时钟信号CK输入高电平,起始信号IN发生跳变,由高电平变为低电平,控制第一晶体管Ml和第四晶体管M4打开,第二时钟信号XCK发生跳变,由高电平变为低电平,控制第二晶体管M2打开,第二电平信号VGL经所述第二晶体管M2传输至第一节点NI,第一晶体管Ml传输低电平的第二时钟信号XCK至第一节点,使得第一节点NI电位为低电平,控制第三晶体管M3打开,第三晶体管M3传输高电平的第一时钟信号CK至第二节点N2,第四晶体管M4传输第一电平信号VGH至第二节点N2,使得第二节点N2电位为高电平。 [0046] Figure 5e is a circuit diagram of a fifth embodiment of a stage driving circuit, i.e., time T5 in FIG. 4, the first clock signal CK inputs a high level, the start signal IN transitions occur, changes from the high level low level, the first control transistor Ml and the fourth transistor M4 is turned on, the second clock signal XCK transition occurs from high to low, the control to open the second transistor M2, a second signal level by the VGL said second transistor M2 is transmitted to the node NI, the low level of the first transistor Ml transmitting the second clock signal XCK to the first node, so that the potential of the first node NI is low, the control to open the third transistor M3, the first the first high level clock signal CK is transmitted three-transistor M3 to the second node N2, the fourth transistor M4 VGH level signal transmission of the first to the second node N2, such that a high level potential of the second node N2.

[0047] 实施例二 [0047] Second Embodiment

[0048] 本发明优选实施例二提供了一种发光控制电路,如图6所示,包括输入单元10和反向单元20,其中,输入单元10包括如实施例一所描述的驱动电路,也即包括第一晶体管Ml、第二晶体管M2、第三晶体管M3和第四晶体管M4,而反向单元20包括第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管MlO、第^^一四晶体管Ml 1、第一电容Cl和第二电容C2,也即整个发光驱动电路包括第一晶体管Ml、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9第十晶体管Ml O、第^^一四晶体管Ml I和第一电容Cl、第二电容C2。 [0048] according to a second preferred embodiment of the present invention there is provided a light emission control circuit, shown in Figure 6, includes an input unit 10 and reverse unit 20, wherein a driving circuit 10 comprises an input unit as described in the embodiment, also i.e., comprising a first transistor Ml, a second transistor M2, a third transistor M3 and a fourth transistor M4, while the reverse unit 20 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, the eighth transistor M8, a ninth transistor M9, a tenth transistor MlO, ^^ fourteen first transistor Ml 1, a first capacitor Cl and second capacitor C2, i.e. the entire light emission drive circuit includes a first transistor Ml, a second transistor M2, a third transistor M3, a first four transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, the eighth transistor M8, a ninth transistor M9 tenth transistor Ml O, the first transistor Ml I ^^ fourteen and a first capacitor Cl, a second capacitor C2.

[0049]其中: [0049] wherein:

[0050] 第一晶体管Ml的栅极耦接用于接收起始信号的起始信号输入端IN,第一端耦接用于接收第二时钟信号的第二时钟信号输入端XCK,第二端耦接第一节点NI; [0050] The gate of the first transistor Ml is coupled to the input terminal IN receives a start signal of the start signal, a first terminal of the second clock signal input terminal connected for receiving a second clock signal XCK, a second end a first node coupled to the NI;

[0051] 第二晶体管M2的栅极耦接第二时钟信号输入端XCK,第一端耦接用于接收第二电平信号的第二电平信号输入端VGL,第二端耦接第一节点NI; [0051] The gate electrode coupled to the second clock signal input terminal of the second transistor M2 XCK, a first terminal coupled for receiving the second level signal of a second level of the signal input terminal VGL, a second terminal coupled to the first node NI;

[0052] 第三晶体管M3的栅极耦接第一节点NI,第一端耦接用于接收第一时钟信号的第一时钟信号输入端CK,第二端耦接第二节点N2; A gate [0052] The third transistor M3 is coupled to the node NI, a first terminal coupled to a first clock signal input terminal for receiving a first clock signal CK, a second terminal coupled to the second node N2 of;

[0053] 第四晶体管M4的栅极耦接起始信号输入端IN,第一端耦接用于接收第一电平信号的第一电平信号输入端VGH,第二端耦接所述第二节点N2; A gate [0053] The fourth transistor M4 is coupled to the start signal input terminal IN, a first terminal coupled to a first level of a first signal input terminal VGH reception level of a signal, a second terminal coupled to the first N2 of second node;

[0054] 第五晶体管M5的栅极耦接第二节点N2,第一端耦接第一电平信号输入端VGH,第二端耦接第四节点N4; [0054] The gate of the fifth transistor M5 is coupled to the second node N2, a first terminal coupled to a first input signal level VGH, a second terminal coupled to the fourth node N4;

[0055] 第六晶体管M6的第一端通过第一电容Cl与第一时钟信号输入端CK耦接,第六晶体管M6的栅极与其第一端耦接,使得第六晶体管M6等效于二极管,只能单向导通,第六晶体管M6的第二端耦接于第四节点N4; [0055] The first terminal of the sixth transistor M6 CK of the first capacitor Cl by a first clock signal input terminal coupled to the gate of the sixth transistor M6 is coupled to the first end thereof, such that the sixth transistor M6 is equivalent to a diode only unidirectional conductive, coupled to a second terminal of the sixth transistor M6 is connected to the fourth node N4;

[0056] 第七晶体管M7的栅极耦接第四节点N4,第二端耦接第六晶体管M6的第一端,第一端耦接用于接收第二电平信号的第二电平信号输入端VGL; [0056] The gate of the seventh transistor M7 is coupled to the fourth node N4, a second terminal coupled to a first terminal of the sixth transistor M6, a first terminal coupled for receiving a second signal level of a second level signal VGL input terminal;

[0057] 第八晶体管M8的栅极耦接于第四节点N4,第一端耦接于所述第一电平信号输入端VGH,第二端耦接于所述第三节点N3; A gate [0057] the eighth transistor M8 is coupled to the fourth node N4, a first terminal coupled to said first input signal level VGH, a second terminal coupled to said third node N3;

[0058] 第九晶体管M9的栅极耦接第二节点N2,第一端耦接于第二电平信号输入端VGL,第二端耦接于第三节点N3; A gate [0058] the ninth transistor M9 is coupled to the second node N2, a first terminal coupled to the second level signal input terminal VGL, a second terminal coupled to the third node N3;

[0059] 第十晶体管MlO的栅极耦接第三节点N3,第一端耦接第一电平信号输入端VGH,第二端耦接发光控制电路的输出端OUT; [0059] The gate of the tenth transistor MlO is coupled to the third node N3, a first terminal coupled to a first input signal level VGH, a second terminal coupled to the output terminal OUT of the light emitting control circuit;

[0060] 第十一晶体管Mll的栅极耦接于第四节点N4,第一端耦接第二电平信号输入端VGL,第二端耦接发光控制电路的输出端OUT; [0060] Mll gate of the eleventh transistor is coupled to the fourth node N4, a first terminal coupled to the second input signal level VGL, a second terminal coupled to the output terminal OUT of the light emitting control circuit;

[0061] 第二电容C2耦接于第四节点N4和发光控制电路输出端OUT之间,用于保持输出端OUT的输出信号稳定。 [0061] The second capacitor C2 is coupled between the fourth node N4 and the light emission control circuit output OUT, an output signal of the output terminal OUT is stably maintained.

[0062] 进一步的,实施例一提供的发光控制电路中第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管MlO、第^^一晶体管Ml I可以是PMOS管,也可以是NMOS管。 [0062] Further, according to a first embodiment of the light emitting control circuit, a first transistor M1, a second transistor M2, a third transistor M3, the fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M1O, ^^ a first transistor may be a PMOS transistor Ml I, may be a NMOS transistor. 优选的,其中第一时钟信号输入端CK输入的第一时钟信号和第二时钟信号输入端XCK输入的第二时钟信号是脉冲信号,相位相差180度。 Preferably, wherein the second clock signal of a first clock signal input terminal CK of the first clock signal input and a second clock signal input terminal XCK is input pulse signal, the phase difference of 180 degrees. 当第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第^^一晶体管Mll均为PMOS管时,第一电平信号输入端VGH输入的第一电平信号为恒定的高电平,第二电平信号输入端VGL输入的第二电平信号为恒定的低电平;当第一晶体管Ml、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管MlO、第^^一晶体管Ml I均为NMOS管时,第一电平信号输入端VGH输入的第一电平信号为恒定的低电平,第二电平信号输入端VGL输入的第二电平信号为恒定的高电平。 When the first transistor M1, a second transistor M2, a third transistor M3, the fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, the eighth transistor M8, a ninth transistor M9, a tenth transistor M10 , a first transistor ^^ Mll are both PMOS transistor, a first level of a first signal level of the input signal input terminal VGH constant high level, a second level of a second signal level of the input signal input terminal VGL constant low level; when the first transistor Ml, a second transistor M2, a third transistor M3, the fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, the eighth transistor M8, a ninth transistor M9, a tenth transistor M1O, a first transistor Ml I ^^ are both NMOS transistors, a first level of a first signal level of the input signal input terminal VGH constant low level, the second level signal input terminal a second input level signal VGL constant high level. 实际使用时,起始信号、第一电平信号、第二电平信号、第一时钟信号和第二时钟信号的高电平的电平值可以选10V,低电平的电平值可以选-5V,也可以根据晶体管的设计类型和实际需要进行设定。 Actual use, the high level value of the start signal, a first signal level, second level signal, the first clock signal and the second clock signal may be selected from 10V, low level values ​​may be selected from -5V, may be set according to the actual needs of the type and design of the transistor. 需要说明书的是,对于PMOS来说,晶体管的第一端指的是源极,第二端指的是漏极。 Specification requires that, for a PMOS transistor first terminal is a source electrode means, the second means is a drain terminal. 而对于NMOS管来说,晶体管的第一端指的是漏极,第二端指的是源极。 For NMOS transistors, the first transistor is a drain terminal means, the second means is a source terminal.

[0063]图7所示为图6中发光控制电路的一种优选工作时序图,其对应的是第一晶体管Ml、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管Ml O、第^^一晶体管Ml I均为PMOS管,第一电平信号输入端VGH输入的第一电平信号为恒定的高电平,第二电平信号输入端VGL输入的第二电平信号为恒定的低电平。 [0063] FIG. 7 is an operation timing diagram in a preferred emission control circuit of Figure 6, which corresponds to a first transistor of Ml, a second transistor M2, a third transistor M3, the fourth transistor M4, a fifth transistor M5 the first, sixth transistor M6, a seventh transistor M7, the eighth transistor M8, a ninth transistor M9, a tenth transistor Ml O, the first transistor Ml I ^^ are a PMOS transistor, a first level of the input signal input terminal VGH a constant level signal is high level, the second level of the second signal level signal is input to input terminal VGL constant low level.

[0064] 实施例二提供的发光控制电路至少包括八个工作时段,图7中的Tl〜T8时刻对应实施例二发光控制电路的八个工作阶段,分别如图8a〜Sh所示。 [0064] The light emission control circuit according to a second embodiment comprises at least eight working hours, in FIG. 7 Tl~T8 time correspond to eight sessions emission control circuit according to the second embodiment, respectively, as shown in FIG 8a~Sh. 下面结合图7和图8a〜Sh详细说明实施例二发光控制电路的工作过程: Below in connection with FIGS. 7 and operation will be described in detail 8a~Sh emission control circuit according to the second embodiment:

[0065]图8a为实施例二中发光控制电路工作的第一阶段电路图,即图7中Tl时段,起始信号IN输入低电平,控制第一晶体管Ml和第四晶体管M4打开,第二时钟信号XCK输入高电平,第一晶体管Ml传输第二时钟信号XCK至第一节点NI,使得第一节点NI的电位为高电平,控制第三晶体管M3关闭,第一电平信号VGH经第四晶体管M4传输至第二节点N2,使得第二节点N2的电位为高电平,控制第五晶体管M5和第九晶体管M9关闭;第一时钟信号CK发生跳变,由高电平变为低电平,通过第一电容Cl的自举效应,使得第六晶体管的栅极电位变低,由于第六晶体管M6以等效二极管方式连接,因此第六晶体管M6打开,并传输低电平值第四节点N4,使得第四节点N4的电位为低电平,然后控制第七晶体管M7、第八晶体管M8和第十一晶体管Mll开启,第八晶体管M8传输第一电平信号VGH至第三节点N3,使得第 [0065] Figure 8a circuit diagram showing a first stage of the control circuit for the light emitting Embodiment Example II, i.e., the period Tl of FIG. 7, the initial input signal IN is low level, the first control transistor Ml and the fourth transistor M4 is opened, the second input clock signal XCK high level, the first transistor Ml transmitting the second clock signal XCK to the first node NI, so that the potential of the first node NI is high, the control of the third transistor M3 turned off by the first level signal VGH the fourth transistor M4 is transmitted to the second node N2, so that the potential of the second node N2 is high level, the fifth transistor M5 controls the ninth transistor M9 and off; a first clock signal CK transition occurs from the high level to low level by the bootstrap effect of the first capacitor Cl, so that the gate potential of the sixth transistor becomes low, since the sixth transistor M6 is diode connected in an equivalent manner, thus opening the sixth transistor M6, and transmits a low value the fourth node N4, so that the potential of the fourth node N4 is low, then the seventh transistor M7 controls, eighth and eleventh transistors Mll transistor M8 is turned on, the eighth transistor M8 transmitted first to the third level signal VGH node N3, so that the first 节点N3的电位变为高电平,控制第十晶体管MlO关闭,第十一晶体管Mll传输第二电平信号VGL至发光控制电路输出端OUT,作为该阶段的输出信号。 Potential of the node N3 becomes a high level, the tenth transistor MlO off control, the eleventh transistor Mll second level signal transmitted to the light emission control circuit VGL output terminal OUT, as the phase of the output signal.

[0066]图8b为实施例二中发光控制电路工作的第二阶段电路图,即图7中T2时段,起始信号IN输入低电平,控制第一晶体管Ml和第四晶体管M4打开,第一时钟信号CK发生跳变,由低电平变为高电平,第二时钟信号XCK输入高电平,第一晶体管Ml传输第二时钟信号XCK至第一节点NI,使得第一节点NI的电位为高电平,控制第三晶体管M3关闭,第一电平信号VGH经第四晶体管M4传输至第二节点N2,使得第二节点N2的电位为高电平,控制第五晶体管M5和第九晶体管M9关闭;第四节点N4电位由第二电容C2保持前一阶段的电位,也即保持低电平,控制第七晶体管M7、第八晶体管M8和第^^一晶体管Ml I开启,第七晶体管M7传输恒定低电平的第二电平信号VGL至第六晶体管M6的栅极,虽然第一时钟信号CK的跳变以及第一电容Cl的耦合效应,对第六晶体管M6的栅极电位有短暂的拉高作用,但第六晶 [0066] FIG 8b is a circuit diagram showing a second stage in the light emission control circuit according to a second embodiment of the work, i.e., a period T2 in FIG. 7, the initial input signal IN is low level, the first control transistor Ml and the fourth transistor M4 is opened, the first a clock signal CK transition occurs from low to high, the second input clock signal XCK high level, the first transistor Ml transmitting the second clock signal XCK to the first node NI, so that the potential of the first node NI is high, the control of the third transistor M3 turned off, the first level signal VGH through the fourth transistor M4 is transmitted to the second node N2, so that the potential of the second node N2 is high level, the fifth transistor M5 and a ninth control transistor M9 is turned off; the potential of the fourth node N4 by the second potential holding capacitor C2 previous stage, i.e. to maintain a low level, the control of the seventh transistor M7, the eighth transistor M8 and a first transistor Ml I ^^ turned on, the seventh the gate of transistor M7 second transmission constant low level signal VGL to the sixth transistor M6, although the first clock signal CK and a transition of the coupling effect of the first capacitor Cl, the gate potential of the sixth transistor M6 there are short-term effect pulled, but the sixth crystal 管M6的栅极会变为低电平,因此第六晶体管M6打开,第八晶体管M8传输第一电平信号VGH至第三节点N3,使得第三节点N3的电位变为高电平,控制第十晶体管MlO关闭,第^^一晶体管Ml I传输第二电平信号VGL至发光控制电路输出端0UT,作为该阶段的输出信号。 The gate of transistor M6 goes low, thus opening the sixth transistor M6, an eighth transistor M8 transmitting a first signal level VGH to the third node N3, so that the potential of the third node N3 becomes a high level, the control Close tenth transistor MlO, Ml I ^^ a first transfer transistor to a second level signal VGL output terminal of the light emission control circuit 0UT, as the phase of the output signal.

[0067]图8c为实施例二中发光控制电路工作的第三阶段电路图,即图7中T3时段,起始信号IN发生跳变,由低电平变为高电平,控制第一晶体管Ml和第四晶体管M4关闭,第一时钟信号CK输入高电平,第二时钟信号XCK发生跳变,由高电平变为低电平,控制第二晶体管M2打开,第二电平信号VGL经第二晶体管M2传输至第一节点NI,使得第一节点NI的电位为低电平,控制第三晶体管M3打开,第一时钟信号CK经第三晶体管M3传输至第二节点N2,使得第二节点N2的电位为高电平,控制第五晶体管M5和第九晶体管M9关闭;第四节点N4的电位由第二电容C2保持前一阶段的电位,也即保持低电平,控制第七晶体管M7、第八晶体管M8和第十一晶体管Ml I开启,第七晶体管M7传输第二电平信号VGL至第六晶体管M6的栅极,以使得第六晶体管M6打开,第八晶体管M8传输第一电平信号VGH至第三节点N3,使 [0067] FIG. 8c two light emitting third stage is a circuit diagram of a control circuit of the embodiment, i.e., a period T3 in FIG. 7, the start signal IN transitions occur, from low to high, the first control transistor Ml and a fourth transistor M4 is turned off, the high level of the first input clock signal CK, a second clock signal XCK transition occurs from high to low, the control to open the second transistor M2, via the second level signal VGL the second transistor M2 is transmitted to the node NI, NI so that the potential of the first node is low, the control of the third transistor M3 turned on, the first clock signal CK transmitted through the third transistor M3 to the second node N2, such that a second potential of the node N2 is at a high level, and controlling the fifth transistor M5 turn off the ninth transistor M9; the fourth node N4 which a potential of a previous stage holding the second capacitor C2, i.e. to maintain a low level, the seventh control transistor M7, the eighth transistor M8 is turned on, and the eleventh transistor Ml I, a second transmission gate of the seventh transistor M7 level signal VGL to the sixth transistor M6, so that the sixth transistor M6 is turned on, the eighth transistor M8 first transmission level signal VGH to the third node N3, so that 得第三节点N3的电位变为高电平,控制第十晶体管MlO关闭,第十一晶体管Mll传输第二电平信号VGL至发光控制电路输出端0UT,作为该阶段的输出信号。 Have the potential of the third node N3 becomes a high level, the tenth transistor MlO off control, the eleventh transistor Mll second level signal transmitted to the light emission control circuit VGL output terminal 0UT, as the phase of the output signal.

[0068]图8d为实施例二中发光控制电路工作的第四阶段电路图,即图7中T4时段,起始信号IN输入高电平,控制第一晶体管Ml和第四晶体管M4关闭,第一时钟信号CK输入高电平,第二时钟信号XCK发生跳变,由低电平变为高电平,控制第二晶体管M2关闭,第一节点NI保持前一阶段电位,也即保持低电平,控制第三晶体管M3打开,第一时钟信号CK经第三晶体管M3传输至第二节点N2,使得第二节点N2的电位为高电平,控制第五晶体管M5和第九晶体管M9关闭;第四节点N4的电位由第二电容C2保持前一阶段的电位,也即保持低电平,控制第七晶体管M7、第八晶体管M8和第^^一晶体管Mll开启,第七晶体管M7传输第二电平信号VGL至第六晶体管M6的栅极,以使得第六晶体管M6打开,第八晶体管M8传输第一电平信号VGH至第三节点N3,使得第三节点N3的电位变为高电平,控制第十晶体管MlO关闭 [0068] FIG. 8d is a circuit diagram showing a fourth stage in emission control according to the second embodiment of the circuit, i.e., the period T4 in FIG. 7, the initial input signal IN is high level, the first control transistor Ml and the fourth transistor M4 is turned off, the first high input clock signal CK, a second clock signal XCK transition occurs from low to high, close control of the second transistor M2, the potential of the first node NI holding the previous stage, i.e., remains low controlling the third transistor M3 turned on, the first clock signal CK transmitted through the third transistor M3 to the second node N2, so that the potential of the second node N2 is high level, the fifth transistor M5 controls the ninth transistor M9 and closed; first the potential of the node N4 is held by four of the second capacitor C2, the potential of the previous stage, i.e. to maintain a low level, the seventh transistor M7 control, the eighth transistor M8 and Mll ^^ a transistor is turned on, the seventh transistor M7 second transmission level signal to the gate of the sixth transistor M6 VGL, is opened so that the sixth transistor M6, an eighth transistor M8 transmitting a first signal level VGH to the third node N3, so that the potential of the third node N3 becomes a high level , the control to close the tenth transistor MlO 第^^一晶体管Ml I传输第二电平信号VGL至发光控制电路输出端0UT,作为该阶段的输出信号。 Ml I ^^ a first transfer transistor to a second level signal VGL output terminal of the light emission control circuit 0UT, as the phase of the output signal.

[0069]图8e为实施例二中发光控制电路工作的第五阶段电路图,即图7中T5时段,起始信号IN输入高电平,控制第一晶体管Ml和第四晶体管M4关闭,第二时钟信号XCK输入高电平,控制第二晶体管M2关闭,第一节点NI保持前一阶段电位,也即保持低电平,控制第三晶体管M3打开,第一时钟信号CK发生跳变,由高电平变为低电平,第一时钟信号CK经第三晶体管M3传输至第二节点N2,使得第二节点N2的电位为低电平,控制第五晶体管M5和第九晶体管M9打开,第一电平信号VGH经第五晶体管M5传输至第四节点N4,使得第四节点N4的电位变为高电平,控制控制第七晶体管M7、第八晶体管M8和第十一晶体管Mll关闭;第二电平信号经第九晶体管M9传输至第三节点N3,使得第三节点N3的电位变为低电平,控制第十晶体管Ml O打开,第一电平信号VGH经第十晶体管MlO传输至发光控制电路输出端 [0069] FIG. 8e fifth stage is a circuit diagram of a control circuit according to a second embodiment of the light-emitting, i.e. the period T5 in FIG. 7, the initial input signal IN is high level, the first control transistor Ml and the fourth transistor M4 is turned off, the second high input clock signal XCK, controls the second transistor M2 is turned off, the potential of the first node NI holding the previous stage, i.e. to maintain a low level, controlling the third transistor M3 turned on, the first clock signal CK transition occurs, a high level to a low level, the first clock signal CK transmitted through the third transistor M3 to the second node N2, so that the potential of the second node N2 is low, the fifth transistor M5 and the control of the ninth transistor M9 is opened, the a level signal VGH through the fifth transistor M5 is transmitted to the fourth node N4, so that the potential of the fourth node N4 becomes a high level, the seventh control transistor M7, and the eighth transistor M8 turn off the eleventh transistor Mll; first a two-level signal of the ninth transistor M9 is transmitted to the third node N3, so that the potential of the third node N3 goes low, the tenth transistor Ml O control opening, a first level signal VGH to transmit via the tenth transistor MlO The light emission control circuit output 作为该阶段的输出信号。 As an output signal of the phase.

[0070]图8f为实施例二中发光控制电路工作的第六阶段电路图,即图7中T6时段,起始信号IN输入高电平,控制第一晶体管Ml和第四晶体管M4关闭,第二时钟信号XCK输入高电平,控制第二晶体管M2关闭,第一节点NI保持前一阶段电位,也即保持低电平,控制第三晶体管M3打开,第一时钟信号CK发生跳变,由低电平变为高电平,第一时钟信号CK经第三晶体管M3传输至第二节点N2,使得第二节点N2的电位为高电平,控制第五晶体管M5和第九晶体管M9关闭,第一时钟信号CK的跳变经过第一电容Cl的耦合,是第六晶体管M6的栅极电位拉高,第六晶体管M6关闭;第四节点N4的电位由第二电容C2保持前一阶段的电位,也即保持高电平,控制第七晶体管M7、第八晶体管M8和第^^一晶体管Mll关闭;第三节点N3保持前一阶段电位,也即第三节点N3电位保持低电平,控制第十晶体管MlO打开, [0070] FIG. 8f sixth stage is a circuit diagram of a control circuit according to a second embodiment of the light-emitting, i.e. the period T6 in Fig. 7, the initial input signal IN is high level, the first control transistor Ml and the fourth transistor M4 is turned off, the second high input clock signal XCK, controls the second transistor M2 is turned off, the potential of the first node NI holding the previous stage, i.e. to maintain a low level, controlling the third transistor M3 turned on, the first clock signal CK transition occurs from low level to a high level, the first clock signal CK transmitted through the third transistor M3 to the second node N2, so that the potential of the second node N2 is high level, and controls the fifth transistor M5 off the ninth transistor M9, a first CK is a clock signal transition is coupled through the first capacitor Cl, and the gate potential is pulled sixth transistor M6, the sixth transistor M6 is turned off; the potential of the potential of the fourth node N4 by the previous stage holding the second capacitor C2 , i.e. remains high, the control of the seventh transistor M7, and the eighth transistor M8 ^^ Mll off a transistor; previous stage holding the potential of the third node N3, i.e., the potential of the third node N3 maintains a low level, the control a tenth transistor MlO open, 一电平信号VGH经第十晶体管MlO传输至发光控制电路输出端,作为该阶段的输出信号;此阶段中主要由第十晶体管MlO的寄生电容保持第三节点N3的电位,因此第十晶体管MlO的宽长比要设计足够的大。 Level signal via a tenth transistor MlO VGH transmitted to the light emission control circuit output, as an output signal of the stage; this stage is mainly the potential of the third node N3 by the parasitic capacitance of the tenth transistor MlO is maintained, so the tenth transistor MlO width to length ratio to design large enough.

[0071]图8g为实施例二中发光控制电路工作的第七阶段电路图,即图7中T7时段,起始信号IN发生跳变,由高电平变为低电平,控制第一晶体管Ml和第四晶体管M4打开,第一时钟信号CK输入高电平,第二时钟信号XCK发生跳变,由高电平变为低电平,控制第二晶体管M2打开,第二电平信号VGL经第二晶体管M2传输至第一节点NI,使得第一节点NI的电位为低电平,控制第三晶体管M3打开,第一时钟信号CK经第三晶体管M3传输至第二节点N2,使得第二节点N2的电位为高电平,控制第五晶体管M5和第九晶体管M9关闭;第四节点N4的电位由第二电容C2保持前一阶段的电位,也即保持高电平,控制第七晶体管M7、第八晶体管M8和第十一晶体管Mll关闭;第三节点N3保持前一阶段电位,也即第三节点N3电位保持低电平,控制第十晶体管MlO打开,第一电平信号VGH经第十晶体管MlO传输至发光 [0071] FIG. 8g two light emitting circuit diagram of a seventh embodiment of a control stage operation of the circuit, i.e., the period T7 in FIG. 7, the start signal IN transitions occur, from high to low, the first control transistor Ml and the fourth transistor M4 is opened, a first clock signal CK inputs a high level, the second clock signal XCK transition occurs from high to low, the control to open the second transistor M2, via the second level signal VGL the second transistor M2 is transmitted to the node NI, NI so that the potential of the first node is low, the control of the third transistor M3 turned on, the first clock signal CK transmitted through the third transistor M3 to the second node N2, such that a second potential of the node N2 is at a high level, and controlling the fifth transistor M5 turn off the ninth transistor M9; the fourth node N4 which a potential of a previous stage holding the second capacitor C2, i.e. remains high, the seventh transistor control M7, and the eighth transistor M8 turn off the eleventh transistor Mll; previous stage holding the potential of the third node N3, i.e., the potential of the third node N3 maintains a low level, the control to open the tenth transistor MlO, through a first level signal VGH transfer to the light emitting tenth transistor MlO 制电路输出端,作为该阶段的输出信号;此阶段中主要由第十晶体管MlO的寄生电容保持第三节点N3的电位,因此第十晶体管MlO的宽长比要设计足够的大。 Circuit output terminal as an output signal of the stage; this stage is mainly by the parasitic capacitance of the tenth transistor MlO holding the potential of the third node N3, so the tenth transistor MlO width to length ratio large enough to be designed.

[0072]图8h为实施例二中发光控制电路工作的第八阶段电路图,即图7中T8时段,起始信号IN输入低电平,控制第一晶体管Ml和第四晶体管M4打开,第一时钟信号CK输入高电平,第二时钟信号XCK发生跳变,由低电平变为高电平,控制第二晶体管M2关闭,第一晶体管Ml传输第二时钟信号XCK至第一节点NI,使得第一节点NI的电位为高电平,控制第三晶体管M3关闭,第四晶体管M4传输第一电平信号VGH至第二节点N2,使得第二节点N2的电位为高电平,控制第五晶体管M5和第九晶体管M9关闭;第四节点N4的电位由第二电容C2保持前一阶段的电位,也即保持高电平,控制第七晶体管M7、第八晶体管M8和第十一晶体管Mll关闭;第三节点N3保持前一阶段电位,也即第三节点N3电位保持低电平,控制第十晶体管MlO打开,第一电平信号VGH经第十晶体管MlO传输至发光控制电路输出端,作为该阶 [0072] FIG. 8h is a circuit diagram showing the eighth stage of the light emission control circuit according to a second embodiment of the work, i.e., period T8 in FIG. 7, the initial input signal IN is low level, the first control transistor Ml and the fourth transistor M4 is opened, the first high input clock signal CK, a second clock signal XCK transition occurs from low to high, close control of the second transistor M2, a first transistor Ml transmitting the second clock signal XCK the NI to a first node, such that the potential of the first node NI is high level, control the third transistor M3 turned off, the fourth transistor M4 transmitting a first signal level VGH to the second node N2, so that the potential of the second node N2 is high level, the control section five of the ninth transistor M9 and transistor M5 off; the potential of the fourth node N4 by the second potential holding capacitor C2 previous stage, i.e. remains high, the control of the seventh transistor M7, and the eighth transistor M8 eleventh transistor Close Mll; previous stage holding the potential of the third node N3, i.e., the potential of the third node N3 maintains a low level, the control to open the tenth transistor MlO, the first level signal VGH through the tenth transistor MlO transmitted to the light emission control circuit output as the order 段的输出信号。 Output signal segment.

[0073]由以上工作过程可知,第四节点N4与发光控制电路输出端OUT存在第二电容C2,可以保持第四节点与输出端的电位稳定,不受第一时钟信号或第二时钟信号跳变的影响,使得发光控制电路输出端OUT输出的信号不会抖动。 [0073] From the above working process, the fourth node N4 circuit output terminal OUT of the presence of the second capacitor C2 and emission control, can maintain a stable electric potential of the fourth node and the output terminal, from the first clock signal or the second clock signal transitions effect, such that the light emission control signal output terminal OUT of the circuit will not jitter. 且整个工作过程中,每一阶段,输出端OUT有第十晶体管MlO传输第一电平信号VGH或者第十一晶体管Mll传输第二电平信号VGL,使得发光控制电路输出端输出的信号不会悬空,输出更加稳定。 And throughout the process, each stage, the output terminal OUT of the tenth transistor MlO has a first transmission signal level VGH or the eleventh transistor Mll transmitting a second signal level VGL, the light emitting output terminal signal control circuit is not floating, output is more stable.

[0074]需要说明的是,实施例二提供的发光控制电路中的第一晶体管〜第十一晶体管可以是NMOS管,其工作过程中,只需起始信号、第一时钟信号、第二时钟信号、第一电平信号、第二电平信号的电平值相反即可。 [0074] Incidentally, the second embodiment provides a light emitting control circuit of the first to eleventh transistor may be an NMOS transistor tube, which during operation, only a start signal, a first clock signal, a second clock signal, a first signal level, the second level value is opposite to the signal level.

[0075] 实施例三 [0075] Example three

[0076] 本发明优选实施例三提供一种显示面板,其截面图如图9所示,包括第一基板11和第二基板12,第一基板11与第二基板12相对设置,其中,所述第一基板11可以为彩膜基板、封装玻璃(Cover Glass)或者盖板玻璃(Cover Lens)等,所述第二基板12可以为像素阵列基板,如常见的OLED像素阵列基板。 Example [0076] Preferably the present invention provides a three display panel, a sectional view thereof shown in Figure 9, includes a first substrate 11 and second substrate 12, the first substrate 11 and second substrate 12 disposed opposite, wherein the said first substrate 11 may be a color filter substrate, encapsulating glass (cover glass) or the cover glass (cover Lens) and the like, the substrate 12 may be a second pixel array substrate, as is common OLED pixel array substrate.

[0077]图10是本发明实施例三的显示面板中第二基板12的结构示意图。 [0077] FIG. 10 is a block diagram of a display panel according to a third embodiment of the second substrate 12 of the present invention. 参见图10,第二基板为像素阵列基板时,可以包括:扫描驱动电路121、数据驱动电路122、发射驱动电路123、m条扫描线(S1、S2……,Sm)、1^条数据线(D1、D2……、Dk)、m条发射驱动线(El、E2、……、Em)以及多个像素124;其中,本实施例中的发射驱动电路123为包括多级如实施例二所述的发光控制电路。 Referring to FIG. 10, when the second substrate is a pixel array substrate, comprising: a scan driving circuit 121, a data driving circuit 122, the emission driver circuit 123, m scan lines (S1, S2 ......, Sm), 1 ^ of data lines (D1, D2 ......, Dk), m drive lines of emission (El, E2, ......, Em) 124 and a plurality of pixels; wherein the emission driver circuit 123 in the present embodiment is a multi-stage according to the second embodiment as the light emission control circuit.

[0078]具体地,本实施例中的扫描驱动电路121,用于向各条扫描线(S1、S2……、Sn)提供扫描信号;数据驱动电路122,用于向各条数据线(D1、D2……、Dm)提供数据信号;发射驱动电路123,用于向各条发射驱动线(E1、E2、……、Em)提供发光驱动信号,以使像素124中的像素驱动电路完成节点初始化、阈值补偿和数据写入等;像素124分别设置在扫描线和数据线交叉形成的区域中。 [0078] Specifically, the scan driving circuit 121 in the present embodiment, for the respective scan lines (S1, S2 ......, Sn) supplying a scanning signal; data driving circuit 122 for each of data lines (D1 , D2 ......, Dm) to provide data signals; emission driving circuit 123 for driving each of emission lines (E1, E2, ......, Em) to provide a light emitting driving signal to the pixel in the pixel driving circuit 124 complete node initialization, threshold compensation data writing and the like; pixels are disposed in the region of 124 scan lines and data lines formed.

[0079]图11是本发明实施例三中发射驱动电路123的连接示意图,如图11所示,发射驱动电路包括多级发光控制电路(El、E2、E3、…),每级发光控制电路的电路图如图6所示,分别连接第一时钟信号CK和第二时钟信号XCK。 [0079] FIG. 11 is a driving circuit 123 according to a third emitter is connected to a schematic embodiment of the present invention, as shown in FIG. 11, the emission driver circuit includes a plurality of light emission control circuit stage (El, E2, E3, ...), each stage emission control circuit the circuit shown in Figure 6, are connected to a first clock signal CK and the second clock signal XCK. 第一级发光控制电路的输入端输入起始触发信号STV,之后,每级发光控制电路的输入端输入前一级发光控制电路的输出信号,如此构成相互级联的连接方式,在第一时钟信号和第二时钟信号的驱动下,逐级产生发光驱动信号。 The first stage of the light emission control circuit input terminal start trigger signal STV, after each stage of the light emission control circuit input terminal before a light emission control signal output circuit, thus constituting a cascade connection to each other, in the first clock the driving signal and the second clock signal, generates light emission drive signal stepwise.

[0080] 本发明实施例四提供的显示面板,通过在显示面板的第二基板中采用输出信号稳定的发射驱动电路,可以使第二基板中的像素能够稳定地工作,从而可以使相应的显示面板达到更好的显示效果。 Embodiment [0080] The display panel according to the present invention is provided in the fourth embodiment, by using the output signal of the second substrate in the display panel stable emission drive circuit, the second substrate may be capable of operating stably pixel, thereby displaying the corresponding panel achieve better display.

[0081] 实施例四 [0081] Fourth Embodiment

[0082]图12所示为本发明优选实施例四提供的显示装置结构示意图,显示装置I包括显示面板2,其中显示面板的结构如实施例三中所述的显示面板结构相同。 As shown in FIG. 12 [0082] a schematic view of a preferred embodiment structure of a display device of a fourth embodiment of the present invention, the display device I includes a display panel 2, the display panel is the same as the panel structure as described in Example III wherein the display.

[0083]需要特别说明的是,本发明实施例中的所说的“耦接”指的是两个元器件之间的电性连接,包括直接电性连接和间接的电性连接。 [0083] Of particular note is the embodiment of said embodiment of the present invention, "coupled" means that two components between the electrical connector, comprising a direct electrical connection or indirect electrical connection.

[0084]显然,上述实施例仅用于详细表述本发明,并不构成对本发明保护范围的限制。 [0084] Clearly, the above-described embodiments are merely detailed embodiments of the present invention is expressed, it does not limit the scope of the present invention. 在本发明的构思下,本领域的普通技术人员任何没有创造性劳动而进行的各种改动和变型,均属于本发明权利要求的保护范围。 In the concept of the invention, those of ordinary skill in the art without any inventive work carried out various modifications and variations, all fall within the scope of the claims of the invention.

Claims (9)

1.一种驱动电路,包括第一晶体管、第二晶体管、第三晶体管和第四晶体管,其中: 所述第一晶体管的栅极耦接用于接收起始信号的起始信号输入端,第一端耦接用于接收第二时钟信号的第二时钟信号输入端,第二端耦接第一节点; 所述第二晶体管的栅极耦接所述第二时钟信号输入端,第一端耦接用于接收第二电平信号的第二电平信号输入端,第二端耦接所述第一节点; 所述第三晶体管的栅极耦接所述第一节点,第一端耦接用于接收第一时钟信号的第一时钟信号输入端,第二端耦接第二节点; 所述第四晶体管的栅极耦接所述起始信号输入端,第一端耦接用于接收第一电平信号的第一电平信号输入端,第二端耦接所述第二节点。 1. A driving circuit comprising a first transistor, a second transistor, a third transistor and a fourth transistor, wherein: a gate coupled to the first transistor connected to an input terminal for receiving a start signal start signal, the first one terminal coupled to a second clock signal input terminal receiving a second clock signal, a second terminal coupled to a first node; a gate of the second transistor is coupled to said second clock signal input terminal, a first terminal coupling a second level signal input for receiving a second signal level, a second terminal coupled to the first node; a gate coupled with the first node of the third transistor, a first terminal coupled a first clock signal input terminal connected for receiving a first clock signal, a second terminal coupled to the second node; the gate of the fourth transistor is coupled to the start signal input terminal, a first terminal coupled to a first level signal input for receiving a first signal level, a second terminal coupled to the second node.
2.如权利要求1所述的驱动电路,其特征在于,所述驱动电路的工作状态包括第一阶段、第二阶段、第三阶段、第四阶段、第五阶段,其中: 所述第一阶段中,所述起始信号控制所述第一晶体管和第四晶体管关闭,所述第二时钟信号控制所述第二晶体管打开,第二电平信号经所述第二晶体管传输至第一节点,控制所述第三晶体管打开,第三晶体管传输第一时钟信号至所述第二节点; 所述第二阶段中,所述起始信号控制所述第一晶体管和第四晶体管关闭,所述第二时钟信号发生跳变,控制所述第二晶体管关闭,所述第一节点保持前一阶段电位,控制所述第三晶体管打开,第三晶体管传输第一时钟信号至所述第二节点; 所述第三阶段中,所述起始信号控制所述第一晶体管和第四晶体管关闭,所述第二时钟信号控制所述第二晶体管关闭,所述第一节点保持 2. The drive circuit according to claim 1, wherein said drive circuit comprises a first operational state stage, second stage, third stage, fourth stage, fifth stage, wherein: the first phase, the starting signal controls the closing of the first and fourth transistors, said second clock signal for controlling the second transistor is turned on, the second level signal transmission of the second transistor to the first node controlling said third transistor is turned on, the third transistor of the first transfer clock signal to the second node; the second stage, the starting signal controls the closing of the first and fourth transistors, said a second clock signal transitions, to control the second transistor is turned off, the potential of the node holding the previous stage, controls the third transistor is turned on, the third transistor of the first transfer clock signal to the second node; the third stage, the starting signal to control the first transistor and the fourth transistor is turned off, the second clock signal for controlling the second transistor is turned off, holding the first node 前一阶段电位,控制所述第三晶体管打开,所述第一时钟信号发生跳变并经所述第三晶体管传输至所述第二节点; 所述第四阶段中,所述起始信号控制所述第一晶体管和第四晶体管关闭,所述第二时钟信号控制所述第二晶体管关闭,所述第一节点保持前一阶段电位,控制所述第三晶体管打开,所述第一时钟信号发生跳变并经所述第三晶体管传输至所述第二节点; 所述第五阶段中,所述起始信号发生跳变,控制所述第一晶体管和第四晶体管打开,所述第二时钟信号发生跳变,控制所述第二晶体管打开,第二电平信号经所述第二晶体管传输至所述第一节点,控制所述第三晶体管打开,所述第四晶体管传输第一电平信号至所述第二节点。 The potential of the previous stage, controls the third transistor is turned on, the first clock signal transitions and transmitted through the third transistor to the second node; the fourth stage, the control start signal said first and fourth transistors off, said second clock signal to control the second transistor is turned off, the potential of the node holding the previous stage, controls the third transistor is turned on, the first clock signal and dried hops of the third transistor is transmitted to said second node; said fifth stage, the starting signal transitions, the control transistor and the fourth transistor of the first opening, the second clock signal transitions, the control transistor of the second opening, the second level signal transmission of the second transistor to the first node, the third control transistor is turned on, a first transmission of the fourth transistor is electrically level signal to the second node.
3.—种发光控制电路,包括输入单元和反向单元,其中所述输入单元包括如权利要求1〜2任一项所述的驱动电路; 所述反向单元包括:第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第一电容和第二电容,其中, 所述第五晶体管的栅极耦接所述第二节点,第一端耦接所述第一电平信号输入端,第二端耦接第四节点; 所述第六晶体管的第一端通过所述第一电容与所述第一时钟信号输入端耦接,所述第六晶体管的栅极与第一端耦接,第二端耦接于所述第四节点; 所述第七晶体管的栅极耦接所述第四节点,第二端耦接所述第六晶体管的第一端,第一端耦接所述第二电平信号输入端; 所述第八晶体管的栅极耦接所述第四节点,第一端耦接于所述第一电平信号输入端,第二端耦接于第三节点; 所述第九晶体 3.- kinds of light emission control circuit, including an input unit and a reverse unit, wherein the input unit includes a drive circuit according to any one of claims 1 to 2; said reverse means comprises: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor and a second capacitor, wherein a gate coupled to the second node of the fifth transistor, the first a first end coupled to the signal level of the input terminal, a second terminal coupled to the fourth node; a first terminal of the sixth transistor via the first capacitor and the first input terminal coupled to the clock signal, gate of the sixth transistor is coupled to a first terminal, a second terminal coupled to the fourth node; the access gate coupled to the fourth node of the seventh transistor, a second terminal coupled to the a first terminal of the sixth transistor, a first terminal coupled to the second level signal input terminal; access gate coupled to the fourth node of the eighth transistor, a first terminal coupled to the first electrical level signal input terminal, a second terminal coupled to the third node; said ninth crystals 的栅极耦接所述第二节点,第一端耦接于所述第二电平信号输入端,第二端耦接于所述第三节点; 所述第十晶体管的栅极耦接所述第三节点,第一端耦接所述第一电平信号输入端,第二端耦接所述发光控制电路的输出端; 所述第十一晶体管的栅极耦接于所述第四节点,第一端耦接所述第二电平信号输入端,第二端耦接所述发光控制电路的输出端; 所述第二电容耦接于所述第四节点和所述发光控制电路输出端之间。 A gate coupled to the second node, a first terminal coupled to the second level signal input terminal, a second terminal coupled to the third node; said gate is coupled to the tenth transistor said third node, a first terminal coupled to the first level signal input terminal, a second terminal coupled to the output terminal of the light emission control circuit; a gate of the eleventh transistor is coupled to the fourth node, a first terminal coupled to the second level signal input terminal, a second terminal coupled to an output terminal connected to the light emission control circuit; said second capacitor is coupled to the fourth node and said light emission control circuit output terminal.
4.根据权利要求3所述的发光控制电路,其特征在于,所述发光控制电路的工作状态包括第一阶段、第二阶段、第三阶段、第四阶段、第五阶段、第六阶段、第七阶段、第八阶段,其中, 所述第一阶段中,所述起始信号控制所述第一晶体管和第四晶体管打开,所述第一晶体管传输所述第二时钟信号至所述第一节点,控制所述第三晶体管关闭,所述第一电平信号经所述第四晶体管传输至所述第二节点,控制所述第五晶体管和第九晶体管关闭;所述第一时钟信号通过所述第一电容控制所述第六晶体管的栅极的电位以使所述第六晶体管开启,所述第六晶体管的栅极的电位通过所述第六晶体管传输至所述第四节点,然后控制第七晶体管、第八晶体管和第十一晶体管开启,所述第八晶体管传输第一电平信号至所述第三节点,控制第十晶体管关闭,所述第十一晶 4. The light emitting control circuit of claim 3, wherein said light emission duty control circuit comprises a first stage, second stage, third stage, fourth stage, fifth stage, sixth stage, seventh stage, the eighth stage, wherein, in said first stage, said start signal to control the first transistor and the fourth transistor is turned on, the first transistor of the second transfer clock signal to the first a node, the third control transistor is turned off, the first level signal transmission of the fourth transistor to the second node, said fifth transistor and a ninth control transistor is turned off; the first clock signal by the gate potential of the first capacitance control of the sixth transistor to the sixth transistor is turned on, the potential of the gate of the sixth transistor via the sixth transistor is transmitted to the fourth node, control then the seventh transistor, the eighth transistor and the eleventh transistor is turned on, the eighth transistor transmitting a first signal level to the third node, a tenth control transistor is turned off, the crystal eleventh 体管传输第二电平信号至所述发光控制电路输出端,作为该阶段的输出信号; 所述第二阶段中,所述起始信号控制所述第一晶体管和第四晶体管打开,所述第一晶体管传输所述第二时钟信号至所述第一节点,控制所述第三晶体管关闭,所述第一电平信号经所述第四晶体管传输至所述第二节点,控制所述第五晶体管和第九晶体管关闭;所述第四节点电位由第二电容保持前一阶段的电位,然后控制第七晶体管、第八晶体管和第十一晶体管打开,所述第七晶体管传输第二电平信号至第六晶体管的栅极,以使得第六晶体管打开,所述第八晶体管传输第一电平信号至所述第三节点,控制第十晶体管关闭,所述第十一晶体管传输第二电平信号至所述发光控制电路输出端,作为该阶段的输出信号; 所述第三阶段中,所述起始信号控制所述第一晶体管和第四晶体 Transmitting a second transistor level signal to the light emitting control circuit output, as an output signal of the stage; the second stage, the starting signal for controlling the opening of the first and fourth transistors, said transmitting the first transistor of the second clock signal to the first node, the third control transistor is turned off, the first level signal transmission of the fourth transistor to the second node, said first control five transistors and ninth transistors off; the potential of the fourth node from the second potential holding capacitor of the previous stage, and then controls the seventh transistor, the eighth transistor and the eleventh transistor is turned on, the seventh transistor of the second electrical transmission level signal to the gate of the sixth transistor, the sixth transistor is turned on so that the eighth transistor transmitting a first signal level to the third node, a tenth control transistor is turned off, the second transmission of the eleventh transistor level signal to the light emitting control circuit output, as an output signal of the stage; the third stage, the starting signal to control the first transistor and the fourth crystal 关闭,所述第二时钟信号控制所述第二晶体管打开,第二电平信号经所述第二晶体管传输至第一节点,控制所述第三晶体管打开,第一时钟信号经所述第三晶体管传输至所述第二节点,控制所述第五晶体管和第九晶体管关闭;所述第四节点电位由第二电容保持前一阶段的电位,然后控制第七晶体管、第八晶体管和第十一晶体管打开,所述第七晶体管传输第二电平信号至第六晶体管的栅极,以使得第六晶体管打开,所述第八晶体管传输第一电平信号至所述第三节点,控制第十晶体管关闭,所述第十一晶体管传输第二电平信号至所述发光控制电路输出端,作为该阶段的输出信号; 所述第四阶段中,所述起始信号控制所述第一晶体管和第四晶体管关闭,所述第二时钟信号发生跳变,控制所述第二晶体管关闭,所述第一节点保持前一阶段电位,控制所述 Closing said second clock signal for controlling the second transistor is turned on, the second level of the signal transmitted to the first node of the second transistor, the third control transistor is turned on, a first clock signal of said third transmitting to the second node of the transistor, the control transistor and the ninth transistor of the fifth closed; the fourth node from the second potential of the potential holding capacitor of the previous stage, and then controls the seventh transistor, the eighth and tenth transistors a transistor is turned on, the gate of the seventh transistor transmitting a second signal to the level of the sixth transistor to the sixth transistor is turned on so that the eighth transistor transmitting a first signal level to the third node, the first control ten transistor is turned off, transmission of the eleventh transistor of said second level signal to the light emission control circuit output, as an output signal of the stage; the fourth stage, the start signal of the first control transistor and a fourth transistor is turned off, the second clock signal transitions, to control the second transistor is turned off, the potential of the node holding the previous stage, the control 三晶体管打开,第一时钟信号经所述第三晶体管传输至所述第二节点,控制所述第五晶体管和第九晶体管关闭;所述第四节点电位由第二电容保持前一阶段的电位,然后控制所述第七晶体管、第八晶体管和第十一晶体管打开,所述第七晶体管传输第二电平信号至第六晶体管的栅极,以使得第六晶体管打开,所述第八晶体管传输第一电平信号至所述第三节点,控制第十晶体管关闭,所述第十一晶体管传输第二电平信号至所述发光控制电路输出端,作为该阶段的输出信号; 所述第五阶段中,所述起始信号控制所述第一晶体管和第四晶体管关闭,所述第二时钟信号控制所述第二晶体管关闭,所述第一节点保持前一阶段电位,控制所述第三晶体管打开,所述第一时钟信号发生跳变并经所述第三晶体管传输至所述第二节点,控制所述第五晶体管和第九晶体 Open the third transistor, a first clock signal transmitted through the third transistor to the second node, said fifth transistor and a ninth control transistor is turned off; the potential of the fourth node of the previous stage by a second potential holding capacitor and controlling said seventh transistor, the eighth transistor and the eleventh transistor is turned on, the gate of the seventh transistor transmitting a second signal to the level of the sixth transistor to the sixth transistor is turned on so that the eighth transistor transmitting a first signal level to the third node, a tenth control transistor is turned off, transmission of the eleventh transistor of said second level signal to the light emission control circuit output, as an output signal of the stage; the second five-stage, the starting signal controls the closing of the first and fourth transistors, said second clock signal for controlling the second transistor is turned off, the potential of the node holding the previous stage, said first control three transistor is turned on, the first clock signal transitions and transmitted through the third transistor to the second node, said fifth transistor and a ninth control crystal 打开,所述第一电平信号经所述第五晶体管传输至第四节点,控制所述第七晶体管、第八晶体管和第十一晶体管关闭;所述第二电平信号经所述第九晶体管传输至所述第三节点,控制第十晶体管打开,所述第一电平信号经所述第十晶体管传输至发光控制电路输出端,作为该阶段的输出信号; 所述第六阶段中,所述起始信号控制所述第一晶体管和第四晶体管关闭,所述第二时钟信号控制所述第二晶体管关闭,所述第一节点保持前一阶段电位,控制所述第三晶体管打开,所述第一时钟信号发生跳变并经所述第三晶体管传输至所述第二节点,控制所述第五晶体管和第九晶体管关闭,所述第三节点和第四节点的电位保持前一阶段,所述发光控制电路输出端的信号保持不变; 所述第七阶段中,所述起始信号发生跳变,控制所述第一晶体管和第四晶体管打开 Opening, the first level of the signal transmitted to the fourth node of the fifth transistor, said seventh control transistor, an eleventh transistor is turned off and the eighth transistor; the second level signal of the ninth transmitted to the third node of the transistor, the tenth transistor control opening, the first level signal transmission of the tenth transistor to the light emitting control circuit output, as an output signal of the stage; the sixth stage, the start signal of the first control transistor and the fourth transistor is turned off, the second clock signal for controlling the second transistor is turned off, the potential of the node holding the previous stage, controls the third transistor is turned on, the first clock signal transitions and transmitted through the third transistor to the second node, said fifth transistor and a ninth control transistor is turned off, the potential of the third node and a fourth node holding the front stage, the signal output terminal of the light emission control circuit remains constant; the seventh stage, the starting signal transitions, the control transistor of the first transistor and the fourth opening 所述第二时钟信号发生跳变,控制所述第二晶体管打开,第二电平信号经所述第二晶体管传输至所述第一节点,控制所述第三晶体管打开,所述第一电平信号经所述第四晶体管传输至所述第二节点,控制所述第五晶体管和第九晶体管关闭,所述第三节点和第四节点的电位保持前一阶段,所述发光控制电路输出端的信号保持不变; 所述第八阶段中,所述起始信号控制所述第一晶体管和第四晶体管打开,所述第二时钟信号发生跳变,控制所述第二晶体管关闭,所述第一晶体管传输第二时钟信号至所述第一节点,控制所述第三晶体管关闭,所述第一电平信号经所述第四晶体管传输至所述第二节点,控制所述第五晶体管和第九晶体管关闭,所述第三节点和第四节点的电位保持前一阶段,所述发光控制电路输出端的信号保持不变。 The second clock signal transitions, the control transistor of the second opening, the second level signal transmission of the second transistor to the first node, the third control transistor is turned on, the first electrical level of the signal transmitted through the fourth transistor to the second node, said fifth transistor and a ninth control transistor is turned off, the potential of the third node and the fourth node holding the previous stage, the light emission control circuit outputs end of the signal remains constant; and the eighth stage, the starting signal for controlling the opening of the first and fourth transistors, the second clock signal transitions, to control the second transistor is turned off, the transmitting a second clock signal of the first transistor to the first node, the third control transistor is turned off, the first level signal transmission of the fourth transistor to the second node, said fifth control transistor and a ninth transistor is turned off, the potential of the third node and the fourth node holding the previous stage, the signal output end of said light emission control circuit remains unchanged.
5.根据权利要求3或4所述的发光控制电路,其特征在于,第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管均为PMOS管,所述第一电平信号为恒定的高电平,所述的第二电平信号为恒定的低电平;或者, 第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管均为NMOS管,所述第一电平信号为恒定的低电平,所述的第二电平信号为恒定的高电平。 The light emitting 3 or claim 4, wherein the control circuit, wherein the first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, the eighth transistor , a ninth transistor, a tenth transistor, an eleventh transistor are PMOS transistors, said first constant level signal is high, said second constant level signal is low; Alternatively, the first a transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor are NMOS transistors, said a first constant level signal is low, said second constant level signal is high.
6.根据权利要求3或4所述的发光控制电路,其特征在于,所述第一时钟信号和所述第二时钟信号的相位相差I The light emitting 3 or claim 4, wherein the control circuit, characterized in that the phase of the first clock signal and the second clock signal phase difference I
7.—种显示面板,其特征在于,包括N级如权利要求3〜6任一项所述的发光控制电路。 7.- kinds of display panel, characterized by comprising a light emitting according to any one of claims 3~6 N level control circuit.
8.如权利要求7所述的显示面板,其特征在于,第一级发光控制电路的起始信号输入端输入起始信号,第I级发光控制电路的起始信号输入端输入上一级发光控制电路的输出信号,Ι = 2,3,...Ν0 The display panel according to claim 7, wherein the first light emission start signal input terminal stage control start signal input circuit, a Class I luminescence emission start signal input terminal of the control circuit the output signal of the control circuit, Ι = 2,3, ... Ν0
9.一种显示装置,其特征在于,包括如权利要求7或8所述的显示面板。 A display device comprising the display panel as claimed in claim 7 or 8.
CN201410784238.8A 2014-12-16 2014-12-16 A driving circuit and a light emitting control circuit, a display panel, a display device CN104599630B (en)

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