CN104599630B - Driving circuit, lighting control circuit, display panel and display device - Google Patents
Driving circuit, lighting control circuit, display panel and display device Download PDFInfo
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- CN104599630B CN104599630B CN201410784238.8A CN201410784238A CN104599630B CN 104599630 B CN104599630 B CN 104599630B CN 201410784238 A CN201410784238 A CN 201410784238A CN 104599630 B CN104599630 B CN 104599630B
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Abstract
The optimal embodiment of the invention provides a driving circuit, a lighting control circuit of the driving circuit, a display panel and a display device. The lighting control circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor and a second capacitor; the sixth transistor is connected in an equivalent diode form and can be conducted in one way; the second capacitor maintains stable level of the output end, thus a signal at the output end is avoided the influence from a clock signal, namely, the signal output by the output end of the lighting control circuit cannot be shaken; in addition, the tenth transistor transmits a first level signal or the eleventh transistor transmits a second level signal at the output end of the lighting control circuit in the whole working process, so that the signal output by the output end cannot be left, the output stability is improved, and the display effect is increased.
Description
Technical field
It is the present invention relates to display technology field more particularly to a kind of drive circuit and emission control circuit, display floater, aobvious
Showing device.
Background technology
Organic light emitting display (Organic light Emitting Display), because it has backlight, right is not required to
The technological merits such as, thickness of thin higher than degree, the wide, reaction speed in visual angle, have become one of emphasis direction of display industry development.Its
By the use of luminous organic material as the luminescent material of pixel, driven using pixel-driving circuit and lighted, and be pixel-driving circuit
The circuit design for providing drive signal is the most important thing for developing organic light emitting display technology.
The content of the invention
The preferred embodiment of the present invention mainly provides a kind of simple structure and output signal more stable emission control circuit.
On the one hand, the preferred embodiment of the present invention provides a kind of drive circuit, including the first transistor, transistor seconds, the
Three transistors and the 4th transistor, wherein：
The grid of the first transistor couples the initial signal input for receiving initial signal, and first end coupling is used
In the second clock signal input part for receiving second clock signal, the second end coupling first node；
The grid of the transistor seconds couples the second clock signal input part, and first end is coupled for receiving second
The second electrical level signal input part of level signal, the second end couples the first node；
The grid of the third transistor couples the first node, and first end is coupled for receiving the first clock signal
The first clock signal input terminal, the second end coupling Section Point；
The grid of the 4th transistor couples the initial signal input, and first end is coupled for receiving the first level
First level signal input of signal, the second end couples the Section Point.
On the other hand, another preferred embodiment of the invention provides a kind of emission control circuit, including input block and reversely
Unit, wherein input block include above-mentioned drive circuit.
Further, the reverse unit includes：5th transistor, the 6th transistor, the 7th transistor, the 8th crystal
Pipe, the 9th transistor, the tenth transistor, the 11st transistor, the first electric capacity and the second electric capacity, wherein, the 5th transistor
Grid couple the Section Point, first end couples the first level signal input, the second end coupling fourth node；
The first end of the 6th transistor is coupled by first electric capacity with first clock signal input terminal, institute
The grid and first end for stating the 6th transistor is coupled, and the second end is coupled to the fourth node；
The grid of the 7th transistor couples the fourth node, and the second end couples the first of the 6th transistor
End, first end couples the second electrical level signal input part；
The grid of the 8th transistor couples the fourth node, and first end is coupled to the first level signal input
End, the second end is coupled to the 3rd node；
The grid of the 9th transistor couples the Section Point, and first end is coupled to the second electrical level signal input
End, the second end is coupled to the 3rd node；
The grid of the tenth transistor couples the 3rd node, and first end couples the first level signal input
End, the second end couples the output end of the emission control circuit；
The grid of the 11st transistor is coupled to the fourth node, and it is defeated that first end couples the second electrical level signal
Enter end, the second end couples the output end of the emission control circuit；
Second electric capacity is coupled between the fourth node and the emission control circuit output end.
On the other hand, another preferred embodiment of the invention also provides a kind of display floater, including the above-mentioned light emitting control electricity of N levels
Road.
Further, the initial signal input input initial signal of the first order emission control circuit, the I levels
The initial signal input of emission control circuit is input into the output signal of upper level emission control circuit, I=2,3 ... N.
On the other hand, the preferred embodiment of the present invention also provides a kind of display device, including above-mentioned display floater.
The drive circuit and emission control circuit, display floater, display device that the preferred embodiment of the present invention is provided at least has
Some beneficial effects：Multi-stage light emitting control circuit is mutually cascaded, and only needs the trigger of a high level；Emission control circuit is tied
Structure is simple and signal that export will not be shaken, and is not in during operation that output is hanging so that output is more stable, improves aobvious
Show effect.
Description of the drawings
Fig. 1 is the emission control circuit schematic diagram of prior art；
Fig. 2 is each signal timing diagram of emission control circuit in Fig. 1；
Fig. 3 is the driver circuit schematic diagram that the preferred embodiment of the present invention one is provided；
Fig. 4 is each signal timing diagram of drive circuit in Fig. 3；
Fig. 5 a～Fig. 5 e are the corresponding circuit diagrams of each working stage of drive circuit in Fig. 4；
Fig. 6 is the emission control circuit schematic diagram that the preferred embodiment of the present invention two is provided；
Fig. 7 is the working timing figure of emission control circuit in Fig. 6；
Fig. 8 a～Fig. 8 h are the corresponding circuit diagrams of each working stage of emission control circuit in Fig. 6；
Fig. 9 is the display floater schematic cross-section that the preferred embodiment of the present invention three is provided；
Figure 10 is the structural representation of second substrate in Fig. 9；
Figure 11 is the connection diagram of emission driving circuit in Figure 10；
Figure 12 is the display device structure schematic diagram that the preferred embodiment of the present invention four is provided.
Specific embodiment
With reference to the accompanying drawings and examples the present invention is described in further detail.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention is illustrate only in description, accompanying drawing and not all.
As stated in the Background Art, the circuit design for providing drive signal for pixel-driving circuit has been the weight that OLED shows
Problem, pixel-driving circuit is wanted to generally require gate drive signal SCAN and LED control signal Emit, the OLED pixel of a line
Multiple gate drive signal SCAN may be needed to drive.Generally, LED control signal is produced by light emission drive circuit.OLED
Display floater has N row pixels, then generally corresponded to N level light emission drive circuits, and one-level light emission drive circuit generally includes displacement and posts
Circuit VSR and phase inverter are deposited, the output end of shift register circuit is connected to the input of phase inverter.And every grade of light emission drive circuit
Shift register circuit VSR connect in cascaded fashion, corresponding LED control signal Emit is so produced step by step.Conventional pixel
Drive circuit is PMOS structures, and LED control signal Emit be high level when gate drive signal SCAN works, therefore,
Light emission drive circuit needs input low level, and then shifted register circuit VSR is transmitted to phase inverter, that is, traditional luminous drive
Dynamic circuit input is low level signal.
The structure of above-mentioned light emission drive circuit is excessively complicated, thus occurs in that substitute technology in succession, as shown in figure 1, being three
Circuit diagram (the patent publication No. of the emission control circuit of star company design：US20140055444A1), it adopts the knot of 10T3C
Structure, whole emission control circuit is not the structure using shift register circuit and phase inverter, but is directly given birth to by the structure of 10T3C
Into LED control signal Emi t.Fig. 2 is the working timing figure of emission control circuit in Fig. 1, as shown in Figure 2, this light emitting control electricity
Road input is high level initial signal, but it is in t4-t5 working hours, and because the current potential of N1 points is high level, M10 pipes are closed
Close, therefore output end occurs vacant state, namely output signal plays pendulum.In addition, this emission control circuit is defeated
When going out, because the current potential of N1 points and N3 points does not keep function, the generation of output jitter phenomenon is also resulted in.Therefore above-mentioned output is hanged
Empty and output jitter, in the course of the work output signal is unstable to cause emission control circuit, affects the display effect of panel.
Embodiment one
The preferred embodiment of the present invention one provides a kind of drive circuit, as shown in figure 3, including the first transistor M1, second brilliant
Body pipe M2, third transistor M3 and the 4th transistor M4, wherein, the grid of the first transistor M1 is coupled for receiving initial signal
Initial signal input IN, first end couples the second clock signal input part XCK for receiving second clock signal, second
End coupling first node N1；The grid coupling second clock signal input part XCK of transistor seconds M2, first end is coupled for connecing
Receive the second electrical level signal input part VGL of second electrical level signal, the second end coupling first node N1；The grid of third transistor M3
Coupling first node N1, first end couples the first clock signal input terminal CK for receiving the first clock signal, the second end coupling
Meet Section Point N2；The grid coupling initial signal input IN of the 4th transistor M4, first end couples electric for receiving first
First level signal input VGH of ordinary mail number, the second end couples the Section Point N2.
Further, the first transistor M1, transistor seconds M2, third transistor in the drive circuit that embodiment one is provided
M3 and the 4th transistor M4 can be PMOS, or NMOS tube.Preferably, wherein the first clock signal input terminal CK is defeated
The first clock signal for entering and the second clock signal of second clock signal input part XCK inputs are pulse signals, phase
180 degree；When described the first transistor M1, transistor seconds M2, third transistor M3 and the 4th transistor M4 are PMOS
When, the first level signal of the first level signal input VGH inputs is constant high level, second electrical level signal input part
The second electrical level signal of VGL inputs is constant low level；When the first transistor M1, transistor seconds M2, third transistor M3
When being NMOS tube with the 4th transistor M4, the first level signal of the first level signal input VGH inputs is constant low
Level, the second electrical level signal of second electrical level signal input part VGL inputs is constant high level.When actually used, starting letter
Number, the high value of output signal, the first clock signal and second clock signal 10V, low level value can be selected to select -5V,
Can also be set with being actually needed according to the kind of design of transistor.Specification is needed, for PMOS, crystal
The first end of pipe refers to source electrode, and the second end refers to drain electrode.And for NMOS tube, the first end of transistor is referred to Lou
Pole, the second end refers to source electrode.
Fig. 4 show a kind of preferred working timing figure of drive circuit in Fig. 3, its is corresponding be the first transistor M1,
Two-transistor M2, third transistor M3 and the 4th transistor M4 are PMOS, and the of the first level signal input VGH inputs
One level signal is constant high level, and the second electrical level signal of second electrical level signal input part VGL inputs is constant low electricity
It is flat.
The drive circuit that embodiment one is provided at least includes five working hours, and the T1～T5 moment correspondence in Fig. 4 is implemented
Five working stages of example one drive circuit, respectively as shown in Fig. 5 a～5e.Describe in detail with reference to Fig. 4 and Fig. 5 a～5e real
Apply the course of work of an one drive circuit：
Fig. 5 a be embodiment one in drive circuit works first stage circuit diagram, i.e. T1 periods, initial signal IN in Fig. 4
Input high level, control the first transistor M1 and the 4th transistor M4 is closed, the first clock signal CK input high level, and second
Clock signal XCK input low level, control transistor seconds M2 is opened, second electrical level signal VGL Jing transistor secondses M2 transmission
To first node N1 so that the current potential of first node is low level, then control third transistor M3 and open, third transistor M3
The first clock signal CK is transmitted to Section Point N2 so that the current potential of Section Point is high level.
Fig. 5 b be embodiment one in drive circuit works second stage circuit diagram, i.e. T2 periods, initial signal IN in Fig. 4
Input high level, control the first transistor M1 and the 4th transistor M4 is closed, the first clock signal CK input high level, when second
There is saltus step in clock signal XCK, from low level high level is changed into, and control transistor seconds M2 is closed, and first node N1 keeps previous
Stage current potential, namely first node N1 current potentials keep low level, control third transistor M3 to open, third transistor M3 transmission the
One clock signal CK is to Section Point N2 so that the current potential of Section Point is high level；It is main by third transistor in this stage
The parasitic capacitance of M3 keeps the current potential of first node N1, therefore the breadth length ratio of third transistor M3 will design enough big.
Fig. 5 c be embodiment one in drive circuit works phase III circuit diagram, i.e. T3 periods, initial signal IN in Fig. 4
Input high level, control the first transistor M1 and the 4th transistor M4 is closed, second clock signal XCK input high levels, control
Transistor seconds M2 is closed, and first node N1 keeps previous stage electronegative potential, control third transistor M3 to open, the first clock letter
There is saltus step in number CK, from high level low level is changed into, and Jing third transistor M3 is transmitted to Section Point N2 so that Section Point
The current potential of N2 is low level.
Fig. 5 d be embodiment one in drive circuit works fourth stage circuit diagram, i.e. T4 periods, initial signal IN in Fig. 4
Input high level, control the first transistor M1 and the 4th transistor M4 is closed, second clock signal XCK input high levels, control
Transistor seconds M2 is closed, and first node N1 keeps previous stage electronegative potential, control third transistor M3 to open, the first clock letter
There is saltus step in number CK, from low level high level is changed into, and Jing third transistor M3 is transmitted to Section Point N2 so that Section Point
The current potential of N2 is high level.
Fig. 5 e are the 5th stage circuit figure of drive circuit works in embodiment one, i.e. T5 periods in Fig. 4, the first clock is believed
There is saltus step in number CK input high levels, initial signal IN, from high level low level is changed into, control the first transistor M1 and the 4th brilliant
Body pipe M4 is opened, and second clock signal XCK occurs saltus step, and from high level low level is changed into, and control transistor seconds M2 is opened,
Transistor seconds M2 described in second electrical level signal VGL Jing is transmitted to first node N1, the first transistor M1 transmission low level the
Two clock signals XCK are to first node so that first node N1 current potentials are low level, and control third transistor M3 is opened, and the 3rd
To Section Point N2, the 4th transistor M4 transmits the first level signal to first clock signal CK of transistor M3 transmission high level
VGH to Section Point N2 so that Section Point N2 current potentials are high level.
Embodiment two
The preferred embodiment of the present invention two provides a kind of emission control circuit, as shown in fig. 6, including input block 10 and instead
To unit 20, wherein, input block 10 includes the drive circuit as described by embodiment one, namely including the first transistor M1,
Transistor seconds M2, third transistor M3 and the 4th transistor M4, and reversely unit 20 includes the 5th transistor M5, the 6th crystal
Pipe M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11st transistor M11,
First electric capacity C1 and the second electric capacity C2, namely whole light emission drive circuit include the first transistor M1, transistor seconds M2, the 3rd
Transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8,
The transistor M10 of nine transistor M9 the tenth, the 11st transistor M11 and the first electric capacity C1, the second electric capacity C2.
Wherein:
The grid of the first transistor M1 couples the initial signal input IN for receiving initial signal, and first end coupling is used
In the second clock signal input part XCK for receiving second clock signal, the second end coupling first node N1；
The grid coupling second clock signal input part XCK of transistor seconds M2, first end couples electric for receiving second
The second electrical level signal input part VGL of ordinary mail number, the second end coupling first node N1；
The grid coupling first node N1 of third transistor M3, first end is coupled for the first of the first clock signal of reception
Clock signal input terminal CK, the second end coupling Section Point N2；
The grid coupling initial signal input IN of the 4th transistor M4, first end is coupled for receiving the first level signal
The first level signal input VGH, the second end couples the Section Point N2；
The grid coupling Section Point N2 of the 5th transistor M5, first end couples the first level signal input VGH, the
Two ends couple fourth node N4；
The first end of the 6th transistor M6 is coupled by the first electric capacity C1 and the first clock signal input terminal CK, the 6th crystal
The grid of pipe M6 and the coupling of its first end so that the 6th transistor M6 is equivalent to diode, can only one-way conduction, the 6th transistor
Second end of M6 is coupled to fourth node N4；
Grid coupling fourth node N4 of the 7th transistor M7, the first end of the 6th transistor M6 of the second end coupling, first
End coupling is used to receive the second electrical level signal input part VGL of second electrical level signal；
The grid of the 8th transistor M8 is coupled to fourth node N4, and first end is coupled to the first level signal input
VGH, the second end is coupled to the 3rd node N3；
The grid coupling Section Point N2 of the 9th transistor M9, first end is coupled to second electrical level signal input part VGL, the
Two ends are coupled to the 3rd node N3；
The grid of the tenth transistor M10 couples the 3rd node N3, and first end couples the first level signal input VGH, the
Two ends couple output end OUT of emission control circuit；
The grid of the 11st transistor M11 is coupled to fourth node N4, first end coupling second electrical level signal input part
VGL, the second end couples output end OUT of emission control circuit；
Second electric capacity C2 is coupled between fourth node N4 and emission control circuit output end OUT, for keeping output end
The stable output signal of OUT.
Further, it is the first transistor M1 in the emission control circuit that embodiment one is provided, transistor seconds M2, the 3rd brilliant
Body pipe M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th
Transistor M9, the tenth transistor M10, the 11st transistor M11 can be PMOS, or NMOS tube.Preferably, wherein
First clock signal of the first clock signal input terminal CK inputs and the second clock letter of second clock signal input part XCK inputs
Number it is pulse signal, phase 180 degree.When the first transistor M1, transistor seconds M2, third transistor M3, the 4th crystal
It is pipe M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth brilliant
When body pipe M10, the 11st transistor M11 are PMOS, the first level signal of the first level signal input VGH inputs is
Constant high level, the second electrical level signal of second electrical level signal input part VGL inputs is constant low level；Work as first crystal
It is pipe M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th brilliant
When body pipe M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11st transistor M11 are NMOS tube, the
First level signal of one level signal input VGH inputs is constant low level, and second electrical level signal input part VGL is input into
Second electrical level signal be constant high level.When actually used, initial signal, the first level signal, second electrical level signal,
The level value of the high level of one clock signal and second clock signal can select 10V, low level level value to select -5V,
Can be set with being actually needed according to the kind of design of transistor.Specification is needed, for PMOS, transistor
First end refer to source electrode, the second end refers to drain electrode.And for NMOS tube, the first end of transistor is referred to Lou
Pole, the second end refers to source electrode.
Fig. 7 show a kind of preferred working timing figure of emission control circuit in Fig. 6, and it is the first transistor that its is corresponding
M1, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th crystal
Pipe M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11st transistor M11 are PMOS, and first is electric
First level signal of flat signal input part VGH input is constant high level, the of second electrical level signal input part VGL inputs
Two level signals are constant low level.
The emission control circuit that embodiment two is provided at least includes eight working hours, the T1～T8 moment correspondence in Fig. 7
Eight working stages of the emission control circuit of embodiment two, respectively as shown in Fig. 8 a～8h.It is detailed with reference to Fig. 7 and Fig. 8 a～8h
Describe the course of work of the emission control circuit of bright embodiment two in detail：
Fig. 8 a are the first stage circuit diagram of emission control circuit work in embodiment two, i.e. T1 periods in Fig. 7, starting is believed
Number IN input low levels, control the first transistor M1 and the 4th transistor M4 is opened, second clock signal XCK input high levels,
The first transistor M1 transmits second clock signal XCK to first node N1 so that the current potential of first node N1 is high level, is controlled
Third transistor M3 is closed, and the transistor M4 of the first level signal VGH Jing the 4th are transmitted to Section Point N2 so that Section Point N2
Current potential be high level, control the 5th transistor M5 and the 9th transistor M9 close；There is saltus step in the first clock signal CK, by height
Level is changed into low level, by the bootstrap effect of the first electric capacity C1 so that the grid potential step-down of the 6th transistor, due to the 6th
Transistor M6 is connected in equivalent diode mode, therefore the 6th transistor M6 is opened, and transmits low level value fourth node N4,
So that the current potential of fourth node N4 is low level, the 7th transistor M7, the 8th transistor M8 and the 11st transistor are then controlled
M11 is opened, the 8th transistor M8 transmission the first level signals VGH to the 3rd node N3 so that the current potential of the 3rd node N3 is changed into
High level, the tenth transistor M1O of control is closed, and the 11st transistor M11 transmits second electrical level signal VGL to emission control circuit
Output end OUT, as the output signal in the stage.
Fig. 8 b are the second stage circuit diagram of emission control circuit work in embodiment two, i.e. T2 periods in Fig. 7, starting is believed
Number IN input low levels, control the first transistor M1 and the 4th transistor M4 is opened, and the first clock signal CK occurs saltus step, by low
Level is changed into high level, second clock signal XCK input high levels, and the first transistor M1 transmits second clock signal XCK to the
One node N1 so that the current potential of first node N1 is high level, control third transistor M3 is closed, the first level signal VGH Jing
4th transistor M4 is transmitted to Section Point N2 so that the current potential of Section Point N2 be high level, control the 5th transistor M5 and
9th transistor M9 is closed；Fourth node N4 current potential is kept the current potential of previous stage by the second electric capacity C2, namely keeps low level,
Control the 7th transistor M7, the 8th transistor M8 and the 11st transistor M11 is opened, the 7th transistor M7 transmission constant low levels
The transistor M6 of second electrical level signal VGL to the 6th grid, although the saltus step of the first clock signal CK and the first electric capacity C1
Coupling effect, have the of short duration effect of drawing high to the grid potential of the 6th transistor M6, but the grid of the 6th transistor M6 can become
Open for low level, therefore the 6th transistor M6, the 8th transistor M8 transmits the first level signal VGH to the 3rd node N3, makes
The current potential for obtaining the 3rd node N3 is changed into high level, and the tenth transistor M1O of control is closed, and the 11st transistor M11 transmission second is electric
Ordinary mail VGL to emission control circuit output end OUT, as the output signal in the stage.
Fig. 8 c are the phase III circuit diagram of emission control circuit work in embodiment two, i.e. T3 periods in Fig. 7, starting is believed
There is saltus step in number IN, from low level high level is changed into, and control the first transistor M1 and the 4th transistor M4 is closed, the first clock letter
There is saltus step in number CK input high levels, second clock signal XCK, from high level low level is changed into, and control transistor seconds M2 beats
Open, second electrical level signal VGL Jing transistor seconds M2 are transmitted to first node N1 so that the current potential of first node N1 is low electricity
Flat, control third transistor M3 is opened, and the first clock signal CK Jing third transistor M3 is transmitted to Section Point N2 so that second
The current potential of node N2 is high level, and the 5th transistor M5 of control and the 9th transistor M9 is closed；The current potential of fourth node N4 is by
Two electric capacity C2 keep the current potential of previous stage, namely keep low level, the 7th transistor M7 of control, the 8th transistor M8 and the tenth
One transistor M11 is opened, and the 7th transistor M7 transmits the grid of the transistor M6 of second electrical level signal VGL to the 6th, so that the
Six transistor M6 are opened, the 8th transistor M8 transmission the first level signals VGH to the 3rd node N3 so that the electricity of the 3rd node N3
Position is changed into high level, and the tenth transistor M1O of control is closed, and the 11st transistor M11 transmits second electrical level signal VGL to luminous control
Circuit output end OUT processed, as the output signal in the stage.
Fig. 8 d are the fourth stage circuit diagram of emission control circuit work in embodiment two, i.e. T4 periods in Fig. 7, starting is believed
Number IN input high levels, control the first transistor M1 and the 4th transistor M4 is closed, the first clock signal CK input high level, the
There is saltus step in two clock signals XCK, from low level high level is changed into, and control transistor seconds M2 is closed, and first node N1 keeps
Previous stage current potential, namely low level is kept, control third transistor M3 is opened, the first clock signal CK Jing third transistor M3
Transmit to Section Point N2 so that the current potential of Section Point N2 is high level, controls the 5th transistor M5 and the 9th transistor M9
Close；The current potential of fourth node N4 is kept the current potential of previous stage by the second electric capacity C2, namely keeps low level, and control the 7th is brilliant
Body pipe M7, the 8th transistor M8 and the 11st transistor M11 are opened, and the 7th transistor M7 transmits second electrical level signal VGL to the
The grid of six transistor M6, so that the 6th transistor M6 is opened, the 8th transistor M8 transmits the first level signal VGH to the 3rd
Node N3 so that the current potential of the 3rd node N3 is changed into high level, the tenth transistor M1O of control is closed, and the 11st transistor M11 is passed
Defeated second electrical level signal VGL to emission control circuit output end OUT, as the output signal in the stage.
Fig. 8 e are the 5th stage circuit figure of emission control circuit work in embodiment two, i.e. T5 periods in Fig. 7, starting is believed
Number IN input high levels, control the first transistor M1 and the 4th transistor M4 is closed, second clock signal XCK input high levels,
Control transistor seconds M2 is closed, and first node N1 keeps previous stage current potential, namely keeps low level, controls third transistor
M3 is opened, and the first clock signal CK occurs saltus step, and from high level low level, the first clock signal CK Jing third transistor M3 are changed into
Transmit to Section Point N2 so that the current potential of Section Point N2 is low level, controls the 5th transistor M5 and the 9th transistor M9
Open, the transistor M5 of the first level signal VGH Jing the 5th are transmitted to fourth node N4 so that the current potential of fourth node N4 is changed into high
Level, control the 7th transistor M7 of control, the 8th transistor M8 and the 11st transistor M11 are closed；Second electrical level signal Jing
Nine transistor M9 are transmitted to the 3rd node N3 so that the current potential of the 3rd node N3 is changed into low level, and the tenth transistor M10 of control beats
Open, the transistor M10 of the first level signal VGH Jing the tenth are transmitted to emission control circuit output end, the output as the stage is believed
Number.
Fig. 8 f are the 6th stage circuit figure of emission control circuit work in embodiment two, i.e. T6 periods in Fig. 7, starting is believed
Number IN input high levels, control the first transistor M1 and the 4th transistor M4 is closed, second clock signal XCK input high levels,
Control transistor seconds M2 is closed, and first node N1 keeps previous stage current potential, namely keeps low level, controls third transistor
M3 is opened, and the first clock signal CK occurs saltus step, and from low level high level, the first clock signal CK Jing third transistor M3 are changed into
Transmit to Section Point N2 so that the current potential of Section Point N2 is high level, controls the 5th transistor M5 and the 9th transistor M9
Close, the saltus step of the first clock signal CK, through the coupling of the first electric capacity C1, is that the grid potential of the 6th transistor M6 is drawn high, the
Six transistor M6 are closed；The current potential of fourth node N4 is kept the current potential of previous stage by the second electric capacity C2, namely keeps high level,
Control the 7th transistor M7, the 8th transistor M8 and the 11st transistor M11 is closed；3rd node N3 keeps previous stage electricity
Position, namely the 3rd node N3 current potentials holding low level, the tenth transistor M10 of control is opened, and the first level signal VGH Jing the tenth is brilliant
Body pipe M10 is transmitted to emission control circuit output end, used as the output signal in the stage；It is main by the tenth transistor in this stage
The parasitic capacitance of M10 keeps the current potential of the 3rd node N3, therefore the breadth length ratio of the tenth transistor M10 will design enough big.
Fig. 8 g are the 7th stage circuit figure of emission control circuit work in embodiment two, i.e. T7 periods in Fig. 7, starting is believed
There is saltus step in number IN, from high level low level is changed into, and control the first transistor M1 and the 4th transistor M4 is opened, the first clock letter
There is saltus step in number CK input high levels, second clock signal XCK, from high level low level is changed into, and control transistor seconds M2 beats
Open, second electrical level signal VGL Jing transistor seconds M2 are transmitted to first node N1 so that the current potential of first node N1 is low electricity
Flat, control third transistor M3 is opened, and the first clock signal CK Jing third transistor M3 is transmitted to Section Point N2 so that second
The current potential of node N2 is high level, and the 5th transistor M5 of control and the 9th transistor M9 is closed；The current potential of fourth node N4 is by
Two electric capacity C2 keep the current potential of previous stage, namely keep high level, the 7th transistor M7 of control, the 8th transistor M8 and the tenth
One transistor M11 is closed；3rd node N3 keeps previous stage current potential, namely the 3rd node N3 current potentials to keep low level, control
Tenth transistor M10 is opened, and the transistor M10 of the first level signal VGH Jing the tenth are transmitted to emission control circuit output end, is made
For the output signal in the stage；The main parasitic capacitance by the tenth transistor M10 keeps the current potential of the 3rd node N3 in this stage,
Therefore the breadth length ratio of the tenth transistor M10 will design enough big.
Fig. 8 h are the 8th stage circuit figure of emission control circuit work in embodiment two, i.e. T8 periods in Fig. 7, starting is believed
Number IN input low levels, control the first transistor M1 and the 4th transistor M4 is opened, the first clock signal CK input high level, the
There is saltus step in two clock signals XCK, from low level high level is changed into, and control transistor seconds M2 is closed, and the first transistor M1 is passed
Defeated second clock signal XCK to first node N1 so that the current potential of first node N1 is high level, control third transistor M3 is closed
Close, the 4th transistor M4 transmits the first level signal VGH to Section Point N2 so that the current potential of Section Point N2 is high level,
Control the 5th transistor M5 and the 9th transistor M9 to close；The current potential of fourth node N4 is kept for previous stage by the second electric capacity C2
Current potential, namely high level is kept, the 7th transistor M7 of control, the 8th transistor M8 and the 11st transistor M11 are closed；Section three,
Point N3 keeps previous stage current potential, namely the 3rd node N3 current potentials to keep low level, the tenth transistor M10 of control to open, and first
The transistor M10 of level signal VGH Jing the tenth are transmitted to emission control circuit output end, used as the output signal in the stage.
From the above course of work, there is the second electric capacity C2 in fourth node N4, can with emission control circuit output end OUT
To keep fourth node to stablize with the current potential of output end, do not affected by the first clock signal or second clock signal saltus step, made
Obtaining the signal of emission control circuit output end OUT output will not shake.And in whole work process, each stage, output end OUT
There is the tenth transistor M10 to transmit the first level signal VGH or the 11st transistor M11 transmission second electrical level signal VGL so that
The signal of emission control circuit output end output will not be hanging, exports more stable.
It should be noted that embodiment two provide emission control circuit in the first transistor～the 11st transistor can
To be NMOS tube, in its course of work, only need initial signal, the first clock signal, second clock signal, the first level signal,
The level value of second electrical level signal is contrary.
Embodiment three
The preferred embodiment of the present invention three provides a kind of display floater, and its sectional view is as shown in figure 9, including the He of first substrate 11
Second substrate 12, first substrate 11 is oppositely arranged with second substrate 12, wherein, the first substrate 11 can for color membrane substrates,
Packaged glass (Cover Glass) or cover-plate glass (Cover Lens) etc., the second substrate 12 can be pel array
Substrate, such as common OLED pixel array base palte.
Figure 10 be the embodiment of the present invention three display floater in second substrate 12 structural representation.Referring to Figure 10, second
When substrate is image element array substrates, can include：Scan drive circuit 121, data drive circuit 122, emission driving circuit
123rd, m bars scan line (S1, S2 ..., Sm), k data lines (D1, D2 ..., Dk), m bars transmitting drives line (E1, E2 ...,
) and multiple pixels 124 Em；Wherein, the emission driving circuit 123 in the present embodiment be include it is multistage as described in embodiment two
Emission control circuit.
Specifically, the scan drive circuit 121 in the present embodiment, for providing to each bar scan line (S1, S2 ..., Sn)
Scanning signal；Data drive circuit 122, for providing data-signal to pieces of data line (D1, D2 ..., Dm)；Transmitting drives
Circuit 123, for each bar transmitting drives line (E1, E2 ..., Em) luminous drive signal is provided so that the picture in pixel 124
Plain drive circuit completes node initializing, valve value compensation and data write etc.；Pixel 124 is separately positioned on scan line and data wire
In the region for intersecting to form.
Figure 11 is the connection diagram of emission driving circuit 123 in the embodiment of the present invention three, and as shown in figure 11, transmitting drives
Circuit include multi-stage light emitting control circuit (E1, E2, E3 ...), the circuit diagram of every grade of emission control circuit is as shown in fig. 6, respectively
Connect the first clock signal CK and second clock signal XCK.The input input start trigger letter of first order emission control circuit
Number STV, afterwards, the input of every grade of emission control circuit is input into the output signal of previous stage emission control circuit, so constitutes
Mutually the connected mode of cascade, under the driving of the first clock signal and second clock signal, produces step by step luminous drive signal.
The display floater that the embodiment of the present invention four is provided, by steady using output signal in the second substrate of display floater
Fixed emission driving circuit, can enable the pixel in second substrate stably work, such that it is able to make corresponding display surface
Plate reaches more preferable display effect.
Example IV
Figure 12 show the display device structure schematic diagram of the offer of the preferred embodiment of the present invention four, and display device 1 includes aobvious
Show panel 2, the wherein structure of the display floater such as display panel structure described in embodiment three is identical.
It should be strongly noted that described " coupling " in the embodiment of the present invention refers to the electricity between two components and parts
Property connection, including being directly electrically connected with and be indirectly electrically connected with.
Obviously, above-described embodiment is only used for the statement present invention in detail, does not constitute limiting the scope of the invention.
Under the design of the present invention, one of ordinary skill in the art any various changes that carry out and modification without creative work,
Belong to the protection domain of the claims in the present invention.
Claims (9)
1. a kind of drive circuit, including the first transistor, transistor seconds, third transistor and the 4th transistor, wherein：
The grid of the first transistor couples the initial signal input for receiving initial signal, and first end is coupled for connecing
Receive the second clock signal input part of second clock signal, the second end coupling first node；
The grid of the transistor seconds couples the second clock signal input part, and first end is coupled for receiving second electrical level
The second electrical level signal input part of signal, the second end couples the first node；
The grid of the third transistor couples the first node, and first end is coupled for the first of the first clock signal of reception
Clock signal input terminal, the second end coupling Section Point；
The grid of the 4th transistor couples the initial signal input, and first end is coupled for receiving the first level signal
The first level signal input, the second end couples the Section Point.
2. drive circuit as claimed in claim 1, it is characterised in that the working condition of the drive circuit includes the first rank
Section, second stage, phase III, fourth stage, the 5th stage, wherein：
In the first stage, the initial signal controls the first transistor and the 4th transistor is closed, when described second
Clock signal controls the transistor seconds and opens, and transistor seconds described in second electrical level signal Jing is transmitted to first node, control
The third transistor is opened, and third transistor transmits the first clock signal to the Section Point；
In the second stage, the initial signal controls the first transistor and the 4th transistor is closed, when described second
There is saltus step in clock signal, control the transistor seconds and close, and the first node keeps previous stage current potential, control described the
Three transistors are opened, and third transistor transmits the first clock signal to the Section Point；
In the phase III, the initial signal controls the first transistor and the 4th transistor is closed, when described second
Clock signal controls the transistor seconds and closes, and the first node keeps previous stage current potential, controls the third transistor
Open, first clock signal occurs saltus step and third transistor described in Jing is transmitted to the Section Point；
In the fourth stage, the initial signal controls the first transistor and the 4th transistor is closed, when described second
Clock signal controls the transistor seconds and closes, and the first node keeps previous stage current potential, controls the third transistor
Open, first clock signal occurs saltus step and third transistor described in Jing is transmitted to the Section Point；
In 5th stage, there is saltus step in the initial signal, controls the first transistor and the 4th transistor is opened, institute
State second clock signal and saltus step occurs, control the transistor seconds and open, transistor seconds described in second electrical level signal Jing is passed
Transport to the first node, control the third transistor and open, the 4th transistor transmits the first level signal to described
Section Point.
3. a kind of emission control circuit, including input block and reverse unit, wherein the input block includes such as claim 1
Drive circuit described in～2 any one；
The reverse unit includes：5th transistor, the 6th transistor, the 7th transistor, the 8th transistor, the 9th transistor,
Tenth transistor, the 11st transistor, the first electric capacity and the second electric capacity, wherein,
The grid of the 5th transistor couples the Section Point, and first end couples the first level signal input, the
Two ends couple fourth node；
The first end of the 6th transistor is coupled by first electric capacity with first clock signal input terminal, and described
The grid of six transistors is coupled with first end, and the second end is coupled to the fourth node；
The grid of the 7th transistor couples the fourth node, and the second end couples the first end of the 6th transistor, the
One end couples the second electrical level signal input part；
The grid of the 8th transistor couples the fourth node, and first end is coupled to the first level signal input,
Second end is coupled to the 3rd node；
The grid of the 9th transistor couples the Section Point, and first end is coupled to the second electrical level signal input part,
Second end is coupled to the 3rd node；
The grid of the tenth transistor couples the 3rd node, and first end couples the first level signal input, the
Two ends couple the output end of the emission control circuit；
The grid of the 11st transistor is coupled to the fourth node, and first end couples the second electrical level signal input
End, the second end couples the output end of the emission control circuit；
Second electric capacity is coupled between the fourth node and the emission control circuit output end.
4. emission control circuit according to claim 3, it is characterised in that the working condition bag of the emission control circuit
First stage, second stage, phase III, fourth stage, the 5th stage, the 6th stage, the 7th stage, the 8th stage are included, its
In,
In the first stage, the initial signal controls the first transistor and the 4th transistor is opened, and described first is brilliant
Body pipe transmits the second clock signal to the first node, controls the third transistor and closes, the first level letter
Number the 4th transistor described in Jing is transmitted to the Section Point, controls the 5th transistor and the 9th transistor is closed；It is described
First clock signal is by the current potential of the grid of the 6th transistor described in first Capacity control so that the 6th transistor
Open, the current potential of the grid of the 6th transistor is transmitted to the fourth node by the 6th transistor, then controlled
7th transistor, the 8th transistor and the 11st transistor are opened, and the 8th transistor transmits the first level signal to described
3rd node, the tenth transistor of control is closed, and the 11st transistor transmits second electrical level signal to light emitting control electricity
Road output end, as the output signal in the stage；
In the second stage, the initial signal controls the first transistor and the 4th transistor is opened, and described first is brilliant
Body pipe transmits the second clock signal to the first node, controls the third transistor and closes, the first level letter
Number the 4th transistor described in Jing is transmitted to the Section Point, controls the 5th transistor and the 9th transistor is closed；It is described
Fourth node current potential is kept the current potential of previous stage by the second electric capacity, then controls the 7th transistor, the 8th transistor and the tenth
One transistor is opened, and the 7th transistor transmits the grid of second electrical level signal to the 6th transistor, so that the 6th crystal
Pipe is opened, and the 8th transistor transmits the first level signal to the 3rd node, and the tenth transistor of control is closed, and described the
11 transistors transmit second electrical level signal to the emission control circuit output end, used as the output signal in the stage；
In the phase III, the initial signal controls the first transistor and the 4th transistor is closed, when described second
Clock signal controls the transistor seconds and opens, and transistor seconds described in second electrical level signal Jing is transmitted to first node, control
The third transistor is opened, and third transistor described in the first clock signal Jing is transmitted to the Section Point, controls described the
Five transistors and the 9th transistor are closed；The fourth node current potential is kept the current potential of previous stage by the second electric capacity, is then controlled
Make the 7th transistor, the 8th transistor and the 11st transistor to open, the 7th transistor transmits second electrical level signal to the
The grid of six transistors, so that the 6th transistor is opened, the 8th transistor transmits the first level signal to the described 3rd
Node, the tenth transistor of control is closed, and the 11st transistor transmission second electrical level signal is defeated to the emission control circuit
Go out end, as the output signal in the stage；
In the fourth stage, the initial signal controls the first transistor and the 4th transistor is closed, when described second
There is saltus step in clock signal, control the transistor seconds and close, and the first node keeps previous stage current potential, control described the
Three transistors are opened, and third transistor described in the first clock signal Jing is transmitted to the Section Point, control the 5th crystal
Pipe and the 9th transistor are closed；The fourth node current potential is kept the current potential of previous stage by the second electric capacity, is then controlled described
7th transistor, the 8th transistor and the 11st transistor are opened, and the 7th transistor transmits second electrical level signal to the 6th
The grid of transistor, so that the 6th transistor is opened, the 8th transistor transmits the first level signal to described Section three
Point, the tenth transistor of control is closed, and the 11st transistor transmission second electrical level signal is exported to the emission control circuit
End, as the output signal in the stage；
In 5th stage, the initial signal controls the first transistor and the 4th transistor is closed, when described second
Clock signal controls the transistor seconds and closes, and the first node keeps previous stage current potential, controls the third transistor
Open, first clock signal occurs saltus step and third transistor described in Jing is transmitted to the Section Point, control described the
Five transistors and the 9th transistor are opened, and the 5th transistor described in first level signal Jing is transmitted to fourth node, control
7th transistor, the 8th transistor and the 11st transistor are closed；9th transistor described in the second electrical level signal Jing
Transmit to the 3rd node, the tenth transistor of control is opened, the tenth transistor described in first level signal Jing transmit to
Emission control circuit output end, as the output signal in the stage；
In 6th stage, the initial signal controls the first transistor and the 4th transistor is closed, when described second
Clock signal controls the transistor seconds and closes, and the first node keeps previous stage current potential, controls the third transistor
Open, first clock signal occurs saltus step and third transistor described in Jing is transmitted to the Section Point, control described the
Five transistors and the 9th transistor are closed, and the current potential of the 3rd node and fourth node keeps previous stage, the luminous control
The signal of circuit output end processed keeps constant；
In 7th stage, there is saltus step in the initial signal, controls the first transistor and the 4th transistor is opened, institute
State second clock signal and saltus step occurs, control the transistor seconds and open, transistor seconds described in second electrical level signal Jing is passed
The first node is transported to, the third transistor is controlled and is opened, the 4th transistor transmission described in first level signal Jing
To the Section Point, control the 5th transistor and the 9th transistor is closed, the electricity of the 3rd node and fourth node
Position is kept for previous stage, and the signal of the emission control circuit output end keeps constant；
In 8th stage, the initial signal controls the first transistor and the 4th transistor is opened, when described second
There is saltus step in clock signal, control the transistor seconds and close, and the first transistor transmits second clock signal to described the
One node, controls the third transistor and closes, and the 4th transistor described in first level signal Jing is transmitted to described second
Node, controls the 5th transistor and the 9th transistor is closed, and the current potential of the 3rd node and fourth node keeps previous
Stage, the signal of the emission control circuit output end keeps constant.
5. the emission control circuit according to claim 3 or 4, it is characterised in that the first transistor, transistor seconds,
Three transistors, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor, the 9th transistor,
Ten transistors, the 11st transistor are PMOS, and first level signal is constant high level, described second electrical level
Signal is constant low level；Or,
It is the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th brilliant
Body pipe, the 8th transistor, the 9th transistor, the tenth transistor, the 11st transistor are NMOS tube, first level signal
For constant low level, described second electrical level signal is constant high level.
6. the emission control circuit according to claim 3 or 4, it is characterised in that first clock signal and described
The phase by pi of two clock signals.
7. a kind of display floater, it is characterised in that including emission control circuit of the N levels as described in any one of claim 3～6.
8. display floater as claimed in claim 7, it is characterised in that the initial signal input of first order emission control circuit
Input initial signal, the output letter of the initial signal input input upper level emission control circuit of I level emission control circuits
Number, I=2,3 ... N.
9. a kind of display device, it is characterised in that including display floater as claimed in claim 7 or 8.
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| CN105489153B (en) * | 2015-12-21 | 2018-06-29 | 上海天马有机发光显示技术有限公司 | Shifting deposit unit and its driving method and shift register |
| CN105679239B (en) * | 2016-03-10 | 2018-06-22 | 北京大学深圳研究生院 | A kind of integrated gate drive circuitry, AMOLED pixel circuit and panel |
| CN105761757B (en) * | 2016-05-13 | 2018-05-18 | 京东方科技集团股份有限公司 | Shift register cell, driving method, array substrate, display panel and device |
| CN105810142B (en) * | 2016-05-20 | 2019-09-27 | 上海天马有机发光显示技术有限公司 | Shifting deposit unit and its driving method, shift-register circuit, display device |
| CN108122534B (en) * | 2016-11-29 | 2019-03-26 | 昆山国显光电有限公司 | A kind of drive control circuit and its driving method, display device |
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| JP2001100653A (en) * | 1999-09-29 | 2001-04-13 | Tdk Corp | Shift register and image display device |
| KR100910562B1 (en) * | 2002-12-17 | 2009-08-03 | 삼성전자주식회사 | Device of driving display device |
| JP4646187B2 (en) * | 2004-02-12 | 2011-03-09 | 東北パイオニア株式会社 | Light emitting display device and drive control method thereof |
| KR100646992B1 (en) * | 2005-09-13 | 2006-11-23 | 삼성에스디아이 주식회사 | Emission driver and organic light emitting display using the same |
| CA2660598A1 (en) * | 2008-04-18 | 2009-06-22 | Ignis Innovation Inc. | System and driving method for light emitting device display |
| US8330702B2 (en) * | 2009-02-12 | 2012-12-11 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, display device, and electronic device |
| CN113903796A (en) * | 2009-10-16 | 2022-01-07 | 株式会社半导体能源研究所 | Logic circuit and semiconductor device |
| CN102760407B (en) * | 2012-07-13 | 2015-11-25 | 京东方科技集团股份有限公司 | Emission control circuit, light-emitting control method and shift register |
| TWI497474B (en) * | 2013-12-25 | 2015-08-21 | Au Optronics Corp | Light emitting control circuit |
| CN103985346B (en) * | 2014-05-21 | 2017-02-15 | 上海天马有机发光显示技术有限公司 | TFT array substrate, display panel and display substrate |
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Effective date of registration: 20211104 Address after: No.8, liufangyuan Henglu, Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: WUHAN TIANMA MICRO-ELECTRONICS Co.,Ltd. Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Patentee after: Tianma Micro-Electronics Co.,Ltd. Address before: 201201, 889, Qing Qing Road, Shanghai, Pudong New Area Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd. Patentee before: Tianma Micro-Electronics Co.,Ltd. |