TWI497474B - Light emitting control circuit - Google Patents

Description

Illumination control circuit

The present invention relates to a control circuit, and more particularly to an illumination control circuit for an organic light emitting diode display panel.

Organic Light Emitting Diode (OLED) has the advantages of self-illumination, high response speed, power saving, light weight, wide viewing angle, wide color gamut, low operating voltage, high contrast, etc., and the process is simple and low cost. Applied to the characteristics of flexible panels, it has been regarded as one of the most promising flat display technologies in the future after thin film transistor liquid crystal display (TFT LCD).

OLED displays can be broadly classified into passive matrix OLED displays and active matrix OLED displays. The main driving method of the active matrix OLED display is to use a thin film transistor (TFT) component, and a capacitor is used to store different data voltages, thereby controlling the grayscale of each pixel on the panel. In other words, the driving circuit of the active matrix OLED display provides a plurality of scanning signals to control the capacitance of each pixel to store the corresponding data voltage, and provides a plurality of illuminating signals to control the respective pixels according to the corresponding resources. The material voltage is illuminated. When the driving circuit of the active matrix OLED display provides more control voltage, the circuit design becomes more complicated, which affects the overall design of the display panel.

The invention provides an illumination control circuit which can be designed separately from the gate drive circuit to simplify the design of the drive circuit of the display panel.

The illumination control circuit of the present invention is suitable for an active matrix organic light emitting diode display panel. The illumination control circuit includes a plurality of illumination control units that respectively receive a first clock signal, a second clock signal, a first voltage, and a second voltage. The illuminating control unit is configured to provide a plurality of illuminating signals to the plurality of pixels of the active matrix organic light emitting diode display panel. The first illumination control unit receives an illumination start signal, and the i-th illumination control unit receives the illumination signal provided by the i-1th illumination control unit, where i is a positive integer greater than or equal to 2. The first voltage and the second voltage are respectively one of a gate low voltage and a gate high voltage, and each of the illumination control units is based on the illumination start signal or the illumination signal provided by the i-1th illumination control unit, The first clock signal and the second clock signal determine whether to output the first voltage or the second voltage as the voltage level of the corresponding illuminating signal. The pulse width of the illuminating signal is proportional to the pulse width of the illuminating start signal.

In an embodiment of the invention, the illumination control unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a second transistor. a seventh transistor, an eighth transistor, a first capacitor, and The second capacitor. The first transistor has a first end, a second end, and a control end, wherein the first end of the first transistor receives the first voltage. The second transistor has a first end, a second end, and a control end, wherein the first end of the second transistor is coupled to the second end of the first transistor. The third transistor has a first end, a second end, and a control end, wherein the first end of the third transistor is coupled to the second end of the second transistor, and the second end of the third transistor receives a first end A clock signal, the control end of the third transistor receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit. The fourth transistor has a first end, a second end and a control end, wherein the first end of the fourth transistor receives the first voltage, and the control end of the fourth transistor receives the illumination start signal or the i-1 Illumination signals provided by the illumination control unit. The fifth transistor has a first end, a second end, and a control end, wherein the first end of the fifth transistor is coupled to the second end of the fourth transistor, and the second end of the fifth transistor is coupled to the second end A control end of the transistor, the control end of the fifth transistor is coupled to the control end of the second transistor. The first capacitor is coupled between the first end of the second transistor and the control end. The second capacitor is coupled to the second end of the fifth transistor for receiving the second clock signal. The sixth transistor has a first end, a second end and a control end, wherein the first end of the sixth transistor is coupled to the control end of the second transistor, and the second end of the sixth transistor receives the start of illumination The signal or the illumination signal provided by the i-1th illumination control unit, and the control terminal of the sixth transistor receives the second clock signal. The seventh transistor has a first end, a second end and a control end, wherein the first end of the seventh transistor receives the first voltage, and the second end of the seventh transistor provides a corresponding illuminating signal, the seventh The control end of the crystal is coupled to the control end of the first transistor. The eighth transistor has a first end, a second end and a control end, wherein the first end of the eighth transistor The second end of the eighth transistor receives the second voltage, and the control end of the eighth transistor is coupled to the control end of the second transistor.

In an embodiment of the invention, the illumination control unit further includes a ninth transistor. The ninth transistor has a first end, a second end and a control end, wherein the first end of the ninth transistor receives the first voltage, and the second end of the ninth transistor is coupled to the control end of the second transistor The control end of the ninth transistor is coupled to the control end of the first transistor.

In an embodiment of the invention, the first to the ninth transistors are respectively a P-type transistor, and the first voltage is a gate high voltage and the second voltage is a gate low voltage.

In an embodiment of the invention, the first to ninth transistors are each an N-type transistor, and the first voltage is a gate low voltage and the second voltage is a gate high voltage.

In an embodiment of the invention, the first clock signal and the second clock signal have the same duty cycle and are mutually inverted signals.

Based on the above, in the illumination control circuit of the embodiment of the present invention, each illumination control unit can generate a reference signal required for the operation of the next-stage illumination control unit, that is, the illumination control circuit can operate independently, and thus the illumination control circuit can be coupled to the gate drive circuit. Designed separately to simplify the design of the drive circuit of the display panel.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Active Matrix Organic Light Emitting Diode Display Panel

110‧‧‧ pixel array

111‧‧‧ scan line

113‧‧‧Information line

115‧‧‧Lighting control line

120‧‧‧Drive circuit

121‧‧‧Lighting control circuit

123‧‧‧ gate drive circuit

125, 300, 400, 500‧‧‧Lighting control unit

127‧‧‧Displacement register

130‧‧‧Compensation unit circuit

C1~C2‧‧‧ capacitor

CK1, CK2, CK3, CK4‧‧‧ clock signals

EM, EMa (1), EMa (2), EMb (1), EMb (2), EMC (1), EMC (2), EM (n-1), EM (n) ‧ ‧ illuminating signals

EM_BT, Q‧‧‧ nodes

Idata‧‧‧ data current

M1~M9, M1a~M9a‧‧‧O crystal

MD‧‧‧ drive transistor

OD1‧‧‧Organic Luminescent Diode

OVDD‧‧‧ system high voltage

OVSS‧‧‧ system low voltage

P, PSa~PSc‧‧‧ pulse width

PX‧‧ ‧ pixels

SN‧‧‧ gate drive signal

STV_EM, STV_EMa~STV_EMc‧‧‧Lighting start signal

STV_G‧‧‧ gate start signal

Vdata‧‧‧ data voltage

VGH‧‧‧ gate high voltage

VGL‧‧‧ gate low voltage

FIG. 1A is a schematic diagram of a system of an active matrix organic light emitting diode display panel according to an embodiment of the invention.

1B is a schematic diagram of a pixel circuit in accordance with an embodiment of the present invention.

2A to 2C are waveform diagrams of an illumination start signal, a first clock signal, a second clock signal, and an illumination signal, respectively, according to an embodiment of the invention.

FIG. 3A is a schematic diagram of the system of the illumination control unit of FIG. 1 according to an embodiment of the invention.

FIG. 3B is a schematic diagram of the driving waveform of FIG. 3A according to an embodiment of the invention.

4 is a circuit diagram of an illumination control unit in accordance with another embodiment of the present invention.

FIG. 5 is a circuit diagram of an illumination control unit according to still another embodiment of the present invention.

FIG. 1A is a schematic diagram of a system of an active matrix organic light emitting diode display panel according to an embodiment of the invention. Referring to FIG. 1A , in the embodiment, the active matrix organic light emitting diode display panel 100 includes a pixel array 110 and a driving circuit 120 . The driving circuit 120 includes a light emitting control circuit 121 and a gate driving circuit 123 . The illuminating control circuit 121 is configured to provide a plurality of illuminating signals EM, and the gate driving circuit 123 is configured to provide a plurality of gate driving signals SN.

The pixel array 110 includes a plurality of pixels PX, a plurality of scan lines 111, and a plurality of pixels The data line 113 and the plurality of illumination control lines 115. Each of the scan lines 111 is coupled between the corresponding pixel PX and the gate driving circuit 123 to transmit a corresponding gate driving signal SN to the corresponding pixel PX. Each of the data lines 113 is coupled between the corresponding pixel PX and the source driving circuit (not shown) to transmit the corresponding data voltage Vdata to the corresponding pixel PX. Each of the illumination control lines 115 is coupled between the corresponding pixel PX and the illumination control circuit 121 to transmit a corresponding illumination signal EM to the corresponding pixel PX.

1B is a schematic diagram of a pixel circuit in accordance with an embodiment of the present invention. Referring to FIG. 1B, in the embodiment, the pixel PX includes a compensation circuit 130, a driving transistor MD, and an organic light emitting diode OD1. The compensation circuit 130 receives the system high voltage OVDD, the corresponding gate drive signal SN and the corresponding data voltage Vdata, and generates a data current Idata after the corresponding write voltage compensation of the data voltage Vdata is performed according to the corresponding gate drive signal SN. The first end of the driving transistor MD is coupled to the compensation circuit 130 to receive the data current Idata, the second end of the driving transistor MD is coupled to the anode of the organic light emitting diode OD1, the control terminal end of the driving transistor MD, and the organic light emitting The cathode of the diode OD1 receives the system low voltage OVSS. The driving transistor MD is turned on according to the corresponding illuminating signal EM, so that the organic light emitting diode OD1 emits light corresponding to the data current Idata.

The illumination control circuit 121 includes a plurality of illumination control units 125. These light emission control units 125 receive the clock signals CK1, CK2, the gate low voltage VGL, and the gate high voltage VGH, respectively, and are activated by being controlled by the light emission start signal STV_EM. And, the first illumination control unit 125 receives the illumination initiation signal STV_EM, and the i-th illumination control unit 125 receives the illumination provided by the i-1th illumination control unit 125. The signal EM,i is a positive integer greater than or equal to 2. Then, the first illumination control unit 125 provides the illumination signal EM to the pixel PX on the display panel 100 according to the clock signal CK1, CK2 and the illumination initiation signal STV_EM, that is, the first illumination control unit 125 depends on the clock. The signals CK1, CK2 and the light-emission start signal STV_EM determine the output gate low voltage VGL or the gate high voltage VGL as the voltage level of the corresponding light-emitting signal EM. The other illumination control unit 125 provides the corresponding illumination signal EM to the pixel PX on the display panel 100 according to the clock signal CK1, CK2 and the illumination signal EM provided by the previous illumination control unit 125, that is, the other illumination control unit 125 The output gate low voltage VGL or the gate high voltage VGL is determined as the voltage level of the corresponding light-emitting signal EM according to the clock signal CK1, CK2 and the light-emitting signal EM provided by the previous light-emitting control unit 125.

The gate drive circuit 123 includes a plurality of shift registers 127. The shift registers 127 receive the clock signals CK3, CK4, the gate low voltage VGL, and the gate high voltage VGH, respectively, and are controlled by the gate start signal STV_G. Then, the shift registers 127 provide the gate drive signal SN to the pixels PX on the display panel 100 according to the clock signals CK3 and CK4. The shift register 127 determines the output clock signal CK3 or CK4 as the corresponding gate drive signal SN according to the clock signals CK3 and CK4, and the clock signals CK3 and CK4 are mutually inverted signals. Moreover, the first shift register 127 receives the gate start signal STV_G, and the i-th shift register 127 receives the gate drive signal SN provided by the i-1th shift register 127.

According to the above, the operation and the gate of the illumination control circuit 121 of the embodiment The operation of the driving circuit 123 is irrelevant, that is, the illuminating control circuit 121 can operate independently. Therefore, the design of the illuminating control circuit 121 of the present embodiment can be simplified, and the circuit area of the illuminating control circuit 121 can be reduced.

2A to 2C are waveform diagrams of an illumination start signal, a first clock signal, a second clock signal, and an illumination signal, respectively, according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 2A to FIG. 2C, wherein the same or similar elements are given the same or similar reference numerals. In this embodiment, the pulse widths of the clock signals CK1 and CK2 are P, and the duty cycles of the immediate pulse signals CK1 and CK2 are the same, wherein the pulse width P can be equal to one horizontal scanning period. Also, the pulse width of the illuminating signal EM may be proportional to the pulse width of the illuminating start signal STV_EM.

Taking FIG. 2A as an example, the duty cycle of the clock signals CK1 and CK2 is 1/4 (ie, 25%), and the pulse width PSa of the light-emission start signal STV_EMa is 4P, for example, four horizontal scanning periods. At this time, the pulse widths of the light-emission signals EMa(1) and ECam(2) are 4P, for example, four horizontal scanning periods. Further, the displacement (or delay time) between the light-emission signals EMa(1) and ECam(2) is 2P, for example, two horizontal scanning periods.

Taking FIG. 2B as an example, the pulse width PSb of the light emission start signal ST_EMb is 8P, for example, 8 horizontal scanning periods. At this time, the pulse widths of the light-emission signals EMb(1) and EMb(2) are 8P, for example, eight horizontal scanning periods. Further, the displacement (or delay time) between the luminescence signals EMb(1) and EMb(2) is 2P, for example, two horizontal scanning periods.

Taking FIG. 2C as an example, the pulse width PSc of the light-emission start signal STV_EMc It is 12P, for example 12 horizontal scanning periods. At this time, the pulse widths of the light-emission signals EMc(1) and ECu(2) are 12P, for example, 12 horizontal scanning periods. Further, the displacement (or delay time) between the light-emission signals EMc(1) and Emc(2) is 2P, for example, two horizontal scanning periods.

The adjustment of the pulse width of the illuminating signal EM and the displacement of the illuminating signal EM may be determined by the design of the pixel array (eg, 110), and is not limited thereto.

FIG. 3A is a schematic diagram of the system of the illumination control unit of FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 3A , the illumination control unit 125 may be the illumination control unit 300 . In this embodiment, the illumination control unit 300 includes transistors M1 M M9 (corresponding to the first transistor to the ninth transistor) and capacitors C1 C C2 (corresponding to the first capacitor and the second capacitor), wherein the transistors M1 M M9 Each is, for example, a P-type transistor.

The source (corresponding to the first end) of the transistor M1 receives the gate high voltage VGH (corresponding to the first voltage). The source of the transistor M2 is coupled to the drain of the transistor M1 (corresponding to the second end). The source of the transistor M3 is coupled to the drain of the transistor M2, the drain of the transistor M3 receives the clock signal CK2 or CK1, and the gate of the transistor M3 (corresponding to the control terminal) receives the light-emitting start signal STV_EM or the n-th The illumination signal EM(n-1) provided by one illumination control unit 300, where n is a positive integer.

The source of the transistor M4 receives the gate high voltage VGH, and the gate of the transistor M4 receives the light emission start signal STV_EM or the light emission signal EM(n-1). The source of the transistor M5 is coupled to the drain of the transistor M4, the gate of the transistor M5 is coupled to the gate of the transistor M1, and the gate of the transistor M5 is coupled to the gate of the transistor M2. Capacitor C1 is coupled Between the source and the gate of the transistor M2. One end of the capacitor C2 is coupled to the drain of the transistor M5, and the other end of the capacitor C2 receives the clock signal CK1 or CK2.

The source of the transistor M6 is coupled to the gate of the transistor M2, the drain of the transistor M6 receives the light-emitting start signal STV_EM or the light-emitting signal EM(n-1), and the gate of the transistor M6 receives the clock signal CK1 or CK2 . The source of the transistor M7 receives the gate high voltage VGH, the drain of the transistor M7 provides a corresponding illuminating signal EM(n), and the gate of the transistor M7 is coupled to the gate of the transistor M1. The source terminal of the transistor M8 is coupled to the drain of the transistor M7, the drain of the transistor M8 receives the gate low voltage VGL (corresponding to the second voltage), and the gate of the transistor M8 is coupled to the gate of the transistor M2.

The source of the transistor M9 receives the gate high voltage VGH, the gate of the transistor M9 is coupled to the gate of the transistor M2, and the gate of the transistor M9 is coupled to the gate of the transistor M1.

In this embodiment, when the drain of the transistor M3 receives the clock signal CK2, the gates of the capacitor C2 and the transistor M6 receive the clock signal CK1; conversely, when the drain of the transistor M3 receives the clock signal CK1. The gate of the capacitor C2 and the transistor M6 receives the clock signal CK2.

FIG. 3B is a schematic diagram of the driving waveform of FIG. 3A according to an embodiment of the invention. Referring to FIG. 3A and FIG. 3B , the first light-emitting control unit 300 is taken as an example, that is, the transistors M3 and M4 receive the light-emission start signal STV_EM, and the capacitor is assumed to receive the clock signal CK2 when the drain of the transistor M3 is received. The gate of C2 and transistor M6 receives the clock signal CK1.

In the period P1, the light emission start signal STV_EM is at a low voltage level. Therefore, the transistors M3 and M4 are turned on. The clock signal CK1 for the low voltage level is energized to the crystal M6 to pull down the voltage level of the node EM_BT to the low voltage level. At this time, the transistors M2, M5 and M8 will be turned on, so that the voltage level of the node Q will be pulled up to the gate high voltage VGH (which can be regarded as a high voltage level), and the gate low voltage VGL will be output as a light-emitting signal. The voltage level of EM(n) (which can be regarded as low voltage level), and capacitor C1 will be charged. In addition, the voltage across the capacitor C2 is reduced or eliminated by the high voltage level clock signal CK1 and the gate high voltage VGH. Among them, the transistors M1, M7 and M9 will not conduct.

In the period P2, the light-emission start signal STV_EM is at a high voltage level, and thus the transistors M3 and M4 are not turned on. Moreover, by the voltage across the capacitor C1, the voltage level of the node EM_BT maintains a low voltage level, and the voltage level of the node Q is maintained at a high voltage level by the high voltage level clock signal CK1, wherein the node The voltage level of EM_BT is pulled low by the low voltage level clock signal CK2. At this time, the gate low voltage VGL is still output as the voltage level of the light-emitting signal EM(n) (which can be regarded as a low voltage level).

In the period P3, the light-emission start signal STV_EM is at a high voltage level, so the transistors M3 and M4 are not turned on. The clock signal CK1, which is at a low voltage level, pulls down the voltage level of the node Q, and the transistor M6 is turned on, so that the voltage level of the node EM_BT is pulled high to the high voltage level. At this time, the transistors M1, M7 and M9 are turned on to further increase the voltage level of the node EM_BT to a high voltage level, eliminating the voltage across the capacitor C1, and outputting the gate low voltage VGL as the illuminating signal EM(n). Voltage level (can be regarded as high voltage level). And, the transistor M1 M7 and M9 are controlled by the voltage level of the node EM_BT of the high voltage level to the high voltage level and are not turned on.

In the period P4, the light-emission start signal STV_EM is at a low voltage level, so the transistors M3 and M4 are turned on. The clock signal CK1 at the high voltage level will be at the high and low voltage levels of the node Q, so that the transistors M1, M7 and M9 will not conduct, and the transistor M6 will not conduct. At this time, the voltage level of the node EM_BT is maintained at a high voltage level, so that the transistors M2 and M8 are not turned on. Due to the influence of the equivalent capacitance, the voltage level of the illuminating signal EM(n) is maintained at a high voltage level.

In the period P5, it is similar to the action in the period P1, and the action described later can be deduced by analogy, and will not be described again here.

4 is a circuit diagram of an illumination control unit in accordance with another embodiment of the present invention. Referring to FIG. 3A and FIG. 4, in the present embodiment, the illumination control unit 400 is substantially the same as the illumination control unit 300, except that the transistor M9 is omitted, but the circuit of the control unit 400 operates the same as the illumination control unit 300. Where the same or similar elements are given the same or similar reference numerals.

FIG. 5 is a circuit diagram of an illumination control unit according to still another embodiment of the present invention. Referring to FIG. 3A and FIG. 5, the circuit structure of the illumination control unit 500 is substantially the same as that of the illumination control unit 300, except that the transistors M1a to M9a are respectively an N-type transistor, and the transistors M1a, M4a, M7a and M9a The source receives the gate low voltage VGL (corresponding to the first voltage), and the drain of the transistor M8a receives the gate high voltage VGH (corresponding to the second voltage). In the present embodiment, the circuit of the control unit 500 operates the same as the illumination control unit 300, in which the same or similar components use the same Or similar label.

In summary, in the illumination control circuit of the embodiment of the invention, each illumination control unit can generate a reference signal required for the operation of the next-level illumination control unit, that is, the illumination control circuit can operate independently, and thus can be separated from the gate drive circuit. Designed to simplify the design of the drive circuit of the display panel. Moreover, the pulse width of the illuminating signal can be changed according to the pulse width of the illuminating start signal, and therefore can be adjusted according to the pixel configuration of the display panel to increase the commonality of the illuminating control circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Active Matrix Organic Light Emitting Diode Display Panel

110‧‧‧ pixel array

111‧‧‧ scan line

113‧‧‧Information line

115‧‧‧Lighting control line

120‧‧‧Drive circuit

121‧‧‧Lighting control circuit

123‧‧‧ gate drive circuit

125‧‧‧Lighting control unit

127‧‧‧Displacement register

CK1, CK2, CK3, CK4‧‧‧ clock signals

EM‧‧‧ illuminating signal

PX‧‧ ‧ pixels

SN‧‧‧ gate drive signal

STV_EM‧‧‧Lighting start signal

STV_G‧‧‧ gate start signal

Vdata‧‧‧ data voltage

VGH‧‧‧ gate high voltage

VGL‧‧‧ gate low voltage

Claims (6)

An illumination control circuit is applicable to an active matrix organic light emitting diode display panel, comprising: a plurality of illumination control units respectively receiving a first clock signal, a second clock signal, a first voltage and a second And a plurality of pixels for providing a plurality of illuminating signals to the active matrix OLED display panel, wherein the first illuminating control unit receives an illuminating start signal, and the ith illuminating control unit receives the ith - an illumination signal provided by the illumination control unit, i is a positive integer greater than or equal to 2, and the first voltage and the second voltage are respectively one of a gate low voltage and a gate high voltage, and each The illumination control unit determines to output the first voltage or the second according to the illumination start signal or the illumination signal provided by the i-1th illumination control unit, the first clock signal, and the second clock signal. The voltage is a voltage level of the corresponding illuminating signal, and the pulse width of the illuminating signals is proportional to the pulse width of the illuminating start signal. The illuminating control circuit of claim 1, wherein each of the illuminating control units comprises: a first transistor having a first end, a second end, and a control end, the first transistor The first end receives the first voltage; a second transistor has a first end, a second end, and a control end, the first end of the second transistor is coupled to the first transistor a second end; a third transistor having a first end, a second end, and a control end, the first end of the third transistor being coupled to the second end of the second transistor, the third Transistor The second end receives a first clock signal, the control end of the third transistor receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit; and a fourth transistor has a a first end, a second end, and a control end, the first end of the fourth transistor receives the first voltage, and the control end of the fourth transistor receives the illuminating start signal or the i-1th a illuminating signal provided by the illuminating control unit; a fifth transistor having a first end, a second end, and a control end, the first end of the fifth transistor being coupled to the first end of the fourth transistor The second end of the second transistor is coupled to the control end of the first transistor, the control end of the fifth transistor is coupled to the control end of the second transistor; a first capacitor The second end of the second transistor is coupled to the second end of the fifth transistor for receiving the second clock signal; a sixth transistor having a first end, a second end, and a control end, wherein the first end of the sixth transistor is coupled to the first The control end of the sixth transistor receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit, and the control end of the sixth transistor receives the first a second transistor having a first end, a second end, and a control end, the first end of the seventh transistor receiving the first voltage, the first of the seventh transistor The second end provides a corresponding illuminating signal, the control end of the seventh transistor is coupled to the control end of the first transistor; and an eighth transistor has a first end, a second end, and a control end , the first The first end of the eighth transistor is coupled to the second end of the seventh transistor, the second end of the eighth transistor receives the second voltage, and the control end of the eighth transistor is coupled to the second end The control end of the second transistor. The illuminating control circuit of claim 2, wherein each of the illuminating control units further comprises: a ninth transistor having a first end, a second end and a control end, the ninth transistor The first end receives the first voltage, the second end of the ninth transistor is coupled to the control end of the second transistor, and the control end of the ninth transistor is coupled to the first transistor The console. The illuminating control circuit of claim 3, wherein the first to the ninth transistors are respectively a P-type transistor, and the first voltage is a high voltage, and the second voltage is a low voltage. . The illuminating control circuit of claim 3, wherein the first to the ninth transistors are respectively an N-type transistor, and the first voltage is a low voltage, and the second voltage is a high voltage. . The illumination control circuit of claim 1, wherein the first clock signal and the second clock signal have the same duty cycle and are mutually inverted signals.