TWI525596B - Light emitting control circuit, driving circuit using the same and active matrix oled display panel using the same - Google Patents

Description

Light-emitting control circuit, driving circuit thereof and active matrix organic light-emitting Diode display panel

The present invention relates to a control circuit, and more particularly to an illumination control circuit, a drive circuit thereof, and an active matrix organic light emitting diode display panel thereof.

Since 1987, the United States Kodak Company has published a practical potential of Organic Light Emitting Diode (OLED) components, which has attracted many manufacturers to invest in OLED display research and mass production, which has been regarded as a thin film transistor liquid crystal. After the thin film transistor liquid crystal display (TFT LCD), one of the most promising flat display technologies in the future. Among them, OLED has the advantages of self-illumination, high response speed characteristics, power saving, light weight, wide viewing angle, wide color gamut, low operating voltage, high contrast, etc., and the process is simple and low-cost, and can be applied to flexural panels and the like.

OLED displays can be broadly classified into passive matrix OLED displays and active matrix OLED displays. initiative The main driving method of the matrix OLED display is to use a thin film transistor (TFT) component, and a capacitor is used to store different data voltages, thereby controlling the grayscale of each pixel on the panel. In other words, the driving circuit of the active matrix OLED display provides a plurality of scanning signals to control the capacitance of the respective pixels to store the corresponding data voltage, and provides a plurality of lighting signals to control the respective pixels to emit light according to the corresponding data voltage. When the driving circuit of the active matrix OLED display provides more control voltage, the circuit area thereof is larger, so that the frame width of the display panel is affected. Therefore, the design of the driving circuit of the active matrix OLED display greatly affects the size of the display panel.

The invention provides an illumination control circuit, a driving circuit thereof and an active matrix organic light emitting diode display panel thereof, which can separate a gate driving circuit and an illumination control circuit of the driving circuit to reduce the circuit area of the driving circuit.

The illumination control circuit of the present invention is suitable for an Active Matrix Organic Light Emitting Diodes (AMOLED) display panel. The illumination control circuit includes a plurality of illumination control units. The illumination control unit receives a first clock signal, a second clock signal, a gate low voltage and a gate high voltage, and is configured to provide a plurality of illumination signals to the active matrix organic light emitting diode display panel. Multiple pixels. Each of the illumination control units determines an output gate low voltage or a gate high voltage as a voltage level of the corresponding illumination signal according to the first clock signal and the second clock signal.

The driving circuit of the present invention is suitable for an active matrix organic light emitting diode display panel. The driving circuit includes the above-mentioned lighting control circuit and a gate driving circuit. The gate drive circuit includes a plurality of shift registers. The shift registers respectively receive a third clock signal, a fourth clock signal, a gate low voltage, and a gate high voltage, and are configured to provide a plurality of gate driving signals to the pixels.

The active matrix organic light emitting diode display panel of the present invention includes a plurality of pixels and the above light emission control circuit.

In an embodiment of the invention, the first illumination control unit receives an illumination start signal, and the i-th illumination control unit receives the illumination signal provided by the i-1th illumination control unit, where i is greater than or equal to Integer.

In an embodiment of the invention, each of the illumination control units includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a logic control unit. The first transistor has a first end, a second end and a first control end, wherein the first end receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit, and the first control terminal receives The first clock signal. The second transistor has a third end, a fourth end and a second control end, wherein the third end receives the gate low voltage, the fourth end provides a corresponding illumination signal, and the second control end is coupled to the second end. The third transistor has a fifth end, a sixth end and a third control end, wherein the fifth end is coupled to the second end, the sixth end receives the gate high voltage, and the third control end receives a logic control signal. The fourth transistor has a seventh end, an eighth end and a fourth control end, wherein the seventh end is coupled to the fourth end, the eighth end receives the gate high voltage, and the fourth control end receives the logic control signal. The first capacitor is coupled to the second clock signal and the second control Between the ends. The logic control unit receives at least one reference signal and is coupled to the third control terminal and the fourth control terminal to provide a logic control signal.

In an embodiment of the invention, the reference signal includes an illumination start signal or an illumination signal provided by the i-1th illumination control unit, and the first clock signal.

In an embodiment of the invention, the logic control unit includes a fifth transistor, a sixth transistor, a seventh transistor, and a second capacitor. The fifth transistor has a ninth end, a tenth end and a fifth control end, wherein the tenth end receives the gate high voltage, and the fifth control end receives the illumination start signal or the i-1th illumination control unit The illuminating signal provided. The sixth transistor has an eleventh end, a twelfth end and a sixth control end, wherein the eleventh end receives the gate low voltage, the twelfth end provides a logic control signal, and the sixth control end is coupled to the first Nine-end. The seventh transistor has a thirteenth end, a fourteenth end and a seventh control end, wherein the thirteenth end is coupled to the twelfth end, the fourteenth end receives the gate high voltage, and the seventh control end receives The illumination start signal or the illumination signal provided by the i-1th illumination control unit. The second capacitor is coupled between the first clock signal and the ninth end.

In an embodiment of the invention, the fifth control end and the seventh control end are coupled to the second end.

In an embodiment of the invention, the fifth control end and the seventh control end are coupled to the first end.

In an embodiment of the invention, the fifth control end is coupled to the first end, and the seventh control end is coupled to the second end.

In an embodiment of the invention, the logic control unit further includes an eighth power Crystal and a third capacitor. The eighth transistor has a fifteenth end, a sixteenth end and an eighth control end, wherein the fifteenth end is coupled to the first end, and the sixteenth end is coupled to the fifth control end and the seventh control end, The eighth control terminal receives the second clock signal. The third capacitor is coupled between the fifth control terminal and the gate high voltage.

In an embodiment of the invention, the first clock signal and the second clock signal have the same duty cycle.

In an embodiment of the invention, the pulse width of the illuminating signals is inversely proportional to the operating ratio of the first clock signal.

In an embodiment of the invention, the pulse width of the illuminating signals is proportional to the pulse width of the illuminating start signal.

In an embodiment of the invention, each pixel includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth A transistor, an organic light emitting diode, and a storage capacitor. The ninth transistor has a seventeenth end, an eighteenth end and a ninth control end, wherein the eighteenth end receives an initial voltage, and the ninth control end receives a first scan signal. The tenth transistor has a nineteenth end, a second ten end and a tenth control end, wherein the nineteenth end receives a system high voltage, and the tenth control end receives the corresponding illuminating signal. The eleventh transistor has a second eleven end, a second twelve end and an eleventh control end, wherein the twenty first end is coupled to the twentieth end, and the eleventh control end is coupled to the seventeenth end end. The twelfth transistor has a second thirteen end, a second fourteen end, and a twelfth control end, wherein the twenty-third end is coupled to the eleven control end, and the twenty-fourth end is coupled to the twentieth end The second end, the twelfth control end receives a second scan signal. The thirteenth transistor has a second ten a fifth end, a twenty-sixth end and a thirteenth control end, wherein the twenty-fifth end is coupled to the twentieth end, the twenty-sixth end receives a data voltage, and the thirteenth control end receives the second scan signal . The fourteenth transistor has a twenty-seventh end, a twenty-eighth end and a fourteenth control end, wherein the twenty-seventh end is coupled to the twenty-second end, and the fourteenth control end receives the corresponding illumination signal. The anode of the organic light emitting diode is coupled to the twenty-eighth end, and the cathode of the organic light emitting diode receives a system low voltage. The storage capacitor is coupled between the high voltage of the system and the seventeenth end.

Based on the above, the illumination control circuit, the drive circuit thereof and the active matrix organic light emitting diode display panel of the embodiment of the invention separate the gate drive circuit and the illumination control circuit of the drive circuit to reduce the circuit area of the drive circuit.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Active Matrix Organic Light Emitting Diode Display Panel

110‧‧‧ pixel array

111‧‧‧ scan line

113‧‧‧Multiple data lines

115‧‧‧Lighting control line

120‧‧‧Drive circuit

121‧‧‧Lighting control circuit

123‧‧‧ gate drive circuit

125‧‧‧Lighting control unit

127‧‧‧Displacement register

410, 410a~410d‧‧‧ logical control unit

C1~C3‧‧‧ capacitor

CK1~CK4, CK1a~CK1c, CK2a~CK2c‧‧‧ clock signals

Cst‧‧‧ storage capacitor

EM, EM(n), EM(n-1), EMa(n), EMa(n+1), EMb(n), EMb(n+1), Emc(n), EMC(n+1), EMd(1), EMd(2), EMe(1), EMe(2), EMf(1), EMf(2)‧ ‧Lighting signal

M1~M14, M5a~M5c, M7a, M7c‧‧‧O crystal

OD1‧‧‧Organic Luminescent Diode

OVDD‧‧‧ system high voltage

OVSS‧‧‧ system low voltage

P, PSa~PSc‧‧‧ pulse width

PX, PXa‧‧ ‧ pixels

SLC‧‧‧Logical Control Signal

SN1, SN2‧‧‧ gate drive signal

SRE‧‧‧ reference signal

STVG‧‧‧ gate start signal

STVL, STVLa~STVLc‧‧‧Lighting start signal

Vdata‧‧‧ data voltage

VGH‧‧‧ gate high voltage

VGL‧‧‧ gate low voltage

Vint‧‧‧ initial voltage

FIG. 1 is a schematic diagram of a system of an active matrix organic light emitting diode display panel according to an embodiment of the invention.

2A to 2C are waveform diagrams of a first clock signal, a second clock signal, and an illumination signal, respectively, according to an embodiment of the invention.

3A to 3C are waveform diagrams of an illumination start signal, a first clock signal, a second clock signal, and an illumination signal, respectively, according to an embodiment of the invention.

4 is a schematic diagram of a system of an illumination control unit according to an embodiment of the invention; Figure.

5A to 5D are respectively circuit diagrams of the illumination control unit of FIG. 4 according to an embodiment of the invention.

FIG. 6 is a circuit diagram of the pixel of FIG. 1 according to an embodiment of the invention.

FIG. 1 is a schematic diagram of a system of an active matrix organic light emitting diode display panel according to an embodiment of the invention. Referring to FIG. 1 , in the embodiment, the active matrix organic light emitting diode display panel 100 includes a pixel array 110 and a driving circuit 120 . The driving circuit 120 includes a light emitting control circuit 121 and a gate driving circuit 123 . The illumination control circuit 121 is configured to provide a plurality of illumination signals EM, and the gate drive circuit 123 is configured to provide a plurality of gate drive signals (eg, SN1, SN2).

The pixel array 110 includes a plurality of pixels PX, a plurality of scan lines 111, a plurality of data lines 113, and a plurality of light emission control lines 115. Each of the scan lines 111 is coupled between the corresponding pixel PX and the gate drive circuit 123 to transmit a corresponding gate drive signal (such as SN1, SN2) to the corresponding pixel PX. Each of the data lines 113 is coupled between the corresponding pixel PX and the source driving circuit (not shown) to transmit the corresponding data voltage Vdata to the corresponding pixel PX. Each of the illumination control lines 115 is coupled between the corresponding pixel PX and the illumination control circuit 121 to transmit a corresponding illumination signal EM to the corresponding pixel PX.

The illumination control circuit 121 includes a plurality of illumination control units 125. The illumination control unit 125 receives the clock signals CK1, CK2, the gate low voltage VGL, and The gate is high voltage VGH and is activated by being controlled by the light emission start signal STVL. Next, the illumination control unit 125 provides the illumination signal EM to the pixel PX on the display panel 100 according to the clock signals CK1, CK2. The illumination control unit 125 determines the output gate low voltage VGL or the gate high voltage VGL as the voltage level of the corresponding illumination signal EM according to the clock signals CK1 and CK2. Further, the first illumination control unit 125 receives the illumination start signal STVL, and the i-th illumination control unit 125 receives the illumination signal EM, i provided by the i-1th illumination control unit 125, which is a positive integer greater than or equal to 2.

The gate drive circuit 123 includes a plurality of shift registers 127. The shift registers 127 receive the clock signals CK3, CK4, the gate low voltage VGL, and the gate high voltage VGH, respectively, and are controlled by the gate start signal STVG. Then, the shift registers 127 provide gate drive signals (such as SN1, SN2) to the pixels PX on the display panel 100 according to the clock signals CK3 and CK4. The shift register 127 determines the output clock signal CK3 or CK4 as the corresponding gate drive signal (such as SN1 and SN2) according to the clock signals CK3 and CK4, and the clock signals CK3 and CK4 are mutually inverted signals. . Moreover, the first shift register 127 receives the gate start signal STVG, and the i-th shift register 127 receives the gate drive signal (such as SN1, SN2) provided by the i-1th shift register 127. .

According to the above, the operation of the illumination control circuit 121 of the present embodiment is not related to the operation of the gate driving circuit 123, that is, the illumination control circuit 121 can operate independently. Therefore, the design of the illumination control circuit 121 of the present embodiment can be simplified. The circuit area of the light emission control circuit 121 is lowered.

2A to 2C are waveform diagrams of a first clock signal, a second clock signal, and an illumination signal, respectively, according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 2A to FIG. 2C, wherein the same or similar elements are given the same or similar reference numerals. In this embodiment, the pulse widths of the clock signals CK1 and CK2 are P, and the duty cycles of the immediate pulse signals CK1 and CK2 are the same, wherein the pulse width P can be the same as one horizontal scanning period. Further, the pulse width of the illuminating signal EM is inversely proportional to the duty ratio of the clock signal CK1 or CK2.

Taking FIG. 2A as an example, the duty ratios of the clock signals CK1a and CK2a are 1/2 (ie, 50%). At this time, the pulse widths of the light-emission signals EMa(n) and EMa(n+1) are two P, for example, two horizontal scanning periods. Further, the displacement (or delay time) between the light-emission signals EMa(n) and EMa(n+1) is one P, for example, one horizontal scanning period. Where n is a positive integer.

Taking FIG. 2B as an example, the duty ratio of the clock signals CK1b and CK2b is 1/4 (ie, 25%). At this time, the pulse widths of the light-emission signals EMb(n) and EMb(n+1) are four P, for example, four horizontal scanning periods. Further, the displacement (or delay time) between the luminescence signals EMb(n) and EMb(n+1) is two P, for example, two horizontal scanning periods.

Taking FIG. 2C as an example, the duty ratio of the clock signals CK1c and CK2c is 1/6 (ie, 16.7%). At this time, the pulse widths of the light-emission signals EMc(n) and Emc(n+1) are six P, for example, six horizontal scanning periods. Further, the displacement (or delay time) between the light-emission signals EMc(n) and Emc(n+1) is three P, for example, three horizontal scanning periods.

The adjustment of the pulse width of the illuminating signal EM depends on the design of the pixel array (eg, 110). For example, if a single illuminating signal EM corresponds to a single row of paintings For the PX, the illuminating signals EMa(n) and EMa(n+1) can be used to drive the pixels PX; if the single illuminating signal EM corresponds to the double-row pixels PX, the illuminating signals EMb(n) and EMb(n) can be used. +1) to drive the pixel PX; if the single illuminating signal EM corresponds to the three columns of pixels PX, the illuminating signals EMc(n) and Emc(n+1) can be used to drive the pixel PX, and the rest can be deduced by Therefore, the description of the present invention is not limited thereto.

3A to 3C are waveform diagrams of an illumination start signal, a first clock signal, a second clock signal, and an illumination signal, respectively, according to an embodiment of the invention. Please refer to FIG. 1, FIG. 2C and FIG. 3A to FIG. 3C, wherein the same or similar elements are given the same or similar reference numerals. In the present embodiment, the pulse width of the light-emission signal EM is proportional to the pulse width of the light-emission start signal STVL.

Taking FIG. 3A as an example, the duty ratio of the clock signals CK1c and CK2c is 1/6 (ie, 16.7%), and the pulse width PSa of the light-emission start signal STVLa is 6 P, for example, 6 horizontal scanning periods. At this time, the pulse widths of the light-emission signals EMd(1) and EMd(2) are six P, for example, six horizontal scanning periods. Further, the displacement (or delay time) between the luminescence signals EMd(1) and EMd(2) is 3 P, for example, three horizontal scanning periods.

Taking FIG. 3B as an example, the pulse width PSb of the light emission start signal STVLb is 12 P, for example, 12 horizontal scanning periods. At this time, the pulse widths of the light-emission signals EMe(1) and EMe(2) are 12 P, for example, 12 horizontal scanning periods. Further, the displacement (or delay time) between the luminescence signals EMe(1) and EMe(2) is 3 P, for example, three horizontal scanning periods.

Taking FIG. 3C as an example, the pulse width PSc of the light-emission start signal STVLc is 18 P, for example 18 horizontal scanning periods. At this time, the pulse widths of the light-emission signals EMf(1) and EMf(2) are 18 P, for example, 18 horizontal scanning periods. Further, the displacement (or delay time) between the luminescence signals EMf(1) and EMf(2) is 3 P, for example, three horizontal scanning periods.

4 is a schematic diagram of the system of the illumination control unit of FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 4, in the present embodiment, the illumination control unit 125 may be an illumination control unit 400, wherein the same or similar elements use the same or similar reference numerals, and the illumination control unit 125 includes transistors M1 to M4 (corresponding to the first A transistor to the fourth transistor), a capacitor C1, and a logic control unit 410. The transistors M1 to M4 are exemplified by a P-type transistor, but the embodiment of the present invention is not limited thereto.

The source (corresponding to the first end) of the transistor M1 receives the illumination start signal STVL or the illumination signal EM(n-1) provided by the n-1th illumination control unit 125, and the gate of the transistor M1 (corresponding to the first The control terminal receives the clock signal CK1 or CK2. The source (corresponding to the third end) of the transistor M2 receives the gate low voltage VGL, and the drain of the transistor M2 (corresponding to the fourth end) provides a corresponding illuminating signal EM(n), the gate of the transistor M2 (corresponding to the first The second control end is coupled to the drain of the transistor M1 (corresponding to the second end). The source of the transistor M3 (corresponding to the fifth end) is coupled to the drain of the transistor M1, the drain of the transistor M3 (corresponding to the sixth end) receives the gate high voltage VGH, and the gate of the transistor M3 (corresponding to the third The control terminal receives the logic control signal SLC provided by the logic control unit 410.

The source (corresponding to the seventh end) of the transistor M4 is coupled to the drain of the transistor M2, and the drain of the transistor M4 (corresponding to the eighth end) receives the gate high voltage VGH, the transistor The gate of M4 (corresponding to the fourth control terminal) receives the logic control signal SLC. The capacitor C1 is coupled between the clock signal CK2 or CK1 and the gate of the transistor M2. The logic control unit 410 receives at least one reference signal SRE and couples the gates of the transistors M3 and M4 to provide a logic control signal SLC. The reference signal SRE may include one or a part of the illuminating start signal STVL, the illuminating signal EM(n-1) provided by the n-1th illuminating control unit 125, and the clock signals CK2 and CK1, which may be based on It is usually set by the person skilled in the art.

In this embodiment, when the gate of the transistor M1 receives the clock signal CK1, the capacitor C1 receives the clock signal CK2; conversely, when the gate of the transistor M1 receives the clock signal CK2, the capacitor C1 receives the clock signal. CK1.

5A to 5D are respectively circuit diagrams of the illumination control unit of FIG. 4 according to an embodiment of the invention. Please refer to FIG. 1, FIG. 4 and FIGS. 5A to 5D, wherein the same or similar elements are given the same or similar reference numerals. In the present embodiment, the reference signal SRE includes a light-emission start signal STVL or a light-emission signal EM(n-1), and a clock signal CK1 or CK2.

Taking FIG. 5A as an example, the logic control unit 410a includes transistors M5 to M7 (corresponding to the fifth to seventh transistors) and a capacitor C2. The transistors M5 to M7 are exemplified by a P-type transistor, but the embodiment of the present invention is not limited thereto. The drain of the transistor M5 (corresponding to the tenth end) receives the gate high voltage VGH, and the gate of the transistor M5 (corresponding to the fifth control terminal) is coupled to the drain of the transistor M1 to receive light through the conductive transistor M1. Start signal STVL or illuminating signal EM(n-1). The source of the transistor M6 (corresponding to the eleventh end) receives the gate low voltage VGL, and the drain of the transistor M6 (corresponding to the twelfth end) A logic control signal SLC is provided, and the gate of the transistor M6 (corresponding to the sixth control terminal) is coupled to the source of the transistor M5 (corresponding to the ninth terminal). The source of the transistor M7 (corresponding to the thirteenth end) is coupled to the drain of the transistor M6, and the drain of the transistor M7 (corresponding to the fourteenth end) receives the gate high voltage VGH, and the gate of the transistor M7 (corresponding The seventh control terminal is coupled to the drain of the transistor M1 to receive the light emission start signal STVL or the light emission signal EM(n-1) through the turned-on transistor M1. The capacitor C2 is coupled between the clock signal CK1 or CK2 and the source of the transistor M5.

In this embodiment, when the gate of the transistor M1 receives the clock signal CK1, the capacitor C1 receives the clock signal CK2, and the capacitor C2 receives the clock signal CK1; conversely, when the gate of the transistor M1 receives the clock signal CK2 When the capacitor C1 receives the clock signal CK1, the capacitor C2 receives the clock signal CK2.

According to the embodiment shown in FIG. 5A and FIG. 5B, the logic control unit 410b is different from the logic control unit 410a in the transistors M5a and M7a, wherein the gates of the transistors M5a and M7a are coupled to the source of the transistor M1 to receive the light. Start signal STVL or illuminating signal EM(n-1).

According to the embodiment shown in FIG. 5A and FIG. 5C, the logic control unit 410c is different from the logic control unit 410a in the transistor M5b, wherein the gate of the transistor M5b is coupled to the source of the transistor M1 to receive the light-emission start signal STVL. Or the illuminating signal EM(n-1). At this time, the gate voltage changes of the transistors M6 and M7 are relatively uniform, that is, the voltage level switching speed of the logic control signal SLC is faster, thereby reducing the chance of the operation of the illumination control unit 125.

According to the embodiment shown in FIG. 5A and FIG. 5D, the logic control unit 410d and The logic control unit 410a is different in that it further includes a transistor M8 and a capacitor C3. The transistor M8 is exemplified by a P-type transistor, but the embodiment of the present invention is not limited thereto. The source of the transistor M8 (corresponding to the fifteenth end) is coupled to the source of the transistor M1, and the drain of the transistor M8 (corresponding to the sixteenth end) is coupled to the gates of the transistors M5c and M7c, and the transistor M8 The gate (corresponding to the eighth control terminal) receives the clock signal CK2 or CK1. The capacitor C3 is coupled between the gate of the transistor M5c and the gate high voltage VGH. The gates of the transistors M5c and M7c receive the light-emission start signal STVL or the light-emission signal EM(n-1) through the turned-on transistor M8. In this embodiment, when the gate of the transistor M1 receives the clock signal CK1, the capacitor C1 receives the clock signal CK2, the capacitor C2 receives the clock signal CK1, and the gate of the transistor M8 receives the clock signal CK2; When the gate of the transistor M1 receives the clock signal CK2, the capacitor C1 receives the clock signal CK1, the capacitor C2 receives the clock signal CK2, and the gate of the transistor M8 receives the clock signal CK1.

FIG. 6 is a circuit diagram of the pixel of FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 6, the pixel PX may be a pixel PXa. In this embodiment, the pixel PXa includes transistors M9-M14 (corresponding to the ninth to fourteenth transistors), a storage capacitor Cst, and an organic light emitting diode OD1, wherein the transistors M9 to M14 are P-type transistors. For example, the embodiment of the present invention is not limited thereto.

The drain of the transistor M9 (corresponding to the eighteenth end) receives the initial voltage Vint, and the gate of the transistor M9 (corresponding to the ninth control terminal) receives the corresponding scan signal SN1. The source of the transistor M10 (corresponding to the nineteenth end) receives the system high voltage OVDD, and the gate of the transistor M10 (corresponding to the tenth control terminal) receives the corresponding illuminating signal EM. The source of the transistor M11 (corresponding to the 21st end) is coupled to the drain of the transistor M10 (corresponding to the twentieth end), and the gate of the transistor M11 (corresponding to the eleventh control end) is coupled to the transistor M9. Source (corresponding to the seventeenth end).

The source of the transistor M12 (corresponding to the twenty-third end) is coupled to the gate of the transistor M11 (corresponding to the eleventh control end), and the drain of the transistor M12 (corresponding to the twenty-fourth end) is coupled to the transistor M11 The drain of the transistor M12 (corresponding to the twelfth control terminal) receives the corresponding scan signal SN2. The source of the transistor M13 (corresponding to the twenty-fifth end) is coupled to the drain of the transistor M10 (corresponding to the twentieth end), and the drain of the transistor M13 (corresponding to the twenty-sixth end) receives the corresponding data voltage Vdata The gate of the transistor M13 (corresponding to the thirteenth control terminal) receives the corresponding scan signal SN2. The source of the transistor M14 (corresponding to the twenty-seventh end) is coupled to the drain of the transistor M11, and the gate of the transistor M14 (corresponding to the fourteenth control terminal) receives the corresponding illuminating signal EM. The anode of the organic light-emitting diode OD1 is coupled to the drain of the transistor M14 (corresponding to the twenty-eighth end), and the cathode of the organic light-emitting diode OD1 receives the low voltage OVSS. The storage capacitor Cst is coupled between the high voltage of the OVDD system and the source of the transistor M9.

In summary, the illumination control circuit, the drive circuit thereof and the active matrix organic light emitting diode display panel of the embodiment of the invention separate the gate drive circuit and the illumination control circuit of the drive circuit to reduce the circuit area of the drive circuit. . Moreover, the pulse width of the illuminating signal can be changed by adjusting the working ratio of the clock signal, thereby further reducing the circuit area of the illuminating control circuit. Furthermore, the pulse width of the illumination signal can be changed by adjusting the pulse width of the illumination start signal to improve the picture quality of the display panel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of the present invention It is subject to the definition of the scope of the patent application attached.

100‧‧‧Active Matrix Organic Light Emitting Diode Display Panel

110‧‧‧ pixel array

111‧‧‧ scan line

113‧‧‧Multiple data lines

115‧‧‧Lighting control line

120‧‧‧Drive circuit

121‧‧‧Lighting control circuit

123‧‧‧ gate drive circuit

125‧‧‧Lighting control unit

127‧‧‧Displacement register

CK1~CK4‧‧‧ clock signal

EM‧‧‧ illuminating signal

PX‧‧ ‧ pixels

SN1, SN2‧‧‧ gate drive signal

STVG‧‧‧ gate start signal

STVL‧‧‧Lighting start signal

Vdata‧‧‧ data voltage

VGH‧‧‧ gate high voltage

VGL‧‧‧ gate low voltage

Claims (31)

An illuminating control circuit is applied to an active matrix organic light emitting diode (AMOLED) display panel, comprising: a plurality of illuminating control units respectively receiving a first clock signal and a second clock a plurality of pixels for providing a plurality of illuminating signals to the active matrix OLED display panel, wherein each of the illuminating control units is responsive to the first The clock signal and the second clock signal determine whether to output the gate low voltage or the gate high voltage as a voltage level of the corresponding illuminating signal, and the first illuminating control unit receives an illuminating start signal, the ith illuminating The control unit receives the illumination signal provided by the i-1th illumination control unit, i is a positive integer greater than or equal to 2, and each of the illumination control units includes: a first transistor having a first end and a second And the first control end, the first end receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit, and the first control terminal receives the first clock signal; The second transistor has a third end, a fourth end and a second control end, the third end receives the gate low voltage, the fourth end provides a corresponding illuminating signal, and the second control end is coupled a second end; a third transistor having a fifth end, a sixth end, and a third control end, wherein the fifth end is coupled to the second end, the sixth end receiving the gate high voltage, The third control terminal receives a logic control signal; a fourth transistor has a seventh end, an eighth end, and a fourth control The seventh end is coupled to the fourth end, the eighth end receives the gate high voltage, and the fourth control terminal receives the logic control signal; a first capacitor coupled to the second clock signal and Between the second control terminals; and a logic control unit, receiving at least one reference signal, and coupling the third control terminal and the fourth control terminal to provide the logic control signal. The illuminating control circuit of claim 1, wherein the at least one reference signal comprises the illuminating start signal or the illuminating signal provided by the i-1th illuminating control unit, and the first clock signal. The illuminating control circuit of claim 2, wherein the logic control unit comprises: a fifth transistor having a ninth end, a tenth end and a fifth control end, the tenth end receiving the a gate high voltage, the fifth control terminal receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit; and a sixth transistor having an eleventh end and a twelfth end a sixth control terminal, the eleventh end receives the gate low voltage, the twelfth end provides the logic control signal, the sixth control end is coupled to the ninth end; a seventh transistor has a first a thirteenth end, a fourteenth end and a seventh control end, the thirteenth end is coupled to the twelfth end, the fourteenth end receives the gate high voltage, and the seventh control end receives the illumination The first signal or the illuminating signal provided by the i-1th illuminating control unit; and a second capacitor coupled between the first clock signal and the ninth end. The illuminating control circuit of claim 3, wherein the fifth control end and the seventh control end are coupled to the second end. The illuminating control circuit of claim 3, wherein the fifth control end and the seventh control end are coupled to the first end. The illuminating control circuit of claim 3, wherein the fifth control end is coupled to the first end, and the seventh control end is coupled to the second end. The illuminating control unit of claim 3, wherein the logic control unit further comprises: an eighth transistor having a fifteenth end, a sixteenth end, and an eighth control end, the fifteenth The first end is coupled to the first end, the sixteenth end is coupled to the fifth control end and the seventh control end, the eighth control end receives the second clock signal; and a third capacitor coupled to the The fifth control terminal is between the gate and the high voltage. The illumination control circuit of claim 1, wherein the first clock signal and the second clock signal have the same duty cycle. The illuminating control circuit of claim 8, wherein a pulse width of the illuminating signals is inversely proportional to a working ratio of the first clock signal. The illuminating control circuit of claim 8, wherein a pulse width of the illuminating signals is proportional to a pulse width of the illuminating start signal. A driving circuit is applicable to an active matrix organic light emitting diode display panel, comprising: an illumination control circuit, comprising: a plurality of illumination control units respectively receiving a first clock signal and a second a clock signal, a gate low voltage, and a gate high voltage, and configured to provide a plurality of illuminating signals to the plurality of pixels of the active matrix OLED display panel, wherein each of the illuminating control units is configured according to the The first clock signal and the second clock signal determine whether to output the gate low voltage or the gate high voltage as a voltage level of the corresponding illuminating signal, and the first illuminating control unit receives an illuminating start signal, i The illumination control unit receives the illumination signal provided by the i-1th illumination control unit, i is a positive integer greater than or equal to 2, and each of the illumination control units comprises: a first transistor having a first end, a a second end and a first control end, the first end receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit, and the first control terminal receives the first clock signal; The second transistor has a third end, a fourth end and a second control end, the third end receives the gate low voltage, the fourth end provides a corresponding illuminating signal, and the second control end is coupled to the a second end; a third transistor having a fifth end, a sixth end, and a third control end, the fifth end is coupled to the second end, the sixth end receives the gate high voltage, and the third control end receives a logic control signal; The fourth transistor has a seventh end, an eighth end and a fourth control end, the seventh end is coupled to the fourth end, the eighth end receives the gate high voltage, and the fourth control end receives The logic control signal is coupled between the second clock signal and the second control terminal; and a logic control unit receives at least one reference signal and is coupled to the third a control terminal and the fourth control terminal to provide the logic control signal; and a gate driving circuit, comprising: a plurality of displacement registers, respectively receiving a third clock signal, a fourth clock signal, and the gate The low voltage and the gate are high voltage and are used to provide a plurality of gate drive signals to the pixels. The driving circuit of claim 11, wherein the at least one reference signal comprises the illumination start signal or the illumination signal provided by the i-1th illumination control unit, and the first clock signal. The driving circuit of claim 12, wherein the logic control unit comprises: a fifth transistor having a ninth end, a tenth end and a fifth control end, the tenth end receiving the gate a very high voltage, the fifth control terminal receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit; and a sixth transistor having an eleventh end, a twelfth end, and a a sixth control end, the eleventh end receives the gate low voltage, the twelfth end provides the logic control signal, the sixth control end is coupled to the ninth end; a seventh transistor has a tenth a third end, a fourteenth end and a seventh control end, the thirteenth end is coupled to the twelfth end, the fourteenth end receives the gate high voltage, and the seventh control end receives the illumination start The signal or the illumination signal provided by the i-1th illumination control unit; and a second capacitor coupled between the first clock signal and the ninth terminal. The driving circuit according to claim 13, wherein the fifth control The terminal end and the seventh control end are coupled to the second end. The driving circuit of claim 13, wherein the fifth control end and the seventh control end are coupled to the first end. The driving circuit of claim 13, wherein the fifth control end is coupled to the first end, and the seventh control end is coupled to the second end. The driving circuit of claim 13, wherein the logic control unit further comprises: an eighth transistor having a fifteenth end, a sixteenth end and an eighth control end, the fifteenth end The first end is coupled to the fifth control end and the seventh control end, the eighth control end receives the second clock signal, and a third capacitor coupled to the first end The fifth control terminal is between the gate and the high voltage. The driving circuit of claim 11, wherein the first clock signal and the second clock signal have the same duty cycle. The driving circuit of claim 18, wherein the pulse width of the illuminating signals is inversely proportional to the working ratio of the first clock signal. The driving circuit of claim 18, wherein a pulse width of the illuminating signals is proportional to a pulse width of the illuminating start signal. An active matrix organic light emitting diode display panel includes: a plurality of pixels; and a plurality of light emitting control units respectively receiving a first clock signal, a second clock signal, a gate low voltage, and a gate a high voltage, and configured to provide a plurality of illuminating signals to the pixels, wherein each of the illuminating control units is configured according to the first clock signal and the The second clock signal determines whether the gate low voltage or the gate high voltage is output as the voltage level of the corresponding illuminating signal, the first illuminating control unit receives an illuminating start signal, and the ith illuminating control unit receives the ith - a illuminating signal provided by the illuminating control unit, i is a positive integer greater than or equal to 2, and each of the illuminating control units comprises: a first transistor having a first end, a second end, and a first a control end, the first end receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit, the first control terminal receives the first clock signal; and a second transistor has a first a third end, a fourth end, and a second control end, the third end receiving the gate low voltage, the fourth end providing a corresponding illumination signal, the second control end coupled to the second end; a third The transistor has a fifth end, a sixth end and a third control end, the fifth end is coupled to the second end, the sixth end receives the gate high voltage, and the third control end receives a logic a control signal; a fourth transistor having a seventh end and an eighth end And a fourth control end, the seventh end is coupled to the fourth end, the eighth end receives the gate high voltage, the fourth control end receives the logic control signal; a first capacitor coupled to the first Between the second clock signal and the second control terminal; and a logic control unit, receiving at least one reference signal, and coupling the third control terminal and the fourth control terminal to provide the logic control signal. The active matrix organic light emitting diode display panel of claim 21, wherein the at least one reference signal comprises the light emission start signal or the i-1th An illumination signal provided by the illumination control unit, and the first clock signal. The active matrix organic light emitting diode display panel of claim 22, wherein the logic control unit comprises: a fifth transistor having a ninth end, a tenth end, and a fifth control end, The tenth end receives the gate high voltage, and the fifth control end receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit; and a sixth transistor has an eleventh end, a twelfth end and a sixth control end, the eleventh end receives the gate low voltage, the twelfth end provides the logic control signal, the sixth control end is coupled to the ninth end; The transistor has a thirteenth end, a fourteenth end and a seventh control end, the thirteenth end is coupled to the twelfth end, and the fourteenth end receives the gate high voltage, the seventh The control terminal receives the illumination start signal or the illumination signal provided by the i-1th illumination control unit; and a second capacitor coupled between the first clock signal and the ninth terminal. The active matrix organic light emitting diode display panel of claim 23, wherein the fifth control end and the seventh control end are coupled to the second end. The active matrix organic light emitting diode display panel of claim 23, wherein the fifth control end and the seventh control end are coupled to the first end. The active matrix OLED display panel of claim 23, wherein the fifth control end is coupled to the first end, and the seventh control end is coupled to the second end. Active matrix organic light-emitting diodes as described in claim 23 a display panel, the logic control unit further includes: an eighth transistor having a fifteenth end, a sixteenth end, and an eighth control end, the fifteenth end coupled to the first end, the tenth The sixth terminal is coupled to the fifth control terminal and the seventh control terminal, the eighth control terminal receives the second clock signal, and a third capacitor coupled to the fifth control terminal and the gate high voltage between. The active matrix organic light emitting diode display panel of claim 21, wherein the first clock signal and the second clock signal have the same duty cycle. The active matrix organic light emitting diode display panel of claim 28, wherein a pulse width of the light emitting signals is inversely proportional to a working ratio of the first clock signal. The active matrix organic light emitting diode display panel of claim 28, wherein a pulse width of the light emitting signals is proportional to a pulse width of the light emission start signal. The active matrix organic light emitting diode display panel according to claim 21, wherein each of the pixels comprises: a ninth transistor having a seventeenth end, an eighteenth end, and a ninth a control terminal, the eighteenth end receives an initial voltage, the ninth control end receives a first scan signal; a tenth transistor has a nineteenth end, a second ten end, and a tenth control end, The nineteenth end receives a system high voltage, and the tenth control end receives a corresponding illuminating signal; An eleventh transistor having a second eleven end, a second twelve end, and an eleventh control end, wherein the second eleven end is coupled to the twentieth end, the eleventh control end coupling Connected to the seventeenth end; a twelfth transistor having a second thirteen end, a second fourteen end, and a twelfth control end, the second thirteen end being coupled to the eleventh control end The twenty-fourth end is coupled to the second twelve end, the twelfth control end receives a second scan signal; and a thirteenth transistor has a second fifteen end and a second sixteen end And a thirteenth control end, the twenty-fifth end is coupled to the twentieth end, the second sixteen end receives a data voltage, and the thirteenth control end receives the second scan signal; The transistor has a twenty-seventh end, a twenty-eighth end, and a fourteenth control end, the twenty-seventh end is coupled to the second end, and the fourteenth control end receives the corresponding illumination a signal; an organic light emitting diode, the anode of the organic light emitting diode is coupled to the second eighteen end, and the cathode of the organic light emitting diode receives a system low voltage; Storage capacitor coupled between the high voltage system to the seventeenth terminal.