TWI740653B - Gate driving circuit - Google Patents

Abstract

A gate driving circuit including a plurality of drive output stages is provided. The drive output stages respectively include a sequence start block, a sequence drive block, a pulse drive block, a conduction control block, and a voltage conduction block. The sequence start block receives a light emitting start signal and a first clock signal to provide an internal control voltage. The sequence driving block receives a first system voltage, the internal control voltage and a second clock signal to provide a light emitting series signal. The pulse drive block receives the first system voltage, the light emitting series signal, and a first pulse width modulation signal to provide a light emitting output signal. The conduction control block and the voltage conduction block provide the second system voltage in response to the first system voltage, the light-emitting start signal, the internal control voltage and the first clock signal.

Description

Gate drive circuit

The present invention relates to a gate driving circuit, and more particularly to a gate driving circuit for a self-luminous display panel.

In recent years, self-luminous displays have risen. Among them, organic light-emitting diode displays (OLED) and quantum dot light-emitting diode displays (QLED) compete for the exclusive position of liquid crystal displays (LCD) in display panels. -LED) display is expected to become the mainstream of next-generation display technology based on its many excellent component characteristics.

In a self-luminous display, in addition to the gate drive signal that drives the pixel for data writing, it also includes the light-emitting drive signal that drives the pixel to emit light. In order to suppress the residual image, the enabling period of the gate driving signal and the enabling period of the light-emitting driving signal usually do not overlap each other, and the gate driving signal and the light-emitting driving signal may be alternately enabled during a picture period, where the light-emitting driving signal It may be provided column by column, or the entire panel may share several light-emitting drive signals. In this case, the overall brightness of the display panel cannot be fine-tuned.

The invention provides a gate drive circuit which can fine-tune the overall brightness of a display panel to improve the uniformity of light emission of the display panel.

The gate drive circuit of the present invention includes a plurality of drive output stages. These drive output stages individually include a sequence start block, a sequence drive block, a pulse drive block, a conduction control block, and a voltage conduction block. The sequence start block receives the light-emitting start signal and the first clock signal among the plurality of clock signals to provide an internal control voltage. The sequence driving block receives the first system voltage, the internal control voltage, and the second clock signal among these clock signals to provide a light-emitting sequence signal. The pulse drive block receives the first system voltage, the light-emitting sequence signal, and the first pulse-width modulation signal of the plurality of pulse-width modulation signals to provide a light-emitting output signal to at least one self-luminous pixel circuit, wherein these pulse-width modulation signals The frequency of the variable signal is smaller than the frequency of these clock signals, and the pulse width of these pulse-width modulated signals is variable. The conduction control block receives the first system voltage, the lighting start signal, the internal control voltage and the first clock signal to provide the conduction control signal. The voltage turn-on block receives the turn-on control signal to turn on the internal control voltage, the light-emitting sequence signal, and the light-emitting output signal to the second system voltage in response to the turn-on control signal, where the second system voltage is different from the first system voltage.

Based on the foregoing, in the gate drive circuit of the embodiment of the present invention, the pulse drive block provides a light-emitting output signal to at least one of the plurality of pulse width modulation signals with variable pulse width based on the first pulse width modulation signal. Luminous pixel circuit. Thereby, by adjusting the pulse width of the pulse width modulation signal, the light emission uniformity of the display panel can be improved.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the following is specially mentioned The embodiments, together with the accompanying drawings, are described in detail as follows.

100: Gate drive circuit

110, 110_1~110_n: drive output stage

111: Sequence start block

112: Sequence Driven Block

113: Pulse Drive Block

114: Conduction control block

115: voltage conduction block

C1: The first capacitor

C2: second capacitor

C3: third capacitor

CLK_EM_A, CLK_EM_B: clock signal

EM_OUT[1]~EM_OUT[n], EM_OUT[x], EM_OUT[R1], EM_OUT[R2], EM_OUT[R3]: luminous output signal

EM_OUT[B]: Blue luminous output signal

EM_OUT[G]: Green luminous output signal

EM_OUT[R]: Red luminous output signal

EM_S[1]~EM_S[n], EM_S[x], EM_S[x-1]: luminous sequence signal

EM_STV: luminous start signal

M11~M13, M21~M23, M31~M33, M41~M43: Transistor

OLDE_B: blue light-emitting element

OLDE_G: Green light emitting element

OLDE_R: Red light-emitting element

OLDE_X: Light-emitting element

P: length of time

PWM_EM_A1, PWM_EM_A2, PWM_EM_B1, PWM_EM_B1: pulse width modulation signal

PXB, B: Blue pixel circuit

PXG, G: Green pixel circuit

PXL: Self-luminous pixel circuit

PXL: pixel circuit

PXR, R: Red pixel circuit

SCC: turn-on control signal

t: pulse width

T1: The first transistor

T10: Tenth Transistor

T11: Eleventh Transistor

T2: second transistor

T3: third transistor

T4: The fourth transistor

T5: fifth transistor

T6: sixth transistor

T7: seventh transistor

T8: Eighth Transistor

T9: Ninth Transistor

VDD: system high voltage

Vdx: data voltage

VdxB: Blue data voltage

VdxG: Green data voltage

VdxR: Red data voltage

VGH: Second system voltage

VGL: The first system voltage

VQ: Internal control voltage

VSS: system low voltage

FIG. 1 is a system schematic diagram of a gate driving circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of driving waveforms of a gate driving circuit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a system for driving an output stage according to an embodiment of the present invention.

4A to 4C are schematic circuit diagrams of light-emitting paths of a self-luminous pixel circuit according to an embodiment of the invention.

5A to 5B are schematic diagrams of driving a display panel according to an embodiment of the invention.

6 is a schematic circuit diagram of a light emitting path of a self-luminous pixel circuit according to another embodiment of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or Or part should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the "first element", "component", "region", "layer" or "portion" discussed below may be referred to as a second element, component, region, layer or section without departing from the teachings herein.

The terminology used here is only for the purpose of describing specific embodiments and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one." "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the related listed items. It should also be understood that when used in this specification, the terms "including" and/or "including" designate the presence of the features, regions, wholes, steps, operations, elements, and/or components, but do not exclude one or more The existence or addition of other features, regions as a whole, steps, operations, elements, components, and/or combinations thereof.

FIG. 1 is a system schematic diagram of a gate driving circuit according to an embodiment of the present invention. 1, in this embodiment, the gate drive circuit 100 includes a plurality of drive output stages 110_1~110_n, and the drive output stages 110_1~110_n respectively include a sequence start block 111, a sequence drive block 112, and a pulse drive area Block 113, conduction control block 114 and voltage conduction block 115, where n is a positive integer greater than 2.

The sequence start block 111 receives the light start signal (such as EM_STV or the light sequence signal provided by the upper drive output stage 110_1~110_n EM_S[1]~EM_S[n]) and the first clock signal (such as CLK_EM_A and CLK_EM_B) among multiple clock signals (such as CLK_EM_A and CLK_EM_B) to provide the internal control voltage VQ. The sequence driving block 112 is coupled to the sequence starting block 111, and receives the first system voltage VGL, the internal control voltage VQ, and a second clock signal (such as CLK_EM_A) of the plurality of clock signals (such as CLK_EM_A and CLK_EM_B) And CLK_EM_B) to provide the lighting sequence signal (such as EM_S[1]~EM_S[n]).

The pulse drive block 113 receives the first system voltage VGL, the light-emitting sequence signal (such as EM_S[1]~EM_S[n]), and a plurality of pulse width modulation signals (such as PWM_EM_A1, PWM_EM_A2, PWM_EM_B1, and PWM_EM_B1). Pulse width modulation signals (such as PWM_EM_A1, PWM_EM_A2, PWM_EM_B1, and PWM_EM_B1) to provide light-emitting output signals (such as EM_OUT[1]~EM_OUT[n]) to at least one self-luminous pixel circuit (such as organic light-emitting diode pixels, One of quantum dot light-emitting diodes and miniature light-emitting diode pixels), wherein the self-luminous pixel circuit may include a red pixel circuit PXR, a green pixel circuit PXG, and a blue pixel circuit as shown in FIGS. 4A to 4C. For the pixel circuit PXB, or the pixel circuit PXL shown in Figure 5A, Figure 5B, or Figure 6, the frequency of the pulse width modulation signal (such as PWM_EM_A1, PWM_EM_A2, PWM_EM_B1, and PWM_EM_B1) is less than the frequency of the clock signal (such as CLK_EM_A and CLK_EM_B) And the pulse width of the pulse width modulation signal (such as PWM_EM_A1, PWM_EM_A2, PWM_EM_B1 and PWM_EM_B1) is variable. Thereby, by adjusting the pulse width of the pulse width modulation signal, the light emission uniformity of the display panel can be improved.

The conduction control block 114 is coupled to the sequence start block 111, and receives the first system voltage VGL, a light-emitting start signal (such as EM_STV or the light-emitting sequence signal EM_S[1]~EM_S[ n]), the internal control voltage VQ and the first clock signal (such as CLK_EM_A and CLK_EM_B) to provide the conduction control signal SCC.

The voltage conduction block 115 is coupled to the sequence start block 111, the sequence drive block 112, the pulse drive block 113, and the conduction control block 114, and receives the conduction control signal SCC to respond to the conduction control signal SCC to control the internal voltage VQ, the light-emitting sequence signal (such as EM_S[1]~EM_S[n]) and the light-emitting output signal (such as EM_OUT[1]~EM_OUT[n]) are turned on to the second system voltage VGH. The second system voltage VGH is different from the first system voltage VGL. For example, the second system voltage VGH may be higher than the first system voltage VGL.

In the embodiment of the present invention, the light-emitting start signal EM_STV received by the driving output stage 110_1 may be provided by a control circuit (for example, a timing controller) external to the gate driving circuit 100.

FIG. 2 is a schematic diagram of driving waveforms of a gate driving circuit according to an embodiment of the present invention. 1 and 2, in this embodiment, the enable levels (such as low voltage levels) of the clock signals CLK_EM_A and CLK_EM_B do not overlap with each other on the time axis, and the pulse width modulation signals PWM_EM_A1, PWM_EM_A2, PWM_EM_B1 And the enable level of PWM_EM_B1 (for example, the low voltage level) does not overlap with each other on the time axis.

Pulse width modulation signal PWM_EM_A1, PWM_EM_A2, The pulse widths of PWM_EM_B1 and PWM_EM_B1 are less than or equal to the pulse widths of the clock signals CLK_EM_A and CLK_EM_B. The enabling periods of the pulse width modulation signals PWM_EM_A1 and PWM_EM_A2 overlap with the enabling period of the clock signal CLK_EM_A, and the pulse width modulation signal The enable periods of PWM_EM_B1 and PWM_EM_B2 overlap with the enable period of the clock signal CLK_EM_B respectively. The falling edges of the pulse width modulation signals PWM_EM_A1 and PWM_EM_A2 can be individually aligned with the falling edges of the clock signal CLK_EM_A, and the falling edges of the pulse width modulation signals PWM_EM_B1 and PWM_EM_B2 can be individually aligned with the falling edges of the clock signal CLK_EM_B.

Taking the driving output stage 110_1 as an example, when the light-emitting start signal EM_STV is at a high voltage level and the clock signal CLK_EM_A is enabled, the internal control voltage VQ is set to a high voltage level (considered as a disabled level), and the conduction control is performed The signal SCC is set to a low voltage level (as an enabling level). Through the disabled internal control voltage VQ and the enabled turn-on control signal SCC, the sequence drive block 112 is turned off to provide a high-voltage level light-emitting sequence signal EM_S[1], and the pulse drive block 113 is also turned off And provide the high-voltage level of the luminous output signal EM_OUT[1].

When the light-emitting start signal EM_STV is at a low voltage level and the clock signal CLK_EM_A is enabled, the internal control voltage VQ is set to a low voltage level (considered as an enable level), and the conduction control signal SCC is set to a high voltage level Position (considered as the prohibition level). Through the enabled internal control voltage VQ and the disabled turn-on control signal SCC, the sequence drive block 112 is activated to provide a low-voltage level light-emitting sequence signal EM_S[1], and the pulse drive block 113 is also activated And based on the clock signal CLK_EM_B provides the pulse width modulation signal PWM_EM_B1 as the light-emitting output signal EM_OUT[1].

During the period when the light emission sequence signal EM_S[1] is at the high voltage level, the pixel circuit will be turned on but will not be lit, so the pixel data can be written. In the embodiment of the present invention, the luminous brightness of the pixel circuit is inversely proportional to the time length P of the period of the first pulse width modulation signal PWM_EM_B. In addition, the luminous brightness of the pixel circuit is proportional to the pulse width t of the pulse width modulation signal PWM_EM_B1.

In the embodiment of the present invention, the number of clock signals (such as CLK_EM_A and CLK_EM_B) and the number of pulse width modulation signals (such as PWM_EM_A1, PWM_EM_A2, PWM_EM_B1, and PWM_EM_B1) are examples for illustration, and pulse width modulation signals (such as CLK_EM_A) And the number of CLK_EM_B) is an integer multiple of the number of clock signals (such as PWM_EM_A1, PWM_EM_A2, PWM_EM_B1 and PWM_EM_B1).

FIG. 3 is a schematic diagram of a system for driving an output stage according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 3, wherein the same or similar components use the same or similar reference numerals. In this embodiment, the drive output stage 110 includes a sequence start block 111, a sequence drive block 112, a pulse drive block 113, a conduction control block 114, and a voltage conduction block 115.

The sequence start block 111 includes a first transistor T1. The first transistor T1 has a first terminal that receives the lighting start signal EM_STV or the lighting sequence signal EM_S[x-1] provided by the driver output stage 110 of the previous stage, a second terminal that provides an internal control voltage VQ, and receives a clock signal (Such as CLK_EM_A and CLK_EM_B) One (corresponding to the first clock signal) control terminal. Among them, x is a guide number.

The sequence driving block 112 includes a second transistor T2 and a first capacitor C1. The second transistor T2 has a first end that receives the first system voltage VGL, a second end that provides a light-emitting sequence signal EM_S[x], and a control end that receives the internal control voltage VQ. The first capacitor C1 is coupled between the other of the clock signals (such as CLK_EM_A and CLK_EM_B) (corresponding to the second clock signal) and the control terminal of the second transistor T2.

The pulse driving block 113 includes a third transistor T3, a fourth transistor T4, and a second capacitor C2. The third transistor T3 has a first terminal and a second terminal for receiving the light-emitting sequence signal EM_S[x], and a control terminal for receiving the first system voltage VGL. The fourth transistor T4 has a first end that receives pulse width modulation signals (such as PWM_EM_A1, PWM_EM_A2, PWM_EM_B1, and PWM_EM_B1) corresponding to the second clock signal (corresponding to the first pulse width modulation signal), and provides light The second end of the output signal EM_OUT[x] and the control end coupled to the second end of the third transistor T3. The second capacitor C2 is coupled between the control terminal of the fourth transistor T4 and the second terminal of the fourth transistor T4.

The conduction control block 114 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. The fifth transistor T5 has a first end that receives the first system voltage VGL, a second end that provides a turn-on control signal SCC, and a control end. The sixth transistor T6 has a first terminal coupled to the control terminal of the fifth transistor T5, a second terminal receiving the second system voltage VGH, and receiving the lighting start signal EM_STV or the lighting sequence signal provided by the driving output stage 110 of the previous stage The control terminal of EM_S[x-1]. The seventh transistor T7 has a first terminal coupled to the second terminal of the fifth transistor T5, a second terminal receiving the second system voltage VGH, and a control for receiving the internal control voltage VQ end. The third capacitor C3 is coupled between the first clock signal and the control terminal of the fifth transistor T5.

The voltage conducting block 115 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The eighth transistor T8 has a first terminal coupled to the internal control voltage VQ (that is, the control terminal of the second transistor T2), a second terminal receiving the second system voltage VGH, and a control terminal receiving the conduction control signal SCC. The ninth transistor T9 has a first terminal coupled to the light-emitting sequence signal EM_S[x] (that is, the second terminal of the second transistor T2) provided by the sequence driving block 112, and a second terminal receiving the second system voltage VGH And the control terminal receiving the conduction control signal SCC.

The tenth transistor T10 has a first terminal coupled to the light-emitting sequence signal EM_S[x] (that is, the first terminal of the third transistor T3) received by the pulse drive block 113, and a second terminal that receives the second system voltage VGH. Terminal and the control terminal receiving the conduction control signal SCC. The eleventh transistor T11 has a first terminal coupled to the light-emitting output signal EM_OUT[x] (that is, the second terminal of the third transistor T3), a second terminal receiving the second system voltage VGH, and receiving the conduction control signal SCC The control end.

4A to 4C are schematic circuit diagrams of light-emitting paths of a self-luminous pixel circuit according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 4A to FIG. 4C, wherein the same or similar components use the same or similar reference numerals. The self-luminous pixel circuit includes a red pixel circuit PXR as shown in FIG. 4A, a green pixel circuit PXG as shown in FIG. 4B, and a blue pixel circuit PXB as shown in FIG. 4C.

As shown in Figure 4A, the light-emitting path of the red pixel circuit PXR is composed of at least transistors M11~M13 and red light-emitting elements OLDE_R, and transistors M11~M13 And the red light-emitting element OLDE_R is connected in series between the system high voltage VDD and the system low voltage VSS. The transistors M11 and M13 are controlled by the red light-emitting output signal EM_OUT[R], and the transistor M12 is controlled by the red data voltage VdxR.

As shown in Figure 4B, the light-emitting path of the green pixel circuit PXG is composed of at least transistors M21~M23 and green light-emitting elements OLDE_G. Transistors M21~M23 and green light-emitting elements OLDE_G are connected in series with the system high voltage VDD and the system low voltage Between VSS. The transistors M21 and M23 are controlled by the green light-emitting output signal EM_OUT[G], and the transistor M22 is controlled by the green data voltage VdxG.

As shown in Figure 4C, the light-emitting path of the blue pixel circuit PXB is composed of at least transistors M31~M33 and blue light-emitting elements OLDE_B. The transistors M31~M33 and blue light-emitting elements OLDE_B are connected in series with the system high voltage VDD and Between system low voltage VSS. The transistors M31 and M33 are controlled by the blue light-emitting output signal EM_OUT[B], and the transistor M32 is controlled by the blue data voltage VdxB.

In the embodiment of the present invention, the red light-emitting element OLDE_R, the green light-emitting element OLDE_G, and the blue light-emitting element OLDE_B can be organic light-emitting diodes, quantum dot light-emitting diodes, miniature light-emitting diodes, or other light-emitting elements for display. Humanware.

In the embodiment of the present invention, the pulse width of the red light-emitting output signal EM_OUT[R] received by the red pixel circuit PXR, and the pulse width of the blue light-emitting output signal EM_OUT[B] received by the blue pixel circuit PXB And the pulse width of the green light-emitting output signal EM_OUT[G] received by the green pixel circuit PXG can be set individually and independently. Thereby, the luminous efficiency of the red pixel circuit PXR, the green pixel circuit PXG, and the blue pixel circuit PXB can be optimized.

5A to 5B are schematic diagrams of driving a display panel according to an embodiment of the invention. 1 and 5A, in this embodiment, a red pixel circuit R, a green pixel circuit G, and a blue pixel circuit B are configured on the display panel, and the red pixel circuit R and the green pixel circuit G And the blue pixel circuit B is sequentially arranged on each row of the display panel. In addition, the light-emitting output signals EM_OUT[1]~EM_OUT[n] provided by the driving output stages 110_1~110_n can be set individually, that is, the pulse width R1% of the light-emitting output signal EM_OUT_R1 in the first row can be the same as that of the second row. The pulse width R2% of the luminous output signal EM_OUT_R2 is independent of the pulse width R2% of the luminous output signal EM_OUT_R2 in the second column and the pulse width R3% of the luminous output signal EM_OUT_R3 in the third column. According to the above, the light-emitting output signals EM_OUT[1] to EM_OUT[n] provided by the driving output stages 110_1 to 110_n are provided to the red pixel circuit R, the blue pixel circuit B, and the green pixel circuit G in the same column.

Please refer to FIG. 1, FIG. 5A and FIG. 5B, where the same or similar components use the same or similar reference numerals. In this embodiment, in this embodiment, a red pixel circuit R, a green pixel circuit G, and a blue pixel circuit B are arranged on the display panel, and each column of the display panel is arranged with a red pixel circuit R, One of the green pixel circuit G and the blue pixel circuit. According to the above, the light-emitting output signals EM_OUT[1]~EM_OUT[n] provided by each drive output stage 110_1~110_n are provided to one of the red pixel circuit R, the blue pixel circuit B, and the green pixel circuit G .

6 is a schematic circuit diagram of a light emitting path of a self-luminous pixel circuit according to another embodiment of the invention. 1 and 6, in this embodiment, the light-emitting sequence The signals EM_S[1]~EM_S[n] can be further provided to the self-luminous pixel circuit PXL, and the light-emitting path of the self-luminous pixel circuit PXL is at least composed of transistors M41~M43 and light-emitting elements OLDE_X, transistors M41~M43 And the light emitting element OLDE_X is connected in series between the system high voltage VDD and the system low voltage VSS. The transistor M41 is controlled by the light-emitting output signal EM_OUT[x], the transistor M42 is controlled by the data voltage Vdx, and the transistor M43 is controlled by the light-emitting sequence signal EM_S[x]. In this way, the light emitting sequence signal EM_S[x] can prevent the performance of the light emitting element from deteriorating due to the high frequency signal.

In summary, in the gate drive circuit of the embodiment of the present invention, the pulse drive block provides a light-emitting output signal to at least A self-luminous pixel circuit. Thereby, by adjusting the pulse width of the pulse width modulation signal, the light emission uniformity of the display panel can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Gate drive circuit

110_1~110_n: drive output stage

111: Sequence start block

112: Sequence Driven Block

113: Pulse Drive Block

114: Conduction control block

115: voltage conduction block

CLK_EM_A, CLK_EM_B: clock signal

EM_OUT[1]~EM_OUT[n]: Luminous output signal

EM_S[1]~EM_S[n]: Luminous sequence signal

EM_STV: luminous start signal

PWM_EM_A1, PWM_EM_A2, PWM_EM_B1, PWM_EM_B2: pulse width modulation signal

SCC: turn-on control signal

VGH: Second system voltage

VGL: The first system voltage

VQ: Internal control voltage

Claims (15)

A gate drive circuit includes: Multiple drive output stages, including: A sequence activation block, receiving a light-emitting activation signal and a first clock signal among a plurality of clock signals to provide an internal control voltage; A sequence driving block receiving a first system voltage, the internal control voltage, and a second clock signal among the clock signals to provide a light-emitting sequence signal; A pulse drive block that receives the first system voltage, the light-emitting sequence signal, and a first pulse-width modulated signal among a plurality of pulse-width modulated signals to provide a light-emitting output signal to at least one self-luminous pixel circuit , Wherein the frequency of the pulse width modulation signals is less than the frequency of the clock signals, and the pulse width of the pulse width modulation signals is variable; A conduction control block that receives the first system voltage, the light-emitting start signal, the internal control voltage, and the first clock signal to provide a conduction control signal; and A voltage turn-on block receives the turn-on control signal to turn on the internal control voltage, the light-emitting sequence signal, and the light-emitting output signal to a second system voltage in response to the turn-on control signal, wherein the second system voltage is different from The first system voltage. The gate driving circuit according to claim 1, wherein the sequence activation block includes: A first transistor has a first terminal for receiving the light-emitting start signal, a second terminal for providing the internal control voltage, and a control terminal for receiving the first clock signal. The gate driving circuit according to claim 1, wherein the sequence driving block includes: A second transistor having a first terminal that receives the first system voltage, a second terminal that provides the light-emitting sequence signal, and a control terminal that receives the internal control voltage; and A first capacitor is coupled between the second clock signal and the control terminal of the second transistor. The gate drive circuit according to claim 1, wherein the pulse drive block includes: A third transistor having a first terminal, a second terminal and a control terminal receiving the first system voltage; A fourth transistor having a first end that receives the first pulse width modulation signal, a second end that provides the light-emitting output signal, and a control end coupled to the second end of the third transistor; and A second capacitor is coupled between the control terminal of the fourth transistor and the second terminal of the fourth transistor. The gate driving circuit according to claim 1, wherein the conduction control block includes: A fifth transistor having a first terminal that receives the first system voltage, a second terminal that provides the conduction control signal, and a control terminal; A sixth transistor having a first terminal coupled to the control terminal of the fifth transistor, a second terminal receiving the second system voltage, and a control terminal receiving the light-emitting start signal; A seventh transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal receiving the second system voltage, and a control terminal receiving the internal control voltage; and A third capacitor is coupled between the first clock signal and the control terminal of the fifth transistor. The gate driving circuit according to claim 1, wherein the voltage conduction block includes: An eighth transistor having a first terminal coupled to the internal control voltage, a second terminal receiving the second system voltage, and a control terminal receiving the conduction control signal; A ninth transistor having a first terminal coupled to the light-emitting sequence signal provided by the sequence driving block, a second terminal receiving the second system voltage, and a control terminal receiving the conduction control signal; A tenth transistor having a first terminal coupled to the light-emitting sequence signal received by the pulse drive block, a second terminal receiving the second system voltage, and a control terminal receiving the conduction control signal; and An eleventh transistor has a first terminal coupled to the light-emitting output signal, a second terminal receiving the second system voltage, and a control terminal receiving the conduction control signal. The gate drive circuit according to claim 1, wherein the light-emitting start signal of each drive output stage is provided by a control circuit outside the gate drive circuit, or the light-emitting signal provided by the drive output stage of the previous stage The sequence signal serves as the light-emitting start signal of each of the drive output stages. The gate driving circuit according to claim 1, wherein the luminous brightness of the at least one self-luminous pixel circuit is inversely proportional to the period of the first pulse width modulation signal. The gate driving circuit according to claim 1, wherein the luminous brightness of the at least one self-luminous pixel circuit is proportional to the pulse width of the first pulse width modulation signal. The gate driving circuit according to claim 1, wherein the light-emitting sequence signal is further provided to the at least one self-luminous pixel circuit. The gate driving circuit according to claim 1, wherein the at least one self-luminous pixel circuit includes a red pixel circuit, a blue pixel circuit, and a green pixel circuit. The gate drive circuit according to claim 11, wherein the pulse width of the light-emitting output signal received by the red pixel circuit, the pulse width of the light-emitting output signal received by the blue pixel circuit, and the green The pulse width of the light-emitting output signal received by the pixel circuit is individually and independently set. The gate driving circuit according to claim 12, wherein the light-emitting output signals provided by the driving output stages are individually and independently set. The gate driving circuit according to claim 13, wherein the light-emitting output signal provided by each of the driving output stages is provided to the red pixel circuit, the blue pixel circuit, and the green pixel circuit. The gate drive circuit according to claim 13, wherein the light-emitting output signal provided by each of the drive output stages is provided to one of the red pixel circuit, the blue pixel circuit, and the green pixel circuit one.

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