CN113380185A

CN113380185A - Gate drive circuit

Info

Publication number: CN113380185A
Application number: CN202110583591.XA
Authority: CN
Inventors: 奚鹏博; 林振祺; 谢嘉定; 庄锦棠; 叶政男
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2020-09-18
Filing date: 2021-05-27
Publication date: 2021-09-10
Anticipated expiration: 2041-05-27
Also published as: CN113380185B; TWI740653B; TW202213318A

Abstract

The invention discloses a gate drive circuit, which includes a plurality of drive output stages. These drive output stages individually include a sequence start block, a sequence drive block, a pulse drive block, a conduction control block and a voltage conduction block. The sequence start block receives the light-emitting start signal and the first clock signal to provide an internal control voltage. The sequence driving block receives the first system voltage, the internal control voltage and the second clock signal to provide the light-emitting sequence signal. The pulse driving block receives the first system voltage, the lighting sequence signal and the first pulse width modulation signal to provide the lighting output signal. The conduction control block and the voltage conduction block provide the second system voltage in response to the first system voltage, the lighting start signal, the internal control voltage and the first clock signal.

Description

Gate drive circuit

Technical Field

The present invention relates to a gate driving circuit, and more particularly, to a gate driving circuit for a self-emitting display panel.

Background

In recent years, light emitting displays have grown, and among them, organic light emitting diode displays (OLEDs) and quantum dot light emitting diode displays (QLEDs) compete for the exclusive position of Liquid Crystal Displays (LCDs) on display panels, and Micro light emitting diode (Micro-LED) displays are expected to become the mainstream of next generation display technologies based on their many excellent element characteristics.

In addition to gate driving signals for driving pixels to perform data writing, the self-luminous display further includes light emission driving signals for driving the pixels to emit light. In order to suppress the image sticking, the enabling period of the gate driving signal and the enabling period of the light-emitting driving signal are not overlapped, and the gate driving signal and the light-emitting driving signal may be enabled alternately in one frame period, wherein the light-emitting driving signal may be provided line by line, or the whole panel may share a plurality of light-emitting driving signals. In this case, the entire luminance of the display panel cannot be finely adjusted.

Disclosure of Invention

The invention provides a gate driving circuit which can finely adjust the overall brightness of a display panel so as to improve the luminous uniformity of the display panel.

The gate driving circuit of the present invention includes a plurality of driving output stages. The driving output stages respectively comprise a serial starting block, a serial driving block, a pulse driving block, a conduction control block and a voltage conduction block. The sequence starting block receives a light-emitting starting signal and a first clock signal in a plurality of clock signals to provide an internal control voltage. The sequence driving block receives a first system voltage, an internal control voltage and a second clock signal of the clock signals to provide a light-emitting sequence signal. The pulse drive block receives a first system voltage, a light-emitting sequence signal and a first pulse width modulation signal in a plurality of pulse width modulation signals to provide a light-emitting output signal to at least one self-luminous pixel circuit, wherein the frequency of the pulse width modulation signals is less than the frequency of the clock signals, and the pulse width of the pulse width modulation signals is variable. The conduction control block receives a first system voltage, a light-emitting starting signal, an internal control voltage and a first clock signal to provide a conduction control signal. The voltage conduction block receives the conduction control signal to conduct the internal control voltage, the light-emitting sequence signal and the light-emitting output signal to a second system voltage in response to the conduction control signal, wherein the second system voltage is different from the first system voltage.

In view of the above, in the gate driving circuit according to the embodiment of the invention, the pulse driving block provides the light emitting output signal to the at least one self-emitting pixel circuit based on the first pulse width modulation signal of the plurality of pulse width modulation signals with variable pulse widths. Therefore, the luminous uniformity of the display panel can be improved by adjusting the pulse width of the pulse width modulation signal.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a system diagram of a gate driving circuit according to an embodiment of the invention.

Fig. 2 is a driving waveform diagram of a gate driving circuit according to an embodiment of the invention.

FIG. 3 is a system diagram of driving an output stage according to an embodiment of the invention.

Fig. 4A to 4C are circuit diagrams illustrating a light emitting path of a self-luminous pixel circuit according to an embodiment of the invention.

Fig. 5A to 5B are schematic driving diagrams of a display panel according to an embodiment of the invention.

FIG. 6 is a circuit diagram illustrating a light emitting path of a self-emissive pixel circuit according to another embodiment of the present invention.

Wherein, the reference numbers:

100: gate drive circuit

110. 110_1 to 110_ n: driving an output stage

111: sequence start block

112: sequential driving block

113: pulse drive block

114: conduction control block

115: voltage conducting block

C1: first capacitor

C2: second capacitor

C3: third capacitor

CLK _ EM _ A, CLK _ EM _ B: clock signal

EM _ OUT [1] -EM _ OUT [ n ], EM _ OUT [ x ], EM _ OUT [ R1], EM _ OUT [ R2], EM _ OUT [ R3 ]: luminous output signal

EM _ OUT [ B ]: blue light emission output signal

EM _ OUT [ G ]: green light emitting output signal

EM _ OUT [ R ]: red light emitting output signal

EM _ S [1] -EM _ S [ n ], EM _ S [ x-1 ]: luminescence sequence signal

EM _ STV: luminous starting signal

M11-M13, M21-M23, M31-M33, M41-M43: transistor with a metal gate electrode

OLDE _ B: blue light emitting element

OLDE _ G: green light emitting element

OLDE _ R: red light emitting element

OLDE _ X: light emitting element

P: length of time

PWM _ EM _ a1, PWM _ EM _ a2, PWM _ EM _ B1, PWM _ EM _ B2: pulse width modulation signal

PXB and B: blue pixel circuit

PXG and G: green pixel circuit

PXL: self-luminous pixel circuit

PXL: pixel circuit

PXR and R: red pixel circuit

SCC: conduction control signal

t: pulse width

T1: a first transistor

T10: the tenth transistor

T11: eleventh transistor

T2: second transistor

T3: a third transistor

T4: a fourth transistor

T5: fifth transistor

T6: sixth transistor

T7: seventh transistor

T8: eighth transistor

T9: ninth transistor

VDD: high voltage of system

Vdx: data voltage

VdxB: blue data voltage

VdxG: green data voltage

VdxR: red data voltage

VGH: second system voltage

VGL: first system voltage

And VQ: internal control voltage

VSS: low voltage of system

Detailed Description

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 is a system diagram of a gate driving circuit according to an embodiment of the invention. Referring to fig. 1, in the present embodiment, the gate driving circuit 100 includes a plurality of driving output stages 110_1 to 110_ n, and the driving output stages 110_1 to 110_ n respectively include a serial start block 111, a serial driving block 112, a pulse driving block 113, a conduction control block 114, and a voltage conduction block 115, where n is a positive integer greater than 2.

The serial enable block 111 receives a light-emitting start signal (e.g., EM _ STV or light-emitting serial signals EM _ S [1] -EM _ S [ n ] provided by the driving output stages 110_ 1-110 _ n of the previous stage) and a first clock signal (e.g., CLK _ EM _ A and CLK _ EM _ B) of a plurality of clock signals (e.g., CLK _ EM _ A and CLK _ EM _ B) to provide the internal control voltage VQ. The serial driving block 112 is coupled to the serial enable block 111 and receives the first system voltage VGL, the internal control voltage VQ and a second clock signal (e.g., CLK _ EM _ A and CLK _ EM _ B) of the plurality of clock signals (e.g., CLK _ EM _ A and CLK _ EM _ B) to provide a light emitting serial signal (e.g., EM _ S [1] EM _ S [ n ]).

The PWM block 113 receives a first system voltage VGL, a light-emitting sequence signal (e.g., EM _ S1-EM _ S n), and a first PWM signal (e.g., PWM _ EM _ A1, PWM _ EM _ A2, PWM _ EM _ B1, and PWM _ EM _ B2) of a plurality of PWM signals (e.g., PWM _ EM _ A1, PWM _ EM _ A2, PWM _ EM _ B1, and PWM _ EM _ B2) to provide a light-emitting output signal (e.g., EM _ OUT 1-EM _ OUT n) to at least one self-emitting pixel circuit (e.g., one of an OLED pixel, a QED pixel, and a micro-LED pixel), wherein the self-emitting pixel circuit may include a red pixel circuit PXR, a green pixel circuit PXG, a blue pixel circuit PXB as shown in FIGS. 4A-4C, or a pixel circuit PXL, PXL 1, PWM signals (e.g., PWM _ EM _ A1, PWM _ EM _ A2, PWM _ EM _ B1, PWM _ M, The frequency of PWM _ EM _ A2, PWM _ EM _ B1, and PWM _ EM _ B2) is less than the frequency of the clock signals (e.g., CLK _ EM _ A and CLK _ EM _ B), and the pulse width of the pulse width modulated signals (e.g., PWM _ EM _ A1, PWM _ EM _ A2, PWM _ EM _ B1, and PWM _ EM _ B2) is variable. Therefore, the luminous uniformity of the display panel can be improved by adjusting the pulse width of the pulse width modulation signal.

The conduction control block 114 is coupled to the serial enable block 111 and receives the first system voltage VGL, the light-emitting start signal (e.g., EM _ STV or the light-emitting serial signals EM _ S [1] -EM _ S [ n ] provided by the previous driving output stages 110_ 1-110 _ n), the internal control voltage VQ and the first clock signal (e.g., CLK _ EM _ A and CLK _ EM _ B) to provide the conduction control signal SCC.

The voltage conducting block 115 is coupled to the serial enable block 111, the serial drive block 112, the pulse drive block 113 and the conduction control block 114, and receives the conduction control signal SCC to conduct the internal control voltage VQ, the light emitting serial signals (e.g., EM _ S1-EM _ S n) and the light emitting output signals (e.g., EM _ OUT 1-EM _ OUT n) to the second system voltage VGH in response to the conduction control signal SCC. The second system voltage VGH is different from the first system voltage VGL, for example, the second system voltage VGH may be higher than the first system voltage VGL.

In the embodiment of the present invention, the light emission start signal EM _ STV received by the driving output stage 110_1 may be provided by a control circuit (e.g., a timing controller) external to the gate driving circuit 100.

Fig. 2 is a driving waveform diagram of a gate driving circuit according to an embodiment of the invention. Referring to fig. 1 and 2, in the present embodiment, the enable levels (e.g., low voltage levels) of the clock signals CLK _ EM _ a and CLK _ EM _ B do not overlap with each other on a time axis, and the enable levels (e.g., low voltage levels) of the PWM signals PWM _ EM _ a1, PWM _ EM _ a2, PWM _ EM _ B1, and PWM _ EM _ B2 do not overlap with each other on the time axis.

Pulse widths of the PWM signals PWM _ EM _ a1, PWM _ EM _ a2, PWM _ EM _ B1 and PWM _ EM _ B2 are less than or equal to pulse widths of the clock signals CLK _ EM _ a and CLK _ EM _ B, enabling periods of the PWM signals PWM _ EM _ a1 and PWM _ EM _ a2 overlap with enabling periods of the clock signal CLK _ EM _ a, and enabling periods of the PWM signals PWM _ EM _ B1 and PWM _ EM _ B2 overlap with enabling periods of the clock signal CLK _ EM _ B. Falling edges of the PWM signals PWM _ EM _ a1 and PWM _ EM _ a2 may be respectively aligned with falling edges of the clock signal CLK _ EM _ a, and falling edges of the PWM signals PWM _ EM _ B1 and PWM _ EM _ B2 may be respectively aligned with falling edges of the clock signal CLK _ EM _ B.

Taking the driving output stage 110_1 as an example, when the emission start signal EM _ STV is at a high voltage level and the clock signal CLK _ EM _ a is enabled, the internal control voltage VQ is set to a high voltage level (regarded as an enable level), and the turn-on control signal SCC is set to a low voltage level (regarded as an enable level). The serial driving block 112 is turned off to provide the high-level emission serial signal EM _ S [1] by the disabled internal control voltage VQ and the enabled conduction control signal SCC, and the pulse driving block 113 is also turned off to provide the high-level emission output signal EM _ OUT [1 ].

When the emission start signal EM _ STV is at the low voltage level and the clock signal CLK _ EM _ a is enabled, the internal control voltage VQ is set to the low voltage level (regarded as the enabled level), and the turn-on control signal SCC is set to the high voltage level (regarded as the disabled level). The serial driving block 112 is enabled by the enabled internal control voltage VQ and the disabled on control signal SCC to provide the light-emitting serial signal EM _ S [1] with a low voltage level, and the pulse driving block 113 is also enabled to provide the pulse width modulation signal PWM _ EM _ B1 as the light-emitting output signal EM _ OUT [1] based on the clock signal CLK _ EM _ B.

During the period when the light emission sequence signal EM _ S [1] is at the high voltage level, the pixel circuit is turned on but not lighted, so that writing of pixel data can be performed. In the embodiment of the invention, the luminance of the pixel circuit is inversely proportional to the time length P of the period of the pulse width modulation signal PWM _ EM _ B1. Furthermore, the luminance of the pixel circuit is proportional to the pulse width t of the PWM signal PWM _ EM _ B1.

In the embodiment of the invention, the number of clock signals (e.g., CLK _ EM _ a and CLK _ EM _ B) and the number of PWM signals (e.g., PWM _ EM _ a1, PWM _ EM _ a2, PWM _ EM _ B1, and PWM _ EM _ B2) are illustrated as examples, and the number of PWM signals (e.g., CLK _ EM _ a and CLK _ EM _ B) is an integer multiple of the number of clock signals (e.g., PWM _ EM _ a1, PWM _ EM _ a2, PWM _ EM _ B1, and PWM _ EM _ B2).

FIG. 3 is a system diagram of driving an output stage according to an embodiment of the invention. Referring to fig. 1 and 3, the same or similar elements are denoted by the same or similar reference numerals. In the present embodiment, the driving output stage 110 includes a serial enable block 111, a serial driving block 112, a pulse driving block 113, a conduction control block 114, and a voltage conduction block 115.

The sequence start block 111 includes a first transistor T1. The first transistor T1 has a first terminal for receiving the light-emitting start signal EM _ STV or the light-emitting serial signal EM _ S [ x-1] provided by the driving output stage 110 of the previous stage, a second terminal for providing the internal control voltage VQ, and a control terminal for receiving one of the clock signals (e.g., CLK _ EM _ a and CLK _ EM _ B) (corresponding to the first clock signal). Wherein x is an index number.

The sequential driving block 112 includes a second transistor T2 and a first capacitor C1. The second transistor T2 has a first terminal receiving the first system voltage VGL, a second terminal providing a light-emitting sequence signal EM _ S [ x ], and a control terminal receiving the internal control voltage VQ. The first capacitor C1 is coupled between the other one of the clock signals (e.g., CLK _ EM _ a and CLK _ EM _ B) (corresponding to the second clock signal) and the control terminal of the second transistor T2.

The pulse driving block 113 includes a third transistor T3, a fourth transistor T4, and a second capacitor C2. The third transistor T3 has a first terminal receiving the light emission sequence signal EM _ S [ x ], a second terminal, and a control terminal receiving the first system voltage VGL. The fourth transistor T4 has a first terminal for receiving one of the PWM signals (e.g., PWM _ EM _ a1, PWM _ EM _ a2, PWM _ EM _ B1, and PWM _ EM _ B2) corresponding to the second clock signal (corresponding to the first PWM signal), a second terminal for providing the light emitting output signal EM _ OUT [ x ], and a control terminal coupled to the second terminal of the third transistor T3. The second capacitor C2 is coupled between the control terminal of the fourth transistor T4 and the second terminal of the fourth transistor T4.

The conduction control block 114 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. The fifth transistor T5 has a first terminal for receiving the first system voltage VGL, a second terminal for providing the turn-on control signal SCC, and a control terminal. The sixth transistor T6 has a first terminal coupled to the control terminal of the fifth transistor T5, a second terminal receiving the second system voltage VGH, and a control terminal receiving the emission start signal EM _ STV or the emission sequence signal EM _ S [ x-1] provided from the driving output stage 110 of the previous stage. The seventh transistor T7 has a first terminal coupled to the second terminal of the fifth transistor T5, a second terminal receiving the second system voltage VGH, and a control terminal receiving the internal control voltage VQ. The third capacitor C3 is coupled between the first clock signal and the control terminal of the fifth transistor T5.

The voltage turn-on block 115 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The eighth transistor T8 has a first terminal coupled to the internal control voltage VQ (i.e., the control terminal of the second transistor T2), a second terminal receiving the second system voltage VGH, and a control terminal receiving the turn-on control signal SCC. The ninth transistor T9 has a first terminal coupled to the light-emitting serial signal EM _ sx (i.e., the second terminal of the second transistor T2) provided by the serial driving block 112, a second terminal receiving the second system voltage VGH, and a control terminal receiving the turn-on control signal SCC.

The tenth transistor T10 has a first terminal coupled to the light-emitting sequence signal EM _ sx (i.e., the first terminal of the third transistor T3) received by the pulse driving block 113, a second terminal receiving the second system voltage VGH, and a control terminal receiving the turn-on control signal SCC. The eleventh transistor T11 has a first terminal coupled to the emission output signal EM _ OUT [ x ] (i.e., the second terminal of the third transistor T3), a second terminal receiving the second system voltage VGH, and a control terminal receiving the turn-on control signal SCC.

Fig. 4A to 4C are circuit diagrams illustrating a light emitting path of a self-luminous pixel circuit according to an embodiment of the invention. Please refer to fig. 1 and fig. 4A to 4C, wherein the same or similar elements are denoted by the same or similar reference numerals. The self-luminous pixel circuit includes a red pixel circuit PXR shown in fig. 4A, a green pixel circuit PXG shown in fig. 4B, and a blue pixel circuit PXB shown in fig. 4C.

As shown in fig. 4A, the light emitting path of the red pixel circuit PXR is at least composed of transistors M11-M13 and the red light emitting element OLDE _ R, and the transistors M11-M13 and the red light emitting element OLDE _ R are connected in series between the system high voltage VDD and the system low voltage VSS. The transistors M11 and M13 are controlled by the red emission output signal EM _ OUT [ R ], and the transistor M12 is controlled by the red data voltage VdxR.

As shown in fig. 4B, the light emitting path of the green pixel circuit PXG is at least composed of transistors M21-M23 and a green light emitting element OLDE _ G, and the transistors M21-M23 and the green light emitting element OLDE _ G are connected in series between a system high voltage VDD and a system low voltage VSS. The transistors M21 and M23 are controlled by the green emitting output signal EM _ OUT [ G ], and the transistor M22 is controlled by the green data voltage VdxG.

As shown in fig. 4C, the light emitting path of the blue pixel circuit PXB is formed by at least the transistors M31 to M33 and the blue light emitting element OLDE _ B, and the transistors M31 to M33 and the blue light emitting element OLDE _ B are connected in series between the system high voltage VDD and the system low voltage VSS. The transistors M31 and M33 are controlled by the blue emission output signal EM _ OUT [ B ], and the transistor M32 is controlled by the blue data voltage VdxB.

In the embodiment of the present invention, the red light emitting element OLDE _ R, the green light emitting element OLDE _ G, and the blue light emitting element OLDE _ B may be organic light emitting diodes, quantum dot light emitting diodes, micro light emitting diodes, or other light emitting elements for display.

In the embodiment of the invention, the pulse width of the red emission output signal EM _ OUT [ R ] received by the red pixel circuit PXR, the pulse width of the blue emission output signal EM _ OUT [ B ] received by the blue pixel circuit PXB, and the pulse width of the green emission output signal EM _ OUT [ G ] received by the green pixel circuit PXG can be set independently. Thus, the light emission efficiency of the red pixel circuit PXR, the green pixel circuit PXG, and the blue pixel circuit PXB can be optimized.

Fig. 5A to 5B are schematic driving diagrams of a display panel according to an embodiment of the invention. Referring to fig. 1 and 5A, in the present embodiment, a red pixel circuit R, a green pixel circuit G, and a blue pixel circuit B are disposed on a display panel, and the red pixel circuit R, the green pixel circuit G, and the blue pixel circuit B are sequentially disposed on each row of the display panel. In addition, the emission output signals EM _ OUT [1] to EM _ OUT [ n ] provided by the driving output stages 110_1 to 110_ n can be individually set independently, i.e., the pulse width R1% of the emission output signal EM _ OUT _ R1 of the first row can be independent of the pulse width R2% of the emission output signal EM _ OUT _ R2 of the second row, and the pulse width R2% of the emission output signal EM _ OUT _ R2 of the second row is independent of the pulse width R3% of the emission output signal EM _ OUT _ R3 of the third row. According to the above, the emission output signals EM _ OUT [1] to EM _ OUT [ n ] provided by the driving output stages 110_1 to 110_ n are provided to the red pixel circuit R, the blue pixel circuit B and the green pixel circuit G on the same row.

Referring to fig. 1, 5A and 5B, the same or similar elements are denoted by the same or similar reference numerals. In this embodiment, the display panel is provided with the red pixel circuit R, the green pixel circuit G and the blue pixel circuit B, and one of the red pixel circuit R, the green pixel circuit G and the blue pixel circuit is arranged on each row of the display panel. According to the above, the emission output signals EM _ OUT [1] to EM _ OUT [ n ] provided by the driving output stages 110_1 to 110_ n are provided to one of the red pixel circuit R, the blue pixel circuit B and the green pixel circuit G.

FIG. 6 is a circuit diagram illustrating a light emitting path of a self-emissive pixel circuit according to another embodiment of the present invention. Referring to FIG. 1 and FIG. 6, in the present embodiment, the light emitting sequence signals EM _ S [1] EM _ S [ n ] can be further provided to the self-luminous pixel circuit PXL, and the light emitting path of the self-luminous pixel circuit PXL is at least composed of transistors M41-M43 and the light emitting device OLDE _ X, and the transistors M41-M43 and the light emitting device OLDE _ X are connected in series between the system high voltage VDD and the system low voltage VSS. The transistor M41 is controlled by the emission output signal EM _ OUT [ x ], the transistor M42 is controlled by the data voltage Vdx, and the transistor M43 is controlled by the emission sequence signal EM _ S [ x ]. Thus, the light emitting sequence signal EM _ Sx can prevent the light emitting element from the performance deterioration caused by the high frequency signal.

In summary, in the gate driving circuit according to the embodiment of the invention, the pulse driving block provides the light emitting output signal to the at least one self-emitting pixel circuit based on the first pulse width modulation signal of the plurality of pulse width modulation signals with variable pulse widths. Therefore, the luminous uniformity of the display panel can be improved by adjusting the pulse width of the pulse width modulation signal.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A gate drive circuit, comprising:

a plurality of drive output stages, each comprising:

a sequence starting block for receiving a light-emitting starting signal and a first clock signal in a plurality of clock signals to provide an internal control voltage;

a serial driving block for receiving a first system voltage, the internal control voltage and a second clock signal of the clock signals to provide a light emitting serial signal;

a pulse drive block receiving the first system voltage, the light-emitting sequence signal and a first pulse width modulation signal of a plurality of pulse width modulation signals to provide a light-emitting output signal to at least one self-luminous pixel circuit, wherein the frequency of the pulse width modulation signals is less than that of the clock signals, and the pulse width of the pulse width modulation signals is variable;

a conduction control block for receiving the first system voltage, the light-emitting start signal, the internal control voltage and the first clock signal to provide a conduction control signal; and

and a voltage conduction block for receiving the conduction control signal and conducting the internal control voltage, the light-emitting sequence signal and the light-emitting output signal to a second system voltage in response to the conduction control signal, wherein the second system voltage is different from the first system voltage.

2. The gate driving circuit of claim 1, wherein the sequence start block comprises:

the first transistor is provided with a first end for receiving the light-emitting starting signal, a second end for providing the internal control voltage and a control end for receiving the first clock signal.

3. The gate driving circuit of claim 1, wherein the sequential driving block comprises:

a second transistor having a first terminal for receiving the first system voltage, a second terminal for providing the light-emitting sequence signal, and a control terminal for receiving the internal control voltage; and

and the first capacitor is coupled between the second clock signal and the control end of the second transistor.

4. The gate driving circuit of claim 1, wherein the pulse driving block comprises:

a third transistor having a first terminal for receiving the light-emitting sequence signal, a second terminal, and a control terminal for receiving the first system voltage;

a fourth transistor having a first terminal for receiving the first pwm signal, a second terminal for providing the light emitting output signal, and a control terminal coupled to the second terminal of the third transistor; and

a second capacitor coupled between the control terminal of the fourth transistor and the second terminal of the fourth transistor.

5. The gate driving circuit of claim 1, wherein the conduction control block comprises:

a fifth transistor having a first terminal for receiving the first system voltage, a second terminal for providing the conduction control signal, and a control terminal;

a sixth transistor having a first terminal coupled to the control terminal of the fifth transistor, a second terminal receiving the second system voltage, and a control terminal receiving the light-emitting start signal;

a seventh transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal receiving the second system voltage, and a control terminal receiving the internal control voltage; and

a third capacitor coupled between the first clock signal and the control terminal of the fifth transistor.

6. The gate driving circuit of claim 1, wherein the voltage pass block comprises:

an eighth transistor having a first terminal coupled to the internal control voltage, a second terminal receiving the second system voltage, and a control terminal receiving the turn-on control signal;

a ninth transistor having a first terminal coupled to the light emitting serial signal provided by the serial driving block, a second terminal receiving the second system voltage, and a control terminal receiving the turn-on control signal;

a tenth transistor having a first terminal coupled to the light-emitting serial signal received by the pulse driving block, a second terminal receiving the second system voltage, and a control terminal receiving the conduction control signal; and

an eleventh transistor having a first terminal coupled to the light emitting output signal, a second terminal receiving the second system voltage, and a control terminal receiving the turn-on control signal.

7. A gate driving circuit as claimed in claim 1, wherein the light emitting start signal of each driving output stage is provided by a control circuit external to the gate driving circuit, or the light emitting sequence signal provided by a driving output stage of a previous stage is used as the light emitting start signal of each driving output stage.

8. The gate driving circuit as claimed in claim 1, wherein the luminance of the at least one self-emissive pixel circuit is inversely proportional to the duration of the period of the first PWM signal.

9. The gate driving circuit as claimed in claim 1, wherein the at least one self-luminous pixel circuit emits light with a brightness proportional to the pulse width of the first PWM signal.

10. A gate driving circuit as claimed in claim 1, wherein the light emitting sequence signal is further provided to the at least one self-emitting pixel circuit.

11. The gate driving circuit of claim 1, wherein the at least one self-emissive pixel circuit comprises a red pixel circuit, a blue pixel circuit, and a green pixel circuit.

12. A gate driving circuit as claimed in claim 11, wherein the pulse width of the light emitting output signal received by the red pixel circuit, the pulse width of the light emitting output signal received by the blue pixel circuit and the pulse width of the light emitting output signal received by the green pixel circuit are individually set independently.

13. A gate drive circuit as claimed in claim 12, wherein the light emission output signals provided by the drive output stages are individually and independently set.

14. A gate drive circuit as claimed in claim 13, wherein the light emission output signal provided by each of the plurality of drive output stages is provided to the red pixel circuit, the blue pixel circuit and the green pixel circuit.

15. A gate drive circuit as claimed in claim 13, wherein the light emission output signal provided by each of the plurality of drive output stages is provided to one of the red pixel circuit, the blue pixel circuit and the green pixel circuit.