CN110176215B - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN110176215B
CN110176215B CN201910559037.0A CN201910559037A CN110176215B CN 110176215 B CN110176215 B CN 110176215B CN 201910559037 A CN201910559037 A CN 201910559037A CN 110176215 B CN110176215 B CN 110176215B
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circuit
row
emission
driving sub
stage
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CN110176215A (en
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李玥
张蒙蒙
周星耀
黄高军
竺笛
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Wuhan Tianma Microelectronics Co Ltd
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Shanghai Tianma AM OLED Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area; the non-display area comprises a first non-display area and a second non-display area which are correspondingly arranged; the display panel also comprises a plurality of rows of pixel rows positioned in the display area, a scanning driving circuit and an emission driving circuit positioned in the non-display area, a plurality of scanning lines and a plurality of emission lines; the scanning driving circuit comprises a plurality of cascaded scanning driving sub-circuits, and the emission driving circuit comprises a plurality of cascaded emission driving sub-circuits; the first-stage scanning driving sub-circuit is electrically connected with two adjacent rows of pixel rows through two scanning lines respectively; the 2N-1 stage emission driving sub-circuit is positioned in the first non-display area, and the 2N stage emission driving sub-circuit is positioned in the second non-display area; the 2N-1 level emission driving sub-circuit is electrically connected with the 4N-3 th row and the 4N-1 th row of pixel rows through two emission lines respectively, the 2N level emission driving sub-circuit is electrically connected with the 4N-2 th row and the 4N th row of pixel rows through two emission lines respectively, and N is a natural number.

Description

Display panel and display device
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to a display panel and a display device.
[ background of the invention ]
Among Display technologies, an Organic Light Emitting Diode (OLED) Display is considered as a third generation Display technology following a Liquid Crystal Display (LCD) due to its advantages of lightness, thinness, active Light emission, fast response speed, wide viewing angle, rich colors, high brightness, low power consumption, and high and low temperature resistance.
In the prior art, the left frame area and the right frame area of the display panel are provided with emission driving circuits, and the sizes of the emission driving circuits limit the narrowing of the left frame area and the right frame area.
[ summary of the invention ]
In order to solve the above technical problems, the present invention provides a display panel and a display device.
In a first aspect, the present invention provides a display panel comprising a display area and a non-display area surrounding the display area;
the non-display area comprises a first non-display area and a second non-display area which are correspondingly arranged;
the display panel also comprises a plurality of rows of pixel rows positioned in the display area, a scanning driving circuit and an emission driving circuit positioned in the non-display area, a plurality of scanning lines and a plurality of emission lines;
the scanning driving circuit comprises a plurality of cascaded scanning driving sub-circuits, and the emission driving circuit comprises a plurality of cascaded emission driving sub-circuits;
the scanning driving sub-circuit at the first stage is electrically connected with two adjacent pixel rows through two scanning lines respectively;
the 2N-1 level emission driving sub-circuit is positioned in the first non-display area, and the 2N level emission driving sub-circuit is positioned in the second non-display area;
the 2N-1 level emission driving sub-circuit is electrically connected with the 4N-3 th row and the 4N-1 th row of the pixel row through the two emission lines respectively, the 2N level emission driving sub-circuit is electrically connected with the 4N-2 th row and the 4N th row of the pixel row through the two emission lines respectively, and N is a natural number.
Optionally, the 2N-1 stage emission driving sub-circuit is arranged corresponding to the pixel rows in the 4N-3 th row, the 4N-2 th row, the 4N-1 th row and the 4N th row;
the 2N-th level emission driving sub-circuit is arranged corresponding to the pixel rows in the 4N-3 th row, the 4N-2 th row, the 4N-1 th row and the 4N th row.
Optionally, the 2N-1 st stage emission driving sub-circuit is arranged corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N th stage scanning driving sub-circuits;
the 2 Nth-stage emission driving sub-circuit corresponds to the 4 Nth-3 th-stage scanning driving sub-circuit, the 4 Nth-2 th-stage scanning driving sub-circuit, the 4 Nth-1 th-stage scanning driving sub-circuit and the 4 Nth-stage scanning driving sub-circuit.
Optionally, the 2N-1 st stage emission driving sub-circuit is electrically connected to the 4N-1 th row of pixels and the 2N stage emission driving sub-circuit through one emission line.
Optionally, the 2 nth stage emission driving sub-circuit is electrically connected to the 4 nth row of pixel rows and the 2N +1 th stage emission driving sub-circuit through one emission line.
Optionally, in the first period, the scan driving sub-circuit of the 4N-4 th stage with N > 1 sends a turn-on signal, which reaches the pixel rows of the 4N-3 th row through the scan lines;
in a second period, the 4N-3 th-level scanning driving sub-circuit sends conducting signals which respectively reach the 4N-3 th row and the 4N-2 th row of the pixel rows through the two scanning lines;
in a third period, the 4N-2 th-stage scanning driving sub-circuit sends conducting signals which respectively reach the 4N-2 th row and the 4N-1 th row of the pixel rows through the two scanning lines;
in a fourth period, the 4N-1 th scanning driving sub-circuit sends conducting signals which respectively reach the 4N-1 th row and the 4N th row of the pixel rows through the two scanning lines;
and after the fourth period, the 2N-1 level emission driving sub-circuit sends a conducting signal which respectively reaches the pixel rows of the 4N-3 th row and the 4N-1 th row through the two emission lines.
Optionally, in a fifth period, the scan driving sub-circuit of the 4 nth stage sends a turn-on signal, which reaches the pixel row of the 4 nth row through the scan line;
after the fifth time period, the 2 nth-stage emission driving sub-circuit sends conducting signals, and the conducting signals respectively reach the 4N-2 th row and the 4 nth-row of pixel rows through the two emission lines.
Optionally, after the fourth period, the on signal sent by the emission driving sub-circuit of the 2N-1 th stage reaches the pixel row of the 4N-1 th row and the emission driving sub-circuit of the 2N-1 th stage through one emission line.
Optionally, after the fifth period, the on signal sent by the emission driving sub-circuit of the 2 nth stage reaches the pixel row of the 4 nth row and the emission driving sub-circuit of the 2N +1 st stage through one emission line.
Optionally, the first period, the second period, the third period, the fourth period, and the fifth period are sequentially repeated.
Optionally, a row of pixels comprises a plurality of pixels, the pixels comprising: the driving circuit comprises a driving transistor, a first initialization transistor, a second initialization transistor, a first data writing transistor, a second data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a storage capacitor, an organic light-emitting diode, a first scanning end, a second scanning end, an emission end, a reference end, a data end and a power end;
the two scanning driving sub-circuits are respectively and electrically connected with the first scanning end and the second scanning end;
the emission driving sub-circuit is electrically connected with the emission end;
the driving transistor is used for generating a driving current according to the grid-source voltage of the driving transistor;
the first initialization transistor is used for being conducted under the control of the first scanning end, so that a reference signal of the reference end is transmitted to the grid electrode of the driving transistor;
the second initialization transistor is used for conducting under the control of the first scanning end, so that a reference signal of the reference end is transmitted to an anode of the organic light emitting diode;
the first data writing transistor is used for being conducted under the control of the second scanning end, so that a data signal of the data end is transmitted to the first electrode of the driving transistor;
the second data writing transistor is used for conducting under the control of the second scanning end and used for detecting and compensating the threshold voltage of the driving transistor;
the first light-emitting control transistor is used for being conducted under the control of the emitting end, so that a signal of the power end is transmitted to the first electrode of the driving transistor;
the second light-emitting control transistor is used for conducting under the control of the emitting end, so that the driving current is transmitted to the anode of the organic light-emitting diode;
the storage capacitor is used for detecting and compensating the threshold voltage of the driving transistor;
the organic light emitting diode is used for emitting light according to the driving current.
In a second aspect, the present invention provides a display device comprising the display panel.
In the present invention, the 2N-1 st stage emission driving sub-circuit is located in the first non-display region, and the 2N-th stage emission driving sub-circuit is located in the second non-display region. The first-stage emission driving sub-circuit is located in the first non-display region or in the second non-display region. Compared with the prior art, the number of stages of the emission driving sub-circuits in the first non-display area and the number of stages of the emission driving sub-circuits in the second non-display area are reduced. The size of the emission drive circuit in the first non-display area and the size of the emission drive circuit in the second non-display area are both made smaller. The width of the first non-display area and the width of the second non-display area both become smaller. The display panel realizes narrow frame. In the embodiment of the invention, the 2N-1 st-stage emission driving sub-circuit is electrically connected with the 4N-3 th row and the 4N-1 th row of pixel rows through two emission lines respectively, and the 2N-stage emission driving sub-circuit is electrically connected with the 4N-2 th row and the 4N th row of pixel rows through two emission lines respectively. The 2N-1 stage emission driving sub-circuit is arranged corresponding to at least 3 rows of pixel rows such as the 4N-3 th row, the 4N-2 th row, the 4N-1 th row and the like. The 2N-th-stage emission driving sub-circuit is arranged corresponding to at least 3 rows of pixel rows such as the 4N-2 th row, the 4N-1 th row, the 4N-th row and the like. The first-stage emission driving sub-circuit is arranged corresponding to at least 3 rows of pixel rows. Compared with the prior art, the number of stages of the emission driving sub-circuit in the first non-display area and the number of stages of the emission driving sub-circuit in the second non-display area are further reduced. The size of the emission drive circuit in the first non-display area and the size of the emission drive circuit in the second non-display area are both further reduced. The width of the first non-display area and the width of the second non-display area are both further reduced. The display panel further realizes narrow frame.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art display panel;
FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a pixel in a display panel according to an embodiment of the invention;
FIG. 4 is a timing diagram of a pixel in a display panel according to an embodiment of the invention;
FIG. 5 is a timing diagram of a display panel according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an emission driving circuit in a display panel according to an embodiment of the present invention;
FIG. 7 is a timing diagram of an emission driving circuit in a display panel according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, etc. may be used herein to describe devices in accordance with embodiments of the present invention, these devices should not be limited by these terms. These terms are only used to distinguish one device from another. For example, a first device may also be referred to as a second device, and similarly, a second device may also be referred to as a first device, without departing from the scope of embodiments of the present invention.
Fig. 1 is a schematic structural diagram of a display panel in the prior art.
As shown in fig. 1, in the related art, a display panel 100 includes a display area 101 and a non-display area 102. Display area 101 includes a plurality of rows of pixel rows 110. The non-display area 102 includes a scan driving circuit 120 and an emission driving circuit 130. The scan driving circuit 120 includes a multi-stage scan driving sub-circuit 121. The emission driving circuit 130 includes a multi-stage emission driving sub-circuit. However, the number of stages of the emission driving sub-circuit is large, the size of the emission driving circuit 130 is large, and the non-display region 102 is wide.
In order to solve the above technical problems, the present invention provides a display panel and a display device.
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the invention.
As shown in fig. 2, the display panel 200 includes a display area AA and a non-display area NA surrounding the display area AA; the non-display area NA includes a first non-display area NA1 and a second non-display area NA2 which are correspondingly disposed; the display panel 200 further includes a plurality of rows of pixel rows PXR located in the display area AA, a scan driving circuit VSRA and an emission driving circuit VSRB located in the non-display area NA, a plurality of scan lines SL, a plurality of emission lines EL; the scan driving circuit VSRA includes a plurality of scan driving sub-circuits VSR1 cascaded, and the emission driving circuit VSRB includes a plurality of emission driving sub-circuits VSR2 cascaded; the primary scanning driving sub-circuit VSR1 is electrically connected to two adjacent rows of pixel rows PXR through two scanning lines SL respectively; the 2N-1 st stage emission driving sub-circuit VSR2 is positioned in the first non-display area NA1, and the 2N th stage emission driving sub-circuit VSR2 is positioned in the second non-display area NA 2; the 2N-1 st-order emission driving sub-circuit VSR2 is electrically connected to the 4N-3 th and 4N-1 th pixel rows PXR through two emission lines EL, respectively, and the 2N-order emission driving sub-circuit VSR2 is electrically connected to the 4N-2 th and 4N th pixel rows PXR through two emission lines EL, respectively, N being a natural number.
In the embodiment of the present invention, the non-display area NA includes a first non-display area NA1 and a second non-display area NA2 that are correspondingly disposed. For example, the first non-display area NA1 is a left bezel area, and the second non-display area NA2 is a right bezel area. The scan driving circuit VSRA includes a plurality of scan driving sub-circuits VSR1 cascaded. An output terminal of the nth-stage scan driving sub-circuit VSR1 is electrically connected to an input terminal of the N +1 th-stage scan driving sub-circuit VSR 1. For example, the output terminal of the 1 st-stage scan driving sub-circuit VSR1 is electrically connected to the input terminal of the 2 nd-stage scan driving sub-circuit VSR 1. An output terminal of the 2 nd-stage scan driving sub-circuit VSR1 is electrically connected to an input terminal of the 3 rd-stage scan driving sub-circuit VSR 1. The rest is analogized in the same way. The emission driving circuit VSRB includes a plurality of emission driving sub-circuits VSR2 cascaded. The output terminal OUT of the nth stage emission driving sub-circuit VSR2 is electrically connected to the input terminal IN of the N +1 th stage emission driving sub-circuit VSR 2. For example, the output terminal OUT of the 1 st stage emission driving sub-circuit VSR2 is electrically connected to the input terminal IN of the 2 nd stage emission driving sub-circuit VSR 2. The output terminal OUT of the 2 nd-stage emission driving sub-circuit VSR2 is electrically connected to the input terminal IN of the 3 rd-stage emission driving sub-circuit VSR 2. The rest is analogized in the same way.
In the embodiment of the invention, the one-stage scan driving sub-circuit VSR1 is electrically connected to two adjacent pixel rows PXR through two scan lines SL respectively. The nth stage scan driving sub-circuit VSR1 is electrically connected to the nth and N +1 th rows of pixel rows PXR through two scan lines SL, respectively. For example, the 1 st-stage scan driving sub-circuit VSR1 is electrically connected to the 1 st and 2 nd row pixel rows PXR through two scan lines SL, respectively. The 2 nd-stage scan driving sub-circuit VSR1 is electrically connected to the 2 nd and 3 rd row pixel rows PXR through two scan lines SL, respectively. The rest is analogized in the same way.
In the embodiment of the present invention, the 2N-1 st stage emission driving sub-circuit VSR2 is located in the first non-display area NA 1. For example, the 1 st-order emission driving sub-circuit VSR2 is located at the first non-display area NA 1. The 3 rd-order emission driving sub-circuit VSR2 is located at the first non-display area NA 1. The rest is analogized in the same way. The 2N-th stage emission driving sub-circuit VSR2 is located in the second non-display area NA 2. For example, the 2 nd stage emission driving sub-circuit VSR2 is located at the second non-display area NA 2. The 4 th-order emission driving sub-circuit VSR2 is located at the second non-display area NA 2. The rest is analogized in the same way. The rest is analogized in the same way.
In the embodiment of the present invention, the 2N-1 st stage emission driving sub-circuit VSR2 is electrically connected to the 4N-3 th and 4N-1 th pixel rows PXR through two emission lines EL, respectively. For example, the 1 st-stage emission driving sub-circuit VSR2 electrically connects the 1 st and 3 rd row pixel rows PXR through two emission lines EL, respectively. The 3 rd-stage emission driving sub-circuit VSR2 electrically connects the 5 th and 7 th row pixel rows PXR through two emission lines EL, respectively. The rest is analogized in the same way. The 2N-th stage emission driving sub-circuit VSR2 is electrically connected to the 4N-2 th row and the 4N-th row of pixel rows PXR through two emission lines EL, respectively. For example, the 2 nd-stage emission driving sub-circuit VSR2 electrically connects the 2 nd and 4 th row pixel rows PXR through two emission lines EL, respectively. The 4 th-stage emission driving sub-circuit VSR2 electrically connects the 6 th and 8 th row pixel rows PXR through two emission lines EL, respectively. The rest is analogized in the same way.
In the embodiment of the invention, the 2N-1 st stage emission driving sub-circuit VSR2 is located in the first non-display area NA1, and the 2N th stage emission driving sub-circuit VSR2 is located in the second non-display area NA 2. The primary emission driving sub-circuit VSR2 is located in the first non-display area NA1 or in the second non-display area NA 2. Compared with the prior art, the number of the stages of the emission driving sub-circuit VSR2 in the first non-display area NA1 and the number of the stages of the emission driving sub-circuit VSR2 in the second non-display area NA2 are reduced in the embodiments of the present invention. The size of the emission driving circuit VSRB in the first non-display area NA1 and the size of the emission driving circuit VSRB in the second non-display area NA2 are both reduced. The width of the first non-display area NA1 and the width of the second non-display area NA2 become small. The display panel 200 realizes a narrow bezel. In the embodiment of the present invention, the 2N-1 st-order emission driving sub-circuit VSR2 is electrically connected to the 4N-3 th and 4N-1 th pixel rows PXR through two emission lines EL, respectively, and the 2N-order emission driving sub-circuit VSR2 is electrically connected to the 4N-2 th and 4N th pixel rows PXR through two emission lines EL, respectively. The 2N-1 stage emission driving sub-circuit VSR2 is provided corresponding to at least 3 rows of pixel rows 4N-3, 4N-2, 4N-1, and PXR, etc. The 2N-th stage emission driving sub-circuit VSR2 is disposed corresponding to at least 3 rows of pixel rows 4N-2, 4N-1, 4N-th pixel row PXR, etc. The one-stage emission driving sub-circuit VSR2 is disposed corresponding to at least 3 rows of pixel rows. Compared with the prior art, the number of stages of the emission driving sub-circuit VSR2 in the first non-display area NA1 and the number of stages of the emission driving sub-circuit VSR2 in the second non-display area NA2 are further reduced in the embodiments of the present invention. The size of the emission driving circuit VSRB in the first non-display area NA1 and the size of the emission driving circuit VSRB in the second non-display area NA2 are both further reduced. The width of the first non-display area NA1 and the width of the second non-display area NA2 are both further reduced. The display panel 200 further realizes a narrow bezel.
FIG. 3 is a circuit diagram of a pixel in a display panel according to an embodiment of the invention; FIG. 4 is a timing diagram of a pixel in a display panel according to an embodiment of the invention.
As shown in fig. 2 to 4, one row of pixel rows PXR includes a plurality of pixels PX, and the pixels PX include: a driving transistor T3, a first initializing transistor T5, a second initializing transistor T7, a first DATA writing transistor T2, a second DATA writing transistor T4, a first light emission controlling transistor T1, a second light emission controlling transistor T6, a storage capacitor C, an organic light emitting diode OD, a first SCAN terminal SCAN1, a second SCAN terminal SCAN2, an emission terminal EMIT, a reference terminal REF, a DATA terminal DATA, a power terminal PVDD; the two SCAN driving sub-circuits VSR1 are electrically connected to the first SCAN terminal SCAN1 and the second SCAN terminal SCAN2, respectively; the emission driving sub-circuit VSR2 is electrically connected to the emission terminal EMIT; the driving transistor T3 is used to generate a driving current according to the gate-source voltage of the driving transistor T3; the first initialization transistor T5 is used to be turned on under the control of the first SCAN terminal SCAN1, so that the reference signal of the reference terminal REF is transmitted to the gate of the driving transistor T3; the second initialization transistor T7 is used to be turned on under the control of the first SCAN terminal SCAN1, such that the reference signal of the reference terminal REF is transmitted to the anode of the organic light emitting diode OD; the first DATA writing transistor T2 is used to turn on under the control of the second SCAN terminal SCAN2, so that the DATA signal of the DATA terminal DATA is transmitted to the first electrode of the driving transistor T3; the second data writing transistor T4 for turning on under the control of the second SCAN terminal SCAN2, for detecting and compensating a threshold voltage of the driving transistor T3; the first light emission controlling transistor T1 is for being turned on under the control of the emission terminal EMIT, so that the power signal of the power source terminal PVDD is transmitted to the first electrode of the driving transistor T3; the second light emission control transistor T6 is for being turned on under the control of the emission terminal EMIT so that the driving current is transmitted to the anode of the organic light emitting diode OD; the storage capacitor C is used to detect and compensate for the threshold voltage of the driving transistor T3; the organic light emitting diode OD is used to emit light according to a driving current.
As shown in fig. 3 and 4, the initialization phase P11, the data writing phase P12, and the light emission control phase P13 are sequentially performed. In the initialization stage P11, the SCAN driving sub-circuit VSR1 performs driving, and the first SCAN terminal SCAN1 controls the first and second initialization transistors T5 and T7 to be turned on. The reference terminal REF transmits a reference signal to the control electrode of the driving transistor T3 and the anode of the organic light emitting diode OD. The second SCAN terminal SCAN2 controls the first data writing transistor T2 and the second data writing transistor T4 to be turned off. The emission terminal EMIT controls the first and second light emission control transistors T1 and T6 to be turned off. In the data writing phase P12, the SCAN driving sub-circuit VSR1 performs driving, and the second SCAN terminal SCAN2 controls the first data writing transistor T2 and the second data writing transistor T4 to be turned on. The DATA terminal DATA transmits a DATA signal to the first electrode of the driving transistor T3. The second data writing transistor T4 detects, compensates for the threshold voltage of the driving transistor T3. The first SCAN terminal SCAN1 controls the first and second initialization transistors T5 and T7 to be turned off. The emission terminal EMIT controls the first and second light emission control transistors T1 and T6 to be turned off. In the light emission control phase P13, the emission driving sub-circuit VSR2 performs driving, and the emission terminal EMIT controls the first light emission control transistor T1 to be turned on. The power source terminal PVDD transmits a power source signal to the first electrode of the driving transistor T3. The driving transistor T3 generates a driving current according to the gate-source voltage of the driving transistor T3. The emission terminal EMIT controls the second light emission control transistor T6 to be turned on. The driving current of the driving transistor T3 is transmitted to the anode of the organic light emitting diode OD. The organic light emitting diode OD emits light according to the driving current. The first SCAN terminal SCAN1 controls the first and second initialization transistors T5 and T7 to be turned off. The second SCAN terminal SCAN2 controls the first data writing transistor T2 and the second data writing transistor T4 to be turned off.
In the embodiment of the present invention, the nth stage scan driving sub-circuit VSR1 is electrically connected to the nth row and the N +1 th row of pixel rows PXR through two scan lines SL, respectively. The nth stage scan driving sub-circuit VSR1 drives the nth and N +1 th rows of pixel rows PXR through two scan lines SL, respectively. The nth row pixel row PXR performs an operation of the data writing phase. The N +1 th pixel row PXR performs the operation of the initialization phase. The 2N-1 st-order emission driving sub-circuit VSR2 is electrically connected to the 4N-3 th and 4N-1 th pixel rows PXR through two emission lines EL, respectively, and the 2N-order emission driving sub-circuit VSR2 is electrically connected to the 4N-2 th and 4N th pixel rows PXR through two emission lines EL, respectively. The 2N-1 st stage emission driving sub-circuit VSR2 drives the 4N-3 th and 4N-1 th row of pixel rows PXR through the two emission lines EL, respectively, to perform the operation of the emission control phase. The 2N-th stage emission driving sub-circuit VSR2 drives the 4N-2 th and 4N-th row of pixel rows PXR through the two emission lines EL, respectively, to perform the operation of the emission control phase.
As shown in fig. 2, the 2N-1 st stage emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N th pixel rows PXR; the 2N-th stage emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N-th rows of pixel rows PXR.
In the embodiment of the present invention, the 2N-1 stage emission driving sub-circuit VSR2 is disposed corresponding to the pixel rows PXR of the 4N-3 th, 4N-2 th, 4N-1 th and 4N th rows. For example, the 1 st-stage emission driving sub-circuit VSR2 is disposed corresponding to the 1 st, 2 nd, 3 rd and 4 th row pixel rows PXR. The 3 rd-stage emission driving sub-circuit VSR2 is disposed corresponding to the 5 th, 6 th, 7 th and 8 th row of pixel rows PXR. The rest is analogized in the same way. The 2N-th stage emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N-th rows of pixel rows PXR. For example, the 2 nd-stage emission driving sub-circuit VSR2 is disposed corresponding to the 1 st, 2 nd, 3 rd and 4 th row pixel rows PXR. The 4 th-stage emission driving sub-circuit VSR2 is disposed corresponding to the 5 th, 6 th, 7 th and 8 th row of pixel rows PXR. The rest is analogized in the same way.
In the embodiment of the present invention, the 2N-1 stage emission driving sub-circuit VSR2 is disposed corresponding to the pixel rows PXR of the 4N-3 th row, the 4N-2 th row, the 4N-1 th row and the 4N th row; the 2N-th stage emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N-th rows of pixel rows PXR. The one-stage emission driving sub-circuit VSR2 is disposed corresponding to 4 rows of pixel rows. Compared with the prior art, the number of stages of the emission driving sub-circuit VSR2 in the first non-display area NA1 and the number of stages of the emission driving sub-circuit VSR2 in the second non-display area NA2 are further reduced in the embodiments of the present invention. The size of the emission driving circuit VSRB in the first non-display area NA1 and the size of the emission driving circuit VSRB in the second non-display area NA2 are both further reduced. The width of the first non-display area NA1 and the width of the second non-display area NA2 are both further reduced. The display panel 200 further realizes a narrower frame.
As shown in fig. 2, the 2N-1 st-level emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N-level scan driving sub-circuits VSR 1; the 2N-th stage emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N-th stage scan driving sub-circuits VSR 1.
In the embodiment of the present invention, the 2N-1 st-stage emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N th-stage scan driving sub-circuits VSR 1. For example, the 1 st stage emission driving sub-circuit VSR2 is disposed corresponding to the 1 st, 2 nd, 3 rd and 4 th stage scan driving sub-circuits VSR 1. The 3 rd stage emission driving sub-circuit VSR2 is disposed corresponding to the 5 th, 6 th, 7 th and 8 th stage scan driving sub-circuits VSR 1. The rest is analogized in the same way. The 2N-th stage emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N-th stage scan driving sub-circuits VSR 1. For example, the 2 nd stage emission driving sub-circuit VSR2 is disposed corresponding to the 1 st, 2 nd, 3 rd and 4 th stage scan driving sub-circuits VSR 1. The 4 th-stage emission driving sub-circuit VSR2 is disposed corresponding to the 5 th, 6 th, 7 th and 8 th-stage scan driving sub-circuits VSR 1. The rest is analogized in the same way.
In the embodiment of the present invention, the 2N-1 st-level emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N-level scan driving sub-circuits VSR 1; the 2N-th stage emission driving sub-circuit VSR2 is disposed corresponding to the 4N-3 th, 4N-2 th, 4N-1 th and 4N-th stage scan driving sub-circuits VSR 1. The one-stage scan drive sub-circuit VSR1 is provided corresponding to one row of pixel rows PXR. The 4N-3 th, 4N-2 th, 4N-1 th and 4N th stage scan driving sub-circuits VSR1 are disposed in one-to-one correspondence with the 4N-3 th, 4N-2 th, 4N-1 th and 4N th rows of pixel rows PXR. The 4N-4 th scan driving sub-circuit VSR1 is electrically connected to the 4N-3 th pixel row PXR through the scan line SL. The 4N-3 th stage scan driving sub-circuit VSR1 is electrically connected to the 4N-3 th row and the 4N-2 th row of pixel rows PXR through two scan lines SL, respectively. The 4N-2 th scan driving sub-circuit VSR1 is electrically connected to the 4N-2 th and 4N-1 th pixel rows PXR through two scan lines SL, respectively. The 4N-1 th scan driving sub-circuit VSR1 is electrically connected to the 4N-1 th and 4N th rows of pixel rows PXR through two scan lines SL, respectively. The 4N-th stage scan driving sub-circuit VSR1 is electrically connected to the 4N-th row of pixel rows PXR through the scan lines SL. The 4N-4 th stage scan driving sub-circuit VSR1 performs an operation of an initialization phase by driving the 4N-3 th row of pixel rows PXR through the scan lines SL. The 4N-3 th stage scan driving sub-circuit VSR1 drives the 4N-3 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N-2 th row of pixel rows PXR to perform the operation of the initialization phase. The 4N-2 th stage scan driving sub-circuit VSR1 drives the 4N-2 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N-1 th row of pixel rows PXR to perform the operation of the initialization phase. The 4N-1 th stage scan driving sub-circuit VSR1 drives the 4N-1 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N th row of pixel rows PXR to perform the operation of the initialization phase. The 4N-th stage scan driving sub-circuit VSR1 drives the 4N-th row pixel row PXR through the scan line SL to perform an operation of a data writing phase. The 2N-1 st-order emission driving sub-circuit VSR2 is electrically connected to the 4N-3 th and 4N-1 th pixel rows PXR through two emission lines EL, respectively, and the 2N-order emission driving sub-circuit VSR2 is electrically connected to the 4N-2 th and 4N th pixel rows PXR through two emission lines EL, respectively. The 2N-1 st stage emission driving sub-circuit VSR2 drives the 4N-3 th and 4N-1 th row of pixel rows PXR through the two emission lines EL, respectively, to perform the operation of the emission control phase. The 2N-th stage emission driving sub-circuit VSR2 drives the 4N-2 th and 4N-th row of pixel rows PXR through the two emission lines EL, respectively, to perform the operation of the emission control phase. Thus, the 4N-3 th, 4N-2 th, 4N-1 th and 4N th pixel rows PXR emit light.
In the embodiment of the present invention, the 1 st row of pixel rows PXR is a dummy pixel row, the primary scanning driving sub-circuit VSR1 is electrically connected to the 1 st row of pixel rows PXR through the scanning line SL, the primary scanning driving sub-circuit VSR1 drives the 1 st row of pixel rows PXR through the scanning line SL to perform the operation of the data writing phase, and the 1 st row of pixel rows PXR does not perform the operation of the initialization phase.
As shown in fig. 2, the 2N-1 st-order emission driving sub-circuit VSR2 electrically connects the 4N-1 th row pixel row PXR and the 2N-order emission driving sub-circuit VSR2 through one emission line EL.
In the embodiment of the present invention, the 2N-1 st-order emission driving sub-circuit VSR2 is electrically connected to the 4N-1 th row pixel row PXR and the 2N-order emission driving sub-circuit VSR2 through one emission line EL. For example, the 1 st-stage emission driving sub-circuit VSR2 electrically connects the 3 rd row pixel row PXR and the 2 nd-stage emission driving sub-circuit VSR2 through one emission line EL. The 3 rd-order emission driving sub-circuit VSR2 electrically connects the 7 th row pixel row PXR and the 4 th-order emission driving sub-circuit VSR2 through one emission line EL. The rest is analogized in the same way. The 2N-1 st-stage emission driving sub-circuit VSR2 drives the 4N-1 th pixel row PXR through the one emission line EL to perform the operation of the emission control phase. Meanwhile, the output terminal OUT of the 2N-1 st-stage emission driving sub-circuit VSR2 transmits a turn-on signal to the input terminal IN of the 2N-th-stage emission driving sub-circuit VSR2 through the one emission line EL. Thus, the 2N-th stage emission driving sub-circuit VSR2 performs driving.
As shown in fig. 2, the 2N-th stage emission driving sub-circuit VSR2 is electrically connected to the 4N-th row pixel row PXR and the 2N + 1-th stage emission driving sub-circuit VSR2 through one emission line EL.
In the embodiment of the present invention, the 2N-th order emission driving sub-circuit VSR2 is electrically connected to the 4N-th row pixel row PXR and the 2N + 1-th order emission driving sub-circuit VSR2 through one emission line EL. For example, the 2 nd-stage emission driving sub-circuit VSR2 electrically connects the 4 th row pixel row PXR and the 3 rd-stage emission driving sub-circuit VSR2 through one emission line EL. The 4 th-stage emission driving sub-circuit VSR2 electrically connects the 8 th row pixel row PXR and the 5 th-stage emission driving sub-circuit VSR2 through one emission line EL. The rest is analogized in the same way. The 2N-th stage emission driving sub-circuit VSR2 drives the 4N-th row pixel row PXR through this one emission line EL to perform the operation of the emission control phase. Meanwhile, the output terminal OUT of the 2N-th-stage emission driving sub-circuit VSR2 transmits a turn-on signal to the input terminal IN of the 2N + 1-th-stage emission driving sub-circuit VSR2 through the one emission line EL. Thus, the 2N +1 th stage emission driving sub-circuit VSR2 performs driving.
FIG. 5 is a timing diagram of a display panel according to an embodiment of the invention.
As shown in fig. 5, in the first period S1, the 4N-4 th stage scan driving sub-circuit VSR1 of N > 1 sends an ON signal ON to the 4N-3 th row of pixel rows PXR through the scan line SL; in the second period S2, the 4N-3 th stage scan driving sub-circuit VSR1 sends ON signals ON that reach the 4N-3 th and 4N-2 th rows of pixel rows PXR through the two scan lines SL, respectively; in the third period S3, the 4N-2 th stage scan driving sub-circuit VSR1 sends ON signals ON that reach the 4N-2 th and 4N-1 th rows of pixel rows PXR through the two scan lines SL, respectively; in the fourth period S4, the 4N-1 th stage scan driving sub-circuit VSR1 sends ON signals ON to the 4N-1 th and 4N th rows of pixel rows PXR through the two scan lines SL, respectively; after the fourth period S4, the 2N-1 st-stage emission driving sub-circuit VSR2 transmits an ON signal ON to the 4N-3 th and 4N-1 th pixel rows PXR through the two emission lines EL, respectively.
In the embodiment of the present invention, the operations of the first period S1, the second period S2, the third period S3, and the fourth period S4 are sequentially performed. For example, in the 1 st first period S1(1), the scan driving sub-circuit VSR1 does not transmit the ON signal ON. In the 1 st second period S2(1), the 1 st-stage scan driving sub-circuit VSR1(1) transmits the ON signal ON reaching the 1 st and 2 nd row pixel rows PXR through the two scan lines SL, respectively. In the 1 st third period S3(1), the 2 nd-stage scan driving sub-circuit VSR1(2) transmits the ON signal ON reaching the 2 nd and 3 rd row pixel rows PXR through the two scan lines SL, respectively. In the 1 st fourth period S4(1), the 3 rd-stage scan driving sub-circuit VSR1(3) transmits the ON signal ON reaching the 3 rd and 4 th row pixel rows PXR through the two scan lines SL, respectively. After the 1 st fourth period S4(1), the 1 st-stage emission driving sub-circuit VSR2(1) transmits an ON signal ON that reaches the 1 st and 3 rd row pixel rows PXR through the two emission lines EL, respectively. In the 2 nd first period S1(2), the 4 th-stage scan driving sub-circuit VSR1(4) transmits an ON signal ON, which reaches the 5 th row of pixel rows PXR through the scan line SL. In the 2 nd second period S2(2), the 5 th-stage scan driving sub-circuit VSR1(5) transmits the ON signal ON reaching the 5 th and 6 th row pixel rows PXR through the two scan lines SL, respectively. In the 2 nd third period S3(2), the 6 th-stage scan driving sub-circuit VSR1(6) transmits the ON signal ON reaching the 6 th and 7 th row pixel rows PXR through the two scan lines SL, respectively. In the 2 nd fourth period S4(2), the 7 th-stage scan driving sub-circuit VSR1(7) transmits the ON signal ON reaching the 7 th and 8 th row pixel rows PXR through the two scan lines SL, respectively. After the 2 nd fourth period S4(2), the 3 rd-stage emission driving sub-circuit VSR2(3) transmits an ON signal ON reaching the 5 th and 7 th row pixel rows PXR through the two emission lines EL, respectively. The rest is analogized in the same way.
In the embodiment of the invention, in the first period S1, the ON signal ON sent by the 4N-4 th scan driving sub-circuit VSR1 reaches the 4N-3 th row of pixel rows PXR through the scan line SL. The 4N-4 th stage scan driving sub-circuit VSR1 performs an operation of an initialization phase by driving the 4N-3 th row of pixel rows PXR through the scan lines SL. In the second period S2, the ON signals ON transmitted by the 4N-3 th stage scan driving sub-circuit VSR1 reach the 4N-3 th and 4N-2 th rows of pixel rows PXR through the two scan lines SL, respectively. The 4N-3 th stage scan driving sub-circuit VSR1 drives the 4N-3 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N-2 th row of pixel rows PXR to perform the operation of the initialization phase. In the third period S3, the ON signals ON transmitted by the 4N-2 th stage scan driving sub-circuit VSR1 reach the 4N-2 th and 4N-1 th rows of pixel rows PXR through the two scan lines SL, respectively. The 4N-2 th stage scan driving sub-circuit VSR1 drives the 4N-2 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N-1 th row of pixel rows PXR to perform the operation of the initialization phase. In the fourth period S4, the ON signal ON transmitted by the 4N-1 th stage scan driving sub-circuit VSR1 reaches the 4N-1 th and 4N th rows of pixel rows PXR through the two scan lines SL, respectively. The 4N-1 th stage scan driving sub-circuit VSR1 drives the 4N-1 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N th row of pixel rows PXR to perform the operation of the initialization phase. After the fourth period S4, the ON signal ON transmitted by the 2N-1 th-stage emission driving sub-circuit VSR2 reaches the 4N-3 th and 4N-1 th pixel rows PXR through the two emission lines EL, respectively. The 2N-1 st stage emission driving sub-circuit VSR2 drives the 4N-3 th and 4N-1 th row of pixel rows PXR through the two emission lines EL, respectively, to perform the operation of the emission control phase. Thus, the 4N-3 th and 4N-1 th pixel rows PXR emit light.
In the embodiment of the present invention, the transistors such as the driving transistor T3 in the pixel driving circuit PX may be PMOS transistors, and the ON signals ON of the scan driving sub-circuit VSR1 and the emission driving sub-circuit VSR2 may be low level signals. The transistors such as the driving transistor T3 in the pixel driving circuit PX may be NMOS transistors, and the ON signal ON of the scanning driving sub-circuit VSR1 and the emission driving sub-circuit VSR2 may be a high level signal.
As shown in fig. 5, in the fifth period S5, the 4N-th stage scan driving sub-circuit VSR1 sends an ON signal ON, which reaches the 4N-th row pixel row PXR through the scan line SL; after the fifth period S5, the 2N-th stage emission driving sub-circuit VSR2 transmits an ON signal ON that reaches the 4N-2 th and 4N th row pixel rows PXR through the two emission lines EL, respectively.
In the embodiment of the present invention, the operation of the fifth period S5 is performed after the operation of the fourth period S4. For example, in the 1 st fifth period S5(1), the 4 th-stage scan driving sub-circuit VSR1(4) transmits an ON signal ON, which reaches the 4 th row of pixel rows PXR through the scan line SL; after the 1 st fifth period S5(1), the 2 nd-stage emission driving sub-circuit VSR2(2) transmits an ON signal ON reaching the 2 nd and 4 th row pixel rows PXR through the two emission lines EL, respectively. In the 2 nd fifth period S5(2), the 8 th-stage scan driving sub-circuit VSR1(8) transmits an ON signal ON to the 8 th row pixel row PXR through the scan line SL; after the 2 nd fifth period S5(2), the 4 th-stage emission driving sub-circuit VSR2(4) transmits an ON signal ON reaching the 6 th and 8 th row pixel rows PXR through the two emission lines EL, respectively. The rest is analogized in the same way.
In the embodiment of the invention, the ON signal ON transmitted by the 4N-3 th stage scan driving sub-circuit VSR1 reaches the 4N-3 th row and the 4N-2 th row of pixel rows PXR through the two scan lines SL, respectively, in the second period S2. The 4N-3 th stage scan driving sub-circuit VSR1 drives the 4N-3 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N-2 th row of pixel rows PXR to perform the operation of the initialization phase. In the third period S3, the ON signals ON transmitted by the 4N-2 th stage scan driving sub-circuit VSR1 reach the 4N-2 th and 4N-1 th rows of pixel rows PXR through the two scan lines SL, respectively. The 4N-2 th stage scan driving sub-circuit VSR1 drives the 4N-2 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N-1 th row of pixel rows PXR to perform the operation of the initialization phase. In the fourth period S4, the ON signal ON transmitted by the 4N-1 th stage scan driving sub-circuit VSR1 reaches the 4N-1 th and 4N th rows of pixel rows PXR through the two scan lines SL, respectively. The 4N-1 th stage scan driving sub-circuit VSR1 drives the 4N-1 th row of pixel rows PXR through the scan lines SL to perform the operation of the data writing phase and drives the 4N th row of pixel rows PXR to perform the operation of the initialization phase. In the fifth period S5, the ON signal ON sent by the 4N-th stage scan driving sub-circuit VSR1 reaches the 4N-th row of pixel rows PXR through the scan line SL. The 4N-th stage scan driving sub-circuit VSR1 drives the 4N-th row pixel row PXR through the scan line SL to perform an operation of a data writing phase. After the fifth period S5, the ON signal ON transmitted by the 2N-th stage emission driving sub-circuit VSR2 reaches the 4N-2 th and 4N-th row pixel rows PXR through the two emission lines EL, respectively. The 2N-th stage emission driving sub-circuit VSR2 drives the 4N-2 th and 4N-th row of pixel rows PXR through the two emission lines EL, respectively, to perform the operation of the emission control phase. Thus, the 4N-2 th and 4N th pixel rows PXR emit light.
As shown in fig. 2, after the fourth period S4, the ON signal ON transmitted by the 2N-1 st stage emission driving sub-circuit VSR2 reaches the 4N-1 th row of pixel rows PXR and the 2N stage emission driving sub-circuit VSR2 through one emission line EL.
In the embodiment of the invention, after the fourth period S4, the ON signal ON transmitted from the 2N-1 st stage emission driving sub-circuit VSR2 reaches the 4N-1 th row of pixel rows PXR and the 2N stage emission driving sub-circuit VSR2 through one emission line EL. For example, after the 1 st fourth period S4, the ON signal ON transmitted by the 1 st stage emission driving sub-circuit VSR2 reaches the 3 rd row pixel row PXR and the 2 nd stage emission driving sub-circuit VSR2 through one emission line EL. After the 2 nd fourth period S4, the ON signal ON transmitted by the 3 rd stage emission driving sub-circuit VSR2 reaches the 7 th row pixel row PXR and the 4 th stage emission driving sub-circuit VSR2 through one emission line EL. The rest is analogized in the same way. The 2N-1 st-stage emission driving sub-circuit VSR2 drives the 4N-1 th pixel row PXR through the one emission line EL to perform the operation of the emission control phase. Meanwhile, the output terminal OUT of the 2N-1 st-stage emission driving sub-circuit VSR2 transmits a turn-on signal to the input terminal IN of the 2N-th-stage emission driving sub-circuit VSR2 through the one emission line EL. Thus, the 2N-th stage emission driving sub-circuit VSR2 performs driving.
As shown in fig. 2, after the fifth period S5, the ON signal ON transmitted by the 2N-th stage emission driving sub-circuit VSR2 reaches the 4N-th row pixel row PXR and the 2N + 1-th stage emission driving sub-circuit VSR2 through one emission line EL.
In the embodiment of the invention, after the fifth period S5, the ON signal ON transmitted by the 2N-th stage emission driving sub-circuit VSR2 reaches the 4N-th row pixel row PXR and the 2N + 1-th stage emission driving sub-circuit VSR2 through one emission line EL. For example, after the 1 st fifth period S5, the ON signal ON transmitted by the 2 nd stage emission driving sub-circuit VSR2 reaches the 4 th row pixel row PXR and the 3 rd stage emission driving sub-circuit VSR2 through one emission line EL. After the 2 nd fifth period S5, the ON signal ON transmitted by the 4 th stage emission driving sub-circuit VSR2 reaches the 8 th row pixel row PXR and the 5 th stage emission driving sub-circuit VSR2 through one emission line EL. The rest is analogized in the same way. The 2N-th stage emission driving sub-circuit VSR2 drives the 4N-th row pixel row PXR through this one emission line EL to perform the operation of the emission control phase. Meanwhile, the output terminal OUT of the 2N-th-stage emission driving sub-circuit VSR2 transmits a turn-on signal to the input terminal IN of the 2N + 1-th-stage emission driving sub-circuit VSR2 through the one emission line EL. Thus, the 2N +1 th stage emission driving sub-circuit VSR2 performs driving.
As shown in fig. 5, the first period S1, the second period S2, the third period S3, the fourth period S4, and the fifth period S5 are sequentially repeated.
In the embodiment of the present invention, the first period S1, the second period S2, the third period S3, the fourth period S4, and the fifth period S5 are sequentially repeated. For example, first, the operations of the 1 st first period S1, the 1 st second period S2, the 1 st third period S3, the 1 st fourth period S4, and the 1 st fifth period S5 are sequentially performed. Then, the operations of the 2 nd first period S1, the 2 nd second period S2, the 2 nd third period S3, the 2 nd fourth period S4, and the 2 nd fifth period S5 are sequentially performed. Wherein the 1 st fifth period S5 coincides with the 2 nd first period S1. The rest is analogized in the same way. Thus, the plurality of pixel rows PXR maintain light emission.
FIG. 6 is a schematic diagram of an emission driving circuit in a display panel according to an embodiment of the present invention; FIG. 7 is a timing diagram of an emission driving circuit in a display panel according to an embodiment of the invention.
As shown IN fig. 6 and 7, the emission driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first clock signal terminal CK, a second clock signal terminal CKB, a low-level signal terminal VGL, a high-level signal terminal VGH, an input terminal IN, and an output terminal OUT.
In the first phase P21, the first clock signal terminal CK transmits a low level signal. The second clock signal terminal CKB transmits a high level signal. The input IN transmits a high level signal. The first transistor M1 is turned on. The second transistor M2 is turned on. The high signal at the input terminal IN is transmitted to the node N1. The tenth transistor M10 is turned off. The N2 node holds a high signal. The ninth transistor M9 is turned off. The output terminal OUT transmits a low level signal. The low level signal of the first clock signal terminal CK is transmitted to the fifth transistor M5. The low level signal of the low level signal terminal VGL is transmitted to the sixth transistor M6. The sixth transistor M6 is turned on. The high level signal of the second clock signal terminal CKB is transmitted to the third capacitor C3. The output terminal OUT transmits a low level signal.
In the second phase P22, the first clock signal terminal CK transmits a high level signal. The second clock signal terminal CKB transmits a low level signal. The input IN transmits a low level signal. The sixth transistor M6 is turned on. The low level signal of the second clock signal terminal CKB is transmitted to the third capacitor C3. The gate potential of the sixth transistor M6 decreases. The seventh transistor M7 is turned on. The ninth transistor M9 is turned on. The high level signal of the high level signal terminal VGH is transmitted to the output terminal OUT. The fifth transistor M5 is turned on. The fourth transistor M4 is turned on. The tenth transistor M10 is turned off. The output terminal OUT transmits a high level signal.
In the third stage P23, the first clock signal terminal CK transmits a low level signal. The second clock signal terminal CKB transmits a high level signal. The input IN transmits a low level signal. The first transistor M1 is turned on. The second transistor M2 is turned on. The low level at the input IN is transmitted to the node N1. The tenth transistor M10 is turned on. The low level signal of the low level signal terminal VGL is transmitted to the output terminal OUT. The eighth transistor M8 is turned on. The high level signal of the high level signal terminal VGH is transmitted to the ninth transistor M9. The ninth transistor M9 is turned off. The output terminal OUT transmits a low level signal.
In the fourth phase P24, the first clock signal terminal CK transmits a high level signal. The second clock signal terminal CKB transmits a low level signal. The input IN transmits a low level signal. The tenth transistor M10 is turned on. The low level signal of the low level signal terminal VGL is transmitted to the output terminal OUT. The high level signal of the first clock signal terminal CK is transmitted to the fifth transistor M5. The fifth transistor M5 is turned off. The eighth transistor M8 is turned on. The high signal of the high signal terminal VGH is transmitted to the N2 node. The ninth transistor M9 is turned off. The output terminal OUT transmits a low level signal.
Fig. 8 is a schematic structural diagram of a display device according to an embodiment of the invention.
As shown in fig. 8, the display device 300 includes a display panel 200.
In the embodiment of the present invention, the display device 300 implements display by using the display panel 200, such as a smart phone or the like. The display panel 200 is described above and will not be described in detail.
In summary, the present invention provides a display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area; the non-display area comprises a first non-display area and a second non-display area which are correspondingly arranged; the display panel also comprises a plurality of rows of pixel rows positioned in the display area, a scanning driving circuit and an emission driving circuit positioned in the non-display area, a plurality of scanning lines and a plurality of emission lines; the scanning driving circuit comprises a plurality of cascaded scanning driving sub-circuits, and the emission driving circuit comprises a plurality of cascaded emission driving sub-circuits; the first-stage scanning driving sub-circuit is electrically connected with two adjacent rows of pixel rows through two scanning lines respectively; the 2N-1 stage emission driving sub-circuit is positioned in the first non-display area, and the 2N stage emission driving sub-circuit is positioned in the second non-display area; the 2N-1 level emission driving sub-circuit is electrically connected with the 4N-3 th row and the 4N-1 th row of pixel rows through two emission lines respectively, the 2N level emission driving sub-circuit is electrically connected with the 4N-2 th row and the 4N th row of pixel rows through two emission lines respectively, and N is a natural number.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A display panel characterized by comprising a display area and a non-display area surrounding the display area;
the non-display area comprises a first non-display area and a second non-display area which are correspondingly arranged;
the display panel also comprises a plurality of rows of pixel rows positioned in the display area, a scanning driving circuit and an emission driving circuit positioned in the non-display area, a plurality of scanning lines and a plurality of emission lines;
the scanning driving circuit comprises a plurality of cascaded scanning driving sub-circuits, and the emission driving circuit comprises a plurality of cascaded emission driving sub-circuits;
the scanning driving sub-circuit at the first stage is electrically connected with two adjacent pixel rows through two scanning lines respectively;
the 2N-1 level emission driving sub-circuit is positioned in the first non-display area, and the 2N level emission driving sub-circuit is positioned in the second non-display area;
the 2N-1 level emission driving sub-circuit is electrically connected with the 4N-3 th row and the 4N-1 th row of the pixel row through the two emission lines respectively, the 2N level emission driving sub-circuit is electrically connected with the 4N-2 th row and the 4N th row of the pixel row through the two emission lines respectively, and N is a natural number;
the 2N-1 level emission driving sub-circuit is electrically connected with the pixel row in the 4N-1 level and the 2N level emission driving sub-circuit through one emission line;
the 2N-th-stage emission driving sub-circuit is electrically connected with the pixel row in the 4N-th row and the 2N + 1-th-stage emission driving sub-circuit through one emission line.
2. The display panel according to claim 1, wherein the emission driving sub-circuits of level 2N-1 are disposed corresponding to the pixel rows of rows 4N-3, 4N-2, 4N-1 and 4N;
the 2N-th level emission driving sub-circuit is arranged corresponding to the pixel rows in the 4N-3 th row, the 4N-2 th row, the 4N-1 th row and the 4N th row.
3. The display panel according to claim 1, wherein the emission driving sub-circuit of level 2N-1 is disposed corresponding to the scan driving sub-circuits of level 4N-3, level 4N-2, level 4N-1 and level 4N;
the 2 Nth-stage emission driving sub-circuit corresponds to the 4 Nth-3 th-stage scanning driving sub-circuit, the 4 Nth-2 th-stage scanning driving sub-circuit, the 4 Nth-1 th-stage scanning driving sub-circuit and the 4 Nth-stage scanning driving sub-circuit.
4. The display panel according to claim 1, wherein in the first period, the scan driving sub-circuit of 4N-4 th stage where N > 1 sends a turn-on signal to the pixel row of 4N-3 th row through the scan line;
in a second period, the 4N-3 th-level scanning driving sub-circuit sends conducting signals which respectively reach the 4N-3 th row and the 4N-2 th row of the pixel rows through the two scanning lines;
in a third period, the 4N-2 th-stage scanning driving sub-circuit sends conducting signals which respectively reach the 4N-2 th row and the 4N-1 th row of the pixel rows through the two scanning lines;
in a fourth period, the 4N-1 th scanning driving sub-circuit sends conducting signals which respectively reach the 4N-1 th row and the 4N th row of the pixel rows through the two scanning lines;
and after the fourth period, the 2N-1 level emission driving sub-circuit sends a conducting signal which respectively reaches the pixel rows of the 4N-3 th row and the 4N-1 th row through the two emission lines.
5. The display panel according to claim 4, wherein in a fifth period, the scan driving sub-circuit of the 4N th stage sends an on signal to the pixel row of the 4N th row through the scan line;
after the fifth time period, the 2 nth-stage emission driving sub-circuit sends conducting signals, and the conducting signals respectively reach the 4N-2 th row and the 4 nth-row of pixel rows through the two emission lines.
6. The display panel according to claim 4, wherein after the fourth period, the on signal sent by the emission driving sub-circuit of the 2N-1 st stage reaches the pixel row of the 4N-1 th row and the emission driving sub-circuit of the 2N stage through one of the emission lines.
7. The display panel according to claim 5, wherein after the fifth period, the on signal sent from the emission driving sub-circuit of the 2N-th stage reaches the pixel row of the 4N-th row and the emission driving sub-circuit of the 2N + 1-th stage through one of the emission lines.
8. The display panel according to claim 5, wherein the first period, the second period, the third period, the fourth period, and the fifth period are sequentially repeated.
9. The display panel of claim 1, wherein a row of pixels comprises a plurality of pixels, the pixels comprising: the driving circuit comprises a driving transistor, a first initialization transistor, a second initialization transistor, a first data writing transistor, a second data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a storage capacitor, an organic light-emitting diode, a first scanning end, a second scanning end, an emission end, a reference end, a data end and a power end;
the two scanning driving sub-circuits are respectively and electrically connected with the first scanning end and the second scanning end;
the emission driving sub-circuit is electrically connected with the emission end;
the driving transistor is used for generating a driving current according to the grid-source voltage of the driving transistor;
the first initialization transistor is used for being conducted under the control of the first scanning end, so that a reference signal of the reference end is transmitted to the grid electrode of the driving transistor;
the second initialization transistor is used for conducting under the control of the first scanning end, so that a reference signal of the reference end is transmitted to an anode of the organic light emitting diode;
the first data writing transistor is used for being conducted under the control of the second scanning end, so that a data signal of the data end is transmitted to the first electrode of the driving transistor;
the second data writing transistor is used for conducting under the control of the second scanning end and used for detecting and compensating the threshold voltage of the driving transistor;
the first light-emitting control transistor is used for being conducted under the control of the transmitting terminal, so that a power supply signal of the power supply terminal is transmitted to the first electrode of the driving transistor;
the second light-emitting control transistor is used for conducting under the control of the emitting end, so that the driving current is transmitted to the anode of the organic light-emitting diode;
the storage capacitor is used for detecting and compensating the threshold voltage of the driving transistor;
the organic light emitting diode is used for emitting light according to the driving current.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
CN201910559037.0A 2019-06-26 2019-06-26 Display panel and display device Active CN110176215B (en)

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CN111477178A (en) * 2020-05-26 2020-07-31 京东方科技集团股份有限公司 Pixel driving circuit, driving method thereof and display device
CN113284453A (en) * 2021-05-31 2021-08-20 合肥维信诺科技有限公司 Display panel, driving method thereof and display device
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