CN109461407B - Organic light-emitting display panel and organic light-emitting display device - Google Patents
Organic light-emitting display panel and organic light-emitting display device Download PDFInfo
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- CN109461407B CN109461407B CN201811598146.5A CN201811598146A CN109461407B CN 109461407 B CN109461407 B CN 109461407B CN 201811598146 A CN201811598146 A CN 201811598146A CN 109461407 B CN109461407 B CN 109461407B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
Abstract
The embodiment of the application provides an organic light-emitting display panel, which comprises a display area and a non-display area surrounding the display area, wherein the display area is provided with pixel rows extending along a first direction and arranged along a second direction; the non-display area is provided with a scanning driving circuit and a light-emitting control circuit; the scanning driving circuit comprises cascaded scanning driving circuit units; the light emission control circuit comprises cascaded light emission control circuit units; the scanning driving circuit unit at one stage drives 2 rows of pixel rows; the first-stage light-emitting control circuit unit drives n rows of the pixel rows, wherein n is an even number which is more than or equal to 4. This application reduces the progression of scanning drive circuit unit and luminous control circuit unit through one-level scanning drive circuit unit and luminous control circuit unit drive multirow, reduces the shared frame of drive circuit, can realize narrow frame.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to the field of display technologies, and in particular, to an organic light emitting display panel and an organic light emitting display device.
[ background of the invention ]
With the great development of display technology, the requirements of consumers on the screen ratio of display devices are higher and higher. More and more consumers are willing to purchase full screen display devices. However, the driving current deviates from the preset value due to the drift of the threshold voltage of the transistor during the use process. Therefore, the pixel driving circuit is required to compensate for the drift of the threshold voltage of the driving transistor. The pixel driving circuit needs to have a scanning driving signal and a light emission control signal controlled together. Therefore, in the related art, the scan driving circuit and the light emission control circuit are disposed in the left and right frame regions of the organic light emitting display panel. However, the provision of the scan driving circuit and the light emission control circuit requires a large number of transistors and signal lines, and occupies a space in the left and right frame regions, making it difficult to form a narrow frame.
[ summary of the invention ]
Embodiments of the present invention provide a mailing light-emitting display panel and an organic light-emitting display device to solve the above-mentioned problems.
In one aspect, the present application discloses an organic light emitting display panel, comprising a display area and a non-display area surrounding the display area, wherein the display area is provided with pixel rows extending along a first direction and arranged along a second direction; the non-display area is provided with a scanning driving circuit and a light-emitting control circuit; the scanning driving circuit comprises cascaded scanning driving circuit units; the light emission control circuit comprises cascaded light emission control circuit units; the scanning driving circuit unit at one stage drives 2 rows of pixel rows; the first-stage light-emitting control circuit unit drives n rows of the pixel rows, wherein n is an even number which is more than or equal to 4.
In one embodiment of the present application, the light-emitting control circuit unit of one stage is disposed corresponding to the scanning drive circuit unit of n/2 stage, and the light-emitting control circuit unit of one stage drives the pixel rows of n adjacent rows; and each stage of the scanning driving circuit unit drives the adjacent 2 rows of pixel rows in the n/2 rows of pixel rows.
In one embodiment of the present application, the start times of the output valid signals of the scan driving circuit units of two adjacent stages differ by a first period T1; the width of the effective signal output by the light-emitting control circuit unit of one stage is a first width W1, wherein W1 ≧ (n/2+1) × T1.
In one embodiment of the present application, each pixel row receives a first scan signal and a second scan signal; each scanning driving circuit unit outputs a second scanning signal to the pixel row corresponding to the scanning driving circuit unit, and simultaneously outputs a first scanning signal to the pixel row corresponding to the next scanning driving unit.
In one embodiment of the present application, the start time of the valid signal output by the light emission control circuit unit is earlier than the start time of the valid signal output by a scan driving circuit unit of a previous stage of the first stage of the scan driving circuit units, which is correspondingly disposed; the end time of the effective signal output by the light-emitting control circuit unit is later than the end time of the effective signal output by the last stage of scanning driving circuit unit in the correspondingly arranged scanning driving circuit unit;
in one embodiment of the application, the effective signals output by the two adjacent stages of the light-emitting control circuit units at least partially overlap, the width of the overlapped part is W2, and W2 ≧ T1.
In one embodiment of the present application, n-8, W1-12T 1; the light emission control circuit includes only a first clock signal and a second clock signal; when the first clock signal is at a low level, the second clock signal is at a high level; the first clock signal is at a high level when the second clock signal is at a low level;
in one embodiment of the present application, n is 4, W1 is 3T 1; the light emission control circuit includes only a first clock signal and a second clock signal; when the first clock signal is at a low level, the second clock signal is at a high level; the first clock signal is at a high level when the second clock signal is at a low level;
in one embodiment of the present application, the pixel row includes pixel driving circuits, each of the pixel driving circuits includes: a driving transistor coupled in series between the light emission control transistor and the light emitting device for generating a driving current; an initialization transistor coupled in series between an initialization signal line and a gate of the driving transistor, initializing the driving transistor in response to a first scan signal; a compensation transistor coupled in series between a gate and a drain of the driving transistor, threshold-compensating the driving transistor in response to a second scan signal; and a light emission control transistor coupled in series between a power signal line and the driving transistor, and controlling the transmission of the power signal to the source of the driving transistor in response to a light emission control signal.
In one embodiment of the present application, in the same pixel column, the sub-pixels in the odd-numbered rows are connected to the first driving signal line, and the sub-pixels in the even-numbered rows are connected to the second driving signal line.
In one embodiment of the present application, further comprising a demultiplexing circuit comprising a first switch and a second switch; a gate of the first switch is connected to a first switching signal, a first pole is connected to a first pole of the second switch, and a second pole is connected to the first driving signal line; the gate of the second switch is connected to a second switching signal, the first pole is connected to the first pole of the first transistor, and the second pole is connected to the second driving signal line.
In one embodiment of the present application, each pixel row receives a first scan signal and a second scan signal; each scanning driving circuit unit outputs a second scanning signal to a pixel row corresponding to the scanning driving circuit unit and simultaneously outputs a first scanning signal to a next pixel row; the active level of the second scan signal is located after the active level of the second switching signal, and the active level of the second switching signal is located after the active level of the first switching signal.
In one embodiment of the present application, the sub-pixels in the odd rows of the display panel are connected to a first pixel driving circuit; the sub-pixels in the even rows are connected with the second pixel driving circuit; the first pixel driving circuit and the second pixel driving circuit are arranged in a mirror image mode, and the mirror image axis is parallel to the direction of the data line.
In another aspect, the present application provides a display device including the display panel.
This application reduces the progression of scanning drive circuit unit and luminous control circuit unit through one-level scanning drive circuit unit and luminous control circuit unit drive multirow, reduces the shared frame of drive circuit, can realize narrow frame.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic view of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic partial enlarged view of the upper left corner of the display panel of the embodiment of FIG. 1;
FIG. 3 is a timing diagram of the display panel of the embodiment of FIG. 2;
FIG. 4 is a schematic enlarged view of a portion of a display panel according to another embodiment of the present application;
FIG. 5 is a timing diagram of the display panel of the embodiment of FIG. 4;
FIG. 6 is a schematic diagram of a pixel driving circuit in a display panel according to an embodiment of the present application;
FIG. 7 is a timing diagram of the pixel driving circuit of the embodiment of FIG. 6;
FIG. 8 is a schematic view of a display panel according to yet another embodiment of the present application;
FIG. 9 is a partially enlarged schematic view of the lower left corner of the display panel of the embodiment of FIG. 8;
FIG. 10 is a diagram of a display panel lighting control circuit according to an embodiment of the present application;
FIG. 11 is a timing diagram of the illumination control circuit of the embodiment of FIG. 10;
FIG. 12 is another timing diagram of the illumination control circuit of the embodiment of FIG. 10;
fig. 13 is a schematic view of a display device according to an embodiment of the present application.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, third, etc. may be used to describe the scan signals in the embodiments of the present invention, the scan signals should not be limited to these terms. These terms are only used to distinguish the scan signals from each other. For example, the first scan signal may also be referred to as the second scan signal, and similarly, the second scan signal may also be referred to as the first scan signal without departing from the scope of the embodiments of the present invention.
The organic light emitting display panel is driven by current to emit light through an OLED device, and belongs to current driving. And a slight current change causes a deviation of the brightness from the preset value. The drive transistor manufactured by the existing technology has the threshold voltage drift along with the increase of the service time and the aging of the transistor. Drive current Ids ═ k (Vgs-Vth)2Where Vgs represents the voltage difference between the gate and source of the drive transistor, Vth represents the threshold voltage, and k represents a transistor-related parameter. When a shift in threshold voltage occurs, Vth varies and the drive current varies. It is therefore necessary to provide a pixel drive circuit to compensate for this. The embodiment of fig. 5 of the present application provides a pixel driving circuit that compensates for threshold voltage drift. Since the pixel driving circuit needs to provide a plurality of transistors and a plurality of scan signals to realize the function of threshold voltage drift compensation. Therefore, in the prior art, the scan driving circuit and the light emitting control circuit are disposed in the left and right frame regions of the organic light emitting display panel to provide the scan signals for the pixel driving circuit. However, the provision of the scan driving circuit and the light emission control circuit requires a large number of transistors and signal lines, and occupies a space in the left and right frame regions, making it difficult to make a narrow frame.
On the other hand, consumers have more and more personalized demands for display panels. There are two requirements for personalization that the prior art has difficulty achieving. VR display and a bid display. Both VR and electronic race displays require a higher refresh rate (also called frame rate) of the display panel, i.e. more frames of a picture can be displayed in 1 second. The prior art cannot achieve such a high frame rate. For example, if the frame rate is increased from 60Hz to 120Hz, the compensation time per row of pixels is reduced to half of the original compensation time per row of pixels, which would greatly reduce the compensation effect, and therefore, the organic light emitting display panel with high frame rate has not been available for mass production.
The present application provides an organic light emitting display panel to solve the above technical problems. Referring to fig. 1 and fig. 2, fig. 1 is a schematic view of a display panel according to an embodiment of the present application; FIG. 2 is a schematic partial enlarged view of the upper left corner of the display panel of the embodiment of FIG. 1;
the application provides an organic light-emitting display panel, which comprises a display area AA and a non-display area NA surrounding the display area, wherein the display area AA is provided with pixel rows 10 which extend along a first direction and are arranged along a second direction; the non-display area NA is provided with a scanning drive circuit 3 and a light emission control circuit 4; the scan driving circuit 3 includes a cascade of scan driving circuit units 30; the light emission control circuit 4 includes cascaded light emission control circuit units 40; the scan driving circuit and the light emission control circuit are both referred to as a shift register circuit, and output valid signals step by step. For example, in the PMOS type organic light emitting display panel, the first stage of the scan driving circuit 3 receives the start signal stv1 and then outputs low level signals step by step. The first stage of the light emission control circuit 4 receives the start signal stv2 and then outputs high level signals step by step. The cascade connection means that a signal output by a previous stage is connected to a next stage as a signal source of the next stage, or a signal output by the next stage is fed back to the previous stage as a signal source of the previous stage. Here, taking the scan driving circuit 3 as an example, the input signal of the first stage scan driving circuit unit is a start signal, and the input signal of the second stage scan driving circuit unit is an output signal of the previous stage scan driving circuit unit. Each pixel row 10 includes a pixel driving circuit 101, and the light emitting devices of the pixel driving circuit 101 are correspondingly disposed. The scanning drive circuit unit 30 supplies scanning signals to the pixel drive circuit through the scanning signal lines 21 and 22; the light emission control circuit unit 40 supplies a light emission control signal to the pixel drive circuit through the light emission control signal line 23.
In this application, the first-stage scan driving circuit unit 30 drives 2 rows of the pixel rows 10; the first-stage light-emission control circuit unit 40 drives n rows of the pixel rows 10, where n is an even number equal to or greater than 4. The number of the scan driving circuit units 30 can be reduced by 1/2, and the light emission control circuit unit 40 can be more than 3/4, so that the left and right frame regions can be greatly reduced. Taking the example that the widths of the scan driving circuit and the light-emitting control circuit are both 100 μm, the scan driving circuit of the display panel using the present application only occupies 50 μm, the light-emitting control circuit only occupies less than 25 μm, and the widths of the left and right frame regions are reduced by more than 125 μm. The width of the frame is greatly reduced.
On the other hand, taking 1280 rows by 720 columns, 60Hz as an example, the time for a conventional row scan is about: 1/60/1280 ≈ 12.8 μ s, if the present embodiment is adopted, one line scan time is about: 1/60/(1280/2) ≈ 25.6 μ s, while the 7T1C circuit shown in FIG. 5 has a compensation threshold time of about 10us, the frame rate of the display panel of the present application can easily reach 120 Hz. Even if the display panel is not used for manufacturing a high-frame-rate display panel, the technical scheme of the application can also increase the time of threshold compensation and improve the effect of threshold compensation, so that the display effect is better.
The scanning signal output by the scanning driving circuit and the light emission control signal output by the light emission control circuit will be described below. Referring to fig. 6 and 7, fig. 6 is a schematic diagram of a pixel driving circuit in a display panel according to an embodiment of the present application; FIG. 7 is a timing diagram of the pixel driving circuit of the embodiment of FIG. 6;
in one embodiment of the present application, the pixel row 10 includes pixel driving circuits 101, and each of the pixel driving circuits 101 includes:
a driving transistor M3, the driving transistor M3 being coupled in series between the light emission controlling transistor M1 and the light emitting device OLED for generating a driving current;
an initialization transistor M5 coupled in series between an initialization signal line VREF and the gate of the driving transistor M3, initializing the driving transistor M3 in response to a first scan driving signal SCANA;
a compensation transistor M4 coupled in series between the gate and the drain of the driving transistor M3, for performing threshold compensation on the driving transistor M3 in response to a second scan driving signal SCANB;
and a light emission control transistor M1 coupled in series between the power supply signal line PVDD and the driving transistor M3, for controlling EMIT to transmit a power supply signal to the source of the driving transistor M3 in response to the light emission control signal.
In addition, the pixel driving circuit of the present embodiment further includes a sixth transistor M6 coupled in series between the third transistor M3 and the light emitting device OLED, and controlling whether the driving current flows through the light emitting device OLED in response to the light emission control signal EMIT.
A light emitting device initialization transistor M7 is further included to initialize the light emitting device OLED in response to the first scan driving signal SCANA.
The operation of the pixel driving circuit of this embodiment will be described with reference to the timing sequence of fig. 6.
In the first period t1, the first scan driving signal SCANA is at a low level, the second scan driving signal SCANB is at a high level, and the emission control signal EMIT is at a high level; at this time, the transistors M5 and M7 are turned on, the other transistors are turned off, and the initialization signal VREF is transmitted to the gate of the driving transistor M3 to initialize the driving transistor; the initialization signal VREF is transmitted to the light emitting device OLED through the transistor M7 to initialize the light emitting device;
in the second period t2, the first scan driving signal SCANA is at a high level, the second scan driving signal SCANB is at a low level, and the emission control signal EMIT is at a high level; the DATA signal DATA at this time is transmitted to the source of the driving transistor M3 through the transistor M2. Since the initialization signal at the previous stage is at a low level, the driving transistor M3 is turned on, the DATA signal DATA is transmitted to the gate of the driving transistor M3 through the compensation transistor M4, and the potential of the gate of the driving transistor M3 is raised, when the potential of the driving transistor M3 reaches Vdata-Vth, the driving transistor is turned off, and the gate potential is stored by the storage capacitor Cst;
in a third period t3, the first scan driving signal SCANA is at a high level, the second scan driving signal SCANB is at a high level, and the emission control signal EMIT is at a low level; the light emission control transistor M1 is turned on, and the power supply voltage PVDD is transmitted to the source of the driving transistor M3, at which time the driving transistor M1 is turned onThe gate voltage of M3 is Vdata-Vth, and thus, the driving current Ids ═ k · (Vgs-Vth)2＝k*(PVDD-(Vdata-Vth) -Vth)2＝k*(PVDD-Vth)2Therefore, the influence of the shift of the threshold voltage Vth on the light emission drive current is eliminated, and the shift of the threshold voltage is compensated.
As can be seen from the above, the pixel driving circuit requires at least three scan signals, the first scan driving signal SCANA, the second scan driving signal SCANB and the emission control signal EMIT to implement the compensation. Since the waveforms of the first scan driving signal SCANA and the second scan driving signal SCANB are the same, and differ by only one period, so that the same shift register can output, the present application uses the scan driving circuit unit 30 to output the first scan driving signal SCANA and the second scan driving signal SCANB, and outputs the emission control signal EMIT through the emission control circuit unit 40.
It should be noted that the term that the one-stage scan driving circuit unit drives the 2 rows of pixel rows refers to that the one-stage scan driving circuit unit simultaneously provides the same driving signal to the 2 rows of pixel rows, for example, the one-stage scan driving circuit unit simultaneously provides the second scan driving signal SCANB to the 2 rows of pixel rows. The one-stage scan driving circuit unit supplies the second scan driving signal SCANB to the pixel rows of 1 row, and supplies the first scan driving signal SCANA to the pixel rows of the next row in a multiplexed manner, instead of simultaneously driving the pixel rows of 2 rows as described in the present application.
Further, the light-emitting control circuit unit 40 of one stage is disposed corresponding to the scanning driving circuit unit 30 of n/2 stage, and the light-emitting control circuit unit 40 of one stage drives the pixel rows 10 of n adjacent rows; and each stage of the scanning driving circuit unit drives the adjacent 2 rows of pixel rows 10 in the n/2 rows of pixel rows. The embodiment of fig. 2 is illustrated by n-4, and the embodiment of fig. 4 is illustrated by n-8.
Taking n-4 as an example, please refer to fig. 2 and fig. 3, and fig. 3 is a timing diagram of the display panel of the embodiment of fig. 2; the first-stage light-emitting control circuit unit 40 is arranged corresponding to the 2-stage scanning driving unit 30, and the first-stage light-emitting control circuit unit 40 drives the adjacent 4 rows of pixel rows 10; each stage of the scan driving circuit unit 30 drives two adjacent rows of the 2 rows of pixel rows.
Taking n-8 as an example, please refer to fig. 4 and 5, fig. 4 is a schematic partial enlarged view of a display panel according to another embodiment of the present disclosure; FIG. 5 is a timing diagram of the display panel of the embodiment of FIG. 4; the first-stage light-emitting control circuit unit 40 is arranged corresponding to the 4-stage scanning driving unit 30, and the first-stage light-emitting control circuit unit 40 drives the adjacent 8 rows of pixel rows 10; each stage of the scan driving circuit unit 30 drives two adjacent rows of the 4 rows of pixel rows.
Further, the start time of the effective signal output by the scanning driving circuit units of two adjacent stages differs by a first period T1; the width of the valid signal output by the light-emitting control circuit unit 40 of one stage is a first width W1, where W1 ≧ (n/2+1) × T1.
Taking n-4 as an example, the width W1 of the valid signal output by the primary light-emitting control circuit unit 40 is greater than or equal to 3T 1. The effective signal is a signal which can enable the speed-limiting driving circuit to effectively work. Taking the PMOS pixel driving circuit shown in fig. 6 as an example, the active signal of the scanning driving signal is at a low level, and the active signal of the emission control signal is at a high level. In fig. 3, S1A represents the first scan driving signal SCANA for the first row of pixels, S1B represents the second scan driving signal SCANB for the first row of pixels, S2A represents the first scan driving signal scab for the second row of pixels, S2B represents the second scan driving signal scab for the second row of pixels, and so on. Since the one-stage scan driving circuit unit 30 in this embodiment drives 2 rows of pixel rows, the waveforms of the first scan driving signal and the second scan driving signal of the first pixel row and the second pixel row are completely identical. Similarly, the waveforms of the first scanning signal and the second scanning signal of the third pixel row and the fourth pixel row are also identical. Since the one-stage emission control circuit unit drives the 4 rows of pixel rows in this embodiment, one emission control signal EMIT is shared for the first pixel row to the fourth pixel row. It should be noted that in this embodiment, the scan driving circuit at the current stage outputs the second scan driving signal SCANB to the corresponding pixel row while outputting the first scan driving signal SCANA to the pixel row corresponding to the scan driving circuit at the next stage, so that the scan time of each row can be reduced. According to the timing sequence of fig. 7, the emission control circuit must be at a high level when the sub-pixels of each row are initialized (the first scan signal is at a low level) and threshold compensated (the second scan signal is at a low level), so that it is necessary to have one more period than the period of the valid signal that can be output by the scan driving circuit unit 30 corresponding to the emission control circuit unit 40 of the first stage, that is, the width W1 of the emission control signal is ≧ (n/2+1) ≧ T1 in this embodiment. For example, if n is 4, W1 is equal to or greater than 3T 1. This ensures that the pixel driving circuits of the pixel rows driven by the same stage of the emission control circuit unit 40 can operate normally.
Taking n as an example, the width W1 of the valid signal output by the primary light-emitting control circuit unit 40 is greater than or equal to 5T 1. The effective signal is a signal which can enable the speed-limiting driving circuit to effectively work. Taking the PMOS pixel driving circuit shown in fig. 6 as an example, the active signal of the scanning driving signal is at a low level, and the active signal of the emission control signal is at a high level. Since the one-stage emission control circuit unit drives the pixel rows of 8 rows in the present embodiment, one emission control signal E1 is shared for the first pixel row to the eighth pixel row. According to the timing sequence of fig. 7, the emission control circuit must be at a high level when the sub-pixels in each row are initialized (the first scan signal is at a low level) and threshold compensated (the second scan signal is at a low level), so that it is necessary to have one more period than the period of the effective signal that can be output by the scan driving circuit unit 30 corresponding to the emission control circuit unit 40 in the first stage, and the width W1 of the emission control signal is ≧ (n/2+1) ≧ T1 in this embodiment. For example, W1 is not less than 5T1 when n is 8. This ensures that the pixel driving circuits of the pixel rows driven by the same stage of the emission control circuit unit 40 can operate normally.
Further, the start time of the effective signal output by the light emission control circuit unit 40 is earlier than the start time of the effective signal output by the previous stage scan driving circuit unit of the first stage scan driving circuit unit in the scan driving circuit units correspondingly arranged; the end time of the effective signal output by the light-emitting control circuit unit 40 is later than the end time of the effective signal output by the last stage of the correspondingly arranged scanning driving circuit units; as can be seen from the foregoing, the scan driving unit 30 outputs the second scan driving signal to the pixel row corresponding thereto, and thus the first scan driving signal of the row corresponding thereto is output by the previous stage scan driving circuit. Therefore, in order to ensure that the pixel start circuits of the pixel rows corresponding to the light emission control circuit unit can operate normally, the start time of the valid signal output by the light emission control circuit unit 40 must be earlier than the start time of the valid signal output by the scan driving circuit unit arranged in front of the first scan driving circuit unit in the scan driving circuit unit. Similarly, the end time of the valid signal output by the light emission control circuit unit 40 is later than the end time of the valid signal output by the last stage of the correspondingly arranged scan driving circuit units; taking the embodiment of fig. 3 as an example, S1A and S2A are scan signals output from a previous stage scan driving circuit unit. The start time of the light emission control signal E1 must be earlier than the start time of the active signals of S1A and S2A. The end time of the same emission control signal E1 must be later than the end time of S3B and S4B. Taking the embodiment of fig. 5 as an example, S1A and S2A are scan signals output from a previous stage scan driving circuit unit. The start time of the light emission control signal E1 must be earlier than the start time of the active signals of S1A and S2A. The end time of the same emission control signal E1 must be later than the end time of the valid signals of S7B and S8B.
Further, when n is 8, let W1 be 12T 1; the light emission control circuit 4 may be made to include only the first clock signal and the second clock signal; the first clock signal and the second clock signal are opposite clock signals. That is, when the first clock signal is at a low level, the second clock signal is at a high level; the first clock signal is at a high level when the second clock signal is at a low level; the low levels of the first clock signal and the second clock signal do not overlap, and the high levels may partially overlap. Since the light emission control signals output by the present embodiment need to be at least partially overlapped, the number of clock signals generally needs to be increased to realize the overlapping according to the circuit of the signals output by the shift register. The inventor of the present application finds that only one group of clock signals is needed when the width of the effective signal of the light-emitting control signal is equal to 12 cycles, so that the number of signal lines can be reduced, the load of the driving chip can be reduced, and the narrow frame can be achieved.
Fig. 10 is a diagram illustrating an embodiment of a light-emitting control circuit according to the present application, and fig. 11 is a diagram illustrating an operation timing of the light-emitting control circuit. FIG. 10 is a diagram of a display panel lighting control circuit according to an embodiment of the present application; FIG. 11 is a timing diagram of the illumination control circuit of the embodiment of FIG. 10;
IN a period t4, the first clock signal CK is at a low level, the second clock signal CKB is at a high level, and the input signal IN is at a high level; the first transistor M1 and the second transistor M2 are turned on, the high level of the input signal IN is transmitted to the N1 node through the first transistor M1, and the tenth transistor M10 is turned off. The node N2 is kept high at the previous time by the second capacitor C2, and the ninth transistor M9 is turned off. The output terminal OUT continuously outputs the low level at the previous time. On the other hand, the low level and VGL of the first all-time signal CK are output to the gates of the fifth transistor M5 and the sixth transistor M6 through the third transistor M3 and the second transistor M2, respectively; the sixth transistor M6 is turned on, and the high level of the second clock signal is transmitted to the other pole of the capacitor C3. At this time, a low level signal is output.
IN a period t5, the first clock signal CK is at a high level, the second clock signal CKB is at a low level, and the input signal IN is at a low level; since the gate of the sixth transistor M6 is at a low level at the previous time, M6 is turned on, and a low level of the second clock signal CKB is transmitted to the other pole of the capacitor C3. At the same time, the other pole of the capacitor C3 is at a high level at the upper moment, which is at a low level, so that the gate potential of the sixth transistor M6 is further lowered by the coupling of the capacitor C3. Meanwhile, the seventh transistor M7 is turned on, and the low level is transmitted to the N2 node, so that the ninth transistor M9 is turned on, and the high level signal VGH is transmitted to the output signal terminal OUT through the ninth transistor M9, at which time the high level signal is output. Meanwhile, the fifth transistor M5 and the fourth transistor M4 are turned on, and a high level signal is transmitted to the N1 node, so that the tenth transistor M10 is turned off. At this time, a high level signal is output.
At the stage t6, the first clock signal CK is at a low level, the second clock signal CKB is at a high level, and the input signal IN is at a low level; the first transistor M1 and the second transistor M2 are turned on, the low level of the input signal IN is transmitted to the N1 node through the first transistor M1, the tenth transistor M10 is turned on, and the low level signal VGL is transmitted to the output terminal OUT by the tenth transistor M10; on the other hand, the gate of the eighth transistor M8 is connected to the N1 node, so that the eighth transistor M8 is turned on, a high level signal VGH is transmitted to the gate of the ninth transistor M9, and the ninth transistor M9 is turned off; at this time, a low level signal is output.
At the stage t7, the first clock signal CK is at a high level, the second clock signal CKB is at a low level, and the input signal IN is at a low level; the node N1 maintains the low level at the previous time, so that the tenth transistor M10 is turned on and a low level signal VGL is transmitted to the output terminal OUT; meanwhile, the second clock signal CKB changes from a high level at the previous time to a low level and is coupled to the N1 node through the first capacitor C1, so that the tenth transistor M10 preferably outputs a low level VGL; meanwhile, the high level of the first always signal CK is transmitted to the gate of the fifth transistor M5 through the third transistor M3, so that the fifth transistor M5 is turned off, preventing the high level VGH from being transmitted to the N1 node. On the other hand, the node N1 is low to turn on the eighth transistor M8, and the high signal VGH is transmitted to the node N2 to turn off the ninth transistor; at this time, a low level signal is output.
Thereafter, the t6 phase and the t7 phase are repeated to output the low level only continuously until the high level start signal of the next frame.
Referring to fig. 12, fig. 12 is another timing diagram of the light-emitting control circuit of the embodiment of fig. 10; referring to fig. 12, when n is 8, let W1 be 12T 1; the light emission control circuit 4 may be made to include only the first clock signal CK and the second clock signal CKB; wherein the period of the first clock signal and the second clock signal is 8T1, and the shaded portion is the phase of the sub-pixel data input writing of the corresponding 8 rows. It can be seen that when W1 is 12T1, adjacent light-emitting control signals can be overlapped by using only one set of clock signals, so that the start time of the effective signal output by the light-emitting control circuit unit 40 is earlier than the start time of the effective signal output by the previous scan driving circuit unit of the first scan driving circuit unit in the scan driving circuit units correspondingly arranged; the end time of the effective signal output by the light-emitting control circuit unit 40 is later than the end time of the effective signal output by the last stage of the correspondingly arranged scanning driving circuit units;
similarly, when n is 4, W1 is 3T1, and the above object can be achieved by only one set of clock signals. Will not be described in detail herein.
In another embodiment of the present application, since the first scan driving signal SCANA and the second scan driving signal SCANB are multiplexed on the corresponding rows of the adjacent scan driving circuits, the active signals output by the two adjacent stages of the emission control circuit units 40 at least partially overlap, and the width of the overlapped portion is W2, W2 ≧ T1. Taking the embodiment of fig. 3 as an example, since S3B and S4B also serve as the first scan signals S5A and S6A for the pixels in the fifth row and the sixth row, the start time of the signal E2 output by the next-stage emission control circuit must be earlier than the start times of S5A and S6A, i.e., earlier than the start times of S3B and S4B. Meanwhile, the end time of E1 must be later than the end times of S3B and S4B. Therefore, it is necessary to include this period for E1 and E2 to ensure that the pixel driving circuits of the pixel rows corresponding to the two adjacent stages of the emission control circuit units 40 operate normally. Taking the embodiment of fig. 5 as an example, since S7B and S8B also serve as the first scan signals S9A and S10A for the pixels in the ninth and tenth rows, the start time of the signal E2 output from the next-stage emission control circuit must be earlier than the start times of S9A and S10A, i.e., earlier than the start times of S7B and S8B. Meanwhile, the end time of E1 must be later than the end times of S7B and S8B. Therefore, it is necessary to include this period for E1 and E2 to ensure that the pixel driving circuits of the pixel rows corresponding to the two adjacent stages of the emission control circuit units 40 operate normally.
In another embodiment of the present application, please refer to fig. 8, fig. 8 is a schematic view of a display panel according to another embodiment of the present application; FIG. 9 is a partially enlarged schematic view of the lower left corner of the display panel of the embodiment of FIG. 8;
in the same pixel column 50, the sub-pixels in the odd-numbered rows are connected to a first driving signal line 51, and the sub-pixels in the even-numbered rows are connected to a second driving signal line 52. Since the first-stage scan driving circuit unit 30 drives the 2 rows of pixel rows 10, and the sub-pixels in the same column are connected to the same data line in the prior art, the two rows of sub-pixels driven by the same scan driving circuit unit 30 write the same data signal and emit the same brightness. In the application, the sub-pixels in the odd-numbered rows and the even-numbered rows are connected with different driving signal lines, and data signals can be written into the two rows of pixels simultaneously by matching with the scanning driving circuit of the application.
For example: the first-stage scanning driving circuit unit drives a first row of pixel rows and a second row of pixel rows simultaneously; when the first scan driving circuit unit outputs a low-level signal, the sub-pixels of the first pixel row and the sub-pixels of the second pixel row start writing data signals. According to the prior art, since only one data line is provided for the sub-pixels of the first pixel row and the second pixel row in the same column, the data signals are written into the sub-pixels of the first pixel row and the second pixel row simultaneously through the data line, and therefore, the sub-pixels in the same column in the first pixel row and the second pixel row can only display the same brightness. According to the present application, the sub-pixels in the first pixel row and the second pixel row in the same column are respectively connected to the first driving signal line 51 and the second driving signal line 52, so that when the first-stage scan driving circuit unit simultaneously outputs low-level signals to the first pixel row and the second pixel row, the first driving signal line 51 and the second driving signal line 52 simultaneously respectively provide respective data signals to the sub-pixels in the first pixel row and the second pixel row, thereby implementing simultaneous driving.
Furthermore, the sub-pixels in the odd rows in the display panel are connected with a first pixel driving circuit; the sub-pixels in the even rows are connected with the second pixel driving circuit; the first pixel driving circuit and the second pixel driving circuit are arranged in a mirror image mode, and the mirror image axis is parallel to the direction of the data line. Referring to fig. 9, black dots in fig. 9 represent connection points between the pixel driving circuit and the driving signal lines. This application sets up the pixel drive circuit mirror image setting of the pixel drive circuit in odd number row and even number row for drive first drive signal line and the dislocation of second drive signal line position on display panel and distribute, avoid first drive signal line and second drive signal line to need overlap the setting, increase the degree of difficulty of technology, reduce and generate efficiency.
Further, a demultiplexing circuit 60 is also included, the demultiplexing circuit 60 includes a first switch 61 and a second switch 62; the gate of the first switch 61 is connected to the first switching signal CKH1, the first pole is connected to the first pole of the second switch, and the second pole is connected to the first driving signal line 51; the gate of the second switch 62 is connected to the second switching signal CKH2, the first pole is connected to the first pole of the first transistor, and the second pole is connected to the second driving signal line 52.
Because each pixel column of the display panel is provided with two driving signal lines, the number of the driving signal lines of the whole display panel is doubled compared with the prior art, and the cost of the driving chip can be increased. In the embodiment, the number of the driving signal lines is halved by the demultiplexing circuit 60, so that the number of the driving signal lines is not increased compared with the prior art.
Further, each pixel row receives a first scanning signal and a second scanning signal; each scanning driving circuit unit outputs a second scanning signal to a pixel row corresponding to the scanning driving circuit unit and simultaneously outputs a first scanning signal to a next pixel row; the active level of the second scan signal is located after the active level of the second switching signal, and the active level of the second switching signal is located after the active level of the first switching signal. Referring to fig. 6 and 7, the stage where the driving signal writing (data writing or threshold compensation) is actually performed is the stage t2, i.e., the stage where the second scan driving signal SCANB is at a low level. The present embodiment writes the driving signal to the driving transistor in a line charge manner. First, CKH1 is low, and the driving signal is written to the first driving signal line 51, and this driving signal is held by the parasitic capacitance of the first driving signal line 51; following a low level of CKH2, the drive signal is written on the second drive signal line 52, held by the secondary capacitance of the second drive signal line 52; next, when the second scan driving signal SCANB is at a low level, the driving signals stored in the first driving signal line 51 and the second driving signal line 52 are written into the pixel driving circuits in the odd-numbered rows and the even-numbered rows, respectively, corresponding to the current scan driving circuit unit.
Taking the embodiment of fig. 2 and 3 as an example, for the first row and the second row of pixel rows, CKH1 is low first, the drive signal is written as the first drive signal line 51, and this drive signal is held by the parasitic capacitance of the first drive signal line 51; following a low level of CKH2, the drive signal is written on the second drive signal line 52, held by the secondary capacitance of the second drive signal line 52; next, the second scan signals S1B and S2B are low-level, and the drive signals stored on the first drive signal line 51 and the second drive signal line 52 are written to the pixel drive circuits of the first and second rows of pixel rows, respectively. Similarly, the S3B and S4B active levels are also after the active levels of CKH1 and CKH 2.
Taking 1280 rows by 720 columns, 60Hz as an example, the time for a conventional row scan is about: 1/60/1280 ≈ 12.8 μ s, if the present embodiment is adopted, one line scan time is about: 1/60/(1280/2) ≈ 25.6 μ S, for example, when the low level of CKH1 is 2 μ S, the low level of CKH2 is also 2 μ S, the interval between CKH1 and CKH2 is 1 μ S, and the interval between CKH2 and S1B is 1 μ S, the available compensation time is 25.6-6 ═ 19.6 μ S. Whereas conventionally available untries are seen to be roughly around 10 mus. Therefore, on the one hand, the compensation time can be increased, and the compensation effect is improved. Or the application only reserves the tasteless time of 10 mus, but can realize the display of high frame rate.
The present application also discloses an organic light emitting display device. The organic light emitting display device of the present application may include the organic light emitting display panel 100 as described above. Including but not limited to a cellular phone 1000, a tablet computer, a display of a computer, a display applied to a smart wearable device, a display device applied to a vehicle such as an automobile, etc., as shown in fig. 13. The display device is considered to fall within the scope of protection of the present application as long as the display device includes the display panel included in the display device disclosed in the present application.
According to the organic light-emitting display panel and the organic light-emitting display device, on one hand, the left frame and the right frame of the display panel can be reduced, and the screen occupation ratio of the display panel is greatly improved; and on the other hand, a display panel with a high frame rate can be realized or the compensation time can be increased to improve the compensation effect.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (12)
1. An organic light emitting display panel comprising a display region and a non-display region surrounding the display region,
the display area is provided with pixel rows which extend along a first direction and are arranged along a second direction;
the non-display area is provided with a scanning driving circuit and a light-emitting control circuit; the scanning driving circuit comprises cascaded scanning driving circuit units; the light emission control circuit comprises cascaded light emission control circuit units;
the scanning driving circuit unit at one stage drives 2 rows of pixel rows;
the first-stage light-emitting control circuit unit drives n rows of the pixel rows, wherein n is an even number which is more than or equal to 4;
the first-stage light-emitting control circuit unit is arranged corresponding to the n/2-stage scanning driving circuit unit and drives the adjacent n rows of pixel rows; each stage of the scanning driving circuit unit drives the adjacent 2 rows of pixel rows in the n/2 rows of pixel rows;
the start time of the effective signal output by the adjacent two stages of scanning driving circuit units is different by a first period T1;
the width of the effective signal output by the light-emitting control circuit unit of one stage is a first width W1, wherein W1 ≧ (n/2+1) × T1.
2. The organic light-emitting display panel according to claim 1,
each pixel row receives a first scanning signal and a second scanning signal;
each scanning driving circuit unit outputs a second scanning signal to the pixel row corresponding to the scanning driving circuit unit, and simultaneously outputs a first scanning signal to the pixel row corresponding to the next scanning driving unit.
3. The organic light-emitting display panel according to claim 1,
the starting time of the effective signal output by the light-emitting control circuit unit is earlier than the starting time of the effective signal output by the previous scanning driving circuit unit of the first scanning driving circuit unit in the correspondingly arranged scanning driving circuit units;
the end time of the effective signal output by the light-emitting control circuit unit is later than the end time of the effective signal output by the last stage of scanning driving circuit unit in the correspondingly arranged scanning driving circuit unit.
4. The organic light-emitting display panel according to claim 3,
the effective signals output by the two adjacent stages of the light-emitting control circuit units at least partially overlap, the width of the overlapped part is W2, and W2 is more than or equal to T1.
5. The organic light-emitting display panel according to claim 1,
n＝8，W1＝12T1；
the light emission control circuit includes only a first clock signal and a second clock signal;
when the first clock signal is at a low level, the second clock signal is at a high level; the first clock signal is at a high level when the second clock signal is at a low level.
6. The organic light-emitting display panel according to claim 1,
n＝4，W1＝3T1；
the light emission control circuit includes only a first clock signal and a second clock signal;
when the first clock signal is at a low level, the second clock signal is at a high level; the first clock signal is at a high level when the second clock signal is at a low level.
7. The organic light-emitting display panel according to claim 2,
the pixel row includes pixel drive circuits, each of the pixel drive circuits including:
a driving transistor coupled in series between the light emission control transistor and the light emitting device for generating a driving current;
an initialization transistor coupled in series between an initialization signal line and a gate of the driving transistor, initializing the driving transistor in response to a first scan signal;
a compensation transistor coupled in series between a gate and a drain of the driving transistor, threshold-compensating the driving transistor in response to a second scan signal;
and a light emission control transistor coupled in series between a power signal line and the driving transistor, and controlling the transmission of the power signal to the source of the driving transistor in response to a light emission control signal.
8. The organic light-emitting display panel according to claim 1,
in the same pixel column, the sub-pixels in the odd-numbered rows are connected with a first driving signal line, and the sub-pixels in the even-numbered rows are connected with a second driving signal line.
9. The organic light-emitting display panel according to claim 8,
the multi-path demultiplexing circuit comprises a first switch and a second switch;
a gate of the first switch is connected to a first switching signal, a first pole is connected to a first pole of the second switch, and a second pole is connected to the first driving signal line;
the gate of the second switch is connected to a second switching signal, the first pole is connected to the first pole of the first switch, and the second pole is connected to the second driving signal line.
10. The organic light-emitting display panel according to claim 9,
each pixel row receives a first scanning signal and a second scanning signal;
each scanning driving circuit unit outputs a second scanning signal to a pixel row corresponding to the scanning driving circuit unit and simultaneously outputs a first scanning signal to a next pixel row;
the active level of the second scan signal is located after the active level of the second switching signal, and the active level of the second switching signal is located after the active level of the first switching signal.
11. The organic light-emitting display panel according to claim 8,
the sub-pixels in the odd rows in the display panel are connected with a first pixel driving circuit; the sub-pixels in the even rows are connected with the second pixel driving circuit;
the first pixel driving circuit and the second pixel driving circuit are arranged in a mirror image mode, and the mirror image axis is parallel to the direction of the data line.
12. An organic light emitting display device comprising the organic light emitting display panel according to any one of claims 1 to 11.
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| CN110277064B (en) * | 2019-06-28 | 2021-01-26 | 厦门天马微电子有限公司 | Display panel and display device |
| CN110400541B (en) * | 2019-07-31 | 2021-09-28 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN110619840B (en) * | 2019-10-31 | 2022-12-20 | 武汉天马微电子有限公司 | Display panel, driving method thereof and display device |
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| CN112114709B (en) * | 2020-09-24 | 2022-11-22 | 厦门天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN112509517B (en) | 2020-11-26 | 2022-07-12 | 合肥维信诺科技有限公司 | Driving method of pixel circuit and display panel |
| CN112863448A (en) * | 2021-01-11 | 2021-05-28 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114005411A (en) * | 2021-11-05 | 2022-02-01 | 武汉天马微电子有限公司 | Array substrate, display panel and display device |
| CN114038383B (en) | 2021-11-30 | 2024-03-08 | 武汉天马微电子有限公司 | Display panel, driving method thereof and display device |
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