CN110400541B - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN110400541B
CN110400541B CN201910705453.7A CN201910705453A CN110400541B CN 110400541 B CN110400541 B CN 110400541B CN 201910705453 A CN201910705453 A CN 201910705453A CN 110400541 B CN110400541 B CN 110400541B
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scanning
scan
positive
reverse
signal
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CN110400541A (en
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李玥
周星耀
张蒙蒙
杨帅
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Wuhan Tianma Microelectronics Co Ltd
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Shanghai Tianma AM OLED Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

An embodiment of the present application provides a display panel, including: a display area and a non-display area surrounding the display area; the display area comprises pixel rows arranged along a column direction; each pixel row comprises a plurality of sub-pixels, a first scanning line and a second scanning line which are connected with the sub-pixels; the non-display area comprises a first positive and negative scanning drive circuit and a second positive and negative scanning drive circuit; the first positive and negative scanning driving circuit is connected with each first scanning line; the second positive and negative scanning driving circuit is connected with each second scanning line; the first positive and negative scanning driving circuit and the second positive and negative scanning driving circuit are respectively arranged in the non-display areas at two sides of the display area; the display panel comprises a forward scanning mode and a reverse scanning mode; in a forward scanning mode and a reverse scanning mode, a first scanning line is used for providing a first scanning signal, and a second scanning line is used for providing a second scanning signal; the effective pulse of the first scanning signal is before the effective pulse of the second scanning signal. The display panel of the application can realize forward scanning and reverse scanning.

Description

Display panel and display device
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to a display panel and a display device.
[ background of the invention ]
At present, the display device in the consumer electronics field can only realize one-way scanning. This results in the prior art display panel being usable in only one orientation. For example, a circular or square wristwatch is difficult to distinguish between the top and bottom in the black state, and is prone to misband, which requires the wearer to re-wear the wristwatch. For example, the frames such as four sides of the tablet computer are easy to be reversed in the black screen state, and the direction needs to be turned off in use to influence the user experience, so that a display panel capable of realizing positive and negative scanning is urgently needed.
[ summary of the invention ]
Embodiments of the present invention provide a display panel and a display device to solve the above technical problems.
In one aspect, the present application provides a display panel, comprising: a display area and a non-display area surrounding the display area; the display area comprises pixel rows arranged along a column direction; each pixel row comprises a plurality of sub-pixels, and a first scanning line and a second scanning line which are connected with the sub-pixels; the non-display area comprises a first positive and negative scanning driving circuit and a second positive and negative scanning driving circuit; the first positive and negative scanning driving circuit is connected with each first scanning line; the second positive and negative scanning driving circuit is connected with each second scanning line; the first positive and negative scanning driving circuit and the second positive and negative scanning driving circuit are respectively arranged in the non-display areas at two sides of the display area; the display panel comprises a forward scanning mode and a reverse scanning mode; in the forward scanning mode and the reverse scanning mode, the first scanning line is used for providing a first scanning signal, and the second scanning line is used for providing a second scanning signal; the effective pulse of the first scanning signal is before the effective pulse of the second scanning signal.
In another aspect, the present application provides a display device including the foregoing display panel.
According to the display panel and the display device, a first positive and negative scanning driving circuit and a second positive and negative scanning driving circuit are arranged; the first positive and negative scanning driving circuit is connected with each first scanning line; the second positive and negative scanning driving circuit is connected with each second scanning line; the first positive and negative scanning driving circuit and the second positive and negative scanning driving circuit are respectively arranged in the non-display areas at two sides of the display area; in the normal scanning mode, the first scanning line is used for providing a first scanning signal, and the second scanning line is used for providing a second scanning signal; the effective pulse of the first scanning signal is before the effective pulse of the second scanning signal. In the reverse scanning mode, the first scanning line is used for providing a first scanning signal, and the second scanning line is used for providing a second scanning signal; the effective pulse of the first scanning signal is before the effective pulse of the second scanning signal. The method and the device can realize forward scanning and reverse scanning. In the forward scanning process and the reverse scanning process, the effective pulse of the first scanning signal is positioned in front of the effective pulse of the second scanning signal, so that the time sequence consistency can be kept in the forward scanning process and the reverse scanning process, the same data signals in the forward scanning process and the reverse scanning process correspond to the same brightness, two sets of gammas are avoided being arranged in the forward scanning process and the reverse scanning process, the display consistency can be improved, and the production efficiency can be improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of AA' of FIG. 1;
FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present application;
FIG. 4 is a timing diagram of the pixel circuit of FIG. 3;
FIG. 5 is a timing diagram illustrating a panel normal scan mode according to an embodiment of the present application;
FIG. 6 is a timing diagram illustrating a reverse scan mode of a display panel according to an embodiment of the present application;
FIG. 7 is a schematic view of a display panel according to an embodiment of the present application;
FIG. 8 is a schematic view of a display panel according to another embodiment of the present application;
FIG. 9 is a schematic view of a display panel according to yet another embodiment of the present application;
FIG. 10 is a schematic view of a display panel according to yet another embodiment of the present application;
FIG. 11 is a schematic view of a display device according to an embodiment of the present application;
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, third, etc. may be used to describe scan lines in embodiments of the present invention, these scan lines should not be limited to these terms. These terms are only used to distinguish scan lines from one another. For example, the first scan line may also be referred to as a second scan line, and similarly, the second scan line may also be referred to as a first scan line without departing from the scope of embodiments of the present invention.
As described in the background, the display panel of the prior art cannot realize the forward and backward scanning. Referring to fig. 1 to 6, the present application provides a display panel capable of realizing forward and reverse scanning. FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application; FIG. 2 is a schematic cross-sectional view of AA' of FIG. 1; FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present application; FIG. 4 is a timing diagram of the pixel circuit of FIG. 3; FIG. 5 is a timing diagram illustrating a panel normal scan mode according to an embodiment of the present application; FIG. 6 is a timing diagram illustrating a reverse scan mode of a display panel according to an embodiment of the present application;
in one embodiment of the present application, a display panel includes a display area AA and a non-display area NA surrounding the display area; the display area AA includes pixel rows 2 arranged in a column direction; each pixel row 2 includes a plurality of sub-pixels 20 and first and second scan lines SCANA and SCANB connected to the sub-pixels; the first scan line SCANA is used for providing a first scan signal SA, and the second scan line SCANB is used for providing a second scan signal SB; the first scan signal SA and the second scan signal SB are used for driving the sub-pixels, respectively. The active pulse of the first scan signal SA precedes the active pulse of the second scan signal SB. The active pulse here is a pulse signal of an active level, and is a pulse signal for operating a transistor controlled by the pulse signal. For example, in the PMOS pixel circuits shown in fig. 3 and 4, the active level refers to a low level for the first scan signal SA and the second scan signal SB, and a high level for the emission control signal EMIT.
In the prior art, the first scan signal SA and the second scan signal SB are generated by the same driving circuit, and in the scan mode, the first scan signal SA of the first row, the second scan signal SB of the first row, the first scan signal SA of the second row, and the second scan signal SB of the second row are sequentially generated; then if the reverse scan is to be performed, the timing sequence is changed to the second scan signal SB of the last line, the first scan signal SA of the last line, the second scan signal SB of the second line, the first scan signal SA of the second line, the second scan signal SB of the first line, and the first scan signal SA of the first line; the active pulse of the second scan signal SB precedes the active pulse of the first scan signal SA in the case of the reverse scan. This may cause timing errors of the scan signals, which may cause the pixel circuits driving the sub-pixels to fail to operate normally. Therefore, the driving circuit of the related art cannot simultaneously realize the forward scan mode and the reverse scan mode.
The present application includes a first positive and negative scan driving circuit 31 and a second positive and negative scan driving circuit 32 in the non-display area NA; the first positive and negative scan driving circuit 31 is connected to each first scan line SCANA; the second forward and reverse scan driving circuit 32 is connected to each second scan line SCANB; the first positive and negative scan driving circuit 31 and the second positive and negative scan driving circuit 32 are respectively disposed in the non-display area NA on both sides of the display area AA;
the display panel comprises a forward scanning mode and a reverse scanning mode;
referring to FIG. 5, in the normal scan mode, the first scan line SCANA is usedThe second scan line SCANB is used for providing a second scan signal SB when providing the first scan signal SA; the active pulse of the first scan signal SA precedes the active pulse of the second scan signal SB. In the normal scan mode, the first scan signal SA for the first row is sequentially generated by the first normal-reverse scan driving circuit 311The second positive and negative scanning driving circuit 32 generates the second scanning signal SB of the first row1The first positive and negative scanning driving circuit 31 generates the first scanning signal SA of the second column2The second positive and negative scan driving circuit 32 generates the second scan signal SB for the second column2In turn, the first positive and negative scan driving circuit 31 generates the first scan signal SA for the (n-1) th rown-1The second positive and negative scan driving circuit 32 generates the second scan signal SB of the n-1 th columnn-1The first positive and negative scan driving circuit 31 generates the first scan signal SA for the nth columnnThe second positive and negative scan driving circuit 32 generates the second scan signal SB of the n-th columnn(ii) a It should be noted that, in the above output sequence, the second scan signal of the ith row may at least partially overlap with the active pulse of the first scan signal of the (i + 1) th row. Sequentially generating a first scanning signal SA for a first row, a second row, a third row, an nth-1 row, and an nth row for the first forward and reverse scanning driving circuit 31; the second forward and reverse scan driving circuit 32 sequentially generates the second scan signals SB of the first, second, and third rows. The output timings of the first positive and negative scan driving circuit 31 and the second positive and negative scan driving circuit 32 are normal, and it can be ensured that the effective pulse of the first scan signal SA precedes the effective pulse of the second scan signal SB for the same pixel row.
Referring to fig. 6, in the reverse scan mode, the first scan line SCANA is used for providing the first scan signal SA, and the second scan line SCANB is used for providing the second scan signal SB; the active pulse of the first scan signal SA precedes the active pulse of the second scan signal SB. In the reverse scan mode, the first scan signal SA for the nth row is sequentially generated by the first forward/reverse scan driving circuit 31nThe second positive and negative scan driving circuit 32 generates the second scan signal SB of the n-th columnnThe first positive and negative scanning driving circuit 31 generates the first scanning signal SA of the n-1 th columnn-1The second positive and negative scan driving circuit 32 generates the second scan signal SB of the n-1 th columnn-1The first forward/reverse scan driving circuit 31 generates the first scan signal SA for the 2 nd column2The second forward/reverse scan driving circuit 32 generates the second scan signal SB for the 2 nd column2The first positive and negative scan driving circuit 31 generates the first scan signal SA of the 1 st column1The second positive and negative scan driving circuit 32 generates the second scan signal SB of the 1 st column1(ii) a It should be noted that, in the above output sequence, the second scan signal of the ith row may at least partially overlap with the active pulse of the first scan signal of the (i-1) th row. Sequentially generating a first scanning signal SA for the nth row, the nth-1 row and the nth-2 row for the first forward and reverse scanning driving circuit 31; the second forward and reverse scan driving circuit 32 sequentially generates second scan signals SB for the n-th, n-1-th, and n-2-th rows; the output timings of the first positive and negative scan driving circuit 31 and the second positive and negative scan driving circuit 32 are normal reverse scan output timings, and it can be ensured that the effective pulse of the first scan signal SA precedes the effective pulse of the second scan signal SB for the same pixel row. For example, for the n-1 th row of sub-pixels, the first positive and negative scan driving circuit 31 outputs the first scan signal SA, and then the second positive and negative scan driving circuit 32 outputs the second scan signal SB. The problem of wrong sequence of effective pulses of the second scanning signal SB and the first scanning signal SA during reverse scanning caused by the fact that the same scanning driving circuit simultaneously outputs the first scanning signal SA and the second scanning signal SB in the prior art can be avoided. Therefore, in the present application, the first positive and negative scan driving circuit 31 and the second positive and negative scan driving circuit 32 are used to output the first scan signal SA and the second scan signal SB respectively, so that in the positive scan mode and the negative scan mode, the first scan signal SA and the effective pulse are located before the effective pulse of the second scan signal SB, thereby avoiding the display abnormality caused by the timing reversal. And the time sequence consistency can be kept in the forward scanning and the reverse scanning, the same data signals in the forward scanning and the reverse scanning correspond to the same brightness, two sets of gammas are avoided in the forward scanning and the reverse scanning, the consistency of display can be improved, and the production efficiency can be improved.
Specifically, referring to fig. 3 and 4, the sub-pixel 20 includes a pixel circuit including a driving transistor DT, a data writing transistor T6 and an organic light emitting device OLED connected in series, and a gate initializing transistor T1 connected to the gate of the driving transistor DT; the first scan signal SA is used to control the gate initialization transistor T1 to transmit a gate initialization signal to the driving transistor DT; the second scan signal SB is used to control the data signal writing transistor T6 to transmit a data signal to the driving transistor DT. In the pixel circuit of this embodiment, the active pulse of the first scan signal SA is used to turn on the gate initialization transistor T1 to transmit an initialization signal to the gate of the driving transistor DT. The active pulse of the second scan signal SB is used to turn on the data writing transistor T6 to transmit the data signal to the gate electrode of the driving transistor DT through the driving transistor DT. The gate N1 node of the driving transistor stores the data signal of the previous frame. If the data signal of the previous frame is large and the data signal of the current frame is small, the driving transistor cannot be turned on because the gate voltage is larger than the source voltage, and the data signal of the current frame cannot be transmitted to the gate of the driving transistor. Therefore, the driving transistor is initialized before data signal writing, and the driving transistor is ensured to be turned on during data writing. That is, the effective pulse of the first scan signal SA must precede the effective pulse of the second scan signal SB. The display panel of the application utilizes the first positive and negative scanning driving circuit 31 and the second positive and negative scanning driving circuit 32 to output the first scanning signal SA and the second scanning signal SB respectively, so that in the positive scanning mode and the negative scanning mode, the first scanning signal SA and the effective pulse are positioned before the effective pulse of the second scanning signal SB, and the abnormal display caused by time sequence reversal is avoided.
More specifically, the pixel circuit further includes an anode initialization transistor T2 connected to the organic light emitting device OLED; the second scan signal SB is also used to control the anode initialization transistor T2 and transmit an anode initialization signal to the organic light emitting device OLED. The pixel circuit further includes a compensation transistor T5 connected in series between the gate and the drain of the driving transistor DT; the second scan signal SB is also used to control the compensation transistor T5 to transmit the data signal to the gate of the driving transistor DT and to accomplish self-compensation.
The pixel row 2 further includes a light emission control signal line connected to the sub-pixel 20, the light emission control signal line E supplying a light emission control signal EMIT to the sub-pixel; the pixel circuit further includes a light emission control transistor T4 connected in series between the driving transistor DT and the organic light emitting device OLED, and the light emission control signal EMIT is used to control the light emission control transistor to transmit a driving current to the organic light emitting device OLED. And a power writing transistor T3 connected in series between the driving transistor DT and the first power signal terminal PVDD, wherein the light emission control signal EMIT is used to control the power writing transistor T3 to supply a power signal to the driving transistor DT to make the driving transistor DT generate a driving current.
Referring to fig. 2, the display panel may include a substrate 110, and an active layer 120, a gate insulating layer 141, a gate metal layer 131, a first interlayer insulating layer 142, a capacitor metal layer 132, a second interlayer insulating layer 143, a source-drain metal layer 133, a planarization layer 144, a first electrode 151, and a pixel defining layer 145 sequentially disposed on the substrate 110; and the pixel defining layer 145 forms an opening in which the organic light emitting material layer 152 is formed; a second electrode 153 is then formed to cover the organic light emitting material layer 152. Finally, the package cover 160 is used for packaging. The transistor and the capacitor in the present application may be formed of the semiconductor layer, the metal conductive layer, and the insulating layer therebetween.
The working process of the pixel circuit of the present application is explained with reference to fig. 3 and 4:
the display mode includes a first initialization period P1, a data write period P2, and a light emission period P3;
at the first initialization period P1: the first scan signal SA is at an on level, and the second scan signal SB and the emission control signal EMIT are at an off level; it should be noted that the on level here refers to a level at which a transistor which can be controlled by another transistor is in an on state, and for example, in the PMOS type pixel circuit of fig. 3, the on level refers to a low level. In the first initialization period P1, the gate initialization transistor T1 is turned on, and the initialization signal REF is transferred from the initialization signal terminal VREF to the driving transistor DT to be reset; at this time, the other transistors are all in the off state, and the initialization signal REF is stored at the node of the gate N1 of the driving transistor.
During the data writing period T2: the second scan signal SB is on level, the first scan signal SA and the emission control signal EMIT are off level; the DATA writing transistor T6 writes the DATA signal Vdata from the DATA signal terminal DATA to the gate N1 node of the driving transistor DT; at this time, the compensation transistor T5 is also in a turned-on state, the data signal Vdata is transmitted to the gate of the driving transistor DT through the first pole of the data writing transistor T6, the driving transistor DT and the compensation transistor T5, and the voltage REF stored at the node of the driving transistor gate N1 at the previous time is raised until the driving transistor DT is turned off when the voltage at the node of the driving transistor gate N1 is Vdata-Vth, where Vth is the threshold voltage of the driving transistor, and the voltage stored at the node of the driving transistor gate N1 is Vdata-Vth. Due to the process of manufacturing transistors, even if the same process parameters are satisfied during the manufacturing of the transistors, the threshold voltages of the transistors on the display panel are different, and the threshold voltages of the transistors drift with the increase of the service time after the transistors age, which causes the brightness of the same written data signals at different positions of the display panel to be different, and the brightness of the same written data signals displayed with the increase of the service time also to be different, which causes the display to be uneven and the color to drift. Therefore, the present embodiment grasps and stores the threshold voltage of the driving transistor DT to the gate N2 node of the driving transistor in order to eliminate the influence of the threshold voltage on the light emission luminance.
In the light emission period P3: the light control signal EMIT is at an on level, and the first scanning signal SA and the second scanning signal SB are at an off level; the power supply writing transistor T3 and the light emitting control transistor T4 are turned on, and the power supply signal VDD is transmitted from the power supply signal terminal PVDD to the first electrode of the driving transistor DT to cause the driving transistor DT to generate a driving current, and is transmitted to the organic light emitting element OLED. The driving transistor DT generates a driving current Ids ═ k ═ (Vsg-Vth) ^ 2 ═ k ═ (VDD- (Vdata-Vth) ^ 2 ═ k ^ 2 (VDD-Vdata). It can be seen that the light emission current of the present embodiment depends on the written data signal regardless of the threshold voltage of the driving transistor DT through the compensation of the data writing period P2, and thus, the influence of the non-uniformity and the drift of the threshold voltage of the driving transistor DT on the light emission current is eliminated.
According to the above timing sequence, the display panel according to the prior art realizes the reverse scan, which inevitably leads to the effective pulse of the second scan signal SB before the effective pulse of the first scan signal SA. In the case where the Data signal Data of the previous frame is large, there may be a case where the Data signal Data cannot be written. Even if the Data signal can be written, since the initialization signal REF is written after the Data signal Data, the potential of the N1 node at which the drive current is finally generated is always the initialization potential REF, and the display panel cannot normally display at all. The display panel of the application utilizes the first positive and negative scanning driving circuit 31 and the second positive and negative scanning driving circuit 32 to output the first scanning signal SA and the second scanning signal SB respectively, so that in the positive scanning mode and the negative scanning mode, the first scanning signal SA and the effective pulse are positioned in front of the effective pulse of the second scanning signal SB, so that each row of pixel circuits can work according to the above time sequence no matter in the positive scanning mode or the negative scanning mode, and the abnormal display caused by the reverse time sequence is avoided.
As can be seen from the timing sequence of fig. 4, the effective pulse waveforms of the first scanning signal SA and the second scanning signal SB may be identical but different in phase. Therefore, the second scan signal SB of a pixel row where scanning is started first and the first scan signal SA of a pixel row where scanning is started next can be made to be performed simultaneously to reduce the total scanning time. Referring to fig. 5 and 6, in the normal scan mode, the active pulse of the second scan signal SB at the k-th row overlaps the active pulse of the first scan signal SA at the k + 1-th row. Similarly, in the reverse scan mode, the active pulse of the second scan signal SB of the k-th row overlaps with the active pulse of the first scan signal SA of the k-1 th row. Wherein k is an integer of 2 to n-1. It should be noted that although the second scan signal SB of one row from which scanning is first started may overlap the first scan signal pulse of the next row in the present application, it is impossible to multiplex the signal lines, that is, any adjacent first scan signal line SCANA and second scan signal line SCANB are insulatively disposed. For example,when the second scanning signal line of the first row is electrically connected to the first scanning signal line of the second row, there is no problem in the normal scanning mode. However, in the reverse scan mode, since the second scan signal line of the first row and the first scan signal line of the second row are electrically connected, the second scan signal SB of the first row1With the first scanning signal SA of the second line2At the same time, and the first scanning signal SA of the second line in the reverse scanning mode2Is earlier than the first scanning signal SA of the first row1Thus, the second scan signal SB of the first row is caused1First scanning signal SA to precede first line1Therefore, the display panel cannot work normally, and the insulating arrangement of any adjacent first scan signal line SCANA and second scan signal line SCANB in this embodiment can avoid the above technical problems.
In another embodiment of the present application, please refer to fig. 7, fig. 7 is a schematic view of a display panel according to an embodiment of the present application;
the first forward-reverse scan driving circuit 31 and the second forward-reverse scan driving circuit 32 include cascaded n-stage driving circuit units; each stage of driving circuit unit comprises a clock signal end CK, an input end IN and an output end OUT; note that the n-stage driving circuit unit of the present application does not include the dummy driving circuit unit, and does not count because the dummy driving circuit unit does not actually output the first scanning signal or the second scanning signal to the pixel row.
The output end OUT of the ith-stage drive circuit unit is connected with the input end IN of the (i + 1) th-stage drive circuit unit through a positive scanning control transistor 51; the output end OUT of the driving circuit unit of the i +1 th stage is connected with the input end IN of the driving circuit of the i th stage through a reverse scanning control transistor 52; wherein i and n are positive integers, and i is more than or equal to 2 and less than or equal to n-1.
For example: an n-stage driving circuit unit 310 in cascade connection with the first forward and reverse scan driving circuit 31; each stage of the driving circuit unit 310 includes a clock signal terminal CK, an input terminal IN, and an output terminal OUT;
output end OUT of the 1 st stage of the driving circuit unit1And an input terminal IN of a 2 nd stage driving circuit unit2Go through betweenThe scan control transistor 51 is connected; output end OUT of the 2 nd stage of the driving circuit unit2And an input terminal IN of a 3 rd stage driving circuit unit3Connected with each other through a positive scanning control transistor 51, and so on; output terminal OUT of nth stage drive circuit unitnAnd an input terminal IN of the driving circuit of the (n-1) th stagen-1Connected to the output terminal OUT of the driving circuit unit of the (n-1) th stage through the inverse scan control transistor 52n-1And an input terminal IN of the driving circuit of the (n-2) th stagen-2Connected to each other through a reverse scan control transistor 52, and so on. Similarly, the same is true for the second forward/reverse scan driving circuit 32.
IN the forward scanning mode, the forward scanning control transistor is switched on, the reverse scanning control transistor is switched off, and the OUT end of the ith-level driving circuit unit transmits a signal to the IN end of the (i + 1) th-level driving circuit unit to realize forward scanning; IN the reverse scan mode, the reverse scan control transistor is turned on, the forward scan control transistor is turned off, and the OUT terminal of the (i + 1) th stage driving circuit unit transmits a signal to the IN terminal of the (i) th stage driving circuit unit, thereby realizing reverse scan. Therefore, the display panel of the embodiment enables the same driving circuit unit to simultaneously output the same scanning signal in the forward and reverse order by arranging the forward scanning control transistor and the reverse scanning control transistor between the driving circuit units, thereby reducing the number of the driving circuit units and reducing the frame width of the display panel.
Referring to FIG. 7, In the first forward/reverse scan driving circuit 31, the input terminal In of the stage 1 driving circuit unit 3101Connecting a first positive scanning start signal line INSL; input terminal In of nth stage driving circuit unitnConnecting a first back sweep start signal line XINSL; in the second forward/reverse scan driving circuit unit 32, the input terminal In of the driving circuit unit 320 of the 1 st stage1Connecting a second normal scanning start signal line INSR; the input end of the nth stage driving circuit unit is connected with a second inverse scanning starting signal line XINSR; specifically, IN the first positive/negative scan driving circuit 31, the input terminal IN of the 1 st stage driving circuit unit 3101Is connected to the first positive scan start signal line INSL through the positive scan control transistor 51; input terminal IN of nth stage drive circuit unitnAnd the firstThe back-scan start signal lines XINSL are connected through a back-scan control transistor 52; IN the second forward/reverse scan driving circuit 32, the input terminal IN of the stage 1 driving circuit unit 3201And the second positive scan start signal line INSR through a positive scan control transistor 51; input terminal IN of nth stage drive circuit unitnAnd the second reverse scan start signal line XINSR via the reverse scan control transistor 52.
In the first forward-reverse scan driving circuit 31, the gates of the forward scan control transistors 51 are commonly connected to a first forward scan control signal line U2 DL; the gate of the reverse-scan control transistor 52 is commonly connected to the first reverse-scan control signal line D2 UL; in the second forward-reverse scan driving circuit 32, the gates of the forward scan control transistors 51 are commonly connected to a second forward scan control signal line U2 DR; the gate of the reverse-scan control transistor 52 is commonly connected to the second reverse-scan control signal line D2 UR;
in the normal scan mode, the first normal scan control signal line U2DL and the second normal scan control signal line U2DR provide an on level; the first reverse-scan control signal line D2UL and the second reverse-scan control signal line D2UR provide a turn-off level. The first positive scan start signal line INSL provides a first positive scan start signal INSL, and the second positive scan start signal line INSR provides a second positive scan start signal INSR; the 1 st stage of the driving unit receives the first positive scanning start signal and outputs a first stage of the first scanning signal SA1(ii) a The effective pulse of the second positive scan start signal insr does not overlap with the effective pulse of the first positive scan start signal insl, and the effective pulse of the second positive scan start signal insr and the first stage first scan signal SA1At least partially overlapping; referring to fig. 5, in the normal scan mode, the first normal scan control signal line U2DL and the second normal scan control signal line U2DR provide turn-on levels; first, the first positive scan start signal line INSL inputs an effective pulse of a first positive scan start signal inl to the 1 st stage driving circuit unit 310 of the first positive scan driving circuit 31; next, the 1 st stage driving circuit unit 310 of the first positive and negative scan driving circuit 31 outputs the first stage first scan signal SA1(ii) a Meanwhile, the second positive scan start signal line INSR inputs an effective pulse of the second positive scan start signal INSR to the first stage driving circuit unit 320 of the second positive scan driving circuit 32, so as toSo that the active pulse of the second positive-scan start signal insr at least partially overlaps the active pulse of the first positive-scan start signal insl; next, the 1 st stage driving circuit unit 320 of the second forward and reverse scan driving circuit 32 outputs the 1 st stage second scan signal SB to the first pixel row1(ii) a Meanwhile, the 2 nd stage driving circuit unit 320 of the first positive and negative scan driving circuit 31 outputs the 2 nd stage first scan signal SA to the 2 nd pixel row2(ii) a Stage 2 first scanning signal SA2And the 1 st stage second scan signal SB1At least partially overlap; by analogy, the n-1 st stage driving circuit unit 320 of the second positive and negative scan driving circuit 32 outputs the n-1 st stage second scan signal SB to the n-1 th pixel rown-1(ii) a Meanwhile, the nth stage driving circuit unit 320 of the first forward and reverse scanning driving circuit 31 outputs the nth stage first scanning signal SA to the nth pixel rown(ii) a Nth stage first scanning signal SAnAnd the (n-1) th stage second scan signal SBn-1At least partially overlap; then, the nth stage driving circuit unit 320 of the second forward and reverse scan driving circuit 32 outputs the nth stage second scan signal SB to the nth pixel rown；
In the reverse scan mode, the first reverse scan control signal line D2UL and the second reverse scan control signal line D2UR provide an on level; the first positive-scan control signal line U2DL and the second positive-scan control signal line U2DR provide a cutoff level. The first inversion start signal line XINSL provides a first inversion start signal XINSL, and the second inversion start signal line XINSR provides a second inversion start signal XINSR; the nth stage driving circuit unit receives the first inverse scanning start signal and outputs the nth stage first scanning signal SAn(ii) a The effective pulse of the second reverse scan start signal xinsr does not overlap with the effective pulse of the first reverse scan start signal xinsl, and the effective pulse of the second reverse scan start signal xinsr and the nth stage first scan signal SAnAt least partially overlapping. Referring to fig. 6, in the reverse scan mode, the first reverse scan control signal line D2UL and the second reverse scan control signal line D2UR provide turn-on levels; first, the first reverse scan start signal line XINSL inputs an effective pulse of the first forward scan start signal XINSL to the nth stage driver circuit unit 310 of the first forward scan driver circuit 31; next, the nth stage driving circuit of the first forward and reverse scan driving circuit 31The unit 310 outputs the nth stage first scan signal SAn(ii) a Meanwhile, the second inverse scan start signal line XINSR inputs the effective pulse of the second inverse scan start signal XINSR to the nth stage driver circuit unit 320 of the second forward and reverse scan driver circuit 32, so that the effective pulse of the second inverse scan start signal XINSR at least partially overlaps with the effective pulse of the first inverse scan start signal xinsl; then, the nth stage driving circuit unit 320 of the second forward and reverse scan driving circuit 32 outputs the nth stage second scan signal SB to the nth pixel rown(ii) a Meanwhile, the n-1 st stage driving circuit unit 320 of the first positive and negative scan driving circuit 31 outputs the n-1 st stage first scan signal SA to the n-1 th pixel rown-1(ii) a The (n-1) th stage first scan signal SAn-1And the nth stage second scan signal SBnAt least partially overlap; by analogy, the 2 nd stage driving circuit unit 320 of the second positive and negative scan driving circuit 32 outputs the 2 nd stage second scan signal SB to the 2 nd pixel row2(ii) a Meanwhile, the 1 st stage driving circuit unit 320 of the first forward and reverse scanning driving circuit 31 outputs the 1 st stage first scanning signal SA to the 1 st pixel row1(ii) a Level 1 first scanning signal SA1And the 2 nd stage second scan signal SB2At least partially overlap; next, the 1 st stage driving circuit unit 320 of the second forward and reverse scan driving circuit 32 outputs the 1 st stage second scan signal SB to the 1 st pixel row1(ii) a In this embodiment, the first positive and negative scan driving circuit outputs the first scan signal, and the second positive and negative scan driving circuit outputs the second scan signal, so that the first scan signal SA and the effective pulse are located before the effective pulse of the second scan signal SB in both the positive scan mode and the negative scan mode, thereby preventing abnormal display caused by timing reversal. And the working time sequence of the pixel circuit is completely the same in the forward scanning mode and the reverse scanning mode, and the working state is also the same, so that the forward scanning mode and the reverse scanning mode are kept to display the same brightness. Two sets of gammas are arranged in the forward scanning and the backward scanning, so that the consistency of display can be improved, and the production efficiency can be improved. And, the second scanning signal SB of the ith rowiFirst scanning signal SA for the i-1 th line in the normal scanning modei-1At least partially overlapping with the first scanning signal SA of the (i + 1) th line in the reverse scanning modei+1At least partially overlapping, reducing by one frameThe scanning time is beneficial to improving the frame rate of the display panel.
In another embodiment of the present application, please continue to refer to fig. 8, fig. 8 is a schematic view of a display panel according to another embodiment of the present application; the non-display area further comprises a forward-and-reverse scanning light-emitting control circuit 40, wherein the forward-and-reverse scanning light-emitting control circuit 40 and one of the first forward-and-reverse scanning driving circuit 31 and the second forward-and-reverse scanning driving circuit 32 are arranged on the same side of the display area AA; for example, the forward-scan/reverse-scan light-emitting control circuit 40 and the first forward-scan/reverse-scan driving circuit 31 are both located in the non-display area on the left side of the display area AA. Or the forward-scan/reverse-scan light-emitting control circuit 40 and the second forward-scan/reverse-scan driving circuit 32 are both located in the non-display area on the left side of the display area AA.
The forward and reverse scanning light-emitting control circuit 40 includes cascaded control circuit units 400; the output end OUT of the control circuit unit 400 is connected to a group of emission control signal line groups EC, which include m adjacent emission control signal lines E, where m is an integer greater than or equal to 2. In the present application, taking m as 2 as an example, a group of emission control signal line groups EC includes 2 emission control signal lines E. The light emitting control signal EMIT corresponding to the first pixel row1Emission control signal EMIT corresponding to the second line2The corresponding 2 light emission control signal lines E correspond to the first light emission control signal line group EC. Emission control signal EMIT corresponding to the 2 nd pixel row3Emission control signal EMIT corresponding to the 4 th pixel row4The corresponding 2 light-emitting control signal lines E correspond to the first light-emitting control signal line group EC, and so on. In this embodiment, the primary forward-backward scanning light-emitting control circuit 400 controls 2 pixel rows, so that the number of control circuit units is reduced by half, the area occupied by the forward-backward scanning light-emitting control circuit 40 is reduced by half, and a narrow frame is realized.
An n/2-level control circuit unit 400 cascaded by the positive and negative scan control circuit 40; each stage of the control circuit unit 400 includes a clock signal terminal CK, an input terminal IN, and an output terminal OUT;
output end OUT of ith stage control circuit unitiAnd input terminal IN of the (i + 1) th stage control circuit uniti+1Connected through a positive scan control transistor 51; output end OUT of control circuit unit of i +1 th stagei+1And ith stageInput terminal IN of control circuitiConnected to each other through the inverse scan control transistor 52; wherein i and n/2 are positive integers, and i is more than or equal to 2 and less than or equal to n/2-1. Input terminal IN of stage 1 control circuit unit 4001A positive scan start signal line INEL connected to the control circuit through the positive scan control transistor 51; input terminal IN of nth/2 stage control circuit unitn/2The reverse scanning start signal line XINEL is connected with the control circuit through a reverse scanning control transistor 52; it should be noted that, since m is 2, the last stage control circuit unit is an n/2 th stage control circuit unit. Note that the n/2 stage control circuit unit of the present application does not include a dummy control circuit unit, and does not count because the dummy control circuit unit does not actually output a light emission control signal to a pixel row.
In the normal scan mode, the first normal scan control signal line U2DL or the second normal scan control signal line U2DR provides a turn-on level (FIG. 8 illustrates the light-emitting control circuit 40 and the first normal scan driving circuit on the same side, so that the normal scan transistor 51 is controlled by the first normal scan control signal line U2DL), and the first reverse scan control signal line D2UL and the second reverse scan control signal line D2UR provide a turn-off level; firstly, a control circuit forward scanning initial signal line INEL inputs an effective pulse of a control circuit initial signal INEL to a 1 st-stage control circuit unit 400 of a forward and reverse scanning light-emitting control circuit 40; then, the level 1 control circuit unit 400 of the forward-reverse scanning light emission control circuit 40 outputs the level 1 light emission control signal EMIT to the light emission control signal line group EC1And a 2 nd-stage emission control signal EMIT2(ii) a Then used as the input signal IN of the 2 nd stage control circuit unit 400 of the positive and negative scan light emitting control circuit 402So that the level-2 control circuit unit 400 outputs the level-3 emission control signal EMIT to the emission control signal line group EC corresponding thereto3And a 4 th-stage emission control signal EMIT4(ii) a And so on. The active pulse of the control circuit positive scan start signal line INEL starts before or at the same time as the active pulse of the first positive scan start signal line INSL and ends after or at the same time as the second positive scan start signal line INSR. So that the effective pulses of the emission control signal EMIT cover the effective pulses of the first and second scan signals SA and SB, so that the pixel circuit is in a positive scanCan work normally in the mode.
In the reverse scan mode, the first reverse scan control signal line D2UL or the second reverse scan control signal line D2UR provides a turn-on level (FIG. 8 illustrates the light-emitting control circuit 40 and the first forward scan driver circuit on the same side, so the forward scan transistor 51 is controlled by the first reverse scan control signal line D2UL), and the first forward scan control signal line U2DL or the second forward scan control signal line U2DR provides a turn-off level; firstly, the control circuit reverse scan start signal line XINEL inputs the effective pulse of the control circuit start signal XINEL to the n/2 th stage control circuit unit 400 of the forward and reverse scan light emission control circuit 40; then, the n/2 th-stage control circuit unit 400 of the forward-and-reverse-scan light emission control circuit 40 outputs the n-th-stage light emission control signal EMIT to the light emission control signal line group ECnAnd an n-1 st stage emission control signal EMITn-1(ii) a Then used as the input signal IN of the n/2-1 stage control circuit unit 400 of the positive and negative scan light-emitting control circuit 40n/2-1So that the n/2-1 th stage control circuit unit 400 outputs the n-2 th stage emission control signal EMITn-2 to the emission control signal line group EC corresponding thereto3And an n-3 th stage emission control signal EMITn-3(ii) a And so on. The control circuit starts the active pulse of the reverse sweep start signal line XINEL before or at the same time as the active pulse of the first reverse sweep start signal line XINSL and ends the active pulse of the second reverse sweep start signal line XINSR after or at the same time as the active pulse of the first reverse sweep start signal line XINSL. So that the active pulses of the emission control signal EMIT cover the active pulses of the first and second scan signals SA and SB, so that the pixel circuit can normally operate in the normal scan mode. In addition, according to the embodiment, the time sequence order of the pixel circuit and the forward scanning mode and the coverage relation of the effective pulse in the reverse scanning mode are the same, so that the working states of the pixel circuit in the forward scanning mode and the reverse scanning mode are the same, and the consistency of the display effect is favorably improved.
Further, please refer to fig. 9, fig. 9 is a schematic view of a display panel according to another embodiment of the present application; the non-display area further comprises a first forward-and-backward scanning light-emitting control circuit 41 and a second forward-and-backward scanning light-emitting control circuit 42, the first forward-and-backward scanning light-emitting control circuit 41 is arranged on the same side of the first forward-and-backward scanning drive circuit 31, and the second forward-and-backward scanning light-emitting control circuit 42 is arranged on the same side of the display area as the second forward-and-backward scanning drive circuit 32; the first forward-reverse scanning light-emission control circuit 41 includes a cascade of first control circuit units 410; the second forward-reverse scanning light-emitting control circuit 42 includes a cascade of second control circuit units 420; the first control circuit units 410 and the second control circuit units 420 are arranged in a one-to-one correspondence manner, and output ends of the correspondingly arranged first control circuit units 410 and second control circuit units 420 are connected to the same group of light-emitting control signal line groups EC, each light-emitting signal line group EC includes m adjacent light-emitting control signal lines, and m is an integer greater than or equal to 2.
In the normal scan mode, the first normal scan control signal line U2DL and the second normal scan control signal line U2DR provide an on level, and the first reverse scan control signal line D2UL and the second reverse scan control signal line D2UR provide an off level; firstly, a first positive scanning start signal line INEL of the control circuit inputs an effective pulse of a control circuit start signal INEL to a 1 st-stage control circuit unit 410 of a first positive and negative scanning light-emitting control circuit 41; meanwhile, the second positive-scan start signal line INER inputs an active pulse of the control circuit start signal INER to the level 1 control circuit unit 420 of the second positive-scan light emission control circuit 42; next, the 1 st-stage control circuit unit 410 of the first forward-and-reverse-scan light-emission control circuit 41 and the 1 st-stage control circuit unit 420 of the second forward-and-reverse-scan light-emission control circuit 42 simultaneously output the 1 st-stage light-emission control signal EMIT to the light-emission control signal line group EC1And a 2 nd-stage emission control signal EMIT2(ii) a Then as the input signal IN of the 2 nd stage control circuit unit 410 of the first forward and reverse scan light-emitting control circuit 41 and the 2 nd stage control circuit unit 420 of the second forward and reverse scan light-emitting control circuit 42, respectively2So that the 2 nd control circuit unit 410 of the first forward/reverse scan light-emitting control circuit 41 and the 2 nd control circuit unit 420 of the second forward/reverse scan light-emitting control circuit 42 output the 3 rd light-emitting control signal EMIT to the corresponding light-emitting control signal line group EC3And a 4 th-stage emission control signal EMIT4(ii) a And so on. The active pulses of the first control circuit normal scan start signal line INEL and the second control circuit normal scan start signal INER start before or simultaneously with the active pulse of the first normal scan start signal line INSL, and start at the second normal scan start signal line INSR is followed or ended simultaneously. So that the active pulses of the emission control signal EMIT cover the active pulses of the first and second scan signals SA and SB, so that the pixel circuit can normally operate in the normal scan mode. In addition, in the embodiment, the light-emitting control signals are simultaneously output from the non-display areas on the two sides of the display panel, so that the driving capability is enhanced.
In the reverse scan mode, the first reverse scan control signal line D2UL and the second reverse scan control signal line D2UR provide an on level, and the first forward scan control signal line U2DL or the second forward scan control signal line U2DR provide an off level; first, the control circuit first reverse scan start signal line XINEL inputs an effective pulse of a control circuit start signal XINEL to the n/2 th-stage control circuit unit 410 of the first forward reverse scan light emission control circuit 41; at the same time, the second reverse scan start signal line XINER inputs the active pulse of the control circuit start signal XINER to the n/2 th-stage control circuit unit 420 of the second forward and reverse scan light emission control circuit 42; then, the nth/2-stage control circuit unit 410 of the first forward-and-reverse-scan light-emission control circuit 41 and the nth/2-stage control circuit unit 420 of the second forward-and-reverse-scan light-emission control circuit 42 simultaneously output the nth-stage light-emission control signal EMITn to the light-emission control signal line group EC1And an n-1 st stage emission control signal EMITn-1(ii) a Then as the input signal IN of the 2 nd stage control circuit unit 410 of the first forward and reverse scan light-emitting control circuit 41 and the 2 nd stage control circuit unit 420 of the second forward and reverse scan light-emitting control circuit 42, respectivelyn/2-1So that the n/2-1 stage control circuit unit 410 of the first forward/reverse scan light emission control circuit 41 and the n/2-1 stage control circuit unit 420 of the second forward/reverse scan light emission control circuit 42 output the n-2 stage light emission control signal EMIT to the corresponding light emission control signal line group ECn-2And an n-3 th stage emission control signal EMITn-3(ii) a And so on. The active pulses of the first control circuit reverse sweep start signal line XINEL and the second control circuit reverse sweep start signal XINER start before or at the same time as the active pulses of the first reverse sweep start signal line XINSL, and end after or at the same time as the second reverse sweep start signal line XINSR. So that the effective pulses of the emission control signal EMIT cover the effective pulses of the first and second scan signals SA and SB to enable the pixel circuit to operate in the reverse scan modeCan work normally. In addition, according to the embodiment, the time sequence order of the pixel circuit and the forward scanning mode and the coverage relation of the effective pulse in the reverse scanning mode are the same, so that the working states of the pixel circuit in the forward scanning mode and the reverse scanning mode are the same, and the consistency of the display effect is favorably improved.
In another embodiment of the present application, fig. 10 is a schematic view of a display panel according to another embodiment of the present application; the non-display area further comprises a third forward-and-backward scanning light-emitting control circuit 43 and a fourth forward-and-backward scanning light-emitting control circuit 44, the third forward-and-backward scanning light-emitting control circuit 43 is arranged on the same side of the first forward-and-backward scanning drive circuit 31, and the fourth forward-and-backward scanning light-emitting control circuit 44 and the second forward-and-backward scanning drive circuit 32 are arranged on the same side of the display area; the third forward-backward scanning light-emitting control circuit 43 may also be disposed on the same side as the second forward-backward scanning driving circuit 32, which is not limited in this application.
The third forward-reverse scanning light-emission control circuit 43 includes a cascade of third light-emission control circuit units 430; the fourth forward-reverse scanning light-emission control circuit 44 includes a cascade of fourth light-emission control circuit units 440; the third control circuit unit 430 is disposed to be staggered with the fourth control circuit unit 440, and the output terminal of the third control circuit unit 430 is connected to the first light-emitting signal line group EC1, and the output terminal of the fourth control circuit unit 440 is connected to the second light-emitting signal line group EC 2; the first light-emitting signal line group EC1 and the second light-emitting signal line group EC2 are alternately arranged in the column direction, and the first light-emitting signal line group EC1 and the second light-emitting signal line group EC2 each include m light-emitting control signal lines, m being an integer equal to or greater than 2.
In the present embodiment, the third forward-scan and reverse-scan light-emitting control circuit 43 and the fourth forward-scan and reverse-scan light-emitting control circuit 44 are arranged to control the first light-emitting signal line group EC1 and the second light-emitting signal line group EC2, respectively, so as to reduce the area occupied by the light-emitting control circuit unit and realize a narrow frame.
In addition, in the present embodiment, the output terminal of the i-th stage third control circuit unit 430 is electrically connected to the first emission control signal line group EC1, and is transmitted to the input terminal of the i + 1-th stage fourth control circuit unit 440 through the first positive scan control transistor 61; the output terminal of the (i + 1) th stage fourth control circuit unit 440 is electrically connected to the second emission control signal line group EC2 and is transmitted to the input terminal of the (i + 2) th stage third control circuit unit 430 through the second positive scan control transistor 62. The output terminal of the ith-stage fourth control circuit unit 440 is electrically connected to the second emission control signal line group EC2 and is transmitted to the input terminal of the i-1 th-stage third control circuit unit 430 through the first anti-scan control transistor 63. The output terminal of the i-1 th-stage third control circuit unit 430 is electrically connected to the first emission control signal line group EC1, and is transmitted to the input terminal of the i-2 th-stage fourth control circuit unit 440 through the second anti-scan control transistor 64; it should be noted that the ith stage of the fourth control circuit unit 440 means that the control circuit units are in the ith stage in the total order of the third control circuit unit 430 and the fourth control circuit unit 440. The connection mode of the embodiment can simultaneously realize the forward scanning and the reverse scanning of the light-emitting control circuit, reduce the number of the initial signal ends and avoid the disorder of time sequence.
In the normal scan mode, the first normal scan control signal line U2DL and the second normal scan control signal line U2DR provide turn-on levels; the first and second positive- scan control transistors 61 and 62 are turned on; the first reverse-scan control signal line D2UL and the second forward-scan control signal line D2UR provide a turn-off level; the first reverse-scan control transistor 63 and the second reverse-scan control transistor 64 are turned on. Firstly, the control circuit positive scanning start signal line INEL inputs the effective pulse of the control circuit start signal INEL to the 1 st stage control circuit unit 430 of the third positive scanning light-emitting control circuit 43; next, the 1 st-stage control circuit unit 430 of the third forward-reverse scanning light emission control circuit 43 outputs the 1 st-stage light emission control signal EMIT to the corresponding first light emission control signal line group EC11And a 2 nd-stage emission control signal EMIT2(ii) a The first emission control signal line group EC1 then transmits an emission control signal to the input signal terminal IN of the level 2 fourth control circuit unit 4402So that the level-2 control circuit unit 440 of the fourth forward-reverse scanning light-emitting control circuit 44 outputs the level-3 light-emitting control signal EMIT to the corresponding second light-emitting control signal line group EC23And a 4 th-stage emission control signal EMIT4(ii) a And so on. It should be noted that the fourth control circuit unit 440 of the 2 nd stage is the third control circuit unit of the control circuit unitThe overall order in the way unit 430 and the fourth control circuit unit 440 is 2 nd. The active pulse of the control circuit positive scan start signal line INEL starts before or at the same time as the active pulse of the first positive scan start signal line INSL and ends after or at the same time as the second positive scan start signal line INSR. So that the active pulses of the emission control signal EMIT cover the active pulses of the first and second scan signals SA and SB, so that the pixel circuit can normally operate in the normal scan mode. In addition, in the embodiment, the light-emitting control signals are simultaneously output from the non-display areas on the two sides of the display panel, so that the driving capability is enhanced.
In the reverse scan mode, the first reverse scan control signal line D2UL and the second reverse scan control signal line D2UR provide an on level; the first reverse-scan control transistor 63 and the second reverse-scan control transistor 64 are turned on; the first forward scan control signal line U2DL and the second reverse scan control signal line U2DR provide a cutoff level; the first and second positive- scan control transistors 61 and 62 are turned on. First, the control circuit reverse scan start signal line XINEL inputs an active pulse of the control circuit start signal XINEL to the n/2-th stage control circuit unit 440 of the fourth forward-reverse scan light emission control circuit 44; then, the nth/2-stage control circuit unit 440 of the fourth forward-reverse scanning light emission control circuit 44 outputs the nth-stage light emission control signal EMIT to the corresponding second light emission control signal line group EC2nAnd an n-1 st stage emission control signal EMITn-1(ii) a The second emission control signal line group EC2 then transmits the emission control signal to the input signal terminal IN of the n/2-1 th stage third control circuit unit 430n/2-1So that the n/2-1 th stage control circuit unit 430 of the third forward/reverse scan light emission control circuit 43 outputs the n-2 nd stage light emission control signal EMIT to the corresponding first light emission control signal line group EC1n-2And an n-3 th stage emission control signal EMITn-3(ii) a And so on. The control circuit starts the active pulse of the reverse sweep start signal line XINEL before or at the same time as the active pulse of the first reverse sweep start signal line XINSL and ends the active pulse of the second reverse sweep start signal line XINSR after or at the same time as the active pulse of the first reverse sweep start signal line XINSL. So that the active pulses of the emission control signal EMIT cover the active pulses of the first and second scan signals SA and SB, so that the pixel circuit can normally operate in the normal scan mode. And, according to the present embodimentThe embodiment can ensure that the time sequence of the pixel circuit and the forward scanning mode under the reverse scanning mode and the coverage relation of the effective pulse are the same, so that the working states of the pixel circuit in the forward scanning mode and the reverse scanning mode are the same, and the consistency of the display effect is favorably improved. And the control circuit units are respectively arranged at two sides of the display area, and cascade connection and gradual signal transmission are realized through the light-emitting control signal line group EC. Meanwhile, the first forward scanning control transistor 61, the second forward scanning control transistor 62, the first reverse scanning control transistor 63 and the second reverse scanning control transistor 64 are arranged to realize forward scanning and reverse scanning, and simultaneously realize narrow frame and forward and reverse scanning.
Referring to fig. 11, fig. 11 is a schematic view of a display device according to an embodiment of the present application. The application also discloses a display device. The display device of the present application may include the display panel as described above. Including but not limited to cellular phone 1000, tablet computers, displays for applications on smart wearable devices, display devices for applications on vehicles such as automobiles, and the like. The display device is considered to fall within the scope of protection of the present application as long as the display device includes the display panel included in the display device disclosed in the present application.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A display panel, comprising: a display area and a non-display area surrounding the display area;
the display area comprises pixel rows arranged along a column direction; each pixel row comprises a plurality of sub-pixels, and a first scanning line and a second scanning line which are connected with the sub-pixels;
the non-display area comprises a first positive and negative scanning driving circuit and a second positive and negative scanning driving circuit; the first positive and negative scanning driving circuit is connected with each first scanning line; the second positive and negative scanning driving circuit is connected with each second scanning line; the first positive and negative scanning driving circuit and the second positive and negative scanning driving circuit are respectively arranged in the non-display areas at two sides of the display area; the sub-pixel comprises a pixel circuit, wherein the pixel circuit comprises a driving transistor, a data writing transistor and an organic light-emitting device which are connected in series, a grid electrode initialization transistor connected with a grid electrode of the driving transistor, and an anode electrode initialization transistor connected with the organic light-emitting device;
the display panel comprises a forward scanning mode and a reverse scanning mode;
in the forward scanning mode and the reverse scanning mode, the first scanning line is used for providing a first scanning signal, and the second scanning line is used for providing a second scanning signal; the effective pulse of the first scanning signal is positioned before the effective pulse of the second scanning signal; the first scanning signal is used for controlling the grid initialization transistor to transmit a grid initialization signal to the driving transistor; the second scanning signal is used for controlling the data writing transistor to transmit a data signal to the driving transistor; the second scanning signal is also used for controlling the anode initialization transistor and transmitting an anode initialization signal to the organic light-emitting device;
the first positive and negative scanning driving circuit and the second positive and negative scanning driving circuit comprise cascaded n-stage driving circuit units; each stage of the driving circuit unit comprises a clock signal end, an input end and an output end;
in the first positive and negative scanning drive circuit, the input end of the 1 st stage of the drive circuit unit is connected with a first positive scanning starting signal line; the input end of the nth stage of the driving circuit unit is connected with a first inverse scanning starting signal line;
in the second positive and negative scanning drive circuit, the input end of the 1 st stage of the drive circuit unit is connected with a second positive scanning starting signal line; the input end of the nth stage of the driving circuit unit is connected with a second inverse scanning starting signal line;
in the normal scan mode, the first normal scan start signal line provides a first normal scan start signal, and the second normal scan start signal line provides a second normal scan start signal; the 1 st stage of the driving circuit unit receives the first positive scanning starting signal and outputs a first stage of a first scanning signal; the effective pulse of the second positive scanning start signal is not overlapped with the effective pulse of the first positive scanning start signal, and the effective pulse of the second positive scanning start signal is at least partially overlapped with the effective pulse of the first stage first scanning signal;
in the reverse scan mode, the first reverse scan start signal line provides a first reverse scan start signal, and the second reverse scan start signal line provides a second reverse scan start signal; the nth stage of the driving circuit unit receives the first inverse scanning starting signal and outputs an nth stage of the first scanning signal; the active pulse of the second reverse scan start signal does not overlap with the active pulse of the first reverse scan start signal, and the active pulse of the second reverse scan start signal and the active pulse of the nth stage first scan signal at least partially overlap.
2. The display panel according to claim 1,
the pixel circuit further comprises a compensation transistor connected between the grid electrode and the drain electrode of the driving transistor in series; the second scanning signal is also used for controlling the compensation transistor to transmit the data signal to the grid electrode of the driving transistor and completing self-compensation.
3. The display panel according to claim 1,
the output end of the ith-stage driving circuit unit is connected with the input end of the (i + 1) th-stage driving circuit unit through a positive scanning control transistor; the output end of the driving circuit unit of the (i + 1) th stage is connected with the input end of the driving circuit of the (i) th stage through a reverse scanning control transistor; wherein i and n are positive integers, and i is more than or equal to 2 and less than or equal to n-1.
4. The display panel according to claim 3,
in the first positive and negative scanning drive circuit, the input end of the 1 st stage of the drive circuit unit is connected with the first positive scanning starting signal line through the positive scanning control transistor; the input end of the driving circuit unit of the nth stage is connected with the first reverse scanning starting signal line through the reverse scanning control transistor;
in the second positive and negative scanning drive circuit, the input end of the 1 st stage of the drive circuit unit is connected with the second positive scanning starting signal line through the positive scanning control transistor; the input end of the driving circuit unit of the nth stage is connected with the second reverse scanning starting signal line through the reverse scanning control transistor.
5. The display panel according to claim 4,
in the first forward and reverse scan driving circuit, the gates of the forward scan control transistors are commonly connected to a first forward scan control signal line; the grid electrodes of the reverse scanning control transistors are connected with a first reverse scanning control signal line in common;
in the second forward-reverse scanning driving circuit, the grids of the forward scanning control transistors are commonly connected with a second forward scanning control signal line; the grid electrodes of the reverse scanning control transistors are connected with a second reverse scanning control signal line in common;
in the normal scan mode, the first and second normal scan control signal lines provide a turn-on level; the first reverse scan control signal line and the second reverse scan control signal line provide a cutoff level;
in the reverse scan mode, the first reverse scan control signal line and the second reverse scan control signal line provide a turn-on level; the first and second positive-scan control signal lines provide a cut-off level.
6. The display panel according to claim 1,
the pixel row further comprises a light-emitting control signal line connected with the sub-pixels, and the light-emitting control signal line provides light-emitting control signals for the sub-pixels;
the pixel circuit further comprises a light-emitting control transistor connected in series between the driving transistor and the organic light-emitting device, and the light-emitting control signal is used for controlling the light-emitting control transistor to transmit driving current to the organic light-emitting device.
7. The display panel according to claim 6,
the non-display area further comprises a forward and backward scanning light-emitting control circuit, and the forward and backward scanning light-emitting control circuit and one of the first forward and backward scanning drive circuit and the second forward and backward scanning drive circuit are arranged on the same side of the display area;
the positive and negative scanning light-emitting control circuit comprises cascaded control circuit units; the output end of the first-stage control circuit unit is connected with a group of light-emitting control signal line groups, each light-emitting control signal line group comprises m adjacent light-emitting control signal lines, and m is an integer greater than or equal to 2.
8. The display panel according to claim 6,
the non-display area further comprises a first forward and reverse scanning light-emitting control circuit and a second forward and reverse scanning light-emitting control circuit, the first forward and reverse scanning light-emitting control circuit and the first forward and reverse scanning drive circuit are arranged on the same side, and the second forward and reverse scanning light-emitting control circuit and the second forward and reverse scanning drive circuit are arranged on the same side of the display area;
the first positive and negative scanning light-emitting control circuit comprises cascaded first control circuit units; the second positive and negative scanning light-emitting control circuit comprises a cascaded second control circuit unit; the first control circuit units and the second control circuit units are arranged in a one-to-one correspondence manner, output ends of the correspondingly arranged first control circuit units and output ends of the correspondingly arranged second control circuit units are connected with the same group of light-emitting control signal line groups, each light-emitting control signal line group comprises m adjacent light-emitting control signal lines, and m is an integer greater than or equal to 2.
9. The display panel according to claim 6,
the non-display area further comprises a third forward-backward scanning light-emitting control circuit and a fourth forward-backward scanning light-emitting control circuit, the third forward-backward scanning light-emitting control circuit and the first forward-backward scanning drive circuit are arranged on the same side, and the fourth forward-backward scanning light-emitting control circuit and the second forward-backward scanning drive circuit are arranged on the same side of the display area;
the third positive and negative scanning light-emitting control circuit comprises a cascaded third control circuit unit; the fourth positive and negative scanning light-emitting control circuit comprises a cascaded fourth control circuit unit; the third control circuit unit and the fourth control circuit unit are arranged in a staggered mode, the output end of the third control circuit unit is connected with the first light-emitting signal line group, and the output end of the fourth control circuit unit is connected with the second light-emitting signal line group; the first light-emitting signal line group and the second light-emitting signal line group are alternately arranged along the column direction, and both the first light-emitting signal line group and the second light-emitting signal line group comprise m light-emitting control signal lines, wherein m is an integer greater than or equal to 2.
10. A display device comprising the display panel according to any one of claims 1 to 9.
CN201910705453.7A 2019-07-31 2019-07-31 Display panel and display device Active CN110400541B (en)

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