CN111179849B - Control unit, control circuit, display device and control method thereof - Google Patents
Control unit, control circuit, display device and control method thereof Download PDFInfo
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- CN111179849B CN111179849B CN202010011352.2A CN202010011352A CN111179849B CN 111179849 B CN111179849 B CN 111179849B CN 202010011352 A CN202010011352 A CN 202010011352A CN 111179849 B CN111179849 B CN 111179849B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application provides a control unit, a control circuit, a display device and a control method thereof, relates to the technical field of display, and can improve the display effect of the display device under different refresh frequencies. Wherein the control unit includes: a pixel control circuit configured to transmit a first input signal provided from the first input signal terminal to the first output signal terminal, and transmit a second input signal provided from the second input signal terminal to the second output signal terminal; and transmitting the third input signal provided by the third input signal terminal to the first output signal terminal and the second output signal terminal. A pixel circuit configured to transmit a data signal provided from the data signal terminal to a first node; the first initial voltage provided by the first initial voltage signal terminal is transmitted to the first node. The first output signal end of the pixel control circuit is electrically connected with the first reset signal end of the pixel circuit, and the second output signal end of the pixel control circuit is electrically connected with the scanning signal end of the pixel circuit.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a control unit, a control circuit, a display device, and a control method thereof.
Background
Compared with a liquid crystal display device, an Organic Light-Emitting diode (OLED) display device has the advantages of high contrast, high response, low energy consumption, flexibility, self-luminescence, wide viewing angle, high response speed and the like.
An AMOLED (Active-matrix organic light emitting diode) display device has a wider viewing angle, a higher refresh rate and a thinner size, and thus has become a research focus in the field of display technology.
Disclosure of Invention
Embodiments of the present invention provide a control unit, a control circuit, a display device and a control method thereof, which can improve display effects of the display device at different refresh frequencies.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in one aspect, a control unit is provided, comprising:
the pixel control circuit is electrically connected with a first input signal end, a second input signal end, a third input signal end, a first voltage signal end, a second voltage signal end, a first output signal end and a second output signal end; the pixel control circuit is configured to transmit a first input signal provided by the first input signal terminal to the first output signal terminal and transmit a second input signal provided by the second input signal terminal to the second output signal terminal under the control of the first voltage signal terminal; and transmitting a third input signal provided by the third input signal terminal to the first output signal terminal and the second output signal terminal under the control of the second voltage signal terminal.
A pixel circuit electrically connected to a first reset signal terminal, a scan signal terminal, a data signal terminal, and a first initial voltage signal terminal, the pixel circuit having a first node; the pixel circuit is configured to transmit a data signal provided by the data signal terminal to a first node under the control of the scan signal terminal; and transmitting a first initial voltage provided by the first initial voltage signal terminal to the first node under the control of the first reset signal terminal.
The first output signal end of the pixel control circuit is electrically connected with the first reset signal end of the pixel circuit, and the second output signal end of the pixel control circuit is electrically connected with the scanning signal end of the pixel circuit.
Optionally, the control unit further includes a shift register, and the shift register is electrically connected to the input signal terminal and the output signal terminal; the input signal end of the shift register is electrically connected with the first input signal end of the pixel control circuit, and the output signal end of the shift register is electrically connected with the second input signal end of the pixel control circuit.
Optionally, the shift register is further electrically connected to a clock signal terminal, a third voltage signal terminal, and a fourth voltage signal terminal; the shift register is configured to transmit a clock signal provided by the clock signal terminal and a fourth voltage signal provided by the fourth voltage signal terminal to the output signal terminal under the control of the input signal terminal and the third voltage signal terminal.
The fourth voltage signal terminal is electrically connected to the third input signal terminal of the pixel control circuit.
Optionally, the pixel control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the grid electrode of the first transistor is electrically connected with a first voltage signal end, the first electrode of the first transistor is electrically connected with the first input signal end, and the second electrode of the first transistor is electrically connected with the first output signal end; a grid electrode of the second transistor is electrically connected with a first voltage signal end, a first electrode of the second transistor is electrically connected with the second input signal end, and a second electrode of the second transistor is electrically connected with the second output signal end; a gate of the third transistor is connected to a second voltage signal terminal, a first electrode of the third transistor is electrically connected to the third input signal terminal, and a second electrode of the third transistor is electrically connected to the first output signal terminal; the gate of the fourth transistor is electrically connected to the second voltage signal terminal, the first electrode of the fourth transistor is electrically connected to the third input signal terminal, and the second electrode of the fourth transistor is electrically connected to the second output signal terminal.
Optionally, the pixel circuit includes:
the data writing module is electrically connected with the scanning signal end, the data signal end and the first node; the data writing module is configured to write the data signal provided by the data signal terminal into the first node under the control of the scan signal terminal.
The driving module is electrically connected with a power supply voltage signal end and the first node, and is configured to output a driving signal under the control of the first node and the power supply voltage signal end, wherein the driving signal is used for driving an element to be driven to emit light.
The control module is electrically connected with the power supply voltage signal end, the enabling signal end, the driving module and the element to be driven, and the control module is configured to enable the driving module to be electrically connected with the element to be driven under the control of the enabling signal end so as to drive the element to be driven to emit light.
The reset module is electrically connected with the first node, the first reset signal terminal, the second reset signal terminal, the first initial voltage signal terminal, the second initial voltage signal terminal and the element to be driven, and is configured to transmit a first initial voltage provided by the first initial voltage signal terminal to the first node under the control of the first reset signal terminal and transmit a second initial voltage provided by the second initial voltage signal terminal to the element to be driven under the control of the second reset signal terminal.
In another aspect, a control circuit is provided, which includes a plurality of control units, wherein the control units are the control units described above.
The first voltage signal ends of all the control units are electrically connected, and the second voltage signal ends of all the control units are electrically connected.
Optionally, under the condition that the control unit includes a shift register, an input signal end of a first-stage shift register in the plurality of shift registers is electrically connected to the start signal, an output signal end of an N-1 th-stage shift register and an output signal end of an nth-stage shift register are respectively connected to second input signal ends of the pixel control circuits corresponding to the N-1 th-stage shift register and the nth-stage shift register, where the nth stage is a last-stage shift register, and N is a positive integer.
Except for the first stage shift register, the N-1 stage shift register and the N stage shift register, the output signal end of the M stage shift register is electrically connected with the input signal end of the M +2 stage shift register and the second input signal end of the pixel control circuit corresponding to the M stage shift register, wherein M is more than 1 and less than N-1.
In another aspect, a display device is provided, which includes a display panel including a control circuit, the control circuit being the control circuit described above.
In still another aspect, there is provided a control method of the display apparatus described above, including:
under the control of a first voltage signal end, a pixel control circuit in the control circuit transmits a first input signal provided by the first input signal end to a first output signal end and transmits a second input signal provided by the second input signal end to a second output signal end under the control of a first voltage signal end.
Under the control of a second voltage signal end, the pixel control circuit transmits a third input signal provided by the third input signal end to the first output signal end and the second output signal end at the same time.
Wherein the first refresh frequency is greater than the second refresh frequency.
Optionally, the pixel control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor.
At the first refresh frequency: the first transistor and the second transistor are turned on, and the third transistor and the fourth transistor are turned off; the first transistor transmits a first input signal provided by the first input signal terminal to a first output signal terminal, and the second transistor transmits a second input signal provided by the second input signal terminal to the second output signal terminal.
At the second refresh frequency: the third transistor and the fourth transistor are turned on, and the first transistor and the second transistor are turned off; the third transistor transmits a third input signal provided from a third input signal terminal to the first output signal terminal, and the fourth transistor transmits a third input signal provided from a third input signal terminal to the second output signal terminal.
Embodiments in the present application provide a control unit, a control circuit, a display device and a control method thereof. The control unit comprises a pixel control circuit and a pixel circuit, the pixel control circuit is used for providing a first reset signal and a scanning signal for a first reset signal end and a scanning signal end in the pixel circuit, and the pixel control circuit can provide different first reset signals and scanning signals for the first reset signal end and the scanning signal end under the control of a first voltage signal end and a second voltage signal end, so that when the display device works under different refreshing frequencies, the signals received by the first reset signal end and the scanning signal end are different, namely, the control unit can provide larger first reset signals and scanning signals for the first reset signal end and the scanning signal end under lower refreshing frequency, so as to reduce the leakage current of the pixel circuit, and further, when the display device works under different refreshing frequencies, the actual display brightness is the same or more similar when the same gray scale is input, so as to improve the display effect of the display device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2a to fig. 2e are schematic structural diagrams of a pixel circuit according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of a pixel control circuit according to an embodiment of the present invention;
fig. 4 a-4 b are schematic structural diagrams of a control unit according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating actual display brightness of elements to be driven at different refresh frequencies when the same gray scale is input in the related art;
fig. 6 a-6 b are schematic structural diagrams of another control unit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another control unit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;
fig. 9 is a flowchart illustrating a control method of a display device according to an embodiment of the invention;
FIG. 10a is a schematic diagram of waveforms of a first voltage signal and a second voltage signal at different refresh frequencies according to an embodiment of the present invention;
FIG. 10b is a schematic diagram of actual display brightness of the to-be-driven device at different refresh frequencies when the same gray scale is inputted according to the embodiment of the present invention.
Reference numerals:
1-a control circuit; 10-a control unit; 100-pixel control circuitry; 101-a pixel circuit; 1010 — a data write module; 1011-a driver module; 1012-a control module; 1013-a reset module; 102-a shift register; 2-a display panel; d-an element to be driven; n1-first node; Input-Input signal terminal; input 1-first Input signal terminal; input 2-second Input signal terminal; input 3-a third Input signal terminal; out-output signal terminal; out 1-first output signal terminal; out 2-second output signal terminal; CLK-clock signal terminal; v1 — first voltage signal terminal; v2-second voltage signal terminal; v3-third Voltage Signal terminal; v4-fourth voltage signal terminal; rst 1-first reset signal terminal; rst 2-second reset signal terminal; gate-scan signal terminal; Data-Data signal terminal; vinit 1-first initial voltage signal terminal; vinit 2-second initial voltage signal terminal; an EM-enable signal terminal; VDD-supply voltage signal terminal.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides an OLED display device which comprises a display panel 2.
As shown in fig. 1, the display panel 2 includes a plurality of sub-pixels P uniformly distributed in a matrix, and a pixel circuit 101 and an element D to be driven connected to the pixel circuit 101 are provided in each sub-pixel P. The element D to be driven is a current-driven Light Emitting device D, and further, the Light Emitting device may be a current-type Light Emitting diode, such as a micro Light Emitting diode, a mini Light Emitting diode, an organic Light Emitting diode, or a Quantum Dot Light Emitting diode (QLED).
As shown in fig. 2a, the pixel circuit 101 is electrically connected to the first reset signal terminal Rst1, the scan signal terminal Gate, the Data signal terminal Data, and the first initial voltage signal terminal Vinit1, and the pixel circuit 101 has a first node N1. The first reset signal terminal Rst1 is configured to receive a first reset signal and transmit the first reset signal to the pixel circuit 101; the scan signal terminal Gate is configured to receive a scan signal and transmit the scan signal to the pixel circuit 101; the Data signal terminal Data is used to receive a Data signal and transmit the Data signal to the pixel circuit 101.
The pixel circuit 101 is configured to transmit a Data signal provided by the Data signal terminal Data to the first node N1 under the control of the scan signal terminal Gate, and write the Data signal into the first node N1; and transmitting the first initial voltage provided by the first initial voltage signal terminal Vinit1 to the first node N1 under the control of the first reset signal terminal Rst1 to reset the first node N1.
As shown in fig. 2b, the pixel circuit 101 includes: the Data writing module 1010 is electrically connected to the scan signal terminal Gate, the Data signal terminal Data, and the first node N1. The scan signal terminal Gate is configured to receive a scan signal and transmit the scan signal to the data writing module 1010; the Data signal terminal Data is used for receiving a Data signal and transmitting the Data signal to the Data writing module 1010.
The Data writing module 1010 is configured to write the Data signal provided by the Data signal terminal Data into the first node N1 under the control of the scan signal terminal Gate.
The driving module 1011, the driving module 1011 is electrically connected to the power voltage signal terminal VDD and the first node N1. The power voltage signal terminal VDD is used for receiving the power voltage signal terminal VDD and transmitting the power voltage signal to the driving module 1011.
The driving module 1011 is configured to output a driving signal under the control of the first node N1 and the power voltage signal terminal VDD, where the driving signal is used to drive the to-be-driven device D to emit light.
And the control module 1012, wherein the control module 1012 is electrically connected with the power supply voltage signal terminal VDD, the enable signal terminal EM, the driving module 1011 and the element D to be driven. The enable signal terminal EM is used for receiving an enable signal and transmitting the enable signal to the control module 1012.
The control module 1012 is used for electrically connecting the driving module 1011 and the device D to be driven under the control of the enable signal terminal EM so as to drive the device D to be driven to emit light.
And the reset module 1013, wherein the reset module 1013 is electrically connected to the first node N1, the first reset signal terminal Rst1, the second reset signal terminal Rst2, the first initial voltage signal terminal Vinit1, the second initial voltage signal terminal Vinit2 and the anode of the element D to be driven. The first reset signal terminal Rst1 is configured to receive a first reset signal and transmit the first reset signal to the reset module 1013; the second reset signal terminal Rst2 is configured to receive a second reset signal and transmit the second reset signal to the reset module 1013; the first initial voltage signal terminal Vinit1 is configured to receive a first initial voltage signal and transmit the first initial voltage signal to the reset module 1013; the second initial voltage signal terminal Vinit2 is used for receiving a second initial voltage signal and transmitting the second initial voltage signal to the reset module 1013.
The reset module 1013 is configured to transmit the first initial voltage signal provided by the first initial voltage signal terminal Vinit1 to the first node N1 under the control of the first reset signal terminal Rst1, so as to reset the first node N1; the second initial voltage signal provided by the second initial voltage signal terminal Vinit2 is transmitted to the anode of the element D to be driven under the control of the second reset signal terminal Rst2, and the anode of the element D to be driven is reset.
Alternatively, as shown in fig. 2c, the reset module 1013 is electrically connected to the first node N1, the first reset signal terminal Rst1, the first initial voltage signal terminal Vinit1, and the anode of the element D to be driven. The reset module 1013 is configured to transmit the first initial voltage signal provided by the first initial voltage signal terminal Vinit1 to the first node N1 and the anode of the element D to be driven under the control of the first reset signal terminal Rst1, and reset the first node N1 and the anode of the element D to be driven.
For example, the first initial voltage signal provided by the first initial voltage signal terminal Vinit1 is at a negative low level, the second initial voltage signal provided by the second initial voltage signal terminal Vinit2 is at a negative low level, and the power supply voltage signal provided by the power supply voltage signal terminal VDD is at a high level.
Alternatively, as shown in fig. 2d and 2e, the pixel circuit 101 is a 7T1C type pixel circuit 101. Illustratively, the pixel circuit 101 includes a driving transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, and a capacitor C.
Alternatively, all the transistors in the pixel circuit 101 are, for example, P-type transistors.
As shown in fig. 2d, the gate of the driving transistor T1 is electrically connected to the first node N1, the first pole of the driving transistor T1 is electrically connected to the second pole of the transistor T2, and the second pole of the driving transistor T1 is electrically connected to the first pole of the transistor T3; the Gate of the transistor T2 is electrically connected to the scan signal terminal Gate, and the first electrode of the transistor T2 is electrically connected to the Data signal terminal Data; a Gate of the transistor T3 is electrically connected to the scan signal terminal Gate, and a second pole of the transistor T3 is electrically connected to the first node N1; a gate of the transistor T4 is electrically connected to the first reset signal terminal Rst1, a first pole of the transistor T4 is electrically connected to the first initial voltage signal terminal Vinit1, and a second pole of the transistor T4 is electrically connected to the first node N1; a gate of the transistor T5 is electrically connected to the second reset signal terminal Rst2, a first pole of the transistor T5 is electrically connected to the second initial voltage signal terminal Vinit2, and a second pole of the transistor T5 is electrically connected to an anode of the element D to be driven; a gate of the transistor T6 is electrically connected to the enable signal terminal EM, a first pole of the transistor T6 is electrically connected to the power supply voltage signal terminal VDD, and a second pole of the transistor T6 is electrically connected to the first pole of the driving transistor T1; the gate of the transistor T7 is electrically connected to the enable signal terminal EM, the first pole of the transistor T7 is electrically connected to the second pole of the driving transistor T1, the second pole of the transistor T7 is electrically connected to the anode of the device D to be driven, and the cathode of the device D to be driven is electrically connected to the ground terminal VSS; the other end of the capacitor C is electrically connected to the power supply voltage signal terminal VDD.
As shown in fig. 2e, the connection relationship of the driving transistor T1, the transistor T2, the transistor T3, the transistor T6, the transistor T7 and the capacitor C is the same as that in fig. 2d, and thus, the description thereof is omitted. A gate of the transistor T4 is electrically connected to the first reset signal terminal Rst1, a first pole of the transistor T4 is electrically connected to the first initial voltage signal terminal Vinit1, and a second pole of the transistor T4 is electrically connected to the first node N1; a gate of the transistor T5 is electrically connected to the first reset signal terminal Rst1, a first pole of the transistor T5 is electrically connected to the first initial voltage signal terminal Vinit1, and a second pole of the transistor T5 is electrically connected to an anode of the element D to be driven.
Referring to fig. 2d, during the reset phase of operation of the pixel circuit 101: the first reset signal terminal Rst1 controls the transistor T4 to be turned on, transmits the first initial voltage signal provided by the first initial voltage signal terminal Vinit1 to the first node N1, and resets the first node N1; the second reset signal terminal Rst2 controls the transistor T5 to be turned on, and transmits the second initial voltage signal provided by the second initial voltage signal terminal Vinit2 to the anode of the element D to be driven, so as to reset the element D to be driven. When the potential of the first node N1 is equal to the potential of the first initial voltage signal (e.g., a negative potential), the driving transistor T1 is in an on state, and the transistors T2, T3, T6, and T7 are in an off state.
In the Data writing stage, the transistor T2 and the transistor T3 are controlled to be turned on by the Gate of the scanning signal end, the Data signal provided by the Data signal end Data is written into the first node N1 through the transistor T2, the driving transistor T1 and the transistor T3, and the capacitor C is charged; the transistor T4, the transistor T5, the transistor T6, and the transistor T7 are in an off state.
In the light emitting stage: under the control of the enable signal end EM, the transistor T6 and the transistor T7 are turned on, the capacitor C discharges to the gate of the driving transistor T1, the driving transistor T1 outputs a driving signal under the control of the gate voltage of the driving transistor T1 and a power supply voltage signal provided by a power supply voltage signal end VDD, and the driving signal is transmitted to the anode of the element D to be driven through the transistor T7 to drive the element D to be driven to emit light; the transistor T2, the transistor T3, the transistor T4, and the transistor T5 are in an off state.
As shown in fig. 1, the display panel 2 further includes a plurality of pixel control circuits 100, the pixel circuits 101 in the same row are electrically connected to the same pixel control circuit 100, and the pixel circuits 101 and the pixel control circuits 100 in the same row form a control unit 10.
As shown in fig. 3, the pixel control circuit 100 is electrically connected to a first Input signal terminal Input1, a second Input signal terminal Input2, a third Input signal terminal Input3, a first voltage signal terminal V1, a second voltage signal terminal V2, a first output signal terminal Out1, and a second output signal terminal Out 2. The first Input signal terminal Input1 is used for receiving a first Input signal and transmitting the first Input signal to the pixel control circuit 100; the second Input signal terminal Input2 is used for receiving a second Input signal and transmitting the second Input signal to the pixel control circuit 100; the third Input signal terminal Input3 is used for receiving a third Input signal and transmitting the third Input signal to the pixel control circuit 100; the first voltage signal terminal V1 is used for receiving a first voltage signal and transmitting the first voltage signal to the pixel control circuit 100; the second voltage signal terminal V2 is used for receiving a second voltage signal and transmitting the second voltage signal to the pixel control circuit 100.
The pixel control circuit 100 is configured to transmit a first Input signal provided by a first Input signal terminal Input1 to a first output signal terminal Out1 and transmit a second Input signal provided by a second Input signal terminal Input2 to a second output signal terminal Out2 under the control of a first voltage signal terminal V1; and transmitting a third Input signal provided by the third Input signal terminal Input3 to the first output signal terminal Out1 and the second output signal terminal Out2 under the control of the second voltage signal terminal V2.
In the following, a connection relationship between one pixel circuit 101 of the plurality of pixel circuits 101 in the control unit 10 and the pixel control circuit 100 is taken as an example to describe a connection relationship between the pixel control circuit 100 and the pixel circuits 101 in the same row, but it should be understood by those skilled in the art that the connection relationship between each pixel circuit 101 in the control unit 10 and the pixel control circuit 100 is the same.
As shown in fig. 4a, the first output signal terminal Out1 of the pixel control circuit 100 is electrically connected to the first reset signal terminal Rst1 of the pixel circuit 101, and the second output signal terminal Out2 of the pixel control circuit 100 is electrically connected to the scan signal terminal Gate of the pixel circuit 101.
Under the control of the first voltage signal terminal V1, the pixel control circuit 100 transmits the first Input signal provided by the first Input signal terminal Input1 to the first reset signal terminal Rst1 in the pixel circuit 101, and transmits the second Input signal provided by the second Input signal terminal Input2 to the scan signal terminal Gate in the pixel circuit 101.
The pixel control circuit 100 transmits the third Input signal provided from the third Input signal terminal Input3 to the first reset signal terminal Rst1 and the scan signal terminal Gate in the pixel circuit 101 under the control of the second voltage signal terminal V2.
On this basis, alternatively, as shown in fig. 4b, in the case where the pixel circuit 101 is also electrically connected to the second reset signal terminal Rst2, the first output signal terminal Out1 of the pixel control circuit 100 is also electrically connected to the second reset signal terminal Rst2 of the pixel circuit 101.
For example, at the first refresh frequency, the first voltage signal terminal V1 controls the pixel control circuit 100 to provide the pixel circuit 101 with the first reset signal and the scan signal. At the second refresh frequency, the second voltage signal terminal V2 controls the pixel control circuit 100 to provide the pixel circuit 101 with the first reset signal and the scan signal, and the first refresh frequency is greater than the second refresh frequency.
And the first refresh frequency and the second refresh frequency are the refresh frequencies of the display device.
Illustratively, the first refresh rate is 120Hz and the second refresh rate is 60 Hz.
The larger the refresh frequency of the display device is, the larger the number of image frames that can be displayed by the display panel 2 in 1S is, and therefore, the higher the refresh frequency can be applied to application scenes requiring better continuity of the picture and clearer picture, such as game scenes. The lower the refresh frequency of the display device, the lower the power consumption of the display device, and therefore, the lower the refresh frequency can be applied to application scenes, such as browsing scenes, with lower requirements on picture continuity and picture definition. The display device has two different refresh frequencies to meet the requirements of the display device in different application scenes.
In a period of each frame image, a display area and a Porch area (blanking area) are included, wherein the Porch area may also be referred to as BlanK area. For example, at the first refresh frequency, the duration of the display area in the period of each frame of image is Active1, the duration of the Porch area is P1, and P1 is a preset value, for example, 16H (H is the scanning time of each line); under the second refreshing frequency, the duration of a display area in the period of each frame of image is Active2, and the duration of a Porch area is P2; the first refresh frequency and the second refresh frequency are switched on the premise that PWM (Pulse Width Modulation) is not changed, so that in 1S, the first refresh frequency is 1/(Active1+ P1), the second refresh frequency is 1/(Active2+ P2), and P2 is Active1+ P1. Since P1 is small, the duration P2 of the second refresh frequency Porch region is approximately equal to Active1, ignoring P1.
When the same gray scale is input to a certain subpixel at the first refresh frequency and the second refresh frequency, when the same gamma (gamma curve) is used, the charging time of the subpixel is the same, that is, the display area duration Active1 of the first refresh frequency is equal to the display area duration Active2 of the second refresh frequency, so that both Active1 and Active2 are hereinafter referred to as Active.
As shown in fig. 5, in the related art, when the display device operates at different refresh frequencies, the durations Active of the display areas are equal, after ignoring the duration of the Porch area at the first refresh frequency, P1, the Porch area exists only at the second refresh frequency, and the duration of the Porch area is P2. That is, at the first refresh frequency, the period of one frame picture is t1, at the second refresh frequency, the period of one frame picture is t2, and t2 is 2t 1.
Referring to fig. 2D, when the driving transistor T1 drives the to-be-driven element D to emit light, although the transistor T3 and the transistor T4 are in an off state, since both transistors have leakage current, the transistor T3 and the transistor T4 cause the potential of the first node N1 to decrease, the longer the driving transistor T1 drives the to-be-driven element D to emit light, the larger the leakage current of the transistor T3 and the transistor T4, the lower the potential of the first node N1, and the lower the potential of the first node N1, which causes the luminance (gray scale determining luminance) of the to-be-driven element D to be higher relative to the luminance that actually needs to be displayed. Since the Porch region exists at the second refresh frequency, the leakage current of the pixel circuit 101 operating at the second refresh frequency is larger than the leakage current of the pixel circuit 101 operating at the first refresh frequency, and finally, when the same gray scale is input, the luminance actually displayed by the element D to be driven at the first refresh frequency is smaller than the luminance actually displayed by the element D to be driven at the second refresh frequency, that is, as shown in fig. 5, the luminance a corresponding to t1 is smaller than the luminance b corresponding to t2, and the difference between the two is c. Therefore, in the related art, since the leakage current of the pixel circuit 101 during operation at the smaller refresh frequency is larger than the leakage current during operation at the higher refresh frequency, when the display device inputs the same gray scale at different refresh frequencies, the actual display luminance at the smaller refresh frequency is larger than the actual display luminance at the higher refresh frequency, and especially when the input gray scale is low, the luminance difference is more obvious and easily recognized by human eyes, so the display effect of the display device in the related art is poor.
It should be noted that, in the pixel circuit 101 shown in fig. 2D, the data signal provided (input) by the data signal terminal determines the gray levels, and different gray levels correspond to different luminances, whereas in the pixel circuit 101 of the present application, the smaller the potential of the first node N1 is, the larger the luminance of the element D to be driven is, and therefore, the larger the leakage current is, the brighter the luminance actually displayed by the driving element D is relative to the luminance it needs to display.
As shown in fig. 2d, the factor affecting the leakage current of the transistor T3 is its Gate signal, i.e. the scan signal provided by the Gate of the scan signal terminal; the factor affecting the magnitude of the leakage current of the transistor T4 is the gate signal thereof, i.e., the first reset signal provided by the first reset signal terminal Rst 1. When the scan signal and the first reset signal are larger, the more thoroughly the transistor T3 and the transistor T4 are turned off, the smaller the respective leakage currents are, and thus the smaller the leakage current of the entire pixel circuit 101 is.
Embodiments in the present application provide a control unit 10, the control unit 10 including a pixel control circuit 100 and a pixel circuit 101, wherein the pixel control circuit 100 is configured to provide a first reset signal and a scan signal to a first reset signal terminal Rst1 and a scan signal terminal Gate in the pixel circuit 101, and the pixel control circuit 100 may provide different first reset signals and scan signals to the first reset signal terminal Rst1 and the scan signal terminal Gate under the control of a first voltage signal terminal V1 and a second voltage signal terminal V2. In the related art, the shift register supplies the first reset signal terminal Rst1 and the scan signal terminal Gate in the pixel circuit 101 with the first reset signal and the scan signal, which do not vary according to the refresh frequency of the display device. In the present application, the pixel control circuit 100 may provide different first reset signals and scan signals to the first reset signal terminal Rst1 and the scan signal terminal Gate under the control of the first voltage signal terminal V1 and the second voltage signal terminal V2, so that when the display device operates at different refresh frequencies, the signals received by the first reset signal terminal Rst1 and the scan signal terminal Gate are different, that is, it may provide larger first reset signals and scan signals to the first reset signal terminal Rst1 and the scan signal terminal Gate at a lower refresh frequency, so as to reduce the leakage current of the pixel circuit 101, so that when the display device operates at different refresh frequencies, the actual display luminance is the same or more similar when the same gray scale is input, thereby improving the display effect of the display device.
Optionally, as shown in fig. 6a, the control unit 10 further includes a shift register 102, and the shift register 102 is electrically connected to the Input signal terminal Input and the output signal terminal Out.
An Input signal terminal Input of the shift register 102 is electrically connected to a first Input signal terminal Input1 of the pixel control circuit 100, and an output signal terminal Out of the shift register 102 is electrically connected to a second Input signal terminal Input2 of the pixel control circuit 100. The Input signal terminal Input is used for receiving an Input signal and inputting the Input signal to the shift register 102.
By supplying the first Input signal and the second Input signal to the first Input signal terminal Input1 and the second Input signal terminal Input2 of the pixel control circuit 100 through the shift register 102, the number of signals in the control unit 10 can be reduced, and the circuit configuration can be simplified.
For example, when the plurality of shift registers 102 are cascaded, the output signal terminal Out of the first stage shift register is electrically connected to the Input signal terminal Input of the second stage shift register, for example, and the Input signal terminal Input of the first stage shift register is electrically connected to a start signal, which is used to start the first stage shift register.
Except for the first stage of shift register, the output signal terminal Out of the other shift register is electrically connected with the Input signal terminal Input of the next stage of shift register.
It should be noted that the cascade connection manner of the shift register 102 is not limited in the present application, and the cascade connection manner is merely an example, and the shift register 102 may also be another cascade connection manner.
On this basis, optionally, as shown in fig. 6b, the shift register 102 is further electrically connected to the clock signal terminal CLK, the third voltage signal terminal V3 and the fourth voltage signal terminal V4. The clock signal terminal CLK is used to receive a clock signal and input the clock signal to the shift register 102; the third voltage signal terminal V3 is used for receiving a third voltage signal and inputting the third voltage signal to the shift register 102; the fourth voltage signal terminal V4 is used for receiving a fourth voltage signal and inputting the fourth voltage signal to the shift register 102.
For example, the clock signal terminal CLK is configured to receive a clock signal, which may be CLK or clb, for example, and the application is not limited herein.
Illustratively, the third voltage signal is a low level signal and the fourth voltage signal is a high level signal.
The shift register 102 is used for transmitting the clock signal provided by the clock signal terminal CLK and the fourth voltage signal provided by the fourth voltage signal terminal V4 to the output signal terminal Out under the control of the Input signal terminal Input and the third voltage signal terminal V3.
The fourth voltage signal terminal V4 is electrically connected to the third Input signal terminal Input3 of the pixel control circuit 100, so that the number of signals in the control unit 10 can be further reduced, and the structure of the control circuit can be simplified.
In the related art, the Input signal terminal Input of the shift register 102 is directly electrically connected to the first reset signal terminal Rst1 of the pixel circuit 101 to provide the first reset signal to the first reset signal terminal Rst1, and the output terminal Out of the shift register 102 is directly electrically connected to the scan signal terminal Gate of the pixel circuit 101 to provide the scan signal to the scan signal terminal Gate. Since the circuit in the shift register 102 is complex and has a large resistance, the output signal output from the output signal terminal Out of the shift register 102 is actually smaller than the fourth voltage signal received by the fourth voltage signal terminal V4, and the output signal is used as the scan signal and the first reset signal (for example, as the first reset signal of the next stage shift register), so the scan signal and the first reset signal are actually smaller than the fourth voltage signal.
In the present application, when the display device operates at a higher refresh frequency, the first reset signal and the scan signal received in the pixel circuit 101 are the same as those in the related art; when the display device operates at a lower refresh frequency, the third Input signal can be directly provided to the third Input signal terminal Input3 of the pixel control circuit 100 through the fourth voltage signal terminal V4 of the shift register 102, and since the resistance of the pixel control circuit 100 is small and can be ignored, the magnitude of the third Input signal is equal to that of the fourth voltage signal, so that the magnitudes of the scan signal and the first reset signal in the pixel circuit 101 can be equal to that of the fourth voltage signal. Therefore, compared with the related art, the magnitude of the scanning signal and the first reset signal when the pixel circuit 101 operates at a lower refresh frequency is increased, so that the leakage current in the pixel circuit 101 can be reduced, and the display effect of the display device is improved. And the third Input signal terminal Input3 is directly electrically connected to the fourth voltage signal terminal V4, so that the number of signals in the control unit 10 can be reduced, and the circuit structure can be simplified.
Alternatively, as shown in fig. 7, the pixel control circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. A gate of the first transistor M1 is electrically connected to the first voltage signal terminal V1, a first pole of the first transistor M1 is electrically connected to the first Input signal terminal Input1, and a second pole of the first transistor M1 is electrically connected to the first output signal terminal Out 1; a gate of the second transistor M2 is electrically connected to the first voltage signal terminal V1, a first pole of the second transistor M2 is electrically connected to the second Input signal terminal Input2, and a second pole of the second transistor M2 is electrically connected to the second output signal terminal Out 2; a gate of the third transistor M3 is connected to the second voltage signal terminal V2, a first pole of the third transistor M3 is electrically connected to the third Input signal terminal Input3, and a second pole of the third transistor M3 is electrically connected to the first output signal terminal Out 1; a gate of the fourth transistor M4 is electrically connected to the second voltage signal terminal V2, a first pole of the fourth transistor M4 is electrically connected to the third Input signal terminal Input3, and a second pole of the fourth transistor M4 is electrically connected to the second output signal terminal Out 2.
Alternatively, the types of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are the same as those of the respective transistors in the pixel circuit 101. Illustratively, each of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the pixel circuit 101 is a P-type transistor.
In this application, the signal input terminal is a first pole of the transistor, and the signal output terminal is a second pole of the transistor. Illustratively, the first pole of the transistor is, for example, a source, and the second pole is, for example, a drain.
The pixel control circuit 100 only needs 4 transistors, and has a simple circuit structure and a small resistance, which is beneficial to reducing the loss of the fourth voltage signal and further reducing the leakage current of the pixel circuit 101.
Optionally, as shown in fig. 8, in a case that the control unit 10 includes the shift register 102, an Input signal terminal of a first stage shift register in the plurality of shift registers 102 in the control circuit 1 is electrically connected to the start signal, and an output signal terminal of an N-1 th stage shift register and an output signal terminal of an nth stage shift register are respectively connected to the second Input signal terminal Input2 of the pixel control circuit 100 corresponding to the N-1 th stage shift register and the nth stage shift register, where the nth stage is a last stage shift register, and N is a positive integer.
Except for the first stage shift register 102, the N-1 th stage shift register 102, and the N-th stage shift register 102, an output signal terminal of the M-th stage shift register 102 is electrically connected to an Input signal terminal Input of the M +2 th stage shift register 102 and a second Input signal terminal Input2 of the pixel control circuit 100 corresponding to the M-th stage shift register 102, where 1 < M < N-1.
As shown in fig. 8, the M +1 th, and M +2 th stage shift registers are electrically connected to a clock signal clk, a clock signal clb, a third voltage signal terminal V3, and a fourth voltage signal terminal V4, respectively. Illustratively, the odd row shift registers 102 use, for example, the clock signal clk, and the even row shift registers 102 use, for example, the clock signal clb.
The pixel control circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4 electrically connected; a first electrode of the first transistor M1 is used as a first Input signal terminal Input1 of the pixel control circuit 100; a second pole of the first transistor M1 and a second pole of the third transistor M3 are electrically connected and serve as a first output signal terminal Out1 of the pixel control circuit 100.
A first pole of the second transistor M2 serves as a second Input signal terminal Input2 of the pixel control circuit 100, and a second pole of the second transistor M2 and a second pole of the fourth transistor M4 are electrically connected and serve as a second output signal terminal Out2 of the pixel control circuit 100.
A first pole of the third transistor M3 and a first pole of the fourth transistor M4 are electrically connected and serve as a third Input signal terminal Input3 of the pixel control circuit 100.
The pixel circuit 101 is electrically connected to the first reset signal terminal Rst1, the second reset signal terminal Rst2, and the scan signal terminal Gate.
Taking the M + 2-th stage shift register as an example, the Input signal terminal Input of the M + 2-th stage shift register is electrically connected to the output signal terminal Out of the M-th stage shift register, the first pole of the first transistor M1, and the second reset signal terminal Rst 2; an output signal terminal of the M +2 th stage shift register 102 is electrically connected to a first pole of the second transistor M2; the fourth voltage signal terminal V4 is electrically connected to the first pole of the third transistor M3 and the first pole of the fourth transistor M4, the second pole of the first transistor M1 is electrically connected to the second pole of the third transistor M3, and the second pole of the second transistor M2 is electrically connected to the second pole of the fourth transistor M4; the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 described above all refer to transistors in the pixel control circuit 100 corresponding to the M +2 th stage of the shift register.
The second pole of the first transistor M1 is electrically connected to the first reset signal terminal Rst1 of the M +2 th pixel circuit 101 to provide the M +2 th pixel circuit 101 with the first reset signal.
The second pole of the second transistor M2 is electrically connected to the scan signal terminal Gate of the M +2 th pixel circuit 101 to provide a scan signal terminal for the M +2 th pixel circuit 101.
An Input signal terminal Input of the M +2 th stage shift register supplies a second reset signal to a second reset signal terminal of the pixel circuit 101. The second reset signal is not controlled by the pixel control circuit 100, is directly electrically connected to the shift register 102, and is controlled by the shift register 102.
Alternatively, as shown in fig. 8, in the control circuit 1, the first voltage signal terminals V1 of all the control units 10 are electrically connected, and the second voltage signal terminals V2 of all the control units 10 are electrically connected.
The control circuit 1 has the same advantages as the control unit 10, and thus the description is omitted.
As shown in fig. 9, an embodiment of the present invention further provides a method for controlling a display device, including:
s1, referring to fig. 8, in the Porch region of one frame of image, at the first refresh frequency, the pixel control circuit 100 in the control circuit 1 transmits the first Input signal provided by the first Input signal terminal Input1 to the first output signal terminal Out1 and transmits the second Input signal provided by the second Input signal terminal Input2 to the second output signal terminal Out2 under the control of the first voltage signal terminal V1.
For example, at the first refresh frequency, the first transistor M1 and the second transistor M2 are turned on, the third transistor M3 and the fourth transistor M4 are turned off, and the Input signal terminal Input of the shift register 102 transmits the Input signal to the first reset signal terminal Rst1 of the pixel circuit 101 through the first transistor M1; the output signal terminal Out of the shift register 102 transmits the output signal to the scan signal terminal Gate in the pixel circuit 101 through the second transistor M2.
S2, in the Porch region of one frame of image, under the control of the second voltage signal terminal V2, the pixel control circuit 100 transmits the third Input signal provided by the third Input signal terminal Input3 to the first output signal terminal Out1 and the second output signal terminal Out2 at the same time at the second refresh frequency; wherein the first refresh frequency is greater than the second refresh frequency.
For example, at the second refresh frequency, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 and the fourth transistor M4 are turned on, the fourth voltage signal terminal V4 of the shift register 102 transmits the fourth voltage signal to the first reset signal terminal Rst1 of the pixel circuit 101 through the third transistor M3, and transmits the fourth voltage signal to the scan signal terminal Gate in the pixel circuit 101 through the fourth transistor M4.
Note that, in the display region of one frame image, the pixel control circuit 100 always controls the first transistor M1 and the second transistor M2 to be turned on, regardless of the refresh frequency of the display device. Only in the Porch region, the control circuit 1 controls the signals transmitted to the first reset signal terminal Rst1 and the scan signal terminal Gate of the pixel circuit 101 through the pixel control circuit 100 according to the refresh frequency of the display device.
Optionally, the pixel control circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.
At a first refresh frequency: the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 and the fourth transistor M4 are turned off; the first transistor M1 transmits a first Input signal provided by the first Input signal terminal Input1 to the first output signal terminal Out1, and the second transistor M2 transmits a second Input signal provided by the second Input signal terminal Input2 to the second output signal terminal Out 2.
At a second refresh frequency: the third transistor M3 and the fourth transistor M4 are turned on, and the first transistor M1 and the second transistor M2 are turned off; the third transistor M3 transmits the third Input signal provided by the third Input signal terminal Input3 to the first output signal terminal Out1, and the fourth transistor M4 transmits the third Input signal provided by the third Input signal terminal Input3 to the second output signal terminal Out 2.
Optionally, the first refresh frequency is 120HZ, and the second refresh frequency is 60 HZ.
Alternatively, as shown in FIG. 10a, at a first refresh frequency, the first voltage signal ≦ -10V; the second voltage signal is more than or equal to 10V. In the case where the transistors in the pixel control circuit 100 are all P-type transistors, the first transistor M1 and the second transistor M2 are turned on.
Under the second refresh frequency, the range of the first voltage signal and the range of the second voltage signal are both-10V, and within the time length P2 range of the Porch region, the first voltage signal is 10V, and the second voltage signal is-10V. The third transistor M3 and the fourth transistor M4 in the control circuit are turned on.
As shown in fig. 10a, those skilled in the art should understand that P2-t 2-t 1-t 1.
For example, t1 is 8.3 ms.
With the structure shown in fig. 8, in conjunction with fig. 10a and 10b, at the second refresh frequency, the pixel control circuit 100 controls the third transistor M3 and the fourth transistor M4 to turn on, and transmits the fourth voltage signal provided from the fourth voltage signal terminal V4 to the first reset signal terminal Rst1 and the scan signal terminal Gate in the pixel circuit 101. The fourth voltage signal is directly transmitted through the third transistor M3 and the fourth transistor M4, and the loss is smaller than the loss when the fourth voltage signal is directly transmitted through the shift register 102 in the related art, that is, in the Porch region at the second refresh frequency, the voltages of the first reset signal terminal Rst1 and the scan signal terminal Gate in the pixel circuit 101 are greater than the voltages of the first reset signal terminal Rst1 and the scan signal terminal Gate in the related art, so that the leakage current of the pixel circuit 101 during the operation of the Porch region can be reduced, and the leakage currents of the pixel circuit 101 during the operation of the display region and the Porch region are equal or similar. Comparing fig. 5 and fig. 10b, when the pixel circuit 101 in the present application operates at the first refresh frequency and the second refresh frequency, the displayed brightness is the same, and the display effect of the display device is better.
In the present application, the low level is, for example, a low level that can turn on the P-type transistor, and the high level is, for example, a high level that can turn off the P-type transistor.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A control unit, comprising:
the pixel control circuit is electrically connected with a first input signal end, a second input signal end, a third input signal end, a first voltage signal end, a second voltage signal end, a first output signal end and a second output signal end; the pixel control circuit is configured to transmit a first input signal provided by the first input signal terminal to the first output signal terminal and transmit a second input signal provided by the second input signal terminal to the second output signal terminal under the control of the first voltage signal terminal; and transmitting a third input signal provided by the third input signal terminal to the first output signal terminal and the second output signal terminal under the control of the second voltage signal terminal;
a pixel circuit electrically connected to a first reset signal terminal, a scan signal terminal, a data signal terminal, and a first initial voltage signal terminal, the pixel circuit having a first node; the pixel circuit is configured to transmit a data signal provided by the data signal terminal to a first node under the control of the scan signal terminal; and transmitting a first initial voltage provided by the first initial voltage signal terminal to the first node under the control of the first reset signal terminal;
the first output signal end of the pixel control circuit is electrically connected with the first reset signal end of the pixel circuit, and the second output signal end of the pixel control circuit is electrically connected with the scanning signal end of the pixel circuit.
2. The control unit of claim 1, further comprising a shift register electrically connected to the input signal terminal and the output signal terminal; the input signal end of the shift register is electrically connected with the first input signal end of the pixel control circuit, and the output signal end of the shift register is electrically connected with the second input signal end of the pixel control circuit.
3. The control unit of claim 2, wherein the shift register is further electrically connected to a clock signal terminal, a third voltage signal terminal, and a fourth voltage signal terminal; the shift register is configured to transmit a clock signal provided by the clock signal terminal and a fourth voltage signal provided by the fourth voltage signal terminal to the output signal terminal under the control of the input signal terminal and the third voltage signal terminal;
the fourth voltage signal terminal is electrically connected to the third input signal terminal of the pixel control circuit.
4. The control unit according to claim 1, wherein the pixel control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the grid electrode of the first transistor is electrically connected with a first voltage signal end, the first electrode of the first transistor is electrically connected with the first input signal end, and the second electrode of the first transistor is electrically connected with the first output signal end; a grid electrode of the second transistor is electrically connected with a first voltage signal end, a first electrode of the second transistor is electrically connected with the second input signal end, and a second electrode of the second transistor is electrically connected with the second output signal end; a gate of the third transistor is connected to a second voltage signal terminal, a first electrode of the third transistor is electrically connected to the third input signal terminal, and a second electrode of the third transistor is electrically connected to the first output signal terminal; the gate of the fourth transistor is electrically connected to the second voltage signal terminal, the first electrode of the fourth transistor is electrically connected to the third input signal terminal, and the second electrode of the fourth transistor is electrically connected to the second output signal terminal.
5. The control unit of claim 1, wherein the pixel circuit comprises:
the data writing module is electrically connected with the scanning signal end, the data signal end and the first node; the data writing module is configured to write the data signal provided by the data signal terminal into the first node under the control of the scanning signal terminal;
the driving module is electrically connected with a power supply voltage signal end and the first node, and is configured to output a driving signal under the control of the first node and the power supply voltage signal end, wherein the driving signal is used for driving an element to be driven to emit light;
the control module is electrically connected with the power supply voltage signal end, the enabling signal end, the driving module and the element to be driven, and the control module is configured to enable the driving module to be electrically connected with the element to be driven under the control of the enabling signal end so as to drive the element to be driven to emit light;
the reset module is electrically connected with the first node, the first reset signal terminal, the second reset signal terminal, the first initial voltage signal terminal, the second initial voltage signal terminal and the element to be driven, and is configured to transmit a first initial voltage provided by the first initial voltage signal terminal to the first node under the control of the first reset signal terminal and transmit a second initial voltage provided by the second initial voltage signal terminal to the element to be driven under the control of the second reset signal terminal.
6. A control circuit comprising a plurality of control units, said control units being as claimed in any one of claims 1 to 5;
the first voltage signal ends of all the control units are electrically connected, and the second voltage signal ends of all the control units are electrically connected.
7. The control circuit according to claim 6, wherein in a case where the control unit includes a shift register, an input signal terminal of a first stage shift register among the plurality of shift registers is electrically connected to the start signal, and an output signal terminal of an N-1 th stage shift register and an output signal terminal of an N-th stage shift register are respectively connected to second input signal terminals of the pixel control circuits corresponding to the N-1 th stage shift register and the N-th stage shift register, where the N-th stage is a last stage shift register and N is a positive integer;
except for the first stage shift register, the N-1 stage shift register and the N stage shift register, the output signal end of the M stage shift register is electrically connected with the input signal end of the M +2 stage shift register and the second input signal end of the pixel control circuit corresponding to the M stage shift register, wherein M is more than 1 and less than N-1.
8. A display device comprising a display panel including a control circuit according to claim 6 or 7.
9. A control method of a display device according to claim 8, comprising:
at a first refresh rate, the refresh rate is,
the pixel control circuit in the control circuit transmits a first input signal provided by the first input signal end to a first output signal end and transmits a second input signal provided by the second input signal end to a second output signal end under the control of a first voltage signal end;
at the second refresh rate, the refresh rate is,
the pixel control circuit transmits a third input signal provided by the third input signal end to the first output signal end and the second output signal end simultaneously under the control of a second voltage signal end;
wherein the first refresh frequency is greater than the second refresh frequency.
10. The method according to claim 9, wherein the pixel control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
at the first refresh frequency: the first transistor and the second transistor are turned on, and the third transistor and the fourth transistor are turned off; the first transistor transmits a first input signal provided by the first input signal terminal to a first output signal terminal, and the second transistor transmits a second input signal provided by the second input signal terminal to the second output signal terminal;
at the second refresh frequency: the third transistor and the fourth transistor are turned on, and the first transistor and the second transistor are turned off; the third transistor transmits a third input signal provided from a third input signal terminal to the first output signal terminal, and the fourth transistor transmits a third input signal provided from a third input signal terminal to the second output signal terminal.
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| CN111583850B (en) * | 2020-05-22 | 2022-05-13 | 昆山国显光电有限公司 | Shift register, light-emitting control circuit and display panel |
| US11688347B2 (en) * | 2020-11-03 | 2023-06-27 | Boe Technology Group Co., Ltd. | Pixel circuit having control circuit for controlling a light emitting element and driving method thereof, display panel and display apparatus |
| KR20220092098A (en) | 2020-12-24 | 2022-07-01 | 엘지디스플레이 주식회사 | Display apparatus |
| CN115701629A (en) * | 2021-08-02 | 2023-02-10 | 华为技术有限公司 | Pixel driving circuit, display and electronic equipment |
| CN113689825A (en) * | 2021-08-20 | 2021-11-23 | 京东方科技集团股份有限公司 | Driving circuit, driving method and display device |
| CN114038418A (en) * | 2021-11-29 | 2022-02-11 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof and display device |
| CN115731839B (en) * | 2022-11-29 | 2024-07-19 | 云谷（固安）科技有限公司 | Display driving circuit and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106875891A (en) * | 2015-10-05 | 2017-06-20 | 乐金显示有限公司 | Organic light emitting diode display and its driving method |
| TW201735542A (en) * | 2010-05-21 | 2017-10-01 | 半導體能源研究所股份有限公司 | Pulse output circuit, shift register, and display device |
| CN107799070A (en) * | 2017-12-08 | 2018-03-13 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display device and grid drive method |
| CN110379351A (en) * | 2019-07-29 | 2019-10-25 | 上海天马有机发光显示技术有限公司 | Driving method, display panel and the display device of display panel |
-
2020
- 2020-01-06 CN CN202010011352.2A patent/CN111179849B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201735542A (en) * | 2010-05-21 | 2017-10-01 | 半導體能源研究所股份有限公司 | Pulse output circuit, shift register, and display device |
| CN106875891A (en) * | 2015-10-05 | 2017-06-20 | 乐金显示有限公司 | Organic light emitting diode display and its driving method |
| CN107799070A (en) * | 2017-12-08 | 2018-03-13 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display device and grid drive method |
| CN110379351A (en) * | 2019-07-29 | 2019-10-25 | 上海天马有机发光显示技术有限公司 | Driving method, display panel and the display device of display panel |
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