CN115662328A - Display device - Google Patents
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- CN115662328A CN115662328A CN202211280723.2A CN202211280723A CN115662328A CN 115662328 A CN115662328 A CN 115662328A CN 202211280723 A CN202211280723 A CN 202211280723A CN 115662328 A CN115662328 A CN 115662328A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a display device, which comprises a display panel, a gate driver and an emission driver, wherein the gate driver comprises a first gate driving unit and a second gate driving unit which output a first scanning signal and a second scanning signal to sub-pixels of the display panel, and the emission driver outputs a light-emitting control signal to the sub-pixels. The display panel comprises a plurality of display periods, and at least one display period is provided with a writing frame and a plurality of holding frames. In the writing frame and the corresponding first time length in each holding frame, the ratio of the period number of the light-emitting control signal to the first time length is larger than the critical flicker frequency, the effective pulse of the first scanning signal is in one-to-one correspondence with the ineffective pulse of the light-emitting control signal, and the effective pulse of the second scanning signal is only positioned in the action time of the ineffective pulse in the first period of the light-emitting control signal of the writing frame, so that the display panel can give consideration to both the display performance and the endurance performance when the ultra-low frequency display is realized.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display device.
Background
With the continuous update and iteration of display devices such as smart phones and smart watches, the requirements of users on the display performance and the cruising performance of the display devices are higher and higher. However, in practical use, the display device has a high display performance, which often increases power consumption and reduces cruising ability, and the display performance needs to be sacrificed to improve cruising ability, so that the display device cannot meet both the display performance requirement and the cruising performance requirement.
Disclosure of Invention
The embodiment of the invention provides a display device which can meet both requirements on display performance and endurance.
An embodiment of the invention provides a display device, which includes a display panel, a gate driver and an emission driver. The display panel comprises a plurality of sub-pixels; the gate driver includes a first gate driving unit configured to output a first scan signal to the sub-pixel and a second gate driving unit configured to output a second scan signal to the sub-pixel; the emission driver is configured to output a light emission control signal to the sub-pixel.
The display panel is provided with a plurality of display periods, at least one display period comprises a writing frame and a plurality of holding frames, and each of the writing frame and the holding frames has a first duration. In each of the write frame and the plurality of hold frames, the light emission control signal has a plurality of periods, and a ratio of the number of periods of the light emission control signal to the first period is greater than a critical flicker frequency.
The light emission control signal has an active pulse and an inactive pulse in each of the periods, the first scan signal has an active pulse in an active time of each of the inactive pulses of the light emission control signal in the write frame and the plurality of the hold frames, and the second scan signal has an active pulse in an active time of the inactive pulse in a first one of the periods of the light emission control signal in the write frame.
The invention provides a display device, which comprises a display panel, a grid driver and an emission driver, wherein the grid driver comprises a first grid driving unit and a second grid driving unit which output a first scanning signal and a second scanning signal to sub-pixels of the display panel, and the emission driver outputs a light-emitting control signal to the sub-pixels. The display panel comprises a plurality of display periods, and at least one display period is provided with a writing frame and a plurality of holding frames. In the corresponding first time length of the writing frame and each holding frame, the ratio of the period number of the luminous control signal to the first time length is larger than the critical flicker frequency, so that the sub-pixels respectively realize the switching of multiple display states and non-display states in the writing frame and the holding frames under the control of the luminous control signal, the feeling of audiences on the flicker problem of the display panel is reduced in the total time length corresponding to the writing frame and the holding frames, and the display panel has better display performance. The effective pulse of the first scanning signal is in one-to-one correspondence with the ineffective pulse of the light-emitting control signal, and the effective pulse of the second scanning signal is only positioned in the action time of the ineffective pulse in the first period of the light-emitting control signal of the writing frame, so that the sub-pixels are switched between a plurality of display states and non-display states in the writing frame and a plurality of holding frames respectively according to the same display content under the control of the light-emitting control signal, the first scanning signal and the second scanning signal in the total time length corresponding to one display period, and the information displayed by the plurality of sub-pixels in the total time length corresponding to the writing frame and the plurality of holding frames is the same, so that the aim of giving consideration to both the display performance and the endurance performance is fulfilled.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;
FIG. 2 is a diagram of human eye perception of flicker provided by an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a sub-pixel according to an embodiment of the present invention;
FIG. 4 is a timing diagram of a corresponding high frequency driving mode according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of increasing a duration corresponding to each frame according to an embodiment of the present invention;
fig. 6 is a timing diagram of a write frame in the corresponding ultra low frequency driving mode according to an embodiment of the present invention;
fig. 7 is a schematic diagram of an actual measurement result of a light-emitting waveform with a brightness of 50nit according to an embodiment of the present invention;
FIG. 8 is a timing diagram of a display period corresponding to the ultra low frequency driving mode according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a power consumption test result provided in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Furthermore, it should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, and are not intended to limit the present invention. In the present invention, unless stated to the contrary, the use of directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, particularly in the direction of the drawing figures; while "inner" and "outer" are with respect to the outline of the device.
Specifically, fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention. The invention provides a display device which comprises a display panel and a drive control module.
Optionally, the display panel includes a self-luminous display panel. Alternatively, the self-light emitting display panel includes an organic light emitting diode display panel, a sub-millimeter light emitting diode display panel, a micro light emitting diode display panel, a quantum dot display panel, and the like.
The display panel includes a plurality of sub-pixels SP, a plurality of scan lines, a plurality of data lines, and a plurality of light emission control lines. The plurality of sub-pixels SP form a plurality of pixel units Pi arranged in an array, and the plurality of scanning lines, the plurality of Data lines and the plurality of light emitting control lines are electrically connected with the plurality of sub-pixels SP, so that the plurality of sub-pixels SP realize a display function according to corresponding scanning signals, data signals Data and light emitting control signals EM.
Optionally, each pixel unit Pi comprises three sub-pixels SP. Alternatively, the three sub-pixels SP included in each pixel unit Pi have different emission colors. The emission color of the sub-pixel SP includes red, green, blue, yellow, white, and the like.
Optionally, the driving control module includes a gate driver, an emission driver, and a data driver.
The gate driver is configured to output a scan signal to the display panel. Alternatively, the gate driver is electrically connected to the plurality of scan lines to transmit scan signals to the plurality of subpixels SP through the plurality of scan lines.
Optionally, the gate driver includes a first gate driving unit and a second gate driving unit. The first gate driving unit is configured to output a first scan signal Pscan1 to the display panel. The second gate driving unit is configured to output the second scan signal Pscan2 to the display panel.
The emission driver is configured to output the emission control signal EM to the display panel. Alternatively, the emission driver is electrically connected to the plurality of light emission control lines to output the light emission control signal EM to the plurality of sub-pixels SP through the plurality of light emission control lines.
The Data driver is configured to output the Data signal Data to the display panel. Alternatively, the Data driver is electrically connected with the plurality of Data lines to output the Data signals Data to the plurality of subpixels SP through the plurality of Data lines.
Optionally, the driving controller includes a receiver, a register, a timing controller, a memory controller, a random access memory, and a dynamic frame rate module. The principle of the driving controller controlling the gate driver, the data driver and the emission driver to realize the control of the display states of the plurality of pixel cells Pi is as follows:
the first stage is as follows: the receiver outputs an instruction c to the register according to the register instruction a sent by the host end, and the register is configured according to the instruction c.
And a second stage: the host sends image data signal b to the receiver at a certain time interval (for example, the time interval is one minute), the receiver outputs image data signal d to the memory controller according to the image data signal b sent by the host, and the memory controller outputs image data signal f to the random access memory according to the image data signal d.
And a third stage: the register outputs an instruction e set by corresponding time sequence control to the time sequence controller, the random access memory outputs an image data signal h to the time sequence controller according to an image data signal f, and the dynamic frame frequency module outputs a high-frequency switching instruction i to the time sequence controller after detecting that the random access memory has an updated data signal g.
A fourth stage: the time schedule controller respectively sends the corresponding high-frequency switching instructions j to the grid driver, the emission driver and the data driver so as to control the display panel to display the plurality of sub-pixels SP in a high-frequency driving mode through the grid driver, the emission driver and the data driver.
The fifth stage: the host stops outputting image data signals to the receiver, the dynamic frame frequency module detects that the random access memory has no updated data signals g, and the low-frequency switching instruction i is output to the time schedule controller.
The sixth stage: and the time schedule controller respectively sends the corresponding low-frequency switching command j to the gate driver, the emission driver and the data driver so as to control the display panel to realize the display of the plurality of sub-pixels SP in an ultralow frequency driving mode through the gate driver, the emission driver and the data driver.
To realize the display function, the display panel may have a plurality of display periods. In order to realize the frequency conversion technology, the corresponding duration of each display period of the display panel can be different. When the display panel adopts the high-frequency driving mode to realize display, only a writing frame WF can be included in the display period, and when the display panel adopts the frequency lower than the high-frequency driving mode to realize display, the display panel can include a writing frame WF and at least one holding frame HF. The Data signal Data is written to the sub-pixel SP during the active time of the second scan signal Pscan2 in the write frame WF, and the Data signal Data written to the sub-pixel SP in the write frame WF is maintained in the hold frame HF, so that the display panel displays the same information in the total time tsu corresponding to one display period when the display panel displays with a frequency lower than the high frequency driving mode.
The lower frequency is adopted by the display panel to realize display, and the endurance performance of the display device is improved. In particular, in order to improve the cruising performance of the display device, the display panel can realize display by adopting ultra-low frequency. The ultra-low frequency is a frequency less than 1Hz. However, when the display panel is used for displaying at an ultra-low frequency, a serious flicker problem is caused.
In order to enable the display panel to realize display by applying ultra-low frequency and improve the flicker problem at the same time, so as to realize the purpose of giving consideration to both display performance and endurance performance, the writing frame WF and the plurality of holding frames HF each have a first time length tfr, the light-emitting control signal EM has a plurality of periods T in each of the writing frame WF and the plurality of holding frames HF, the ratio of the period number Ncft of the light-emitting control signal EM to the first time length tfr is larger than the critical flicker frequency CFF, namely Ncft/tfr > CFF, so that the sub-pixel SP can realize the switching between a plurality of display states and a non-display state in the writing frame WF and the plurality of holding frames HF respectively under the control of the light-emitting control signal EM, thereby reducing the feeling of the audience on the flicker problem of the display panel in the total time tsu corresponding to the writing frame WF and the plurality of holding frames HF, and enabling the display panel to have better display performance.
The light emission control signal EM is made to have an active pulse and an inactive pulse in each period, the first scan signal Pscan1 has an active pulse in the action time of each inactive pulse of the light emission control signal EM in the write frame WF and the plurality of hold frames HF, and the second scan signal Pscan2 has an active pulse in the action time of the inactive pulse in the first period of the light emission control signal EM in the write frame WF, so that the sub-pixels SP are made to switch between the multi-display state and the non-display state according to the same display contents in the write frame WF and the plurality of hold frames HF under the control of the light emission control signal EM, the first scan signal Pscan1, and the second scan signal Pscan2 in the total duration tsu corresponding to the write frame WF and the plurality of hold frames HF, respectively, thereby making the information displayed by the plurality of sub-pixels SP the same in the total duration tsu corresponding to the write frame WF and the plurality of hold frames HF, so as to achieve both the display performance and the endurance performance.
The critical flicker frequency CFF is the frequency of the minimum flicker light that human eyes can perceive as stable light. Optionally, the critical flicker frequency CFF is greater than or equal to 45Hz.
Fig. 2 is a diagram illustrating the human eye's perception of flicker according to the embodiment of the present invention, because the critical flicker frequency CFF is closely related to the display brightness, the ambient brightness, the viewing distance, and other factors, and is not constant, it can be seen from fig. 2 that the human eye cannot perceive the flicker problem when the frequency is greater than or equal to 60 Hz. Therefore, the ratio of the number of cycles Ncft of the light emission control signal EM in each of the write frame WF and the plurality of holding frames HF to the first time length tfr may be made greater than or equal to 60Hz; namely: ncft/tfr is more than or equal to 60Hz, so that the flicker problem of the display picture cannot be perceived by human eyes when the display device is actually applied.
It is understood that the total time length tsu corresponding to a display period is the sum of the write frame WF and the first time lengths tfr corresponding to the hold frames HF included in a display period. I.e., sut = m tfr; where m is the total number of frames, and the total number of frames m is the sum of the number of write frames WF and the number of hold frames HF included in one display period.
Optionally, in order to enable the display panel to realize display with an ultra-low frequency, the total number m of frames included in one display period needs to be less than or equal to the frame skipping upper limit SKL provided in the driving control module; namely: and m is less than or equal to SKL. Correspondingly, the ratio of the total time length tsu corresponding to a display period to the first time length tfr is less than or equal to the frame skipping upper limit SKL provided in the drive control module; namely sut/tfr is less than or equal to SKL. Alternatively, the skip frame upper limit SKL that can be provided in the drive control module is determined by the number of bits of a register that controls the number of skip frames included in the drive control module. Specifically, the register for controlling the frame skipping quantity is xbit, and the frame skipping upper limit is equal to 2^ x; if the register for controlling the frame skipping quantity is 8 bits, the frame skipping upper limit SKL is equal to 2^8=256; and the register for controlling the frame skipping number is 10 bits, and the frame skipping upper limit SKL is equal to 2^10=1024. Among them, the register shown in fig. 1 represents all registers included in the display device, not only a register for controlling the number of frame skipping.
Alternatively, since the Data signal Data is written to the sub-pixel SP within the effective pulse duration of the second scan signal Pscan2 in the write frame WF, and the display panel displays the same information within the total duration tsu corresponding to one display period, the target frequency f1 of the second scan signal Pscan2 within the total duration tsu corresponding to one display period (i.e., the sum of the write frame WF and the first durations corresponding to the holding frames HF) may be less than 1Hz, i.e., f1<1Hz, so that the sub-pixel SP updates the display information according to each display period, thereby implementing the ultra-low frequency display on the display panel. Correspondingly, the total time length tsu corresponding to a display period and the target frequency f1 of the second scan signal Pscan2 in a display period are inverse; i.e. tsu =1/f1.
Optionally, the target frequency f1 is a frequency used when the display panel implements display in the ultra-low frequency driving mode. <xnotran> f1 0.99Hz, 0.98Hz, … …, 0.9Hz, 0.89Hz, … …, 0.75Hz, … …, 0.5Hz, … …, 0.11Hz, 0.1Hz, 0.099Hz, 0.098Hz, … …, 0.09Hz, 0.089Hz, … …, 0.08Hz, 0.079Hz, … …, 0.07Hz, 0.069Hz, … …, 0.064Hz, … …, 0.06Hz, … …, 0.05Hz, … …, 0.04Hz, … …, 0.032Hz, … …, 0.03Hz, … …, 0.02Hz, … …, 0.016Hz, 0.015Hz, … …, 0.01Hz, 0.009Hz, 0.008Hz … …, 0.006Hz, 0.005Hz, 0.004Hz … … . </xnotran>
Optionally, in the write frame WF, the product of the base frequency f3 of the second scan signal Pscan2 and the number Ncft of cycles of the emission control signal EM is equal to the middle frequency f2 of the emission control signal EM, so that the number Ncft of cycles included in the emission control signal EM is satisfied in the first time period tfr corresponding to each of the write frame WF and the plurality of hold frames HF, thereby the display screen of the display panel satisfies the display performance requirement.
Since the Data signal Data is written to the sub-pixel SP during the active time of the second scan signal Pscan2 in the write frame WF and the display panel displays the same information during the total duration tsu corresponding to a display period, the first duration tfr corresponding to the write frame WF and each hold frame HF is reciprocal to the fundamental frequency f3 of the second scan signal Pscan2 in the write frame WF; that is, tfr =1/f3, so that the sub-pixels SP display the same information in one display period, thereby realizing ultra low frequency display of the display panel.
Alternatively, the total number of frames m can be obtained according to the base frequency f3 and the target frequency f1, i.e. the ratio of the base frequency f3 to the target frequency f1 is equal to the total number of frames m (i.e. the ratio of the base frequency f3 to the target frequency f1 is equal to the sum of the number of the write frames WF and the plurality of hold frames HF); i.e. f3/f1= m.
The operation principle of the display panel in the high-frequency driving mode and the low-frequency driving mode will be described with reference to the specific form of the sub-pixel SP. Optionally, as shown in fig. 3, is a schematic structural diagram of the sub-pixel SP according to an embodiment of the present invention. It is to be understood that the structure of the sub-pixel SP is not limited to the form shown in fig. 3.
Each subpixel SP includes a driving transistor Tdr, a first reset transistor Ti1, a second reset transistor Ti2, a data transistor Tda, a light emission control transistor, and a light emitting device D.
The driving transistor Tdr is configured to generate a driving current according to the Data signal Data to drive the light emitting device D to emit light. Alternatively, the driving transistor Tdr includes an input electrode connected to the first node N1, an output electrode connected to the second node N2, and a control electrode connected to the third node N3. The control electrode is a grid electrode, the input electrode is one of a source electrode and a drain electrode, and the output electrode is the other of the source electrode and the drain electrode.
The first reset transistor Ti1 is configured to reset the anode potential of the light emitting device D in accordance with the first scan signal Pscan 1. Alternatively, the first reset transistor Ti1 includes a control electrode configured to receive the first scan signal Pscan1, an input electrode configured to receive the first reset signal VI1, and an output electrode connected to the fourth node N4.
The second reset transistor Ti2 is configured to reset the input electrode potential and the output electrode potential of the driving transistor Tdr in accordance with the first scan signal Pscan 1. Alternatively, the second reset transistor Ti2 includes a control electrode configured to receive the first scan signal Pscan1, an input electrode configured to receive the second reset signal VI2, and an output electrode connected to the first node N1. The first reset transistor Ti1 and the second reset transistor Ti2 are turned on by a level state corresponding to the active pulse of the first scan signal Pscan1 and are turned off by a level state corresponding to the inactive pulse of the first scan signal Pscan 1.
The Data transistor Tda is configured to transmit a Data signal Data to the driving transistor Tdr through the first node N1 according to the second scan signal Pscan 2. Alternatively, the Data transistor Tda includes a control electrode configured to receive the second scan signal Pscan2, an input electrode configured to receive the Data signal Data, and an output electrode connected to the first node N1. The data transistor Tda is turned on by a level state corresponding to an active pulse of the second scan signal Pscan2 and turned off by a level state corresponding to an inactive pulse of the second scan signal Pscan 2.
The emission control transistor is configured to control on/off of a circulation path of the driving current according to the emission control signal EM. Alternatively, the light emission control transistor includes a first switching transistor Ts1 and a second switching transistor Ts2; the first switching transistor Ts1 includes a control electrode configured to receive the emission control signal EM, an input electrode configured to be connected to a first power terminal VDD, and an output electrode connected to a first node N1; the second switching transistor Ts2 includes a control electrode configured to receive the emission control signal EM, an input electrode configured to be connected to the second node N2, and an output electrode connected to the fourth node N4. The first switching transistor Ts1 and the second switching transistor Ts2 are turned on by a level state corresponding to an active pulse of the emission control signal EM and turned off by a level state corresponding to an inactive pulse of the emission control signal EM.
The light emitting device D includes an anode connected to the fourth node N4 and a cathode configured to be connected to a second power source terminal VSS. Alternatively, the light emitting device D includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, or the like.
Optionally, with continued reference to fig. 1 to fig. 3, the gate driver further includes a third gate driving unit configured to output a third scan signal Nscan1 and a fourth scan signal Nscan2 to the sub-pixel SP.
Alternatively, the third scan signal Nscan1 and the fourth scan signal Nscan2 each have an active pulse during the action time of the inactive pulse in the first period of the light emission control signal EM in the write frame WF to initialize the potential of the third node N3 in the write frame WF and transmit the Data signal Data to the gate of the driving transistor Tdr in the write frame WF, thereby causing the sub-pixel SP to keep displaying in the hold frame HF according to the Data signal Data written in the sub-pixel SP in the write frame WF.
The sub-pixel SP further includes a compensation transistor Tc, a third reset transistor Ti3, and a storage capacitor Cst.
The compensation transistor Tc includes a control electrode configured to receive the third scan signal Nscan1, an input electrode configured to be connected to a third node N3, and an output electrode connected to a second node N2.
The third reset transistor Ti3 includes a control electrode configured to receive the fourth scan signal Nscan2, an input electrode configured to receive the third reset signal VI3, and an output electrode connected to the third node N3.
The storage capacitor Cst includes a first electrode configured to be connected to the first power terminal VDD and a second electrode connected to the third node N3.
Alternatively, the active layer of the compensation transistor Tc and the active layer of the third reset transistor Ti3 each include an oxide semiconductor, and the active layer of the driving transistor Tdr, the active layer of the first reset transistor Ti1, the active layer of the second reset transistor Ti2, the active layer of the data transistor Tda, and the active layer of the light emission control transistor each include a silicon semiconductor. Alternatively, the silicon semiconductor includes single crystal silicon, polycrystalline silicon, amorphous silicon, or the like, and the oxide semiconductor includes at least one of zinc oxide, zinc tin oxide, zinc indium oxide, titanium oxide, indium gallium zinc oxide, indium zinc tin oxide, or the like. Alternatively, the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, and the emission control transistor are manufactured using a low temperature polysilicon process.
In order to improve the flicker problem, the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4 are kept equal when the non-display state or the display state is realized a plurality of times in each of the write frame WF and the hold frame HF corresponding to the sub-pixel SP.
Alternatively, during the action time of the plurality of ineffective pulses of the emission control signal EM, the potential of the first node N1 is kept equal, the potential of the second node N2 is kept equal, the potential of the third node N3 is kept equal, and the potential of the fourth node N4 is kept equal, so as to improve the flicker problem.
Alternatively, the voltage volts of the second reset signal VI2 may be controlled to keep the potential of the first node N1 equal and the potential of the second node N2 equal during the action time of the plurality of inactive pulses of the emission control signal EM. Alternatively, the driving transistor Tdr is a P-type transistor, and during the action time of each effective pulse of the first scanning signal Pscan1, the difference between the potential of the third node N3 and the second reset signal VI2 is smaller than the threshold voltage of the driving transistor Tdr, so that when the second reset transistor Ti2 is turned on, the driving transistor Tdr is also turned on, thereby causing the second reset transistor Ti2 to reset the input electrode potential (i.e., the potential of the first node N1) and the output electrode potential (i.e., the potential of the second node N2) of the driving transistor Tdr according to the first scanning signal Pscan 1.
Fig. 4 is a timing diagram of a corresponding high frequency driving mode according to an embodiment of the invention. The working principle of the sub-pixel SP shown in fig. 3 will be described by taking as an example that the corresponding frequency in the high-frequency driving mode is 60Hz, the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, the first switching transistor Ts1, and the second switching transistor Ts2 are all P-type transistors, and the compensation transistor Tc and the third reset transistor Ti3 are all N-type transistors. One display cycle only includes a write frame WF, which includes an initialization phase P1, a data write phase P2, a node reset phase P3, and a light emitting phase P4.
Initialization phase P1: the emission control signal EM, the first scan signal Pscan1, the second scan signal Pscan2, the third scan signal Nscan1, and the fourth scan signal Nscan2 all correspond to a high level state, the third reset transistor Ti3 is turned on in response to the fourth scan signal Nscan2, the compensation transistor Tc is turned on in response to the third scan signal Nscan1 so that the driving transistor Tdr is diode-connected, the driving transistor Tdr is turned on, and the third reset signal resets the potentials of the third node N3, the second node N2, and the first node N1. The first and second reset transistors Ti1 and Ti2 are both turned off in response to the first scan signal Pscan1, the data transistor Tda is turned off in response to the second scan signal Pscan2, and the first and second switching transistors Ts1 and Ts2 are both turned off in response to the emission control signal EM.
Data write phase P2: the emission control signal EM, the first scan signal Pscan1 and the third scan signal Nscan1 correspond to a high state, the second scan signal Pscan2 and the fourth scan signal Nscan2 correspond to a low state, the Data transistor Tda is turned on in response to the second scan signal Pscan2, the compensation transistor Tc is turned on in response to the third scan signal Nscan1 so that the driving transistor Tdr is diode-connected, the driving transistor Tdr is turned on, and the Data signal Data is transmitted to the third node N3 through the Data transistor Tda, the first node N1, the driving transistor Tdr, the second node N2 and the compensation transistor Tc, so as to write the Data signal Data and capture a threshold voltage of the driving transistor Tdr. The first and second reset transistors Ti1 and Ti2 are both turned off in response to the first scan signal Pscan1, the first and second switching transistors Ts1 and Ts2 are turned off in response to the light emission control signal EM, and the third reset transistor Ti3 is turned off in response to the fourth scan signal Nscan 2.
Node reset phase P3: the emission control signal EM and the second scan signal Pscan2 both correspond to a high level state, the first scan signal Pscan1, the third scan signal Nscan1, and the fourth scan signal Nscan2 all correspond to a low level state, the first reset transistor Ti1 and the second reset transistor Ti2 are both turned on in response to the first scan signal Pscan1, and the first reset signal VI1 resets the potential of the fourth node N4. The second reset signal VI2 has a higher voltage value, and the voltage difference between the gate and the source of the driving transistor Tdr is the voltage difference between the third node N3 and the first node N1, so that the voltage difference between the third node N3 and the first node N1 is smaller than the threshold voltage of the driving transistor Tdr, and the driving transistor Tdr can be turned on, so that the second reset signal VI2 resets the potentials of the first node N1 and the second node N2. The data transistor Tda is turned off in response to the second scan signal Pscan2, the compensation transistor Tc is turned off in response to the third scan signal Nscan1, the third reset transistor Ti3 is turned off in response to the fourth scan signal Nscan2, and both the first switching transistor Ts1 and the second switching transistor Ts2 are turned off in response to the emission control signal EM.
Light emission phase P4: the light emission control signal EM, the third scan signal Nscan1, and the fourth scan signal Nscan2 all correspond to a low level state, the first scan signal Pscan1 and the second scan signal Pscan2 all correspond to a high level state, the first switching transistor Ts1 and the second switching transistor Ts2 are both turned on in response to the light emission control signal EM, the driving transistor Tdr is maintained to be turned on by the storage capacitor, and a driving current generated by the driving transistor Tdr according to the Data signal Data flows in a path between the first power source terminal VDD and the second power source terminal VSS to make the light emitting device D emit light. The first and second reset transistors Ti1 and Ti2 are turned off in response to the first scan signal Pscan1, the data transistor Tda is turned off in response to the second scan signal Pscan2, the compensation transistor Tc is turned off in response to the third scan signal Nscan1, and the third reset transistor Ti3 is turned off in response to the fourth scan signal Nscan 2.
Table 1 shows potential changes of the first node N1, the second node N2, the third node N3, and the fourth node N4 in the sub-pixel SP in each operating phase in the corresponding high-frequency driving mode. Vth in table 1 is a threshold voltage of the driving transistor Tdr, and lum.vo represents a change in potential actually subjected to a charge/discharge state in the circuit, and has a constant floating.
In order to improve the flicker problem caused by the ultra-low frequency driving mode while realizing the display function of the ultra-low frequency driving mode, the duration of each frame included in the next display period corresponding to the ultra-low frequency driving mode is increased, and then the display function of the ultra-low frequency driving mode is realized in a frame skipping way.
Fig. 5 is a schematic diagram of increasing a duration corresponding to each frame according to an embodiment of the present invention. Wherein VBP in fig. 5 represents a vertical back porch, VFP represents a vertical front porch, HBP represents a horizontal back porch, HFP represents a horizontal front porch, y1, y3, and y5 each represent a row number of pixel units Pi, and y2, y4, and y6 each represent a column number of pixel units Pi; y1 is not equal to y3 is not equal to y5; y2 ≠ y4 ≠ y6.
Since the resolution of the display panel is fixed after the display panel is manufactured, if the time duration corresponding to each frame is desired to be increased, the driving control module can determine the number N of the scanning lines V-proch to be controlled V-porch A number of rows larger than the number of pixel units Pi, and/or a number N of scans of pixel units Pi to be controlled per row H-line Larger than the number of columns of pixel cells Pi. I.e. the number N of scans of the pixel cells Pi that can be controlled in each row H-line Under the condition of no change, the number N of the scanning line number V-proch required to be controlled is increased V-porch The number of lines required to be scanned in each frame is increased, so that the corresponding time length of each frame is increased; the number N of the scanning line V-proch can be controlled V-porch Under the same condition, the scanning time N of the pixel units Pi required to be controlled in each row is increased H-line /f osc Thus realizing the increase of the corresponding duration of each frame; the number N of scanning lines V-proch to be controlled can be increased V-porch And the scanning time N of the pixel units Pi to be controlled for each row H-line /f osc Thereby realizing the increase of the duration corresponding to each frame. Wherein, f osc Crystal frequency 1/f of the drive control module osc Which represents the time required for the drive control module to control one pixel cell Pi to achieve a display.
Duration T corresponding to each frame frame ＝N V-porch *N H-line /f osc And is limited by the function of the driving control module, N H-line And N V-porch Have an upper limit, e.g. 1 bit for the register controlling the number of frame jumps H-line The maximum of 1024,N can be taken V-porch The maximum desirable VAA +1028, VAA is N V-porch The minimum possible value.
After the duration corresponding to each frame is increased, the ratio of the write-in frame WF and the first duration tfr corresponding to each hold frame HF included in a display period to the duration (i.e., t1 f) required by the driving controller to control one pixel unit Pi to realize display osc ＝N V-porch *N H-line ) Larger than the number of pixel cells Pi of the display device.
The timing is optimized because the flicker problem occurs when each frame is displayed at a frequency below the critical flicker frequency CFF. Specifically, at the initialization stage P1 of the write frame WF, the data write stage P2, and the node reset stage P3, the display panel adopts a high frequency driving mode to realize display, and adopts an ultra-low frequency driving mode to realize display. And when the ultra-low driving mode is adopted to realize the display, the light-emitting phase P4 is made to include a plurality of light-emitting sub-phases and a plurality of non-light-emitting sub-phases. In each emission sub-phase, the emission control signal EM has an active pulse, and the first scan signal Pscan1, the second scan signal Pscan2, the third scan signal Nscan1, and the fourth scan signal Nscan2 each have an inactive pulse, so that the first switching transistor Ts1 and the second switching transistor Ts2 are both turned on in response to the emission control signal EM, and the driving transistor Tdr controls the light emitting device D to emit light by flowing a driving current generated according to the Data signal Data in a path between the first power source terminal VDD and the second power source terminal VSS. In each of the sub-non-emission periods, the emission control signal EM, the third scan signal Nscan1 and the fourth scan signal Nscan2 all have an inactive pulse, the first scan signal Pscan1 has an active pulse within a time period in which the emission control signal EM has an inactive pulse, and a duration of the active pulse of the first scan signal Pscan1 is less than or equal to a duration of the inactive pulse of the emission control signal EM, so that the first reset transistor Ti1 and the second reset transistor Ti2 are both turned on in response to the first scan signal Pscan1, thereby resetting the potential of the fourth node N4 by the first reset signal VI1, and turning on the driving transistor Tdr by the second reset signal VI2 having a higher voltage v value, thereby resetting the potentials of the first node N1 and the second node N2 by the second reset signal VI 2. By switching the sub-pixels SP between the display state and the non-display state during the light emission period, the display frequency is increased, and the flicker problem is improved.
Specifically, a timing chart of writing the frame WF in the ultralow frequency drive mode will be described. Fig. 6 is a timing diagram of a write frame WF in the corresponding ultra low frequency driving mode according to an embodiment of the present invention; the operation principle of the light emitting stage P4 in the ultra low frequency driving mode corresponding to the sub-pixel SP shown in fig. 3 will be described with reference to the example that the first time duration tfr corresponding to the write frame WF is the base frequency f3 of the second scan signal Pscan2 is 16Hz, the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, the first switching transistor Ts1, and the second switching transistor Ts2 are P-type transistors, and the compensation transistor Tc and the third reset transistor Ti3 are N-type transistors. The light-emitting phase P4 includes a first light-emitting sub-phase P41, a first non-light-emitting sub-phase P42, a second light-emitting sub-phase P43, a second non-light-emitting sub-phase P44, a third light-emitting sub-phase P45, a third non-light-emitting sub-phase P46, and a fourth light-emitting sub-phase P47.
In the first, second, third and fourth emission sub-phases P41, P43, P45, P47: the emission control signal EM, the third scanning signal Nscan1, and the fourth scanning signal Nscan2 all correspond to a low level state, the first scanning signal Pscan1 and the second scanning signal Pscan2 all correspond to a high level state, the first switching transistor Ts1 and the second switching transistor Ts2 are both turned on in response to the emission control signal EM, the driving transistor Tdr is maintained to be turned on by the storage capacitor Cst, and a driving current generated by the driving transistor Tdr according to the Data signal Data flows in a path between the first power source terminal VDD and the second power source terminal VSS to cause the light emitting device D to emit light.
In the first, second and third non-emitting sub-phases P42, P44, P46: the emission control signal EM and the second scan signal Pscan2 both correspond to a high state, the third scan signal Nscan1 and the fourth scan signal Nscan2 both correspond to a low state, and the first scan signal Pscan1 has a low state with a certain duration within a duration in which the emission control signal EM corresponds to a high state. The first reset transistor Ti1 and the second reset transistor Ti2 are both turned on in response to the first scan signal Pscan1, and the first reset signal VI1 resets the potential of the fourth node N4. The second reset signal VI2 has a higher voltage value to turn on the driving transistor Tdr, and the second reset signal VI2 resets the potentials of the first node N1 and the second node N2.
Table 2 shows potential changes of the first node N1, the second node N2, the third node N3, and the fourth node N4 in the sub-pixel SP in each operating phase in the corresponding high-frequency driving mode.
As can be seen from table 2, in the plurality of non-emission sub-periods, the potential of the first node N1 is kept equal, the potential of the second node N2 is kept equal, the potential of the third node N3 is kept equal, and the potential of the fourth node N4 is kept equal. In the multiple light-emitting sub-stages, the potential of the first node N1 is kept equal, the potential of the second node N2 is kept equal, the potential of the third node N3 is kept equal, and the potential of the fourth node N4 is kept equal, so that the display luminance of the sub-pixel SP can be kept consistent in each light-emitting sub-stage.
Fig. 7 is a schematic diagram of an actual measurement result of a light-emitting waveform with a luminance of 50nit according to an embodiment of the present invention, where a light-emitting stage includes a plurality of light-emitting sub-stages and a plurality of non-light-emitting sub-stages, so that the display luminance of the sub-pixel SP in each light-emitting sub-stage can be kept consistent, and the flicker problem can be improved.
In the embodiment shown in fig. 6, the write frame WF has a base frequency f3 of 16Hz and the number Ncft of cycles of the emission control signal EM is 4 for the first time period tfr, and thus the emission control signal EM has an intermediate frequency f2 of 64Hz. Here, the number Ncft of the cycle of the light emission control signal EM may be determined by the sum of the number of light emission sub-stages and the number of non-light emission sub-stages included in the write frame WF. Namely, the stages of the write frame WF corresponding to the initialization stage P1, the data write stage P2 and the node reset stage P3 also belong to a non-light-emitting sub-stage, and the sum of the non-light-emitting sub-stage and the light-emitting sub-stage comprised by the stages of the initialization stage P1, the data write stage P2 and the node reset stage P3 is equal to 2 times of the cycle number Ncft of the light-emitting control signal EM; that is, each period T of the emission control signal EM actually corresponds to one non-emission sub-phase and one emission sub-phase.
Alternatively, the number of cycles Ncft of the emission control signal EM is an integer to keep the number of emission sub-stages and non-emission sub-stages included in each frame equal when the subsequent frame skipping is performed to realize the ultra low frequency display mode.
In order to realize the display function in the ultra low frequency driving mode, the light emitting stage also has a plurality of light emitting sub-stages and a plurality of non-light emitting sub-stages within the hold frame HF. Optionally, the number of light-emitting sub-phases included in each hold frame HF is equal to the number of light-emitting sub-phases included in the write frame WF, and the number of non-light-emitting sub-phases included in each hold frame HF is equal to the number of non-light-emitting sub-phases included in the write frame WF, so that the write frame WF and each hold frame HF have the first time duration tfr.
On the basis that the duration of each frame can be increased, the frame skipping times corresponding to one display period when the ultra-low frequency driving mode is adopted are explained. FIG. 8 is a timing diagram of a display period corresponding to the ultra low frequency driving mode according to an embodiment of the present invention; within a total time length tsu corresponding to a display period, the target frequency f1 of the second scanning signal Pscan2 is 0.016Hz; the number of frame skipping operations corresponding to one display period in the ultra low frequency driving mode will be described with reference to the sub-pixels shown in fig. 3, in which the base frequency f3 of the second scanning signal Pscan2 is 16Hz for the first time period tfr corresponding to the write frame WF.
Within each hold frame HF, the sub-pixels SP are switched between a non-display state and a display state under the control of the emission control signal EM. A total number of frames m =16/0.016=1000 (i.e., the sum of the number of write frames WF and the number of holding frames HF included in one display cycle is equal to 16/0.016= 1000), i.e., one display cycle includes one write frame WF (i.e., corresponding to 1 in fig. 8) st 16 Hz) and 999 hold frames HF (i.e., corresponding to 2 in fig. 8) nd ～999 th 16Hz and 1000 Hz th 16 Hz). And the number of frame skipping SKF is equal to the number of a plurality of hold frames HF included in one display period, i.e., the number of frame skipping SKF is equal to 999.
Alternatively, the number of times of frame skipping SKF is an integer, so that the number of write frames WF and hold frames HF included in each display period is an integer. Optionally, the number of frame skipping SKF is smaller than the upper frame skipping limit SKL, so that the display device can achieve the target frequency to be achieved.
The writing frame WF and the holding frames HF are included in one display period, so that the display panel can display the same display content in the total time length tsu corresponding to the display period, and because the sub-pixels SP are switched between the display state and the non-display state for a plurality of times in the first time length tfr corresponding to the writing frame WF and each holding frame HF, human eyes can not perceive the flicker problem of the display panel in the total time length tsu corresponding to the display period.
It is understood that, in addition to the display with the target frequency f1 of 0.016Hz, more corresponding ultra-low frequency displays can be obtained according to the relationship among the target frequency f1, the intermediate frequency f2, the fundamental frequency f3, the number of cycles Ncft of the emission control signal EM, the total number of frames m, the first time period tfr, and the total time period tsu. Only a partial example when the corresponding skip upper limit SKL is equal to 2^10=1024 is shown in table 3, and is not used to limit the present application.
As can be seen from table 3, there may be a plurality of fundamental frequencies f3 for achieving the target frequency f1, and there may also be a plurality of intermediate frequencies f2 for achieving the target frequency f1. The plurality of fundamental frequencies f3 has a maximum fundamental frequency fmax and the plurality of intermediate frequencies f2 has a minimum intermediate frequency fmin. Wherein, in a writing frame WF included in a display period and a first time length tfr corresponding to each holding frame HF, the period number Ncft of the light-emitting control signal EM is larger than or equal to the ratio of the minimum intermediate frequency to the maximum basic frequency; that is, ncft.gtoreq.fmin/fmax.
The maximum fundamental frequency fmax can be determined from the skip frame upper limit SKL and the target frequency f1. If the difference is made between the ratio of the plurality of fundamental frequencies f3 and the target frequency f1 and the skip frame upper limit SKL, a plurality of first difference values are obtained, and the fundamental frequency f3 corresponding to the minimum difference value in the plurality of first difference values is the maximum fundamental frequency fmax. And the ratio of the plurality of basic frequencies f3 to the target frequency f1 is smaller than the skip frame upper limit SKL.
The minimum intermediate frequency fmin may be determined from the product of the critical flicker frequency CFF and the number of cycles Ncft. If the difference between the intermediate frequencies f2 and the critical flicker frequency CFF is respectively used, a plurality of second difference values are obtained, and the intermediate frequency f2 corresponding to the minimum difference value in the plurality of second difference values is the minimum intermediate frequency fmin. Wherein, the plurality of intermediate frequencies f2 are all larger than the critical flicker frequency CFF.
That is, if the skip frame upper limit SKL is equal to 2^10=1024, the target frequency f1 is 0.016Hz, the minimum intermediate frequency fmin is 64Hz, and the maximum base frequency fmax is 16Hz, then the light-emission control signal EM has the number of cycles Ncft greater than or equal to 4 within the first time period tfr corresponding to the write frame WF and each hold frame HF included in one display period.
It can be understood that, in the ultra low frequency driving display mode, the time sequence corresponding to the write frame WF and the time sequence corresponding to a display period are different from those in fig. 6 and 8 according to the difference of the target frequency f1 to be achieved, and those skilled in the art can obtain the write frame WF time sequence and the time sequence corresponding to the target frequency f1 to be achieved according to the present application, which will not be described again for the sake of brevity in the present application.
Table 4 shows the results of the flicker test, wherein the base frequency f3 was 16Hz, the intermediate frequency f2 was 64Hz, and the target frequency f1 was 0.016Hz.
As can be seen from table 4, when the display panel realizes display in the ultra low frequency driving mode with the target frequency f1 of 0.016Hz, the flicker degree of the display panel is still smaller than the specification value, so that the display panel can not sense the flicker problem when realizing ultra low frequency display, and the display panel has better display performance.
Fig. 9 is a schematic diagram of a power consumption test result provided in the embodiment of the present invention. Wherein 25% OPR means that the screen has 25% of the display area emitting light, and 10% OPR means that the screen has 25% of the display area emitting light. As can be seen from FIG. 9, the display in the ultra low frequency driving mode according to the present invention reduces the power consumption by 14.1% when accounting for 25% OPR and by 18.4% when accounting for 10% OPR, compared with the display in the conventional low frequency driving mode. Therefore, the purpose of reducing power consumption can be achieved, and the display device can have better cruising ability.
It is understood that the display device includes a movable display device (such as a notebook computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a temperature measuring instrument, etc.), and the like.
The principle and the embodiment of the present invention are explained by applying specific examples, and the above description of the embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (11)
1. A display device, comprising:
a display panel including a plurality of sub-pixels;
a gate driver including a first gate driving unit configured to output a first scan signal to the sub-pixel and a second gate driving unit configured to output a second scan signal to the sub-pixel; and (c) a second step of,
an emission driver configured to output a light emission control signal to the sub-pixels;
the display panel is provided with a plurality of display periods, at least one display period comprises a writing frame and a plurality of holding frames, and each of the writing frame and the holding frames has a first duration; within each of the write frame and the plurality of hold frames, the light emission control signal has a plurality of periods, and a ratio of the number of periods of the light emission control signal to the first time period is greater than a critical flicker frequency;
the light emission control signal has an active pulse and an inactive pulse in each of the periods, the first scan signal has an active pulse in an active time of each of the inactive pulses of the light emission control signal in the write frame and the plurality of the hold frames, and the second scan signal has an active pulse in an active time of the inactive pulse in a first one of the periods of the light emission control signal in the write frame.
2. The display device according to claim 1, wherein the second scanning signal has a target frequency of less than 1Hz in a total duration corresponding to the write frame and the plurality of hold frames.
3. The display device according to claim 2, wherein the second scan signal has a base frequency multiplied by the number of cycles of the light emission control signal equal to an intermediate frequency of the light emission control signal in the write frame.
4. The display device according to claim 3, wherein a ratio of the base frequency to the target frequency is equal to a sum of the number of the write frames and the plurality of the hold frames.
5. The display device according to claim 3, wherein the base frequency is 16Hz, the intermediate frequency is 64Hz, and the target frequency is 0.016Hz.
6. The display device according to claim 1, wherein each of the sub-pixels comprises:
a light emitting device;
a driving transistor configured to generate a driving current according to a data signal to drive the light emitting device to emit light;
a first reset transistor configured to reset an anode potential of the light emitting device according to the first scan signal,
a second reset transistor configured to reset an input electrode potential and an output electrode potential of the driving transistor according to the first scan signal;
a data transistor configured to transmit the data signal to the driving transistor through a first node according to the second scan signal;
and the light-emitting control transistor is configured to control the on-off of the circulation path of the driving current according to the light-emitting control signal.
7. The display device according to claim 6,
the driving transistor includes the input electrode connected to the first node, the output electrode connected to a second node, and a control electrode connected to a third node;
the data transistor includes a control electrode configured to receive the second scan signal, an input electrode configured to receive the data signal, and an output electrode connected to the first node;
the light emission control transistor includes a first switching transistor and a second switching transistor; the first switching transistor includes a control electrode configured to receive the light emission control signal, an input electrode configured to be connected to a first power supply terminal, and an output electrode connected to the first node; the second switching transistor includes a control electrode configured to receive the light emission control signal, an input electrode configured to be connected to the second node, and an output electrode connected to a fourth node;
the first reset transistor includes a control electrode configured to receive the first scan signal, an input electrode configured to receive a first reset signal, and an output electrode connected to the fourth node;
the second reset transistor includes a control electrode configured to receive the first scan signal, an input electrode configured to receive a second reset signal, and an output electrode connected to the first node; and
the light emitting device includes an anode connected to the fourth node and a cathode configured to be connected to a second power supply terminal;
in the action time of the plurality of ineffective pulses of the light-emitting control signal, the potential of the first node is kept equal, the potential of the second node is kept equal, the potential of the third node is kept equal, and the potential of the fourth node is kept equal.
8. The display device according to claim 7, wherein the driving transistor is a P-type transistor, and a difference between a potential of the third node and the second reset signal is smaller than a threshold voltage of the driving transistor during an active time of each of the active pulses of the first scan signal.
9. The display device according to claim 7,
the gate driver further includes a third gate driving unit configured to output a third scan signal and a fourth scan signal to the sub-pixels;
the sub-pixel also comprises a compensation transistor, a third reset transistor and a storage capacitor;
the compensation transistor includes a control electrode configured to receive the third scan signal, an input electrode configured to be connected to the third node, and an output electrode connected to the second node;
the third reset transistor includes a control electrode configured to receive the fourth scan signal, an input electrode configured to receive a third reset signal, and an output electrode connected to the third node;
the storage capacitor includes a first electrode configured to be connected to the first power supply terminal and a second electrode connected to the third node;
wherein the third scanning signal and the fourth scanning signal each have an active pulse during an active time of the inactive pulse in the first period of the light emission control signal in the write frame.
10. The display device according to claim 1, wherein a plurality of the sub-pixels form a plurality of pixel units arranged in an array, each of the pixel units comprising three of the sub-pixels; the display device further comprises a drive controller configured to generate control signals to control the gate driver and the emission driver to enable control of display states of a plurality of the pixel units;
wherein the ratio of the first time length to the time length required by the driving controller to control one pixel unit to realize display is greater than the number of the pixel units of the display device.
11. A display device as claimed in claim 10, characterized in that the ratio is equal to N H-line And N V-porch The product of (a);
wherein N is H-line Greater than the number of columns, N, of the pixel cells V-porch Greater than the number of rows of the pixel cells.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211280723.2A CN115662328A (en) | 2022-10-19 | 2022-10-19 | Display device |
| PCT/CN2023/103980 WO2024082703A1 (en) | 2022-10-19 | 2023-06-29 | Display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211280723.2A CN115662328A (en) | 2022-10-19 | 2022-10-19 | Display device |
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| Publication Number | Publication Date |
|---|---|
| CN115662328A true CN115662328A (en) | 2023-01-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211280723.2A Pending CN115662328A (en) | 2022-10-19 | 2022-10-19 | Display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115662328A (en) |
| WO (1) | WO2024082703A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024082703A1 (en) * | 2022-10-19 | 2024-04-25 | 武汉华星光电半导体显示技术有限公司 | Display apparatus |
| WO2024156246A1 (en) * | 2023-01-29 | 2024-08-02 | 京东方科技集团股份有限公司 | Pixel driving circuit and control method therefor and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10902793B2 (en) * | 2018-09-12 | 2021-01-26 | Lg Display Co., Ltd. | Gate driver circuit outputting a plurality of emission signals having different delay times or pulse widths or combinations thereof |
| CN111968574B (en) * | 2020-09-03 | 2022-04-12 | 上海天马微电子有限公司 | Display device and driving method |
| US20240105119A1 (en) * | 2021-04-23 | 2024-03-28 | Boe Technology Group Co., Ltd. | Pixel Circuit, Driving Method Therefor, and Display Apparatus |
| CN115662328A (en) * | 2022-10-19 | 2023-01-31 | 武汉华星光电半导体显示技术有限公司 | Display device |
-
2022
- 2022-10-19 CN CN202211280723.2A patent/CN115662328A/en active Pending
-
2023
- 2023-06-29 WO PCT/CN2023/103980 patent/WO2024082703A1/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024082703A1 (en) * | 2022-10-19 | 2024-04-25 | 武汉华星光电半导体显示技术有限公司 | Display apparatus |
| WO2024156246A1 (en) * | 2023-01-29 | 2024-08-02 | 京东方科技集团股份有限公司 | Pixel driving circuit and control method therefor and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024082703A1 (en) | 2024-04-25 |
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