CN111415612B - Scanning circuit of display panel, display panel and display device - Google Patents
Scanning circuit of display panel, display panel and display device Download PDFInfo
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- CN111415612B CN111415612B CN202010246731.XA CN202010246731A CN111415612B CN 111415612 B CN111415612 B CN 111415612B CN 202010246731 A CN202010246731 A CN 202010246731A CN 111415612 B CN111415612 B CN 111415612B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention discloses a scanning circuit of a display panel, the display panel and a display device. The scanning circuit includes: the first scanning module is used for sequentially outputting first scanning signals to pixel circuits of each row, and the pixel circuits are initialized within the pulse duration of the first scanning signals; the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits write data in the pulse duration of the second scanning signals; the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal. The embodiment of the invention can shorten the light-emitting period of the display panel during light-emitting, thereby improving the refresh rate.
Description
Technical Field
Embodiments of the present invention relate to display technologies, and in particular, to a scanning circuit of a display panel, a display panel and a display device.
Background
With the development of display technology, the application of display panels is becoming more and more extensive, and the requirements for display panels are also becoming higher and higher accordingly.
However, in the conventional display panel, the light emitting period of the light emitting signal per frame is long during display, and it is difficult to realize a high refresh frequency.
Disclosure of Invention
The embodiment of the invention provides a scanning circuit of a display panel, the display panel and a display device, which are used for shortening the light emitting period of each frame of light emitting signals and further improving the refreshing frequency.
In a first aspect, an embodiment of the present invention provides a scanning circuit of a display panel, where the display panel includes a plurality of rows of pixel circuits, and the scanning circuit includes: the first scanning module is used for sequentially outputting first scanning signals to pixel circuits of each row, and the pixel circuits are initialized within the pulse duration of the first scanning signals; the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits carry out data writing in the pulse duration of the second scanning signals; the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal.
Optionally, the pulse duration of the first scan signal provided to the same row of pixel circuits is greater than the pulse duration of the second scan signal, and the pulse duration of the first scan signal does not at least partially overlap with the pulse duration of the second scan signal.
Optionally, the first scanning module includes a plurality of cascaded first shift registers, and an output terminal of each first shift register is used to be electrically connected to a corresponding first scanning signal input terminal of the pixel circuit; the second scanning module comprises a plurality of cascaded second shift registers, and the output ends of the second shift registers are used for being electrically connected with the second scanning signal input ends of the corresponding pixel circuits.
Optionally, the pulse duration of the first scan signal supplied to the same row of pixel circuits at least partially overlaps with the pulse duration of the second scan signal.
Optionally, a time of an overlapping portion of the first scanning signal pulse duration and the second scanning signal pulse duration is less than or equal to one third of the second scanning signal pulse duration.
In a second aspect, embodiments of the present invention further provide a display panel, which includes a plurality of rows of pixel circuits and the scanning circuit as described in the first aspect.
Optionally, the display panel includes a display area and a first non-display area and a second non-display area located on both sides of the display area; the second scanning module comprises a first sub-module located in the first non-display area and a second sub-module located in the second non-display area, and the first sub-module and the second sub-module are used for simultaneously providing a second scanning signal to the corresponding row of pixel circuits.
Optionally, the first scanning module is located in the first non-display area or the second non-display area.
Optionally, the display panel further includes an enable circuit, the enable circuit is configured to sequentially provide an enable signal to each row of pixel circuits, and the enable circuit and the first scanning module are respectively located in non-display areas on two sides of the display area.
In a third aspect, an embodiment of the present invention further provides a display device, including the display panel according to the second aspect.
In the technical scheme of this embodiment, the adopted scanning circuit includes a first scanning module, the first scanning module is configured to sequentially output first scanning signals to pixel circuits in each row, and the pixel circuits are initialized within a pulse duration of the first scanning signals; the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits carry out data writing in the pulse duration of the second scanning signals; the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal. In this embodiment, the first scan signal and the second scan signal do not need a time Gap and do not interfere with each other, and a time Gap is reduced compared with the conventional light emitting period, so that the light emitting period can be shortened, and the refresh rate can be increased.
Drawings
FIG. 1 is a timing diagram of a conventional pixel circuit;
fig. 2 is a schematic circuit diagram of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a pixel circuit according to an embodiment of the invention;
FIG. 4 is a timing diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a pixel circuit according to another embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of another display panel according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings, not all of them.
As mentioned in the background art, the problem of long signal time per frame of the display panel in the prior art is that the applicant has found through careful study that the reason for this technical problem is: for a conventional display panel, such as an OLED (Organic Light-Emitting Diode) display panel, it is necessary to drive a corresponding Light-Emitting structure to emit Light through a pixel circuit, fig. 1 is a timing diagram of a conventional pixel circuit, referring to fig. 1, the driving of the pixel circuit includes an initialization stage t1 ', a data writing stage t2 ', and a Light-Emitting stage, and in the initialization stage t1 ', under the action of a first SCAN signal SCAN1 ' and a third SCAN signal SCAN3 ', an initialization signal initializes an anode of the Light-Emitting structure and a gate of a driving transistor; in the data writing phase t2 ', under the action of the second SCAN signal SCAN2 ', the data signal Vdata ' is written into the storage capacitor; in the light-emitting stage, the enabling signal EM' drives the corresponding transistor to be turned on, and the driving transistor generates current driving current to drive the light-emitting structure to emit light; the driving of the pixel circuit requires the provision of timing pulses by the scanning circuit to turn on different transistors at different stages; however, in the conventional SCAN circuit, a SCAN module is used in the initialization phase and the data writing phase, a certain time Gap needs to exist between the initialization phase t1 'and the data writing phase t 2' to avoid crosstalk between the first SCAN signal SCAN1 'and the third SCAN signal SCAN 3' in the initialization phase and the second SCAN signal SCAN2 'in the data writing phase, and due to the existence of the time Gap, the light emitting period H' of the light emitting signal of one frame is long, and it is difficult to achieve a high refresh rate.
Based on the technical problem, the invention provides the following solution:
fig. 2 is a schematic circuit diagram of a display panel according to an embodiment of the present invention, and referring to fig. 2, the display panel includes a plurality of rows of pixel circuits 10, and a scan circuit 11 of the display panel according to the embodiment of the present invention includes: the first scanning module 110, the first scanning module 110 is configured to sequentially output first scanning signals to each row of the pixel circuits 10, and the pixel circuits 10 are initialized within a first scanning signal pulse duration; a second scanning module 111, where the second scanning module 111 is configured to sequentially output second scanning signals to the pixel circuits 10 in each row, and the pixel circuits 10 perform data writing within a second scanning signal pulse duration; the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal. Specifically, the display panel may be an OLED display panel, and includes a plurality of rows of pixel circuits 10, where the scan circuit provides scan signals to each row of pixel circuits of the display panel line by line, for example, in a first light emitting period, a first scan module 110 in the scan circuit provides a first scan signal to a first row of pixel circuits to enable the row of pixel circuits to enter an initialization stage, and after a period of time from the initialization stage, a second scan module 111 provides a second scan signal to the pixel circuits to enable the row of pixel circuits to enter a data writing stage. The pulse ending time of the first scanning signal is not earlier than the pulse starting time of the second scanning signal, which means that the second scanning signal pulse starts when the first scanning signal pulse ends; or the second scanning signal pulse starts before the first scanning signal pulse ends. That is, the first scan signal and the second scan signal do not need a time Gap and do not interfere with each other, and compared with the conventional light emitting period, the light emitting period is reduced by one time Gap, so that the light emitting period can be shortened, and the refresh rate can be improved.
In the technical scheme of this embodiment, the adopted scanning circuit includes a first scanning module, the first scanning module is configured to sequentially output first scanning signals to pixel circuits in each row, and the pixel circuits are initialized within a pulse duration of the first scanning signals; the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits carry out data writing in the pulse duration of the second scanning signals; the end time of the pulse of the first scanning signal provided to the pixel circuits of the same row is not earlier than the start time of the pulse of the second scanning signal. In this embodiment, the first scan signal and the second scan signal do not need a time Gap and do not interfere with each other, and compared with the existing light emitting period, the light emitting period is reduced by one time Gap, so that the light emitting period can be shortened, and the refresh rate can be improved.
Optionally, the pulse duration of the first scan signal provided to the pixel circuits of the same row is longer than the pulse duration of the second scan signal, and the pulse duration of the first scan signal does not at least partially overlap with the pulse duration of the second scan signal.
Specifically, in this embodiment, since the second scan signal of a certain row of pixel circuits is output by the second scan module, the first scan signal is output by the first scan module, and the first scan signal is not obtained by multiplexing the second scan signal of the previous row of pixel circuits, the pulse duration of the first scan signal provided to the same row of pixel circuits can be longer than that of the second scan signal, and thus the time of the initialization stage of the pixel circuits can be longer, the initialization can be more thorough, and the afterimage phenomenon can be improved; and because the pulse duration of the first scanning signal and the pulse duration of the second scanning signal are at least partially non-overlapped, the luminous data can be ensured to be written into the pixel circuit. Under the condition of high frequency, even if the light emitting period (line period) corresponding to each line of pixel circuits is shortened, the pulse duration of the second scanning signal is also shortened, but because the first scanning signal is output by the first scanning module and the second scanning signal is output by the second scanning signal, the pulse duration of the first scanning signal does not affect the pulse duration of the second scanning signal, namely the pulse duration of the first scanning signal is not shortened along with the shortening of the pulse duration of the second scanning signal, and the crosstalk between the first scanning signal and the second scanning signal is not required to be considered, when the pulse duration of the first scanning signal is ensured to be less than the time of one line period, and the pulse duration of the first scanning signal is not at least partially overlapped with the pulse duration of the second scanning signal, the pulse duration of the first scanning signal can be prolonged as much as possible, therefore, the initialization time of the pixel circuit is longer, the initialization of the light-emitting structure and the grid electrode of the driving transistor in the pixel circuit is more thorough, and the afterimage phenomenon is effectively improved.
It should be noted that, the second scan signal of a certain row of pixel circuits in the existing display panel is obtained by multiplexing the second scan signal of the previous row of pixel circuits, that is, the pulse durations of the existing first scan signal and the second scan signal are the same, and a certain time gap needs to exist between the pulse of the first scan signal and the second scan signal of the same row of pixel circuits, so as to avoid interference caused by signal overlapping; in the embodiment, because the first scanning signal and the second scanning signal are output by different scanning modules of the scanning circuit, no time gap is required between the pulse of the first scanning signal and the pulse of the second scanning signal of the same row of pixel circuits, that is, compared with the existing first scanning signal, the pulse duration of the first scanning signal of the embodiment can be longer, so that the initialization of the pixel circuits is more thorough, and the afterimage phenomenon is improved; in some other embodiments, if the pulse duration of the first scan signal is longer than that of the existing first scan signal, the effect of improving the afterimage can also be achieved if the pulse duration of the second scan signal is longer than that of the first scan signal.
Exemplarily, fig. 3 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present invention, and referring to fig. 3, the pixel circuit 10 includes: a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a fifth transistor P5, and a light emitting unit L; wherein the second transistor P2 is connected between the first electrode L1 of the light emitting cell L and the initialization power Vref, and is turned on in response to the first SCAN signal at the first SCAN signal input terminal SCAN 1; the fourth transistor P4 is connected between the first driving power supply PVDD and the first pole S1 of the first transistor P1, the fifth transistor P5 is connected between the second pole D1 of the first transistor P1 and the light emitting cell L, the second pole L2 of the light emitting cell L is connected to the second driving power supply PVEE, and the fourth transistor P4 and the fifth transistor P5 are turned on in response to an enable signal on the enable signal input terminal EM; the third transistor P3 is connected to the data line Vdata and the first transistor P1, and is turned on in response to the second SCAN signal on the second SCAN signal input terminal SCAN 2; the pixel circuit may further include a storage capacitor Cst connected between the first driving power source PVDD and the gate G1 of the first transistor P1; a sixth transistor P6 connected between the gate G1 of the first transistor P1 and the initialization power Vref and turned on in response to the third SCAN signal on the third SCAN signal input terminal SCAN 3; the seventh transistor P7 is connected between the gate G1 of the first transistor P1 and the second diode D1 of the first transistor P1 and turned on in response to the second SCAN signal on the second SCAN signal line SCAN 2. The first to seventh transistors P1 to P7 may be P-type transistors or N-type transistors, and in some other embodiments, some P-type transistors may be used and the other N-type transistors may be used, and in this embodiment, P-type transistors are used as the first to seventh transistors P1 to P7. The light emitting unit L may be an OLED, which is a current type device capable of emitting light when a current flows therethrough, wherein the first transistor P1 is a driving transistor of the pixel circuit and supplies a driving current to the light emitting unit L. The first driving power supply PVDD may be a positive voltage signal, and the second driving power supply PVEE may be a negative voltage signal. It should be noted that, when the first to seventh transistors P1 to P7 are all P-type transistors, the voltage value of the initialization signal on the initialization power Vref may be smaller than the voltage value of the voltage signal on the second driving power PVEE, so as to ensure that the light emitting unit L does not emit light during the initialization phase, and avoid the light emitting unit L from emitting light by mistake. It should be noted that the first SCAN signal input terminal SCAN1 of the pixel circuit can be reused as the third SCAN signal input terminal SCAN3, that is, the first SCAN signal input terminal SCAN1 and the third SCAN signal input terminal SCAN3 are both electrically connected to the corresponding first SCAN module, the initialization process of the light emitting unit is performed simultaneously with the initialization process of the driving transistor, and the second SCAN signal input terminal is electrically connected to the corresponding second SCAN module. Fig. 4 is a timing diagram of a pixel circuit according to an embodiment of the invention, which may correspond to the pixel circuit in fig. 3, and fig. 5 is a timing diagram of another pixel circuit according to an embodiment of the invention, which may correspond to the pixel circuit in fig. 3, in combination with fig. 2 to 5, each row of the pixel circuits sequentially corresponds to one row period H, and in an initialization phase t1, the first SCAN signal input terminal SCAN1 and the third SCAN signal input terminal SCAN3 are connected to the first SCAN signal output by the first SCAN module, so that the second transistor P2 and the sixth transistor P6 are turned on to initialize the anode of the light emitting unit and the gate of the driving transistor; in the data writing phase t2, the third transistor P3 and the seventh transistor P7 are turned on, and the data signal is written into the storage capacitor Cst through the first transistor P1 (driving transistor), so as to complete the data writing process, which can be understood as having the threshold compensation effect; in the subsequent light emitting stage, the fourth transistor P4 and the fifth transistor P5 are turned on, and the driving transistor drives the light emitting unit to emit light. It should be noted that the pulse termination time tA of the first scan signal in fig. 4 is equal to the pulse start time tB of the second scan signal; the pulse termination time tA of the first scan signal in fig. 5 is later than the pulse start time tB of the second scan signal; in both modes, the time gap in the existing driving mode does not exist, so that the light-emitting period can be shortened, and the refresh rate can be improved.
Optionally, with continued reference to fig. 2, the first scanning module includes a plurality of cascaded first shift registers 1011, and output terminals of the first shift registers 1011 are configured to be electrically connected to first scanning signal input terminals of corresponding pixel circuits; the second scanning module comprises a plurality of cascaded second shift registers 1111, and an output terminal of the second shift register 1111 is used for being electrically connected with a second scanning signal input terminal of a corresponding pixel circuit.
Specifically, the plurality of cascaded first shift registers 1101 may shift the first scan signal one by one to be respectively output to the pixel circuits of different rows; the plurality of cascaded second shift registers 1111 may shift the second scan signal one by one to output to the pixel circuits of different rows, respectively. Exemplarily, fig. 6 is a schematic circuit structure diagram of a shift register according to an embodiment of the present invention, and referring to fig. 6, the shift register is composed of a transistor and a storage capacitor, which are connected to have the structure shown in fig. 6, and under the action of a clock signal Input from a first clock signal Input terminal CK1, a clock signal Input from a second clock signal Input terminal CK2, a first level VGH, and a second level VGL, an Output of an Output is shifted compared to a signal Input from an Input of an Input. In this embodiment, the load of the second scanning module is small, which can solve the problem of the display panel being dark and bright, and further improve the display effect.
Alternatively, referring to fig. 5, the pulse duration of the first scan signal supplied to the pixel circuits of the same row at least partially overlaps with the pulse duration of the second scan signal.
Specifically, the overlapping portion of the pulse duration of the first scan signal and the pulse duration of the second scan signal is sub-phase t3, and in this phase, there exists both the initialization process of the pixel circuit and the data writing process of the pixel circuit, so that the pulse duration of the first scan signal can be further increased to further prolong the initialization time and further improve the afterimage phenomenon of the display panel.
Alternatively, with continued reference to fig. 5, the time of the portion of the first scan signal pulse duration that overlaps the second scan signal pulse duration is less than or equal to one third of the second scan signal pulse duration.
If the duration of the sub-phase t3 is less than or equal to one third of the duration of the data writing phase t2, if the duration of the sub-phase t3 is too long, the time of the part of the data writing phase t2 which is not overlapped with the initialization phase t1 is less, and data writing may be insufficient; the duration of the sub-phase t3 is less than or equal to one third of the duration of the data writing phase t2, so that the data can be written sufficiently, and the occurrence of display errors can be avoided.
Optionally, the duration of the first scanning signal pulse is equal to or greater than twice the duration of the second scanning signal pulse. If the duration of the first scanning signal pulse is too short, the initialization process of the corresponding pixel circuit is too short, and the initialization process may not be effectively completed; the present embodiment is configured in this way, so that it can further ensure that the initialization time is longer, the initialization of the pixel circuit is more thorough, and the ghost image improvement effect is more obvious.
Embodiments of the present invention further provide a display panel including a plurality of rows of pixel circuits and a scan circuit as provided in any of the embodiments of the present invention.
Specifically, the scan circuit can provide the first scan signal and the second scan signal for the pixel circuit, and the display panel provided by the embodiment of the present invention includes the scan circuit provided by any embodiment of the present invention, so that the same advantageous effects are also provided, and details are not described herein.
Optionally, fig. 7 is a schematic circuit structure diagram of another display panel according to an embodiment of the present invention, and referring to fig. 7, the display panel includes a display area AA, and a first non-display area NAA1 and a second non-display area NAA2 located at two sides of the display area AA; the second scan module 111 includes a first sub-module 1112 located in the first non-display area NAA1 and a second sub-module 1113 located in the second non-display area NAA2, the first sub-module 1112 and the second sub-module 1113 being configured to simultaneously provide the second scan signals to the corresponding row of pixel circuits.
Specifically, the first submodule 1112 and the second submodule 1113 may both include cascaded shift registers, and the first submodule 1112 and the second submodule 1113 are symmetrically distributed on two sides of the display area AA, so that the second scanning signal received by the pixel circuit of the display area is more uniform, the display uniformity of the display panel is improved, and the display effect of the display panel is further improved.
Alternatively, the first scan module 110 is located in the first non-display area NAA1 or the second non-display area NAA 2.
Specifically, the first scan module 110 may be disposed only in the first non-display area NAA1 or the second non-display area NAA2, so as to reduce the area of the non-display area, thereby facilitating the display panel to implement a narrow bezel.
Optionally, with continued reference to fig. 7, the display panel further includes an enable circuit 201, which is a circuit for sequentially providing an enable signal to each row of pixel circuits, and is a non-display area where the enable circuit and the first scan module are respectively located at two sides of the display area.
Specifically, as shown in fig. 7, the pixel circuit turns on the driving transistor and the light emitting unit under the action of the enable signal, so that the light emitting unit emits light; the enabling circuit 201 and the first sub-module 1112 may be located in the first non-display area NAA1, and the first scanning module 110 and the second sub-module 1113 may be located in the second non-display area NAA2, so as to set the circuit distribution in the non-display area of the display panel to be uniform, and the width of each non-display area of the display panel to be uniform, thereby facilitating the improvement of the use experience.
Fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention, referring to fig. 6, the display panel 20 is driven and displayed by applying the driving method according to any embodiment of the present invention, and the display panel 20 may be applied to a mobile phone, a computer, a tablet, or a wearable device, and therefore, the driving method according to any embodiment of the present invention is included, so that the same beneficial effects are also obtained, and further description is omitted here.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.
Claims (9)
1. A scan circuit of a display panel including a plurality of rows of pixel circuits, the scan circuit comprising:
the first scanning module is used for sequentially outputting first scanning signals to pixel circuits of each row, and the pixel circuits are initialized within the pulse duration of the first scanning signals;
the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits write data in the pulse duration of the second scanning signals;
the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse starting time of the second scanning signal;
the pulse duration of the first scanning signal provided to the same row of pixel circuits at least partially overlaps with the pulse duration of the second scanning signal.
2. The scan circuit of claim 1,
the pulse duration of the first scanning signal provided to the same row of pixel circuits is larger than that of the second scanning signal, and the pulse duration of the first scanning signal is at least partially non-overlapped with that of the second scanning signal.
3. The scan circuit of claim 1, wherein the first scan module comprises a plurality of cascaded first shift registers, an output terminal of the first shift register being electrically connected to a first scan signal input terminal of the corresponding pixel circuit;
the second scanning module comprises a plurality of cascaded second shift registers, and the output ends of the second shift registers are used for being electrically connected with the second scanning signal input ends of the corresponding pixel circuits.
4. The scan circuit of claim 1, wherein the time of the portion of the first scan signal pulse duration that overlaps the second scan signal pulse duration is less than or equal to one third of the second scan signal pulse duration.
5. A display panel comprising a plurality of rows of pixel circuits and the scanning circuit of any one of claims 1-4.
6. The display panel according to claim 5, wherein the display panel comprises a display area and a first non-display area and a second non-display area located on both sides of the display area;
the second scanning module comprises a first sub-module located in the first non-display area and a second sub-module located in the second non-display area, and the first sub-module and the second sub-module are used for simultaneously providing second scanning signals for corresponding row pixel circuits.
7. The display panel according to claim 6, wherein the first scanning module is located in the first non-display area or the second non-display area.
8. The display panel according to claim 7, further comprising an enable circuit, wherein the enable circuit is configured to sequentially provide an enable signal to each row of pixel circuits, and the enable circuit and the first scan module are respectively located in non-display areas on two sides of the display area.
9. A display device characterized by comprising the display panel according to any one of claims 5 to 8.
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| CN202010246731.XA CN111415612B (en) | 2020-03-31 | 2020-03-31 | Scanning circuit of display panel, display panel and display device |
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| CN202010246731.XA CN111415612B (en) | 2020-03-31 | 2020-03-31 | Scanning circuit of display panel, display panel and display device |
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| CN113971936B (en) * | 2020-07-23 | 2023-09-29 | 京东方科技集团股份有限公司 | Display panel and driving method thereof |
| CN112735314B (en) * | 2020-12-30 | 2023-01-13 | 合肥维信诺科技有限公司 | Pixel circuit, driving method thereof, display panel and display device |
| CN113892132B (en) * | 2021-06-23 | 2022-08-09 | 京东方科技集团股份有限公司 | Pixel circuit, driving method and display device |
| CN113870771B (en) * | 2021-09-30 | 2023-01-17 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114822404B (en) * | 2022-05-13 | 2023-05-12 | 北京奕斯伟计算技术股份有限公司 | Pixel circuit, time sequence control method, time sequence controller and display device |
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