CN111415612A - Scanning circuit of display panel, display panel and display device - Google Patents
Scanning circuit of display panel, display panel and display device Download PDFInfo
- Publication number
- CN111415612A CN111415612A CN202010246731.XA CN202010246731A CN111415612A CN 111415612 A CN111415612 A CN 111415612A CN 202010246731 A CN202010246731 A CN 202010246731A CN 111415612 A CN111415612 A CN 111415612A
- Authority
- CN
- China
- Prior art keywords
- scanning
- pixel circuits
- scan
- signal
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
Abstract
The embodiment of the invention discloses a scanning circuit of a display panel, the display panel and a display device. The scanning circuit includes: the first scanning module is used for sequentially outputting first scanning signals to pixel circuits of each row, and the pixel circuits are initialized within the pulse duration of the first scanning signals; the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits carry out data writing in the pulse duration of the second scanning signals; the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal. The embodiment of the invention can shorten the light-emitting period of the display panel during light-emitting, thereby improving the refresh rate.
Description
Technical Field
Embodiments of the present invention relate to display technologies, and in particular, to a scanning circuit of a display panel, a display panel and a display device.
Background
With the development of display technology, the application of display panels is becoming more and more extensive, and the requirements for display panels are becoming higher and higher accordingly.
However, in the conventional display panel, the light emitting period of the light emitting signal per frame is long when displaying, and it is difficult to realize a high refresh frequency.
Disclosure of Invention
The embodiment of the invention provides a scanning circuit of a display panel, the display panel and a display device, which are used for shortening the light emitting period of each frame of light emitting signals and further improving the refreshing frequency.
In a first aspect, an embodiment of the present invention provides a scanning circuit of a display panel, where the display panel includes a plurality of rows of pixel circuits, and the scanning circuit includes: the first scanning module is used for sequentially outputting first scanning signals to pixel circuits of each row, and the pixel circuits are initialized within the pulse duration of the first scanning signals; the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits carry out data writing in the pulse duration of the second scanning signals; the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal.
Optionally, the pulse duration of the first scan signal provided to the same row of pixel circuits is greater than the pulse duration of the second scan signal, and the pulse duration of the first scan signal does not at least partially overlap with the pulse duration of the second scan signal.
Optionally, the first scanning module includes a plurality of cascaded first shift registers, and an output terminal of each first shift register is used to be electrically connected to a corresponding first scanning signal input terminal of the pixel circuit; the second scanning module comprises a plurality of cascaded second shift registers, and the output ends of the second shift registers are used for being electrically connected with the second scanning signal input ends of the corresponding pixel circuits.
Optionally, the pulse duration of the first scan signal supplied to the same row of pixel circuits at least partially overlaps with the pulse duration of the second scan signal.
Optionally, a time of an overlapping portion of the first scanning signal pulse duration and the second scanning signal pulse duration is less than or equal to one third of the second scanning signal pulse duration.
In a second aspect, embodiments of the present invention further provide a display panel, which includes a plurality of rows of pixel circuits and the scanning circuit as described in the first aspect.
Optionally, the display panel includes a display area and a first non-display area and a second non-display area located on both sides of the display area; the second scanning module comprises a first sub-module located in the first non-display area and a second sub-module located in the second non-display area, and the first sub-module and the second sub-module are used for simultaneously providing a second scanning signal to the corresponding row of pixel circuits.
Optionally, the first scanning module is located in the first non-display area or the second non-display area.
Optionally, the display panel further includes an enable circuit, the enable circuit is configured to sequentially provide an enable signal to each row of pixel circuits, and the enable circuit and the first scanning module are respectively located in non-display areas on two sides of the display area.
In a third aspect, an embodiment of the present invention further provides a display device, including the display panel according to the second aspect.
In the technical scheme of this embodiment, the adopted scanning circuit includes a first scanning module, the first scanning module is configured to sequentially output first scanning signals to pixel circuits in each row, and the pixel circuits are initialized within a pulse duration of the first scanning signals; the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits carry out data writing in the pulse duration of the second scanning signals; the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal. In this embodiment, the first scan signal and the second scan signal do not need a time Gap and do not interfere with each other, and compared with the existing light emitting period, the light emitting period is reduced by one time Gap, so that the light emitting period can be shortened, and the refresh rate can be improved.
Drawings
FIG. 1 is a timing diagram of a conventional pixel circuit;
fig. 2 is a schematic circuit diagram of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a pixel circuit according to another embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of another display panel according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, the problem of long signal time per frame of display of the prior display panel is discovered by the applicant after careful study, the problem is caused by the fact that for the prior display panel, such as O L ED (Organic light Emitting Diode) display panel, the corresponding light Emitting structure needs to be driven by the pixel circuit to emit light, FIG. 1 is a timing diagram of a prior pixel circuit, referring to FIG. 1, the driving of the pixel circuit includes an initialization phase t1 ', a data writing phase t2 ' and a light Emitting phase, at the initialization phase t1 ', the initialization signal is used to initialize the anode of the light Emitting structure and the gate of the driving transistor under the action of a first SCAN signal SCAN1 ' and a third SCAN signal SCAN3 ', at the data writing phase t2 ', at the action of a second SCAN signal SCAN2 ', the data signal Vdata ' is written into the storage capacitor, at the light Emitting phase, the enabling signal EM ' drives the corresponding transistor, the driving transistor is turned on, the driving transistor generates a driving current, the driving circuit generates a second SCAN signal, the light Emitting signal is used to avoid the light Emitting structure to emit light with a different time from the initialization phase T2 ', the prior pixel circuit, the initialization phase T2 ' and the initialization phase is used to avoid the initialization phase, the initialization phase T2, the initialization phase is used to generate a data signal, the data writing phase T2, the data writing phase is required to be used to drive the light Emitting phase, and the initialization phase, the pixel circuit, the initialization phase, and the initialization phase is different from the initialization phase, the driving phase, and the driving phase, the initialization phase.
Based on the technical problem, the invention provides the following solution:
referring to fig. 2, a circuit structure of a display panel according to an embodiment of the present invention is shown, in which the display panel includes a plurality of rows of pixel circuits 10, a scan circuit 11 of the display panel according to an embodiment of the present invention includes a first scan module 110, the first scan module 110 is configured to sequentially output a first scan signal to each row of pixel circuits 10, the pixel circuits 10 perform initialization within a duration of a pulse of the first scan signal, a second scan module 111, the second scan module 111 is configured to sequentially output a second scan signal to each row of pixel circuits 10, the pixel circuits 10 perform data writing within a duration of a pulse of the second scan signal, an end time of the pulse of the first scan signal provided to the same row of pixel circuits is not earlier than a start time of the pulse of the second scan signal, specifically, the display panel may be an O L display panel, and includes a plurality of pixel circuits 10, the scan circuit provides scan signals to each row of pixel circuits of the display panel, and the scan circuit does not need to provide scan signals to the first row of pixel circuits 110 in the first scan circuit during a first light emitting period, and thus the scan signal is capable of providing a scan signal to the first row of the first scan circuit, and the second scan signal is not needed to reduce a scanning signal output during the second scan period, and a scanning signal is not needed to reduce a scanning signal output during the second scan signal, and a scanning signal input period, so that the second scan signal input to the second scan signal is not needed during the first scan signal, the second scan signal input to the first scan signal input stage, the second scan module.
In the technical scheme of this embodiment, the adopted scanning circuit includes a first scanning module, the first scanning module is configured to sequentially output first scanning signals to pixel circuits in each row, and the pixel circuits are initialized within a pulse duration of the first scanning signals; the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits carry out data writing in the pulse duration of the second scanning signals; the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal. In this embodiment, the first scan signal and the second scan signal do not need a time Gap and do not interfere with each other, and compared with the existing light emitting period, the light emitting period is reduced by one time Gap, so that the light emitting period can be shortened, and the refresh rate can be improved.
Optionally, the pulse duration of the first scan signal provided to the pixel circuits in the same row is longer than the pulse duration of the second scan signal, and the pulse duration of the first scan signal and the pulse duration of the second scan signal are at least partially non-overlapping.
Specifically, in this embodiment, since the second scan signal of a certain row of pixel circuits is output by the second scan module, the first scan signal is output by the first scan module, and the first scan signal is not obtained by multiplexing the second scan signal of the previous row of pixel circuits, the pulse duration of the first scan signal provided to the same row of pixel circuits can be longer than that of the second scan signal, and thus the time of the initialization stage of the pixel circuits can be longer, the initialization can be more thorough, and the afterimage phenomenon can be improved; and because the pulse duration of the first scanning signal and the pulse duration of the second scanning signal are at least partially non-overlapped, the luminous data can be ensured to be written into the pixel circuit. Under the condition of high frequency, even if the light emitting period (line period) corresponding to each line of pixel circuit is shortened, the pulse duration of the second scanning signal is also shortened, but because the first scanning signal is output by the first scanning module and the second scanning signal is output by the second scanning signal, the pulse duration of the first scanning signal does not affect the pulse duration of the second scanning signal, namely the pulse duration of the first scanning signal is not shortened along with the shortening of the pulse duration of the second scanning signal, and the crosstalk between the first scanning signal and the second scanning signal is not required to be considered, the pulse duration of the first scanning signal is ensured to be less than the time of one line period, and the pulse duration of the first scanning signal is at least partially not overlapped with the pulse duration of the second scanning signal, so that the pulse duration of the first scanning signal can be prolonged as much as possible, therefore, the initialization time of the pixel circuit is longer, the initialization of the light-emitting structure and the grid electrode of the driving transistor in the pixel circuit is more thorough, and the afterimage phenomenon is effectively improved.
It should be noted that, the second scan signal of a certain row of pixel circuits in the existing display panel is obtained by multiplexing the second scan signal of the previous row of pixel circuits, that is, the pulse durations of the existing first scan signal and the second scan signal are the same, and a certain time gap needs to exist between the pulse of the first scan signal and the second scan signal of the same row of pixel circuits, so as to avoid the interference caused by signal overlapping; in the embodiment, because the first scanning signal and the second scanning signal are output by different scanning modules of the scanning circuit, no time gap is required between the pulse of the first scanning signal and the pulse of the second scanning signal of the same row of pixel circuits, that is, compared with the existing first scanning signal, the pulse duration of the first scanning signal of the embodiment can be longer, so that the initialization of the pixel circuits is more thorough, and the afterimage phenomenon is improved; in some other embodiments, if the pulse duration of the first scan signal is longer than that of the existing first scan signal, the effect of improving the afterimage can be achieved if the pulse duration of the second scan signal is longer than that of the first scan signal.
In the present embodiment, the pixel circuit 10 includes a first transistor P, a second transistor P, a third transistor P, a fourth transistor P, a fifth transistor P and a light emitting cell, wherein the second transistor P is connected between a first electrode 01 of the light emitting cell and an initialization power supply Vref and is turned on in response to a first SCAN signal at a first SCAN signal input SCAN, the fourth transistor P is connected between the first driving power supply PVDD and a first electrode S of the first transistor P, the fifth transistor P is connected between a second electrode D of the first transistor P and the light emitting cell 1, the second electrode 2 of the light emitting cell is connected to a second driving power supply PVEE, the fourth transistor P and the fifth transistor P are turned on in response to an enable signal at an enable signal input EM, the third transistor P is connected to a data line Vdata line P and the first transistor P, the third transistor P is connected to the data line Vdata line P, the second SCAN signal input is connected to the second SCAN signal P, the pixel circuit can be turned on in response to a second SCAN signal at a second SCAN signal P, the second SCAN signal P is also connected to a second SCAN signal P, the drive transistor P, the drive signal input of the second SCAN signal P can be turned on, the drive circuit, the drive transistor P can be turned on, the drive circuit can be turned on, the pixel circuit can be further included in a pixel circuit according to a third SCAN signal, the pixel circuit can be a pixel circuit according to a pixel initialization process, the pixel initialization signal, the pixel circuit can be performed when the pixel initialization period of the pixel circuit according to the pixel initialization process, the pixel circuit can be performed when the pixel circuit according to the pixel initialization period of the pixel initialization process, the pixel circuit can be performed when the pixel circuit according to the pixel initialization process, the pixel circuit according to the pixel initialization period of the pixel circuit according to the pixel initialization period of the pixel circuit according to the pixel initialization period of the pixel circuit, the pixel circuit can be performed when the pixel circuit, the pixel circuit can be performed when the pixel initialization period of the pixel circuit can be performed when the pixel initialization period of the pixel circuit, the pixel circuit can be performed when the pixel initialization period of the pixel circuit, the pixel circuit can be performed when the pixel initialization period of the pixel can be performed when the pixel circuit can be performed when the pixel circuit, the pixel can be performed when the pixel circuit can be performed when the pixel.
Optionally, with continued reference to fig. 2, the first scanning module includes a plurality of cascaded first shift registers 1011, and output terminals of the first shift registers 1011 are configured to be electrically connected to first scanning signal input terminals of corresponding pixel circuits; the second scanning module comprises a plurality of cascaded second shift registers 1111, and output terminals of the second shift registers 1111 are used for being electrically connected with second scanning signal input terminals of corresponding pixel circuits.
Specifically, the plurality of cascaded first shift registers 1101 can shift the first scan signal one by one to Output the first scan signal to the pixel circuits in different rows, and the plurality of cascaded second shift registers 1111 can shift the second scan signal one by one to Output the second scan signal to the pixel circuits in different rows, fig. 6 is a schematic circuit structure diagram of a shift register according to an embodiment of the present invention, and referring to fig. 6, the shift register is composed of transistors and storage capacitors, and is connected as shown in fig. 6, under the effect of the clock signal Input from the first clock signal Input terminal CK1, the clock signal Input from the second clock signal Input terminal CK2, the first level VGH, and the second level VG L, the Output terminal Output realizes a shift function compared with the signal Input from the Input terminal.
Alternatively, referring to fig. 5, the pulse duration of the first scan signal supplied to the same row of pixel circuits at least partially overlaps with the pulse duration of the second scan signal.
Specifically, the overlapping portion of the pulse duration of the first scan signal and the pulse duration of the second scan signal is sub-phase t3, and in this phase, there exists both the initialization process of the pixel circuit and the data writing process of the pixel circuit, so that the pulse duration of the first scan signal can be further increased to further prolong the initialization time and further improve the afterimage phenomenon of the display panel.
Alternatively, with continued reference to fig. 5, the time of the portion of the first scan signal pulse duration that overlaps the second scan signal pulse duration is less than or equal to one third of the second scan signal pulse duration.
If the duration of the sub-phase t3 is less than or equal to one third of the duration of the data writing phase t2, if the duration of the sub-phase t3 is too long, the time of the part of the data writing phase t2 which is not overlapped with the initialization phase t1 is less, and data writing may be insufficient; the duration time of the sub-phase t3 is less than or equal to one third of the duration time of the data writing phase t2, so that the data writing is ensured to be more sufficient, and the occurrence of display errors is avoided.
Optionally, the duration of the first scanning signal pulse is equal to or greater than twice the duration of the second scanning signal pulse. If the duration of the first scanning signal pulse is too short, the initialization process of the corresponding pixel circuit is too short, and the initialization process may not be effectively completed; the present embodiment is configured in this way, so that it can further ensure that the initialization time is longer, the initialization of the pixel circuit is more thorough, and the ghost image improvement effect is more obvious.
Embodiments of the present invention further provide a display panel including a plurality of rows of pixel circuits and a scan circuit as provided in any of the embodiments of the present invention.
Specifically, the scan circuit can provide the first scan signal and the second scan signal for the pixel circuit, and the display panel provided by the embodiment of the present invention includes the scan circuit provided by any embodiment of the present invention, so that the same advantageous effects are also provided, and details are not described herein.
Alternatively, fig. 7 is a schematic circuit structure diagram of another display panel according to an embodiment of the present invention, and referring to fig. 7, the display panel includes a display area AA, and a first non-display area NAA1 and a second non-display area NAA2 located at two sides of the display area AA; the second scan module 111 includes a first sub-module 1112 located in the first non-display area NAA1 and a second sub-module 1113 located in the second non-display area NAA2, the first sub-module 1112 and the second sub-module 1113 being configured to simultaneously provide the second scan signals to the corresponding row of pixel circuits.
Specifically, the first sub-module 1112 and the second sub-module 1113 may both include cascaded shift registers, and the first sub-module 1112 and the second sub-module 1113 are symmetrically distributed on two sides of the display area AA, so that the second scanning signals received by the pixel circuits in the display area are more uniform, the display uniformity of the display panel is improved, and the display effect of the display panel is further improved.
Alternatively, the first scanning module 110 is located in the first non-display area NAA1 or the second non-display area NAA 2.
Specifically, the first scan module 110 may be disposed only in the first non-display area NAA1 or the second non-display area NAA2, so as to reduce the area of the non-display area, thereby facilitating the display panel to realize a narrow bezel.
Optionally, with continued reference to fig. 7, the display panel further includes an enable circuit 201, which is a circuit for sequentially providing an enable signal to each row of pixel circuits, and is a non-display area where the enable circuit and the first scan module are respectively located at two sides of the display area.
Specifically, as shown in fig. 7, the pixel circuit turns on the driving transistor and the light emitting unit under the action of the enable signal, so that the light emitting unit emits light; the enabling circuit 201 and the first sub-module 1112 may be located in the first non-display area NAA1, and the first scanning module 110 and the second sub-module 1113 may be located in the second non-display area NAA2, so as to set the circuit distribution in the non-display area of the display panel to be uniform, and the width of each non-display area of the display panel to be uniform, thereby facilitating the improvement of the use experience.
Fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention, referring to fig. 6, the display panel 20 is driven and displayed by applying the driving method according to any embodiment of the present invention, and the display panel 20 may be applied to a mobile phone, a computer, a tablet, or a wearable device, and therefore, the driving method according to any embodiment of the present invention is included, so that the same beneficial effects are also obtained, and further description is omitted here.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A scan circuit of a display panel including a plurality of rows of pixel circuits, the scan circuit comprising:
the first scanning module is used for sequentially outputting first scanning signals to pixel circuits of each row, and the pixel circuits are initialized within the pulse duration of the first scanning signals;
the second scanning module is used for sequentially outputting second scanning signals to the pixel circuits of each row, and the pixel circuits carry out data writing in the pulse duration of the second scanning signals;
the pulse termination time of the first scanning signal provided to the pixel circuits of the same row is not earlier than the pulse start time of the second scanning signal.
2. The scan circuit of claim 1,
the pulse duration of the first scanning signal provided to the same row of pixel circuits is larger than that of the second scanning signal, and the pulse duration of the first scanning signal is at least partially non-overlapped with that of the second scanning signal.
3. The scan circuit of claim 1, wherein the first scan module comprises a plurality of cascaded first shift registers, an output terminal of the first shift register being electrically connected to a first scan signal input terminal of the corresponding pixel circuit;
the second scanning module comprises a plurality of cascaded second shift registers, and the output ends of the second shift registers are used for being electrically connected with the second scanning signal input ends of the corresponding pixel circuits.
4. The scan circuit of claim 1, wherein a pulse duration of the first scan signal supplied to the same row of pixel circuits at least partially overlaps with a pulse duration of the second scan signal.
5. The scan circuit of claim 4, wherein the time of the portion of the first scan signal pulse duration that overlaps the second scan signal pulse duration is less than or equal to one third of the second scan signal pulse duration.
6. A display panel comprising a plurality of rows of pixel circuits and a scanning circuit as claimed in any one of claims 1 to 5.
7. The display panel according to claim 6, wherein the display panel comprises a display area and a first non-display area and a second non-display area located on both sides of the display area;
the second scanning module comprises a first sub-module located in the first non-display area and a second sub-module located in the second non-display area, and the first sub-module and the second sub-module are used for simultaneously providing a second scanning signal to the corresponding row of pixel circuits.
8. The display panel according to claim 6, wherein the first scanning module is located in the first non-display area or the second non-display area.
9. The display panel of claim 8, further comprising an enable circuit for sequentially providing an enable signal to each row of pixel circuits, wherein the enable circuit and the first scan module are respectively located in non-display areas on two sides of the display area.
10. A display device characterized by comprising the display panel according to any one of claims 5 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010246731.XA CN111415612B (en) | 2020-03-31 | 2020-03-31 | Scanning circuit of display panel, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010246731.XA CN111415612B (en) | 2020-03-31 | 2020-03-31 | Scanning circuit of display panel, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111415612A true CN111415612A (en) | 2020-07-14 |
| CN111415612B CN111415612B (en) | 2022-09-30 |
Family
ID=71494725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010246731.XA Active CN111415612B (en) | 2020-03-31 | 2020-03-31 | Scanning circuit of display panel, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111415612B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112735314A (en) * | 2020-12-30 | 2021-04-30 | 合肥维信诺科技有限公司 | Pixel circuit, driving method thereof, display panel and display device |
| CN113870771A (en) * | 2021-09-30 | 2021-12-31 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN113892132A (en) * | 2021-06-23 | 2022-01-04 | 京东方科技集团股份有限公司 | Pixel circuit, driving method and display device |
| CN113971936A (en) * | 2020-07-23 | 2022-01-25 | 京东方科技集团股份有限公司 | Display panel and driving method thereof |
| CN114822404A (en) * | 2022-05-13 | 2022-07-29 | 北京奕斯伟计算技术有限公司 | Pixel circuit, time sequence control method, time sequence controller and display device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012189752A (en) * | 2011-03-10 | 2012-10-04 | Japan Display East Co Ltd | Display device |
| CN105609047A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, display panel |
| CN107731150A (en) * | 2017-11-30 | 2018-02-23 | 武汉天马微电子有限公司 | Scanning circuit and its driving method and display panel |
| CN108364611A (en) * | 2018-01-29 | 2018-08-03 | 昆山国显光电有限公司 | Bilateral scanning circuit, bilateral scanning method and display device |
| CN108806578A (en) * | 2018-06-08 | 2018-11-13 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN109461407A (en) * | 2018-12-26 | 2019-03-12 | 上海天马微电子有限公司 | A kind of organic light emitting display panel and organic light-emitting display device |
| CN110033737A (en) * | 2019-05-31 | 2019-07-19 | 上海天马有机发光显示技术有限公司 | A kind of scanning circuit, display panel and display device |
| CN110148384A (en) * | 2019-06-28 | 2019-08-20 | 上海天马有机发光显示技术有限公司 | A kind of driving method of array substrate, display panel and pixel-driving circuit |
| CN110400541A (en) * | 2019-07-31 | 2019-11-01 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN110930944A (en) * | 2019-12-13 | 2020-03-27 | 云谷（固安）科技有限公司 | Display panel driving method and display device |
-
2020
- 2020-03-31 CN CN202010246731.XA patent/CN111415612B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012189752A (en) * | 2011-03-10 | 2012-10-04 | Japan Display East Co Ltd | Display device |
| CN105609047A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, display panel |
| CN107731150A (en) * | 2017-11-30 | 2018-02-23 | 武汉天马微电子有限公司 | Scanning circuit and its driving method and display panel |
| CN108364611A (en) * | 2018-01-29 | 2018-08-03 | 昆山国显光电有限公司 | Bilateral scanning circuit, bilateral scanning method and display device |
| CN108806578A (en) * | 2018-06-08 | 2018-11-13 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN109461407A (en) * | 2018-12-26 | 2019-03-12 | 上海天马微电子有限公司 | A kind of organic light emitting display panel and organic light-emitting display device |
| CN110033737A (en) * | 2019-05-31 | 2019-07-19 | 上海天马有机发光显示技术有限公司 | A kind of scanning circuit, display panel and display device |
| CN110148384A (en) * | 2019-06-28 | 2019-08-20 | 上海天马有机发光显示技术有限公司 | A kind of driving method of array substrate, display panel and pixel-driving circuit |
| CN110400541A (en) * | 2019-07-31 | 2019-11-01 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN110930944A (en) * | 2019-12-13 | 2020-03-27 | 云谷（固安）科技有限公司 | Display panel driving method and display device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113971936A (en) * | 2020-07-23 | 2022-01-25 | 京东方科技集团股份有限公司 | Display panel and driving method thereof |
| CN113971936B (en) * | 2020-07-23 | 2023-09-29 | 京东方科技集团股份有限公司 | Display panel and driving method thereof |
| CN112735314A (en) * | 2020-12-30 | 2021-04-30 | 合肥维信诺科技有限公司 | Pixel circuit, driving method thereof, display panel and display device |
| CN112735314B (en) * | 2020-12-30 | 2023-01-13 | 合肥维信诺科技有限公司 | Pixel circuit, driving method thereof, display panel and display device |
| US11869402B2 (en) | 2020-12-30 | 2024-01-09 | Hefei Visionox Technology Co., Ltd. | Pixel circuit and display panel thereof |
| CN113892132A (en) * | 2021-06-23 | 2022-01-04 | 京东方科技集团股份有限公司 | Pixel circuit, driving method and display device |
| CN113870771A (en) * | 2021-09-30 | 2021-12-31 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114822404A (en) * | 2022-05-13 | 2022-07-29 | 北京奕斯伟计算技术有限公司 | Pixel circuit, time sequence control method, time sequence controller and display device |
| CN114822404B (en) * | 2022-05-13 | 2023-05-12 | 北京奕斯伟计算技术股份有限公司 | Pixel circuit, time sequence control method, time sequence controller and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111415612B (en) | 2022-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111415612B (en) | Scanning circuit of display panel, display panel and display device | |
| US11508298B2 (en) | Display panel and driving method thereof and display device | |
| US11081061B2 (en) | Shift register, gate driving circuit, display device and gate driving method | |
| US10068658B2 (en) | Shift register unit, driving circuit and method, array substrate and display apparatus | |
| US20220284863A1 (en) | Shift register unit, gate driving circuit and control method thereof and display apparatus | |
| US10672343B2 (en) | Signal control apparatus and method, display control apparatus and method, and display apparatus | |
| US20120086682A1 (en) | Driving apparatus and driving method | |
| US20230024029A1 (en) | Display driving module, method for driving the same and display device | |
| CN113436583B (en) | Display panel and driving method thereof | |
| CN112992070B (en) | Pixel circuit, driving method thereof, display panel and display device | |
| CN113012638B (en) | Display panel, driving method thereof and display device | |
| US11749210B2 (en) | Signal control apparatus and method, display control apparatus and method, and display apparatus | |
| CN110930944B (en) | Display panel driving method and display device | |
| CN111179849B (en) | Control unit, control circuit, display device and control method thereof | |
| WO2020238490A1 (en) | Pixel circuit, display panel, display device, and driving method | |
| CN111710285B (en) | Scanning circuit of display panel, driving method of display panel and display device | |
| US20230154384A1 (en) | Display panel and display device | |
| CN110827765A (en) | Display panel, driving method thereof and display device | |
| CN110322827B (en) | Digital driving method of display panel and display panel | |
| US11450257B2 (en) | Gate driving circuit and electroluminescence display apparatus including the same | |
| CN112037718B (en) | Shift register, grid drive circuit and display device | |
| CN115731839A (en) | Display driving circuit and display device | |
| CN111243522A (en) | Display device and driving method thereof | |
| CN109036292B (en) | Display method and display device | |
| CN113348498A (en) | Display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |