CN110930944A - Display panel driving method and display device - Google Patents
Display panel driving method and display device Download PDFInfo
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- CN110930944A CN110930944A CN201911284744.XA CN201911284744A CN110930944A CN 110930944 A CN110930944 A CN 110930944A CN 201911284744 A CN201911284744 A CN 201911284744A CN 110930944 A CN110930944 A CN 110930944A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
The invention discloses a display panel driving method and a display device. The driving method comprises the following steps: in a first initialization stage, a first gate signal is supplied to the first gate line, and the second transistor is turned on; supplying a second gate signal to the second gate line, the fourth transistor and the fifth transistor being turned on; in a data writing phase, a third gating signal is supplied to the third gating line, and the third transistor is turned on; in a light emitting stage, a first turn-off signal is supplied to the first gate line, and the second transistor is turned off; providing a second gating signal to the fourth transistor and the fifth transistor, the fourth transistor and the fifth transistor being conductive. The embodiment of the invention can improve the problem of uneven display of the display panel and improve the display uniformity.
Description
Technical Field
Embodiments of the present invention relate to display technologies, and in particular, to a driving method of a display panel and a display device.
Background
With the development of display technology, the application of display panels is more and more extensive, and the requirements on the display technology are further improved.
However, the conventional display panel, such as an OLED (Organic Light-Emitting Diode) display panel, has a problem of display non-uniformity during the display process, and the display effect is poor.
Disclosure of Invention
The invention provides a driving method of a display panel and a display device, which are used for improving the problem of uneven display of the display panel and improving the display uniformity.
In a first aspect, an embodiment of the present invention provides a driving method for a display panel, where the display panel includes a pixel circuit, and the pixel circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a light emitting unit; wherein the second transistor is connected between the first electrode of the light emitting unit and an initialization power supply, and is turned on in response to a gate signal on the first gate line; the fourth transistor is connected between a first driving power source and the first pole of the first transistor, the fifth transistor is connected between the second pole of the first transistor and the first pole of the light emitting unit, the second pole of the light emitting unit is connected with a second driving power source, and the fourth transistor and the fifth transistor are turned on in response to a gate signal on the second gate line; the third transistor is connected with a data line and the first transistor and is turned on in response to a gating signal on a third gating line; the driving method includes: in a first initialization stage, a first gate signal is supplied to the first gate line, and the second transistor is turned on; supplying a second gate signal to the second gate line, the fourth transistor and the fifth transistor being turned on; in a data writing phase, a third gating signal is supplied to the third gating line, and the third transistor is turned on; in a light emitting stage, a first turn-off signal is supplied to the first gate line, and the second transistor is turned off; providing a second gating signal to the fourth transistor and the fifth transistor, the fourth transistor and the fifth transistor being conductive.
Optionally, the pixel circuit further includes a sixth transistor connected between the gate of the first transistor and the initialization power supply and turned on in response to a gate signal on a fourth gate line. Before the data writing phase, the method further comprises the following steps: and a second initialization stage of supplying a fourth gate signal to the fourth gate line, and the sixth transistor is turned on.
Optionally, the second initialization phase precedes the first initialization phase.
Optionally, the first initialization phase and the second initialization phase are performed simultaneously.
Optionally, the first strobe signal comprises a first strobe pulse, the second strobe signal comprises a second strobe pulse, the third strobe signal comprises a third strobe pulse, and the fourth strobe signal comprises a fourth strobe pulse; the pulse width of the first gate pulse, the pulse width of the third gate pulse and the pulse width of the fourth gate pulse are the same.
Optionally, the first strobe signal comprises a first strobe pulse, the second strobe signal comprises a second strobe pulse, the third strobe signal comprises a third strobe pulse, and the fourth strobe signal comprises a fourth strobe pulse; the first strobe pulse and the second strobe pulse have overlapping rising edges or falling edges.
Optionally, the pulse width of the first gate pulse is wider than the pulse width of the fourth gate pulse.
Optionally, the fourth strobe pulse overlaps with the second strobe pulse.
Optionally, a pulse width of the fourth gate pulse is equal to a pulse width of the third gate pulse.
In a second aspect, an embodiment of the present invention further provides a display device, including: a plurality of pixel circuits in the display region and a scan driver in the non-display region; the pixel circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a light emitting unit; wherein the second transistor is connected between the first electrode of the light emitting unit and an initialization power supply, and is turned on in response to a gate signal on the first gate line; the fourth transistor is connected between a first driving power source and the first pole of the first transistor, the fifth transistor is connected between the second pole of the first transistor and the first pole of the light emitting unit, the second pole of the light emitting unit is connected with a second driving power source, and the fourth transistor and the fifth transistor are turned on in response to a gate signal on the second gate line; the third transistor is connected with a data line and the first transistor and is turned on in response to a gating signal on a third gating line; the scan driver is to: in a first initialization stage, a first gate signal is supplied to the first gate line, and the second transistor is turned on; supplying a second gate signal to the second gate line, the fourth transistor and the fifth transistor being turned on; in a data writing phase, a third gating signal is supplied to the third gating line, and the third transistor is turned on; in a light emitting stage, a first turn-off signal is supplied to the first gate line, and the second transistor is turned off; providing a second gating signal to the fourth transistor and the fifth transistor, the fourth transistor and the fifth transistor being conductive.
The invention provides a driving method of a display panel, which comprises the steps that in a first initialization stage, a first gating signal is supplied to a first gating line, and a second transistor is conducted; supplying a second gate signal to the second gate line, and turning on the fourth transistor and the fifth transistor; in a data writing stage, a third gating signal is supplied to a third gating line, and the third transistor is turned on; in a light emitting stage, a first off signal is supplied to the first gate line, and the second transistor is turned off; the second gate signal is supplied to the fourth transistor and the fifth transistor, and the fourth transistor and the fifth transistor are turned on. The initialization of the first pole and the second pole of the first transistor can be completed without modifying the pixel circuits, so that when each frame starts, the signal change of the first pole of the first transistor in each pixel circuit is consistent, and the signal change of the second pole of the first transistor in each pixel circuit is consistent, the problem of uneven display caused by inconsistent change process can be avoided, and the display uniformity of the display panel can be improved on the premise of not additionally increasing the cost.
Drawings
Fig. 1 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of a pixel circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a connection between a scan circuit and a pixel circuit according to an embodiment of the invention;
FIG. 6 is a timing diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a connection between a scan circuit and a pixel circuit according to another embodiment of the present invention;
FIG. 8 is a timing diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 9 is a timing diagram of a pixel circuit according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, the inventor has found through careful study that the image sticking occurs in the display process of the conventional display panel, the reason for the image sticking is that, for the driving transistors in the pixel circuits, due to the hysteresis effect of the transistors, when the driving transistors are in the biased state for a long time, the plurality of pixel circuits may need to display different images, for example, a part of the pixel circuits need to drive and display a high gray scale, another part of the pixel circuits need to drive and display a low gray scale, and the actual display gray scales when the high gray scale is switched to the intermediate gray scale and when the low gray scale is switched to the intermediate gray scale are different, the display panel may generate a serious image sticking problem when displaying; in addition, since the first and second electrodes of the driving transistor are not initialized in the pixel circuit, when a next frame signal starts, the first and second electrodes of the driving transistor have different signal changes, which further causes the display of the light emitting unit corresponding to each pixel circuit to be different, that is, there is a problem of display non-uniformity.
Based on the technical problem, the invention provides the following solution:
fig. 1 is a flowchart of a driving method of a display panel according to an embodiment of the present invention, fig. 2 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present invention, fig. 3 is a timing diagram of a pixel circuit according to an embodiment of the present invention, which may correspond to the pixel circuit shown in fig. 2, and referring to fig. 1 to fig. 3, the pixel circuit 10 includes: a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a fifth transistor P5, and a light emitting unit L; wherein the second transistor P2 is connected between the first electrode L1 of the light emitting cell L and the initialization power Vref, and is turned on in response to the gate signal on the first gate line SCAN 1; the fourth transistor P4 is connected between the first driving power source PVDD and the first pole S1 of the first transistor P1, the fifth transistor P5 is connected between the second pole D1 of the first transistor P1 and the light emitting cell L, the second pole L2 of the light emitting cell L is connected to the second driving power source PVEE, and the fourth transistor P4 and the fifth transistor P5 are turned on in response to the gate signal on the second gate line EM; the third transistor P3 is connected to the data line Vdata and the first transistor P1 and is turned on in response to a gate signal on the third gate line SCAN 2.
Specifically, the pixel circuit may further include a storage capacitor Cst connected between the first driving power source PVDD and the gate G1 of the first transistor P1; a sixth transistor P6 connected between the gate G1 of the first transistor P1 and the initialization power Vref and turned on in response to the gate signal on the fourth gate line SCAN 3; the seventh transistor P7 is connected between the gate G1 of the first transistor P1 and the second diode D1 of the first transistor P1 and turned on in response to the gate signal on the third gate line SCAN 2. The first to seventh transistors P1 to P7 may be P-type transistors or N-type transistors, and in some other embodiments, some P-type transistors may be used and the other N-type transistors may be used, and in this embodiment, P-type transistors are used as the first to seventh transistors P1 to P7. The light emitting unit L may be an OLED, which is a current type device capable of emitting light when a current flows therethrough, wherein the first transistor P1 is a driving transistor of the pixel circuit and supplies a driving current to the light emitting unit L. The first driving power supply PVDD may be a positive voltage signal, and the second driving power supply PVEE may be a negative voltage signal. It should be noted that, when the first to seventh transistors P1 to P7 are all P-type transistors, the voltage value of the initialization signal on the initialization power Vref may be smaller than the voltage value of the voltage signal on the second driving power PVEE, so as to ensure that the light-emitting unit L does not emit light in the first initialization stage, and avoid the light-emitting unit L emitting light by mistake.
The driving method of the display panel comprises the following steps:
step S301, in a first initialization stage, providing a first gate signal to the first gate line, and turning on the second transistor; supplying a second gate signal to the second gate line, and turning on the fourth transistor and the fifth transistor;
specifically, as shown in fig. 2 and 3, in the first initialization stage t1, a first gate signal, for example, a low level signal, is provided on the first gate line SCAN1, when the second transistor P2 is turned on, the initialization signal on the initialization power source Vref is transmitted to the first pole L1 of the light emitting unit L, and at the same time, the fourth transistor P4 and the fifth transistor P5 are turned on due to the second gate signal provided on the second gate line EM, on one hand, the signal on the first driving power source PVDD is transmitted to the first pole S1 of the first transistor P1 through the fourth transistor P4, and the signal on the initialization power source Vref is transmitted to the second pole D1 of the first transistor P1 through the fifth transistor P5, thereby completing the initialization of the first pole S1 and the second pole S2 of the first transistor P1, and the corresponding potentials of the first pole S582 of each first transistor P1 are the same at the start time of each frame in the display panel, the potentials of the second electrodes D1 of the first transistors P1 are the same, and when the potentials are changed to the same potentials, the changing processes are the same, so that the problem of non-uniform display caused by non-uniform changing processes is solved, and the display uniformity is improved. Meanwhile, the pixel circuit does not need to be modified, and only the first gate signal is provided to the first gate line SCAN1 and the second gate signal is provided to the second gate line EM in the first initialization stage t1, so that the problem of uneven display of the display panel can be avoided, and the cost of the display panel cannot be additionally increased.
In step S302, in the data writing phase, a third gate signal is provided to the third gate line, and the third transistor is turned on.
Specifically, in the data writing phase t2, the third transistor P3 is turned on, the data signal on the data line Vdata is transmitted to the first electrode S1 of the first transistor P1 through the third transistor P3, and since the potential on the storage capacitor Cst is low, the first transistor P1 is turned on, the seventh transistor P7 is turned on under the third gate signal on the third gate line SCAN2, that is, the data signal on the data line Vdata is transmitted to the storage capacitor Cst, when the potential on the storage capacitor Cst rises to turn off the first transistor P1, the data signal cannot be written onto the storage capacitor Cst, so that the compensation of the threshold voltage of the first transistor P1 is completed, and the final light emitting unit L is not affected by the threshold voltage of the first transistor when emitting light, thereby further improving the display uniformity of the display panel.
In step S303, in the light emitting stage, the first gate line is supplied with a first off signal, the second transistor is turned off, the fourth transistor and the fifth transistor are supplied with a second gate signal, and the fourth transistor and the fifth transistor are turned on.
Specifically, in the light emitting period t3, the fourth transistor P4 and the fifth transistor P5 are turned on by the second gate signal on the second gate line EM, so that a conductive path is formed between the first transistor P1 and the light emitting cell L, the driving current output from the first transistor P1 can be transmitted to the light emitting cell L, and the driving current output from the first driving transistor P1 is related to the charge stored on the storage capacitor Cst, thereby enabling the light emitting cell L to perform display according to the data signal previously written in the storage capacitor Cst.
In the technical solution of this embodiment, a driving method of a display panel is provided, including in a first initialization stage, providing a first gate signal to a first gate line, and turning on a second transistor; supplying a second gate signal to the second gate line, and turning on the fourth transistor and the fifth transistor; in a data writing stage, a third gating signal is supplied to a third gating line, and the third transistor is turned on; in a light emitting stage, a first off signal is supplied to the first gate line, and the second transistor is turned off; the second gate signal is supplied to the fourth transistor and the fifth transistor, and the fourth transistor and the fifth transistor are turned on. The initialization of the first pole and the second pole of the first transistor can be completed without modifying the pixel circuits, so that when each frame starts, the signal change of the first pole of the first transistor in each pixel circuit is consistent, and the signal change of the second pole of the first transistor in each pixel circuit is consistent, the problem of uneven display caused by inconsistent change process can be avoided, and the display uniformity of the display panel is improved on the premise of additionally increasing the cost.
Optionally, fig. 4 is still another timing diagram of a pixel circuit according to an embodiment of the present invention, which may correspond to the pixel circuit in fig. 2, and with reference to fig. 2 and fig. 4, before the data writing phase, further includes: in the second initialization stage, the fourth gate signal is supplied to the fourth gate line, and the sixth transistor is turned on.
For example, as shown in fig. 4, the second initialization stage t4 may be performed before the first initialization stage t1, in the second initialization stage t4, the sixth transistor P6 is turned on, the initialization signal on the initialization power source Vref is transmitted to the gate G1 of the first transistor P1, the gate G1 of the first transistor P1 is initialized, so that the first transistor P1 is turned on in the subsequent stages (the first initialization stage t1 and the data writing stage t2 in this embodiment), in the first initialization stage t1, the first transistor P1 is turned on, and since the fourth transistor P4 and the fifth transistor P5 are both turned on at this time, a current flows between the first pole S1 and the second pole D1 of the first transistor P1, that is, currents flowing through the first transistor P1 in each pixel circuit of the display panel are all the same, thereby reducing the drift of the threshold voltage of the first transistor P1 caused by the stress deviation and improving the image sticking phenomenon, the display effect is further improved.
Fig. 5 is a schematic diagram illustrating a connection between a scan circuit and a pixel circuit according to an embodiment of the invention, where fig. 5 may correspond to the timing diagram of fig. 4, a plurality of rows of cascaded scan circuits 11 may be included in the display panel, and a plurality of rows of cascaded enable circuits 12 may be included, an INPUT terminal INPUT of the present row scan circuit 11 is electrically connected to an OUTPUT terminal OUTPUT of the previous row scan circuit, a signal INPUT from the INPUT terminal INPUT of the first row scan circuit 11 may be provided by a driving chip on the main board, and the input terminal IN of the present row enable circuit 12 is electrically connected to the output terminal OUT of the previous row enable circuit 12, the input terminal of the first row enable circuit may also be provided by a driver chip on the motherboard, in the present embodiment, the enable circuit is electrically connected to the second gate line EM corresponding to the same row of pixel circuits 10 to supply the second gate signal to the pixel circuits 10, and the scan circuit 11 and the enable circuit 12 may be shift registers. The third gate line SCAN2 corresponding to the nth row pixel circuit 10 is electrically connected to the nth row SCAN circuit, the first gate line SCAN1 corresponding to the nth row pixel circuit 10 is electrically connected to the nth-1 row SCAN circuit, the fourth gate line SCAN3 corresponding to the nth row pixel circuit 10 is electrically connected to the nth-2 row SCAN circuit, the first gate signal may include a first gate pulse, the second gate signal may include a second gate pulse, the third gate signal may include a third gate pulse, and the fourth gate pulse may include a fourth gate pulse. Wherein N is a positive integer.
Fig. 6 is another exemplary timing diagram of a pixel circuit according to an embodiment of the present invention, which may correspond to the pixel circuit in fig. 2, and in conjunction with fig. 2 and fig. 6, the first initialization phase t1 and the second initialization phase are performed simultaneously.
Specifically, the second initialization phase may be performed simultaneously with the first initialization phase t1, in the second initialization phase, the sixth transistor P6 is turned on, the initialization signal on the initialization power Vref is transmitted to the gate of the first transistor P1, and the gate of the first transistor P1 is initialized, so that the first transistor P1 is turned on in a subsequent phase (in this embodiment, the data writing phase t2), and at this time, the first transistor P1, the fourth transistor P4, and the fifth transistor P5 are all turned on, and a current flows between the first pole and the second pole of the first transistor P1, that is, the currents flowing through the first transistor P1 in each pixel circuit of the display panel are all the same, so as to reduce the shift of the threshold voltage of the first transistor P1 caused by the stress deviation, improve the image sticking phenomenon, and further improve the display effect. Meanwhile, the first initialization stage and the second initialization stage are performed simultaneously, so that the overall duration of each frame signal is reduced, the frame frequency is improved, and the display effect is further improved.
Fig. 7 is a schematic diagram of another exemplary connection between a SCAN circuit and a pixel circuit according to an embodiment of the invention, where fig. 7 may correspond to the timing diagram of fig. 6, a third gate line SCAN2 corresponding to the pixel circuit 10 in the nth row is electrically connected to the nth row SCAN circuit, a first gate line SCAN1 corresponding to the pixel circuit 10 in the nth row is electrically connected to the N-1 th row SCAN circuit, and a fourth gate line SCAN3 corresponding to the pixel circuit 10 in the nth row is electrically connected to the N-1 th row SCAN circuit. At this time, the pulse width of the first gating pulse, the pulse width of the third gating pulse and the pulse width of the fourth gating pulse are the same, the layout design of the display panel is simpler, the scanning circuit on the display panel can be directly utilized, and the design cost cannot be additionally increased.
Alternatively, fig. 8 is another timing diagram of a pixel circuit according to an embodiment of the present invention, fig. 9 is another timing diagram of a pixel circuit according to an embodiment of the present invention, and referring to fig. 8 and 9, the timing diagrams in fig. 8 and 9 may both correspond to the pixel circuit in fig. 2, and there is an overlap between rising edges or falling edges of the first gate pulse and the second gate pulse.
Specifically, when the first to seventh transistors P1 to P7 each employ a P-type transistor, it may be configured that there is an overlap between rising edges of the first gate pulse and the second gate pulse, that is, there is an overlap between a gate signal on the first gate line SCAN1 and a gate signal on the second gate line EM, and at this time, the first initialization stage t1 includes two stages, i.e., a first stage t11 and a second stage t12, in which the second transistor P2 is turned on at the first stage t11, the initialization signal on the initialization power source Vref is transmitted to the first pole of the light emitting unit L, and at the same time, the fourth transistor P4 and the fifth transistor P5 are turned on due to the second gate signal provided on the second gate line EM, the signal on the first driving power source PVDD is transmitted to the first pole of the first transistor P1 through the fourth transistor P4, the Vref signal on the initialization power source is transmitted to the second pole of the first transistor P1 through the fifth transistor P5, therefore, the initialization of the first pole and the second pole of the first transistor P1 is completed, that is, in the display panel, at the time when each frame starts, the first pole and the second pole of the first transistor P1 of the first transistor P1 in each pixel circuit have the same electric potential, and when the electric potentials are changed to the same electric potential, the changing processes are consistent, so that the problem of display unevenness caused by inconsistent changing processes is avoided, and the display uniformity is further improved. In the second stage t12, the first gate line SCAN1 is still at a low level, the second transistor P2 is still turned on, the signal on the second gate line EM is at a high level, the fourth transistor P4 and the fifth transistor P5 are both turned off, and the initialization signal on the initialization power Vref is written into the first electrode of the light emitting cell L, so that the initialization of the light emitting cell L is completed, and the display effect is further improved.
In the timing sequence shown in fig. 8, the second initialization period t2 precedes the first initialization period t1, so that the gate of the first transistor P1 is initialized completely; in the timing shown in fig. 9, the second initialization stage t2 and the first stage t11 are performed simultaneously, so that the overall time of one frame is short, which is advantageous for improving the frame rate.
Alternatively, with continued reference to fig. 8, the pulse width d1 of the first gate pulse is wider than the pulse width d2 of the fourth gate pulse, so as to ensure that when the second initialization phase is performed simultaneously with the first phase t11, the high level signal on the second gate line EM does not overlap the low level signal on the fourth gate line SCAN3, and the fourth gate pulse only overlaps the second gate pulse, so that in the first phase t11, the initialization signal on the initialization power source Vref only initializes the gate of the first transistor P1, thereby improving the initialization degree and further improving the display effect.
Optionally, the pulse width d2 of the fourth gate pulse and the pulse width d3 of the third gate pulse are equal.
Thus, the fourth gate line SCAN3 and the third gate line SCAN2 can be provided by the SCAN circuit, thereby being beneficial to reducing the overall cost of the display panel.
Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 10, the display device 20 includes: a plurality of pixel circuits in the display region and a scan driver in the non-display region; the pixel circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a light emitting unit; the second transistor is connected between the first pole of the light-emitting unit and the initialization power supply, and is turned on in response to the gate signal on the first gate line; the fourth transistor is connected between the first driving power supply and the first pole of the first transistor, the fifth transistor is connected between the second pole of the first transistor and the first pole of the light emitting unit, the second pole of the light emitting unit is connected with the second driving power supply, and the fourth transistor and the fifth transistor are turned on in response to the gating signal on the second gating line; the third transistor connects data link and first transistor, respond to the gating signal on the third strobe line and turn on; the scan driver is to: in a first initialization stage, a first gate signal is supplied to a first gate line, and a second transistor is turned on; supplying a second gate signal to the second gate line, and turning on the fourth transistor and the fifth transistor; in a data writing stage, a third gating signal is supplied to a third gating line, and the third transistor is turned on; in a light emitting stage, a first off signal is supplied to the first gate line, and the second transistor is turned off; the second gating signal is provided to the fourth transistor and the fifth transistor, which are turned on. The non-display region may further include a data driver and a timing controller, and the display panel may be connected to the scan driver through scan lines. The display panel may be connected to the data driver through data lines. The scan driver may supply scan signals to the pixel circuits included in the display panel, the data driver may supply data signals to the pixel circuits included in the display panel, and the timing controller may generate a plurality of control signals to supply the control signals to the scan driver, the data driver, and the like. The display device 20 may be a mobile phone, a computer, a tablet, a wearable device, or the like.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A driving method of a display panel, the display panel including a pixel circuit, the pixel circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a light emitting unit; wherein the second transistor is connected between the first electrode of the light emitting unit and an initialization power supply, and is turned on in response to a gate signal on the first gate line; the fourth transistor is connected between a first driving power source and the first pole of the first transistor, the fifth transistor is connected between the second pole of the first transistor and the first pole of the light emitting unit, the second pole of the light emitting unit is connected with a second driving power source, and the fourth transistor and the fifth transistor are turned on in response to a gate signal on the second gate line; the third transistor is connected with a data line and the first transistor and is turned on in response to a gating signal on a third gating line;
the driving method includes:
in a first initialization stage, a first gate signal is supplied to the first gate line, and the second transistor is turned on; supplying a second gate signal to the second gate line, the fourth transistor and the fifth transistor being turned on;
in a data writing phase, a third gating signal is supplied to the third gating line, and the third transistor is turned on;
in a light emitting stage, a first turn-off signal is supplied to the first gate line, and the second transistor is turned off; providing a second gating signal to the fourth transistor and the fifth transistor, the fourth transistor and the fifth transistor being conductive.
2. The driving method according to claim 1,
the pixel circuit further includes a sixth transistor connected between the gate of the first transistor and the initialization power supply and turned on in response to a gate signal on a fourth gate line;
before the data writing phase, the method further comprises the following steps:
and a second initialization stage of supplying a fourth gate signal to the fourth gate line, and the sixth transistor is turned on.
3. The driving method according to claim 2,
the second initialization phase precedes the first initialization phase.
4. The driving method according to claim 2,
the first initialization phase and the second initialization phase are performed simultaneously.
5. The driving method according to claim 2,
the first strobe signal comprises a first strobe pulse, the second strobe signal comprises a second strobe pulse, the third strobe signal comprises a third strobe pulse, and the fourth strobe signal comprises a fourth strobe pulse;
the pulse width of the first gate pulse, the pulse width of the third gate pulse and the pulse width of the fourth gate pulse are the same.
6. The driving method according to claim 2,
the first strobe signal comprises a first strobe pulse, the second strobe signal comprises a second strobe pulse, the third strobe signal comprises a third strobe pulse, and the fourth strobe signal comprises a fourth strobe pulse; the first strobe pulse and the second strobe pulse have overlapping rising edges or falling edges.
7. The driving method according to claim 6,
the pulse width of the first gate pulse is wider than that of the fourth gate pulse.
8. The driving method according to claim 7, wherein the fourth gate pulse overlaps with the second gate pulse.
9. The driving method according to claim 7,
the pulse width of the fourth gate pulse is equal to the pulse width of the third gate pulse.
10. A display device, comprising:
a plurality of pixel circuits in the display region and a scan driver in the non-display region;
the pixel circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a light emitting unit; wherein the second transistor is connected between the first electrode of the light emitting unit and an initialization power supply, and is turned on in response to a gate signal on the first gate line; the fourth transistor is connected between a first driving power source and the first pole of the first transistor, the fifth transistor is connected between the second pole of the first transistor and the first pole of the light emitting unit, the second pole of the light emitting unit is connected with a second driving power source, and the fourth transistor and the fifth transistor are turned on in response to a gate signal on the second gate line; the third transistor is connected with a data line and the first transistor and is turned on in response to a gating signal on a third gating line;
the scan driver is to:
in a first initialization stage, a first gate signal is supplied to the first gate line, and the second transistor is turned on; supplying a second gate signal to the second gate line, the fourth transistor and the fifth transistor being turned on;
in a data writing phase, a third gating signal is supplied to the third gating line, and the third transistor is turned on;
in a light emitting stage, a first turn-off signal is supplied to the first gate line, and the second transistor is turned off; providing a second gating signal to the fourth transistor and the fifth transistor, the fourth transistor and the fifth transistor being conductive.
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