CN109036292B - Display method and display device - Google Patents
Display method and display device Download PDFInfo
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- CN109036292B CN109036292B CN201811108747.3A CN201811108747A CN109036292B CN 109036292 B CN109036292 B CN 109036292B CN 201811108747 A CN201811108747 A CN 201811108747A CN 109036292 B CN109036292 B CN 109036292B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
- G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
The invention provides a display method and a display device, belongs to the technical field of display, and can at least partially solve the problem of excessive power consumption caused by excessive switching times of a switching element of a storage unit in a display panel in the conventional display device. The display method comprises a plurality of line periods, wherein data voltage is written into a row of sub-pixels in each line period, each storage unit connected with the same data end receives and stores the data voltage from the data end in turn, and each storage unit receives and only receives the data voltage once; in at least two adjacent row periods, at least one memory cell is caused to receive a data voltage in both a subsequent stage of a preceding row period and a preceding stage of a subsequent row period.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display method and a display device.
Background
A display panel (e.g., a liquid crystal display panel, an OLED display panel, a micro light emitting diode display panel, etc.) generally includes a plurality of sub-pixels arranged in an array. A plurality of data terminals are provided in the display panel, and data voltages are provided to the data terminals by a driving circuit (specifically, for example, by a Source driving chip, also referred to as Source IC), and the driving circuit (specifically, for example, by a timing driving chip, also referred to as T-con IC) controls each row of sub-pixels to sequentially receive corresponding data voltages. The sub-pixels emit light according to the magnitude of the data voltage.
When the density of the sub-pixels in the display panel is too high, or the PPI is too high, this results in a limited space in the display panel where the data terminal can be disposed. The existing solution is to supply the data voltages to two columns of sub-pixels from one data terminal (also known as MUX 1: 2 technology). Fig. 1 is a schematic circuit diagram of a conventional display panel 1, and fig. 2 is a timing diagram of sub-pixels in the display panel according to the prior art.
As shown in fig. 1, a plurality of sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B) are arranged in an array in the display panel 1. The display panel 1 is, for example, an OLED display panel. A plurality of data terminals are also provided in the display panel 1, of which only three are shown in fig. 1: a first data terminal S1, a second data terminal S2, and a third data terminal S3. Each data terminal is connected with two memory cells, namely a first memory cell M1 and a second memory cell M2 in FIG. 1. The circuit structures of the first memory cell M1 and the second memory cell M2 may be identical, and they differ only in the operation timing. All the first memory cells M1 operate simultaneously, and all the second memory cells M2 operate simultaneously. The memory cell is provided with, for example, a switching element, a capacitor, an isolator, and the like, and the data voltage obtained from the external driving circuit at the data terminal can be stored in the memory cell, and the data line DL is driven by the memory cell to write the data voltage into the sub-pixel to which the data line DL is connected. Each row of sub-pixels is connected to a Gate line GL, which provides a Gate control signal to the Gate control signal terminal 101 in the corresponding sub-pixel (the Gate1 signal is the Gate control signal corresponding to the sub-pixel in the first row, and the Gate2 signal is the Gate control signal corresponding to the sub-pixel in the second row). Only when the gate control signal is active will the data voltage be written to the sub-pixel.
In fig. 2, the Gate control signals Gate1, Gate2 and the control signals applied to the switching elements of the first memory cell M1 and the second memory cell M2 (still labeled as M1, M2, respectively) are all active low. In each row period (a period in which a Data voltage is written to a row of subpixels, two row periods are shown in fig. 2) of the operating timing of the subpixels in the OLED display panel, the switching element control signal applied to the first memory cell M1 is asserted first, and each Data terminal stores Data voltage Data required on the corresponding Data line into the corresponding first memory cell M1. The process lasts for example 2.6 us. Then, each data terminal is disconnected from the first memory cell M1 and is connected to the second memory cell M2 instead. The switching process continues, for example, for 0.6us (during which time neither first memory cell M1 nor second memory cell M2 receive the data voltage) in order to establish a stable connection between the data terminals and second memory cell M2. Of course, this handover procedure may be omitted, and it can be said that the handover procedure lasts for 0 us. Each data terminal then supplies the required data voltage to the corresponding second memory cell M2, which process lasts for 2.6us, for example. After the data voltage input to the second memory cell M2 is finished, after a buffering time, for example, lasting for 0.6us, the Gate control signal Gate1 corresponding to the first row of sub-pixels is asserted, the data voltages stored in the first memory cell M1 and the second memory cell M2 are written to two different sub-pixels in the same row through different data lines DL (for example, the first memory cell M1 connected to the first data terminal S1 writes the data voltage to the red sub-pixel R, and the second memory cell M2 connected to the first data terminal S1 writes the data voltage to the green sub-pixel G, although the two data voltages may be different or the same, depending on the image data to be displayed by the display panel). The timing of the next row period is the same as the timing of this row period, except that in the next row period, the Gate control signal Gate2 corresponding to the sub-pixels of the second row is activated, and the data voltages stored in the respective memory cells are written in the sub-pixels of the second row, respectively.
The prior art has at least the following problems: in each row period, the switching elements inside each memory cell need to be sequentially turned on and off. Frequent turn-on and turn-off operations can cause a significant increase in power consumption.
Disclosure of Invention
The invention at least partially solves the problem of overlarge power consumption caused by overhigh switching frequency of a switching element of a storage unit in a display panel in the conventional display device, and provides a display method and a display device.
According to a first aspect of the present invention, a display method is provided, which is applied to a display panel, where the display panel includes sub-pixels distributed in an array, and a plurality of data terminals, each of the data terminals is connected to a plurality of storage units, and each of the storage units is connected to a data line, and is configured to provide a data voltage stored therein to a corresponding data line; in each row of sub-pixels, different data lines corresponding to the same data terminal are connected with different sub-pixels, the display method comprises a plurality of row periods, and data voltages are written into the sub-pixels in one row in each row period, wherein,
in each row period, enabling each storage unit connected with the same data end to receive and store the data voltage from the data end in turn, and enabling each storage unit to receive and only receive the data voltage once;
in at least two adjacent row periods, at least one memory cell is caused to receive a data voltage in both a subsequent stage of a preceding row period and a preceding stage of a subsequent row period.
Optionally, in any two adjacent row periods, one of the memory cells connected to the same data terminal receives and stores the data voltage at the data terminal in a later stage of a previous row period and in a former stage of a next row period.
Optionally, each data terminal is connected to two storage units respectively; in any two adjacent line periods of the row period,
enabling one memory cell in two memory cells connected with the same data terminal to receive and store the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period;
and enabling the other memory cell in the two memory cells connected with the data terminal to receive and store the data voltage on the data terminal at the front section of the previous line period and the rear section of the next line period.
Alternatively, in each row period, in two memory cells connected to the same data terminal, after the memory cell receiving the data voltage first finishes receiving the data voltage, the memory cell receiving the data voltage later starts receiving the data voltage after a first time interval.
Optionally, the display panel further includes a plurality of gate lines extending along the row direction, each row of sub-pixels corresponds to one gate line, the gate lines are connected to gate control signal terminals of each sub-pixel in the corresponding row of sub-pixels, the gate control signal terminals are used for controlling writing of the data voltages stored in the storage unit into the corresponding sub-pixels, and the display method further includes:
in each row period, after the memory cell that receives the data voltage last starts receiving the data voltage, the effective voltage is supplied to the corresponding gate line.
Optionally, in each row period, after the supply of the effective voltage to the corresponding gate line is stopped, the supply of the data voltage to the memory cell that receives the data voltage last is stopped after a second time interval.
Optionally, the sub-pixel comprises a light emitting diode.
According to a second aspect of the present invention, there is provided a display device, comprising a display panel and a driving circuit, wherein the display panel comprises sub-pixels distributed in an array, a plurality of data terminals, each data terminal is connected to a plurality of storage units, and each storage unit is connected to a data line and is configured to provide a data voltage stored therein to a corresponding data line; in each row, different data lines corresponding to the same data end are connected with different sub-pixels, the driving circuit is used for writing data voltage into a row of sub-pixels in each row period in a plurality of row periods, the driving circuit comprises a storage unit control module, the storage unit control module is connected with the storage unit, and the storage unit control module is configured to:
in each row period, enabling each storage unit connected with the same data end to receive and store the data voltage from the data end in turn, and enabling each storage unit to receive and only receive the data voltage once;
in at least two adjacent row periods, at least one memory cell is caused to receive a data voltage in both a subsequent stage of a preceding row period and a preceding stage of a subsequent row period.
Optionally, the storage unit control module is specifically configured to: in any two adjacent row periods, one memory cell in each memory cell connected with the same data terminal receives and stores the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period.
Optionally, each data terminal is connected to two storage units respectively; the storage unit control module is specifically configured to: in any two adjacent line periods of the row period,
one of the two memory cells connected with the same data terminal receives and stores the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period,
and enabling the other memory cell in the two memory cells connected with the data terminal to receive and store the data voltage on the data terminal at the front section of the previous line period and the rear section of the next line period.
Optionally, the storage unit control module is specifically configured to:
in each row period, in two memory cells connected to the same data terminal, after a first time interval elapses after a memory cell that previously received the data voltage finishes receiving the data voltage, the memory cell that subsequently received the data voltage starts receiving the data voltage.
Optionally, the display panel further includes a plurality of gate lines extending along the row direction, each row of sub-pixels corresponds to one gate line, the gate lines are connected to gate control signal terminals of each sub-pixel in the corresponding row of sub-pixels, the gate control signal terminals are used for controlling writing of the data voltage stored in the storage unit into the corresponding sub-pixels, the driving circuit further includes a gate driving module, and the gate driving module is configured to:
in each row period, after the memory cell that receives the data voltage last starts receiving the data voltage, the effective voltage is supplied to the corresponding gate line.
Optionally, the driving circuit further includes a source driving module, where the source driving module is configured to provide, to the data terminal, a data voltage required by a corresponding sub-pixel in a currently corresponding row of the memory cell in a period in which the memory cell receives the data voltage in each row cycle.
Drawings
FIG. 1 is a schematic circuit diagram of a conventional display panel;
FIG. 2 is a timing diagram of driving sub-pixels in the circuit structure of FIG. 1 according to a conventional display method;
FIG. 3 is a timing diagram illustrating a display method according to an embodiment of the invention corresponding to driving of sub-pixels in the display panel shown in FIG. 1;
FIG. 4 is a block diagram of a display device according to an embodiment of the present invention;
wherein the reference numerals are: r, red subpixel; G. a green sub-pixel; B. a blue sub-pixel; m1, a first storage unit; m2, a second storage unit; s1, a first data terminal; s2, a second data terminal; s3, a third data terminal; DL, data line; GL, grid line; 1. a display panel; 101. a gate control signal terminal; 2. a drive circuit; 21. a storage unit control module; 22. a gate driving module; 23. and a source driving module.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
In the following description, the effective level of each type of control signal is described by taking the low level effective as an example. The times indicated in the figures are examples of the durations of the corresponding periods.
Example 1:
the embodiment provides a display method applied to a display panel.
Referring to fig. 1, the display panel 1 includes sub-pixels (e.g., red sub-pixel R, green sub-pixel G, and blue sub-pixel B) arranged in an array, a plurality of data terminals (e.g., a first data terminal S1, a second data terminal S2, and a third data terminal S3), each of the data terminals being respectively connected to a plurality of memory cells (e.g., a first memory cell M1 and a second memory cell M2), each of the memory cells being respectively connected to one of the data lines DL and configured to provide the data voltage stored therein to a corresponding data line DL; in each row of sub-pixels, different data lines DL corresponding to the same data terminal are connected to different sub-pixels.
The sub-pixels may include light emitting diodes (organic light emitting diodes or micro light emitting diodes, etc.). That is, the display panel 1 may be an Organic Light Emitting Diode (OLED) display panel, a micro light emitting diode display panel, or the like. Of course, the liquid crystal display surface may be used. It should be noted that the sub-pixel structure according to the present invention can be configured according to the prior art, and therefore, is not specifically described again.
Each data terminal in the display panel 1 writes a data voltage into a plurality of different memory cells (for example, the first data terminal S1 writes a data voltage into the first memory cell M1 and the second memory cell M2 connected thereto), each memory cell being configured to transfer its stored data voltage into a subpixel connected to the memory cell through the data line DL. The design of the memory cell can also be set according to the prior art.
The display method provided by the embodiment comprises a plurality of row periods, and data voltages are written into sub-pixels of one row in each row period.
In each row period, the storage units connected with the same data terminal receive and store the data voltage from the data terminal in turn, and each storage unit receives and only receives the data voltage once. That is, in each row period, each data terminal has a period of time to receive and store the data voltage from the corresponding data terminal. Of course, this data voltage is the data voltage required for the sub-pixels of the corresponding current row determined according to the picture to be displayed.
In at least two adjacent row periods, at least one memory cell is caused to receive a data voltage in both a subsequent stage of a preceding row period and a preceding stage of a subsequent row period. Since the memory cell always receives the data voltage during this period (of course, the data voltages received during the two previous and next line periods may be different), the switching element in the memory cell only performs one on-action and one off-action during the two line periods, the switching frequency of the switching element is reduced, and the power consumption is also reduced.
Taking the second memory cell M2 in FIG. 3 as an example, it receives and stores the data voltage on the corresponding data terminal during the later period (e.g. lasting for 5.1us) of the first row period T1 and the earlier period (e.g. lasting for 5.1us) of the second row period T2. It is easy to understand that the Data voltage Data received by the Data terminal from the external driving circuit 2 at this time should be the Data voltage required to be displayed by the sub-pixel on the Data line DL connected to the second memory cell M2 in the sub-pixel of the row corresponding to the current row period.
In the timing shown in fig. 3, both the first memory cell M1 and the second memory cell M2 satisfy the improvement. Those skilled in the art can also make the above improvement to the timing of only one of the memory cells.
Optionally, in any two adjacent row periods, one of the memory cells connected to the same data terminal receives and stores the data voltage at the data terminal in a later stage of a previous row period and in a former stage of a next row period.
The same data terminal may be connected with 2 or more memory cells. That is, the timing sequence of receiving the data voltage by each memory cell connected to the same data terminal is designed, so that in any two adjacent row cycles, the period of receiving the data voltage by one memory cell is in the rear section of the previous row cycle and in the front section of the next row cycle. This also further reduces the power consumption of the switching elements in the memory cells.
Optionally, each data terminal is connected to two storage units respectively; in any two adjacent row periods, one of the two storage units connected with the same data terminal receives and stores the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period, and the other of the two storage units connected with the data terminal receives and stores the data voltage on the data terminal at the front section of the previous row period and the rear section of the next row period.
Referring to fig. 3, the period in which the first memory cell M1 receives the data voltage is continuous (each lasting 5.1us before and after) at the boundary of the second and third row periods T2 and T3, and the period in which the second memory cell M2 receives the data voltage is continuous at the boundary of the first and second row periods M1 and M2. This is because the same data terminal can supply the data voltage to only one memory cell at the same time, which results in that the timing of the first memory cell M1 and the timing of the second archive cell M2 are staggered by one row period.
Alternatively, in each row period, of two memory cells connected to the same data terminal, a memory cell that previously received the data voltage ends receiving the data voltage, and after a first time interval (for example, 0.7us) elapses, a memory cell that subsequently received the data voltage starts receiving the data voltage.
The first time interval is set to provide enough time for the data side and each device in the first and second memory cells M1 and M2 to complete the state switching. Of course, the skilled person can also set the time interval to 0 seconds, ignoring the effect of such a handover.
Optionally, the display panel 1 further includes a plurality of gate lines GL extending along the row direction, each row of sub-pixels corresponds to one gate line GL, the gate lines GL are connected to the gate control signal terminal 101 of each sub-pixel in the corresponding row of sub-pixels, the gate control signal terminal 101 is configured to control writing of the data voltage stored in the storage unit into the corresponding sub-pixel, and the display method further includes: in each row period, after the memory cell that receives the data voltage last starts receiving the data voltage, the effective voltage is supplied to the corresponding gate line GL.
Referring to fig. 3, in the first row period T1, the second memory cell M2 receives the data voltage later. The Gate control signal Gate1 (supplied from the external driving circuit through the Gate line GL corresponding to the first row of sub-pixels) required for the first row of sub-pixels becomes active (for example, for 3.5us) after the second memory cell M2 starts receiving the data voltage. That is, the data voltage is written to the corresponding subpixel in the first row of subpixels after the second memory cell M2 has received the data voltage. And, in the second row period T2, the first memory cell M1 receives the data voltage later. The Gate control signal Gate2 required for the second row of subpixels becomes active after the first memory cell M1 starts receiving the data voltage. A third line period T3, a fourth line period T4, and so on.
Alternatively, in each row period, after the supply of the effective voltage to the corresponding gate line is stopped, the supply of the data voltage to the memory cell which receives the data voltage last is stopped after a second time interval (for example, 1 us).
The time when the supply of the data voltage required for the sub-pixels of the corresponding row to the memory cell which has received the data voltage last is stopped can also be considered as the time when the row period ends. This is so because the sub-pixels of the row start to emit light in the next row period after the signal of the gate control signal terminal 101 is deactivated in one row period of the conventional OLED display panel, that is, after the writing of the data voltage to the sub-pixels is finished. The purpose of this time interval is to give the device in the sub-pixel time to reach a steady state.
Example 2:
the present embodiment provides a display device to implement the display method provided in embodiment 1.
As shown in fig. 1 and 4, includes a display panel 1 and a driving circuit 2. The display panel 1 comprises sub-pixels distributed in an array manner, and a plurality of data terminals, wherein each data terminal is respectively connected with a plurality of storage units, and each storage unit is respectively connected with one data line DL and used for supplying the data voltage stored in the storage unit to the corresponding data line GL; in each row of sub-pixels, different data lines DL corresponding to the same data terminal are connected to different sub-pixels. With particular reference to the foregoing description.
The driving circuit 2 is configured to write a data voltage to a row of sub-pixels in each of a plurality of row periods according to the aforementioned display method.
Specifically, the driving circuit 2 includes a storage unit control module 21, the storage unit control module 21 is connected to the storage unit, and the storage unit control module 21 is configured to: in each row period, enabling each storage unit connected with the same data end to receive and store the data voltage from the data end in turn, and enabling each storage unit to receive and only receive the data voltage once; in at least two adjacent row periods, at least one memory cell is caused to receive a data voltage in both a subsequent stage of a preceding row period and a preceding stage of a subsequent row period.
Specifically, the memory cell control module 21 is integrated within a timing control chip (TCON), for example. The control signal provided by the display panel to control each memory cell meets the above requirements.
Optionally, the storage unit control module 21 is specifically configured to: in any two adjacent row periods, one memory cell in each memory cell connected with the same data terminal receives and stores the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period.
Optionally, each data terminal is connected to two storage units respectively; the storage unit control module 21 is specifically configured to: in any two adjacent row periods, one of the two storage units connected with the same data terminal receives and stores the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period, and the other of the two storage units connected with the data terminal receives and stores the data voltage on the data terminal at the front section of the previous row period and the rear section of the next row period.
Optionally, the storage unit control module 21 is specifically configured to: in each row period, in two memory cells connected to the same data terminal, after a first time interval elapses after a memory cell that previously received the data voltage finishes receiving the data voltage, the memory cell that subsequently received the data voltage starts receiving the data voltage.
Optionally, the display panel 1 further includes a plurality of gate lines GL extending along the row direction, each row of sub-pixels corresponds to one gate line GL, the gate lines GL are connected to the gate control signal terminal 101 of each sub-pixel in the corresponding row of sub-pixels, the gate control signal terminal 101 is configured to control writing of the data voltage stored in the storage unit into the corresponding sub-pixel, the driving circuit 2 further includes a gate driving module 22, and the gate driving module 22 is configured to: in each row period, after the memory cell that receives the data voltage last starts receiving the data voltage, the effective voltage is supplied to the corresponding gate line GL.
Specifically, the gate driving module 22 is also integrated within the timing control chip, for example.
Optionally, the driving circuit 2 further includes a source driving module 23, and the source driving module 23 is configured to provide the data voltage required by the corresponding sub-pixel in the currently corresponding row of the memory cell to the data terminal in a period in which the memory cell receives the data voltage in each row cycle.
Specifically, the Source drive module 23 is integrated within a Source drive chip (Source IC), for example.
Specifically, the display device can be any product or component with a display function, such as a liquid crystal display module, an Organic Light Emitting Diode (OLED) display module, a micro-led display module, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. That is, the display device formed by the display panel whose data terminal needs to provide data voltages for different memory cells can be applied to the display method provided in embodiment 1.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (9)
1. A display method is applied to a display panel, the display panel comprises sub-pixels distributed in an array mode and a plurality of data ends, each data end is respectively connected with a plurality of storage units, and each storage unit is respectively connected with a data line and used for supplying stored data voltage to the corresponding data line; in each row of sub-pixels, different data lines corresponding to the same data terminal are connected to different sub-pixels, wherein the display method comprises a plurality of row periods, and data voltages are written into the sub-pixels in one row in each row period, wherein,
in each row period, enabling each storage unit connected with the same data end to receive and store the data voltage from the data end in turn, and enabling each storage unit to receive and only receive the data voltage once; in each memory cell connected with the same data terminal, after the memory cell which receives the data voltage in advance finishes receiving the data voltage, after a first time interval, the memory cell which receives the data voltage in the later time interval starts receiving the data voltage;
in at least two adjacent row periods, at least one memory cell is caused to receive a data voltage in both a subsequent stage of a preceding row period and a preceding stage of a subsequent row period.
2. The display method according to claim 1,
in any two adjacent row periods, one memory cell in each memory cell connected with the same data terminal receives and stores the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period.
3. The display method according to claim 2, wherein each data terminal is connected to two storage units; in any two adjacent line periods of the row period,
enabling one memory cell in two memory cells connected with the same data terminal to receive and store the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period;
and enabling the other memory cell in the two memory cells connected with the data terminal to receive and store the data voltage on the data terminal at the front section of the previous line period and the rear section of the next line period.
4. The display method according to claim 1, wherein the display panel further comprises a plurality of gate lines extending along a row direction, one gate line corresponds to each row of sub-pixels, the gate lines connect gate control signal terminals of each sub-pixel in the corresponding row of sub-pixels, the gate control signal terminals are used for controlling writing of the data voltages stored in the storage units into the corresponding sub-pixels, and the display method further comprises:
in each row period, after the memory cell that receives the data voltage last starts receiving the data voltage, the effective voltage is supplied to the corresponding gate line.
5. The display method of claim 4, wherein in each row period, after the supply of the effective voltage to the corresponding gate line is stopped, the supply of the data voltage to the memory cell which last receives the data voltage is stopped after a second time interval.
6. The display method according to claim 1, wherein the sub-pixel comprises a light emitting diode.
7. A display device comprises a display panel and a driving circuit, wherein the display panel comprises sub-pixels distributed in an array mode and a plurality of data ends, each data end is respectively connected with a plurality of storage units, and each storage unit is respectively connected with a data line and used for supplying data voltage stored in the storage unit to the corresponding data line; in each row of sub-pixels, different data lines corresponding to the same data terminal are connected to different sub-pixels, wherein the driving circuit is configured to write a data voltage to a row of sub-pixels in each of a plurality of row periods, the driving circuit includes a memory cell control module, the memory cell control module is connected to the memory cell, and the memory cell control module is configured to:
in each row period, enabling each storage unit connected with the same data end to receive and store the data voltage from the data end in turn, and enabling each storage unit to receive and only receive the data voltage once; in each memory cell connected with the same data terminal, after the memory cell which receives the data voltage in advance finishes receiving the data voltage, after a first time interval, the memory cell which receives the data voltage in the later time interval starts receiving the data voltage;
in at least two adjacent row periods, at least one memory cell is caused to receive a data voltage in both a subsequent stage of a preceding row period and a preceding stage of a subsequent row period.
8. The display device according to claim 7, wherein the storage unit control module is specifically configured to: in any two adjacent row periods, one memory cell in each memory cell connected with the same data terminal receives and stores the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period.
9. The display device according to claim 8, wherein each data terminal is connected with two storage units respectively; the storage unit control module is specifically configured to: in any two adjacent line periods of the row period,
one of the two memory cells connected with the same data terminal receives and stores the data voltage on the data terminal at the rear section of the previous row period and the front section of the next row period,
and enabling the other memory cell in the two memory cells connected with the data terminal to receive and store the data voltage on the data terminal at the front section of the previous line period and the rear section of the next line period.
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| EP0275140B1 (en) * | 1987-01-09 | 1995-07-19 | Hitachi, Ltd. | Method and circuit for scanning capacitive loads |
| JP3819760B2 (en) * | 2001-11-08 | 2006-09-13 | 株式会社日立製作所 | Image display device |
| KR100688800B1 (en) * | 2004-11-17 | 2007-03-02 | 삼성에스디아이 주식회사 | Light Emitting Display and Driving Method Thereof |
| KR100739335B1 (en) * | 2006-08-08 | 2007-07-12 | 삼성에스디아이 주식회사 | Pixel and organic light emitting display device using the same |
| KR102063130B1 (en) * | 2013-04-16 | 2020-01-08 | 삼성디스플레이 주식회사 | Organic light emitting display device |
| CN104867452A (en) * | 2015-06-08 | 2015-08-26 | 深圳市华星光电技术有限公司 | Signal separator and AMOLED display device |
| CN107942556B (en) * | 2018-01-05 | 2020-07-03 | 鄂尔多斯市源盛光电有限责任公司 | Array substrate, liquid crystal display panel and driving method thereof |
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