CN113870771B

CN113870771B - Display panel and display device

Info

Publication number: CN113870771B
Application number: CN202111162580.0A
Authority: CN
Inventors: 刘冬妮; 肖丽; 郑皓亮; 赵蛟; 玄明花; 韩承佑; 陈亮; 崔晓荣
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2023-01-17
Anticipated expiration: 2041-09-30
Also published as: CN113870771A

Abstract

The embodiment of the disclosure provides a display panel and a display device. The display panel includes pixel units arranged in an array, each pixel unit including: a light emitting element and a pixel driving circuit configured to drive the light emitting element to emit light; the pixel driving circuit includes: a reset signal terminal and a scan signal terminal; the time when the scan signal terminal receives the active level signal partially overlaps the time when the reset signal terminal receives the active level signal. The display panel disclosed by the invention overcomes the technical problem of abnormal data signal writing in the prior art.

Description

Display panel and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and particularly relates to a display panel and a display device.

Background

The display market is developing vigorously at present, and with the continuous improvement of the demands of consumers on various display products such as notebook computers, smart phones, televisions, tablet computers, smart watches, fitness wristbands and the like, more new display products can emerge in the future. Among them, the Micro Light Emitting Diode (Micro LED) display technology has the advantages of low power consumption, high brightness, ultra-high resolution, high color saturation, fast response speed, long service life, high efficiency, etc., and is considered to be the most competitive next generation display technology.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

In a first aspect, the present disclosure provides a display panel including pixel units arranged in an array, each pixel unit including: a light emitting element and a pixel driving circuit configured to drive the light emitting element to emit light; the pixel driving circuit includes: a reset signal terminal and a scan signal terminal;

the time when the scanning signal end receives the effective level signal is partially overlapped with the time when the reset signal end receives the effective level signal.

In an exemplary embodiment, a time length of an overlapping portion of a time when the scan signal terminal receives the active level signal and a time when the reset signal terminal receives the active level signal is greater than or equal to 1 microsecond.

In an exemplary embodiment, the pixel driving circuit includes: a reset sub-circuit, a write sub-circuit, a compensation sub-circuit, a drive sub-circuit and a light emitting sub-circuit;

a reset sub-circuit, which is respectively connected with the initial signal terminal, the reset signal terminal, the first node and the first pole of the light-emitting element, and is configured to write the initial signal of the initial signal terminal into the first node and the first pole of the light-emitting element under the control of the reset signal terminal;

the writing sub-circuit is respectively connected with the scanning signal end, the data signal end and the third node and is arranged to write the signal of the data signal end into the third node under the control of the scanning signal end;

the compensation sub-circuit is respectively connected with the first power supply end, the scanning signal end, the first node and the second node, and is set to provide a signal of the second node for the first node under the control of the scanning signal end until the signal of the first node meets a threshold condition;

a driving sub-circuit respectively connected with the first node, the second node and the third node and configured to provide a driving current to the second node according to signals of the first node and the third node;

a light-emitting sub-circuit which is respectively connected with the first power end, the second node, the third node, the light-emitting signal end and the first pole of the light-emitting element and is arranged to write the signal of the first power end into the third node and write the signal of the second power end into the first pole of the light-emitting element under the control of the light-emitting signal end;

the second pole of the light-emitting element is connected with a second power supply end.

In an exemplary embodiment, the reset sub-circuit includes a first transistor and a seventh transistor;

a control electrode of the first transistor is connected with a reset signal end, a first electrode of the first transistor is connected with an initial signal end, and a second electrode of the first transistor is connected with a first node;

a control electrode of the seventh transistor is connected with a reset signal end, a first electrode of the seventh transistor is connected with an initial signal end, and a second electrode of the seventh transistor is connected with a first electrode of the light-emitting element.

In an exemplary embodiment, the write sub-circuit includes a fourth transistor;

the control electrode of the fourth transistor is connected with the scanning signal end, the first electrode of the fourth transistor is connected with the data signal end, and the second electrode of the fourth transistor is connected with the third node.

In an exemplary embodiment, the compensation sub-circuit includes a second transistor and a first capacitor;

a control electrode of the second transistor is connected with a scanning signal end, a first electrode of the second transistor is connected with a first node, and a second electrode of the second transistor is connected with a second node;

the first end of the first capacitor is connected with a first power supply end, and the second end of the first capacitor is connected with a first node.

In an exemplary embodiment, the driving sub-circuit includes a third transistor;

a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the third node, and a second electrode of the third transistor is connected to the second node.

In an exemplary embodiment, the light emitting sub-circuit includes a fifth transistor and a sixth transistor;

a control electrode of the fifth transistor is connected with a light-emitting signal end, a first electrode of the fifth transistor is connected with a first power supply end, and a second electrode of the fifth transistor is connected with a third node;

a control electrode of the sixth transistor is connected to the light-emitting signal terminal, a first electrode of the sixth transistor is connected to the second node, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting element.

In an exemplary embodiment, the reset sub-circuit includes a first transistor and a seventh transistor; the write subcircuit includes a fourth transistor; the compensation sub-circuit comprises a second transistor and a first capacitor; the driving sub-circuit includes a third transistor; the light emitting sub-circuit comprises a fifth transistor and a sixth transistor;

a control electrode of the seventh transistor is connected with a reset signal end, a first electrode of the seventh transistor is connected with an initial signal end, and a second electrode of the seventh transistor is connected with a first electrode of the light-emitting element;

a control electrode of the fourth transistor is connected with a scanning signal end, a first electrode of the fourth transistor is connected with a data signal end, and a second electrode of the fourth transistor is connected with a third node;

a first end of the first capacitor is connected with a first power supply end, and a second end of the first capacitor is connected with a first node;

a control electrode of the third transistor is connected with a first node, a first electrode of the third transistor is connected with a third node, and a second electrode of the third transistor is connected with a second node;

a control electrode of the sixth transistor is connected with the light-emitting signal end, a first electrode of the sixth transistor is connected with the second node, and a second electrode of the sixth transistor is connected with the first electrode of the light-emitting element.

In an exemplary embodiment, the types of the first to seventh transistors are P-type transistors or N-type transistors, or the types of the first to seventh transistors include P-type transistors and N-type transistors.

In an exemplary embodiment, the display panel further includes a scan driving circuit, a reset driving circuit, m rows of scan signal lines, m rows of reset signal lines, n columns of data signal lines; the pixel driving circuit further includes: a data signal terminal;

the scan driving circuit includes: the output end of the jth scanning shift register is connected with the jth row of scanning signal lines, and j is more than or equal to 1 and less than or equal to m;

the reset driving circuit includes: the output end of the jth reset shift register is electrically connected with the jth row of reset signal lines;

an ith column of data signal lines are positioned on one side of the ith column of pixel units, data signal ends of pixel driving circuits of the ith column of pixel units are electrically connected with the ith column of data signal lines, and i is more than or equal to 1 and less than or equal to n;

for the pixel driving circuit of each pixel unit in the jth row, a scanning signal end is electrically connected with a jth row scanning signal line, and a reset signal end is electrically connected with a jth row reset signal line.

In an exemplary embodiment, the display panel further includes a multiplexing circuit, z multiplexing signal lines, and k columns of data output lines, k = n/z, n and z are positive integers greater than or equal to 2, and n is an integer multiple of z;

the multiplexing circuit is respectively connected with the n columns of data signal lines, the z multiplexing signal lines and the k columns of data output lines, and is configured to output data signals of the k columns of data output lines to the n columns of data signal lines in a time-sharing manner under the control of the z multiplexing signal lines.

In an exemplary embodiment, a time at which the scan signal terminal receives the active level signal and a time at which the reset signal terminal receives the active level signal overlap each other is earlier than a time at which the z multiplexed signal lines receive the active level signal.

In an exemplary embodiment, z has a value of 2, the multiplexed signal line includes a first multiplexed signal line and a second multiplexed signal line, and the multiplexing circuit includes k first multiplexing transistors and k second multiplexing transistors;

the control electrode of the s-th first multiplexing transistor is electrically connected with the first multiplexing signal line, the first electrode of the s-th first multiplexing transistor is electrically connected with the 2s-1 th column of data signal line, the second electrode of the s-th first multiplexing transistor is electrically connected with the s-th column of data output line, and s is more than or equal to 1 and less than or equal to k;

the control electrode of the s-th second multiplexing transistor is electrically connected with the second multiplexing signal line, the first electrode of the s-th second multiplexing transistor is electrically connected with the 2 s-th column data signal line, and the second electrode of the s-th second multiplexing transistor is electrically connected with the s-th column data output line.

In a second aspect, the present disclosure further provides a display device including the display panel according to any one of the above embodiments.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of the various elements in the drawings are not to scale and are merely illustrative of the present disclosure.

FIG. 1 is a schematic view of a display device;

FIG. 2 is a schematic diagram illustrating a structure of a display panel according to an exemplary embodiment;

FIG. 3 is an equivalent circuit diagram of a multiplexing circuit provided in an exemplary embodiment;

FIG. 4a is a schematic diagram of a pixel driving circuit according to an exemplary embodiment;

fig. 4b is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment;

fig. 5 is a timing diagram illustrating an operation of a display panel according to an exemplary embodiment of the present disclosure.

Detailed Description

The embodiments in the present disclosure may be embodied in many different forms. Those skilled in the art will readily appreciate the fact that the disclosed embodiments and examples can be modified into various forms without departing from the spirit and scope of the disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of constituent elements, the thickness of layers, or regions may be exaggerated for clarity. Thus, any one implementation of the present disclosure is not necessarily limited to the dimensions shown in the figures, and the shapes and sizes of the components in the figures are not intended to reflect actual proportions. Further, the drawings schematically show ideal examples, and any one implementation of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present disclosure are provided to avoid confusion of the constituent elements, and are not limited in number.

In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of describing embodiments and simplifying description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components may be appropriately changed according to the direction of the described components. Therefore, the words described herein are not limited to the words described herein, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise explicitly specified or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood as appropriate to one of ordinary skill in the art.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (or a drain electrode terminal, a drain connection region, or a drain electrode) and a source electrode (or a source electrode terminal, a source connection region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities or in the case where the direction of current flow during circuit operation changes, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other. In the present disclosure, the control electrode may be a gate electrode.

In the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. The "element having some kind of electric function" may be, for example, an electrode, a wiring, a switching element such as a transistor, or another functional element such as a resistor, an inductor, or a capacitor.

Fig. 1 is a schematic structural diagram of a display device, where a display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light-emitting signal driving circuit, and a pixel array, the timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light-emitting signal driving circuit, the data signal driving circuit is connected to a plurality of data signal lines (D1 to Dn), the scan signal driving circuit is connected to a plurality of scan signal lines (G1 to Gm), and the light-emitting signal driving circuit is connected to a plurality of light-emitting signal lines (E1 to Eo), respectively. The pixel array may include a plurality of subpixels Pxij, i and j may be natural numbers, at least one subpixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line and a pixel driving circuit. In an exemplary embodiment, the timing controller may supply a gray scale value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, may supply a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and may supply a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit may generate data voltages to be supplied to the data signal lines D1, D2, D3, … … and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driving circuit may sample a gray value with a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan signal driving circuit may generate scan signals to be supplied to the scan signal lines G1, G2, G3, … … and Gm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driving circuit may sequentially supply scan signals having on-level pulses to the scan signal lines G1 to Gm. For example, the scan signal driving circuit may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number. The light emission signal driving circuit can generate emission signals to be supplied to the light emission signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission signal driving circuit may sequentially supply the emission signals having the off-level pulse to the light emission signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and the emission signal may be generated in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, and o may be a natural number.

For display products with high resolution and spliced screens, in order to save wiring space, a multiplexing circuit is usually adopted to drive the display products, and when the data signal driving circuit adopts the multiplexing circuit, and a data signal output to the same data signal line in the multiplexing circuit is switched from a high level to a low level, a condition that the low level data signal cannot be normally written into the pixel driving circuit exists, so that abnormal data signal writing is caused.

In order to solve the technical problem of abnormal writing of data signals of an existing display product, an embodiment of the present disclosure provides a display panel, which may include pixel units arranged in an array, where each pixel unit may include: a light emitting element and a pixel driving circuit configured to drive the light emitting element to emit light; the pixel driving circuit may include: a reset signal terminal and a scan signal terminal;

the scan signal terminal may receive an active level signal at a time partially overlapping with the reset signal terminal.

In the pixel driving circuit of the display panel, the time when the scanning signal end receives the effective level signal is partially overlapped with the time when the reset signal end receives the effective level signal, so that the data signal can be smoothly written into the pixel driving circuit, and the technical problem of abnormal data signal writing in the prior art is solved.

Fig. 2 is a schematic structural diagram of a display panel according to an exemplary embodiment, and fig. 3 is an equivalent circuit diagram of a multiplexing circuit according to an exemplary embodiment; FIG. 4a is a schematic diagram of a pixel driving circuit according to an exemplary embodiment; FIG. 4b is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment; fig. 5 is a timing diagram illustrating an operation of a display panel according to an exemplary embodiment of the present disclosure.

As shown in fig. 2, the display panel includes pixel units 10 arranged in an array, each pixel unit 10 including a light emitting element and a pixel driving circuit 11 configured to drive the light emitting element to emit light; the pixel drive circuit 11 may include: a reset signal terminal and a scan signal terminal; the time when the scan signal terminal receives the active level signal partially overlaps the time when the reset signal terminal receives the active level signal.

In an exemplary embodiment, a time period of an overlapping portion of a time when the scan signal terminal receives the active level signal and a time when the reset signal terminal receives the active level signal is greater than or equal to 1 microsecond. For example, the time length of the overlapping portion of the time when the scan signal terminal receives the active level signal and the time when the reset signal terminal receives the active level signal may be 2 microseconds, 3 microseconds, 5 microseconds, or the like.

As shown in fig. 2, a display panel provided by an embodiment of the present disclosure may include: m rows and n columns of pixel units 10, n columns of data signal lines D1 to Dn, m rows of scanning signal lines G1 to Gm, and m rows of reset signal lines (not shown in the figure), the pixel driving circuit 11 in each pixel unit 10 includes: data signal terminal, scanning signal terminal, reset signal terminal.

In an exemplary embodiment, a scan driving circuit includes: the output end of the jth scanning shift register is connected with the jth row of scanning signal lines, and j is more than or equal to 1 and less than or equal to m; the reset driving circuit includes: and the output end of the jth reset shift register is connected with the jth row reset signal line.

In the exemplary embodiment, the ith column data signal line Di is positioned at one side of the ith column pixel unit 10, the data signal end of the pixel driving circuit 11 of the ith column pixel unit is electrically connected with the ith column data signal line Di, and 1 ≦ i ≦ n.

In an exemplary embodiment, for the pixel driving circuit of each pixel unit in the j-th row, the scanning signal terminal is electrically connected to the j-th row scanning signal line Gj, and the reset signal terminal is electrically connected to the j-th row reset signal line.

In an exemplary real-time manner, the scan driving circuit and the reset driving circuit may be two independent driving circuits.

In an exemplary embodiment, the display panel may further include m rows of light emitting signal lines (not shown in the drawings). The pixel driving circuit may further include: and a light emitting signal terminal. For the pixel driving circuit of each pixel unit in the jth row, a light emission signal terminal is electrically connected to the jth row light emission signal line.

In an exemplary embodiment, the display panel may further include a multiplexing circuit 20, z multiplexing signal lines Mux (1) to Mux (z), and k columns of data output lines DT1 to DTk, k = n/z, n and z are positive integers greater than or equal to 2, and n is an integer multiple of z; a multiplexing circuit 20, connected to the n columns of data signal lines D1 to Dn, the z multiplexing signal lines Mux (1) to Mux (z), and the k columns of data output lines DT1 to DTk, respectively, is configured to time-divisionally output data signals of the k columns of data output lines DT1 to DTk to the n columns of data signal lines D1 to Dn under the control of the z multiplexing signal lines DT1 to DTk.

In an exemplary embodiment, in each pixel driving circuit, a time at which the scan signal terminal receives the active level signal overlaps with a time at which the reset signal terminal receives the active level signal is earlier than a time at which the z multiplexing signal lines receive the active level signal.

In one exemplary embodiment, the s-th column data output line DTs time-divisionally supplies data signals to the 2 s-1-th column data signal line and the 2 s-th column data signal line, 1 ≦ s ≦ k.

As shown in fig. 3, z may have a value of 2, the multiplexing signal line may include a first multiplexing signal line Mux (1) and a second multiplexing signal line Mux (2), and the multiplexing circuit 20 may include k first multiplexing transistors MT1 and k second multiplexing transistors MT2. The multiplexing circuit 20 may be configured to time-divisionally output the data signals of the k columns of data output lines DT1 to DTk to the n data signal lines D1 to Dn under the control of the first multiplexing signal line Mux (1) and the second multiplexing signal line Mux (2).

In an exemplary embodiment, a control electrode of the s-th first multiplexing transistor MT1 is electrically connected to the first multiplexing signal line Mux (1), a first electrode of the s-th first multiplexing transistor MT1 is electrically connected to the 2s-1 th column data signal line, a second electrode of the s-th first multiplexing transistor MT1 is electrically connected to the s-th column data output line DTs, and 1 ≦ s ≦ k. Illustratively, the control electrode of the 1 st first multiplexing transistor MT1 is electrically connected to the first multiplexing signal line Mux (1), the first electrode of the 1 st first multiplexing transistor MT1 is electrically connected to the 1 st column data signal line D1, the second electrode of the 1 st first multiplexing transistor MT1 is electrically connected to the 1 st column data output line DT1, the control electrode of the 2 nd first multiplexing transistor MT1 is electrically connected to the first multiplexing signal line Mux (1), the first electrode of the 2 nd first multiplexing transistor MT1 is electrically connected to the 3 rd column data signal line D3, the second electrode of the 2 nd first multiplexing transistor MT1 is electrically connected to the 2 nd column data output line DT2, and so on.

In an exemplary embodiment, a control electrode of the s-th second multiplexing transistor MT2 is electrically connected to the second multiplexing signal line Mux (2), a first electrode of the s-th second multiplexing transistor MT2 is electrically connected to the 2 s-th column data signal line, and a second electrode of the s-th second multiplexing transistor MT2 is electrically connected to the s-th column data output line DTs. Illustratively, the control electrode of the 1 st second multiplexing transistor MT2 is electrically connected to the second multiplexing signal line Mux (2), the first electrode of the 1 st second multiplexing transistor MT2 is connected to the 2 nd column data signal line D2, the second electrode of the 1 st second multiplexing transistor MT2 is electrically connected to the 1 st column data output line DT1, the control electrode of the 2 nd second multiplexing transistor MT2 is electrically connected to the second multiplexing signal line Mux (2), the first electrode of the 2 nd second multiplexing transistor MT2 is electrically connected to the 4 th column data signal line D4, the second electrode of the 2 nd second multiplexing transistor MT2 is electrically connected to the 2 nd column data output line DT2, and so on.

In an exemplary embodiment, the first multiplexing transistor MT1 and the second multiplexing transistor MT2 may be switching transistors. The first multiplexing transistor MT1 and the second multiplexing transistor MT2 may be both P-type transistors or both N-type transistors; or one of the first multiplexing transistor MT1 and the second multiplexing transistor MT2 is an N-type transistor, and the other is a P-type transistor.

It is understood that the display panel may further include a substrate base plate on which the pixel unit is disposed.

In one exemplary embodiment, the substrate base plate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass, metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

In an exemplary embodiment, the pixel unit may be any one of a red (R) pixel unit, a green (G) pixel unit, a blue (B) pixel unit, and a white pixel unit, and the disclosure is not limited herein. When the display panel includes red (R), green (G) and blue (B) pixel cells, the three pixel cells may be arranged in a horizontal, vertical, or delta manner. When the display panel includes a red (R) pixel unit, a green (G) pixel unit, a blue (B) pixel unit, and a white pixel unit, the four pixel units may be arranged in a horizontal parallel manner, a vertical parallel manner, or an array manner, and the disclosure is not limited thereto.

In one exemplary embodiment, the light emitting element may employ a light emitting diode. In an exemplary embodiment, the Light Emitting element includes a current-driven type device, and a current-driven type Light Emitting Diode may be adopted, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED), an Organic Light Emitting Diode (OLED), or a Quantum dot Light Emitting Diode (QLED).

In an exemplary embodiment, the light emitting element in the red pixel unit is a red light emitting diode, the light emitting element in the blue pixel unit is a blue light emitting diode, and the light emitting element in the green pixel unit is a green light emitting diode, or the light emitting elements of the red pixel unit, the blue pixel unit, the green pixel unit, and the white pixel unit are all blue light emitting diodes, and light emitting of corresponding colors of red, blue, green, and white is realized by matching with a color conversion material (such as quantum dots, fluorescent powder, and the like).

In an exemplary embodiment, as shown in fig. 4a, the pixel driving circuit 11 may include: a reset sub-circuit 11, a write sub-circuit 12, a compensation sub-circuit 13, a drive sub-circuit 14, and a light-emitting sub-circuit 15;

a reset sub-circuit 11, respectively connected to the initial signal terminal Vint, the reset signal terminal RST, the first node N1 and the first pole of the light emitting element, and configured to write the initial signal of the initial signal terminal Vint into the first node N1 and the first pole of the light emitting element under the control of the reset signal terminal RST;

a write-in sub-circuit 12, which is respectively connected to the scan signal terminal Gate, the Data signal terminal Data and the third node N3, and is configured to write the signal of the Data signal terminal Data into the third node N3 under the control of the scan signal terminal Gate;

a compensation sub-circuit 13, connected to the first power terminal VDD, the scan signal terminal Gate, the first node N1, and the second node N2, respectively, and configured to provide a signal of the second node N2 to the first node N1 under the control of the scan signal terminal Gate until the signal of the first node N1 satisfies a threshold condition;

a driving sub-circuit 14 connected to the first node N1, the second node N2, and the third node N3, respectively, and configured to supply a driving current to the second node N2 according to signals of the first node N1 and the third node N3;

a light emitting sub-circuit 15, respectively connected to the first power terminal VDD, the second node N2, the third node N3, the light emitting signal terminal EM, and the first electrode of the light emitting device, and configured to write the signal of the first power terminal VDD into the third node N3 and write the signal of the second power terminal VSS into the first electrode of the light emitting device under the control of the light emitting signal terminal EM;

the second electrode of the light emitting element is connected to a second power source terminal VSS.

In an exemplary embodiment, as shown in fig. 4b, the reset sub-circuit 11 may include a first transistor T1 and a seventh transistor T7;

a control electrode of the first transistor T1 is connected with a reset signal end RST, a first electrode of the first transistor T1 is connected with an initial signal end Vint, and a second electrode of the first transistor T1 is connected with a first node N1;

a control electrode of the seventh transistor T7 is connected to the reset signal terminal RST, a first electrode of the seventh transistor T7 is connected to the initial signal terminal Vint, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element.

In an exemplary embodiment, the write sub-circuit 12 may include a fourth transistor T4;

a control electrode of the fourth transistor T4 is connected to the scan signal terminal Gate, a first electrode of the fourth transistor T4 is connected to the Data signal terminal Data, and a second electrode of the fourth transistor T4 is connected to the third node N3.

In an exemplary embodiment, the compensation sub-circuit 13 may include a second transistor T2 and a first capacitor C1;

a control electrode of the second transistor T2 is connected to the Gate of the scan signal terminal, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the second node N2;

a first terminal of the first capacitor C1 is connected to a first power terminal VDD, and a second terminal of the first capacitor C1 is connected to a first node N1.

In an exemplary embodiment, the driving sub-circuit 14 may include a third transistor T3;

a control electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the third node N3, and a second electrode of the third transistor T3 is connected to the second node N2.

In an exemplary embodiment, the light emitting sub-circuit 15 may include a fifth transistor T5 and a sixth transistor T6;

a control electrode of the fifth transistor T5 is connected to the emission signal terminal EM, a first electrode of the fifth transistor T5 is connected to the first power terminal VDD, and a second electrode of the fifth transistor T5 is connected to the third node N3;

a control electrode of the sixth transistor T6 is connected to the emission signal terminal EM, a first electrode of the sixth transistor T6 is connected to the second node N2, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element OLED.

In an exemplary embodiment, as shown in fig. 4a and 4b, the reset sub-circuit 11 in the pixel driving circuit 11 includes a first transistor T1 and a seventh transistor T7; the write sub-circuit 12 includes a fourth transistor T4; the compensation sub-circuit 13 includes a second transistor T2 and a first capacitor C1; the drive sub-circuit 14 includes a third transistor T3; the light emitting sub-circuit 15 includes a fifth transistor T5 and a sixth transistor T6;

a control electrode of the seventh transistor T7 is connected to the reset signal terminal RST, a first electrode of the seventh transistor T7 is connected to the initial signal terminal Vint, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element;

a control electrode of the fourth transistor T4 is connected to the scan signal terminal Gate, a first electrode of the fourth transistor T4 is connected to the Data signal terminal Data, and a second electrode of the fourth transistor T4 is connected to the third node N3;

a first end of the first capacitor C1 is connected to a first power supply terminal VDD, and a second end of the first capacitor C1 is connected to a first node N1;

a control electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the third node N3, and a second electrode of the third transistor T3 is connected to the second node N2;

As shown in fig. 4b, the pixel driving circuit 11 in each pixel unit 10 may include: 7 transistors (T1 to T7), 1 capacitive unit (C1), 5 signal input terminals (RST, EM, gate, data, and Vint), 3 nodes (N1 to N3), and 2 power supply terminals (VDD and VSS).

In an exemplary embodiment, the first to seventh transistors T1 to T7 in the pixel driving circuit 11 may be the same type of transistors, for example, all of the transistors may be P-type transistors or all of the transistors may be N-type transistors, so as to simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

In an exemplary embodiment, the signal of the second power source terminal VSS is a low-level signal, and the signal of the first power source terminal VDD is a high-level signal that is continuously supplied.

The following description will obviously illustrate the operation process of the panel by taking an example that the multiplexing circuit 20 includes the first multiplexing transistor MT1 and the second multiplexing transistor MT2, and the first multiplexing transistor MT1, the second multiplexing transistor MT2, and the first to seventh transistors T1 to T7 are all P-type transistors. Fig. 5 shows a timing chart of the pixel driving circuits 11 in adjacent columns of the same row. As shown in FIG. 5, data (n-1) is the Data signal end of the pixel driving circuit in the pixel unit of the (i) th row and the (n-1) th column; data (n) is a Data signal end of a pixel driving circuit in the pixel unit of the ith row and the nth column; DTh is a data output line to which the n-1 th column and the n-th column of data signal lines in the i-th row are connected (i.e., an h-th column data output line), where h = n/2,n is an even number greater than or equal to 2; RST (n-1) is a reset signal end of a pixel driving circuit in a pixel unit of an nth column in an ith row, RST (n) is a reset signal end of a pixel driving circuit in a pixel unit of an nth column in the ith row, EM (n-1) is a light emitting signal end of a pixel driving circuit in a pixel unit of an nth column in the ith row, EM (n) is a light emitting signal end of a pixel driving circuit in a pixel unit of an nth column in the ith row, gate (n-1) is a scanning number end of a pixel driving circuit in a pixel unit of an nth column in the ith row, gate (n) is a scanning number end of a pixel driving circuit in a pixel unit of an nth column in the ith row, mux (1) is a first multiplexing signal line in a multiplexing circuit, and Mux (2) is a second multiplexing signal line Mux (2) in the multiplexing circuit.

As shown in fig. 5, an exemplary embodiment provides a working process of a display panel, which may include: first to fourth phases P1 to P4.

First phase P1: in the first reset stage, the signals of the reset signal terminals RST (n-1)/RST (n) are low-level signals, and the signals of the scan signal terminals Gate (n-1)/Gate (n), the emission signal terminals EM (n-1)/EM (n), the first multiplexing signal line Mux (1), and the second multiplexing signal line Mux (2) are high-level signals. The signal of the reset signal end RST (N-1)/RST (N) is a low level signal, so that a first transistor T1 and a seventh transistor T7 of the pixel driving circuit in the (N-1) th column and the nth column are turned on, an initial signal of the initial signal end Vint is provided to a first node N1 and a first electrode of the light emitting element, a control electrode of the first capacitor C1, a control electrode of the third transistor T3 and the first electrode of the light emitting element are initialized, and a data voltage is cleared from the first capacitor C1, the control electrode of the third transistor T3 and the first electrode of the light emitting element; signals of the scanning signal terminal Gate (n-1)/Gate (n), the emission signal terminal EM (n-1)/EM (n), the first multiplexing signal line Mux (1) and the second multiplexing signal line Mux (2) are high level signals, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 of the pixel drive circuit in the n-1 th column and the n-th column, and the first multiplexing transistor MT1 and the second multiplexing transistor MT2 of the multiplexing circuit are turned off, and a signal of the Data output line DTh cannot be written into the Data signal terminals Data (n-1) and Data (n) of the pixel drive circuit in the n-1 th column and the n-th column through the first multiplexing transistor MT1 and the second multiplexing transistor MT2. The light emitting element OLED driven by the pixel driving circuit in the n-1 th column and the pixel driving circuit in the nth column does not emit light at this stage.

A second stage P2: in the second reset phase, the signals of the reset signal terminal RST (n-1)/RST (n) and the scan signal terminal Gate (n-1)/Gate (n) are low level signals, and the signals of the emission signal terminal EM (n-1)/EM (n), the first multiplexing signal line Mux (1) and the second multiplexing signal line Mux (2) are high level signals. Signals of a reset signal end RST (N-1)/RST (N) and a scanning signal end Gate (N-1)/Gate (N) are low level signals, so that a first transistor T1, a second transistor T2, a fourth transistor T4 and a seventh transistor T7 of a pixel driving circuit in an N-1 th column and an N-th column are conducted, an initial signal of an initial signal end Vint is written into a first node N1 due to the conduction of the first transistor T1, a third transistor T3 is conducted, an initial signal of the first node N1 is written into a second node N2 due to the conduction of the second transistor T2, an initial signal of the second node N2 is written into a third node N3 due to the conduction of the third transistor T3, therefore, the initialization of a pixel driving circuit third node N3 in an N-1 th column and an N-th column is achieved, and data voltage in the third node N3 is cleared; since the seventh transistor T7 is continuously turned on, the initial signal of the initial signal terminal Vint is provided to the first electrode of the light emitting element, ensuring that the light emitting element does not emit light; since the signals of the first multiplexing signal line Mux (1), the second multiplexing signal line Mux (2), and the emission signal terminal EM (n-1)/EM (n) are high-level signals, the first multiplexing transistor MT1, the second multiplexing transistor MT2, the fifth transistor T5, and the sixth transistor T6 are turned off, and the signal of the Data output line DTh cannot be written into the Data signal terminals Data (n-1), data (n) of the pixel driving circuit in the n-th column and the n-th column via the first multiplexing transistor MT1 and the second multiplexing transistor MT2. At this stage, the light emitting elements OLED driven by the pixel driving circuit of the n-1 th column and the pixel driving circuit of the n-th column do not emit light.

Third stage P3: in the data writing stage, the signals of the reset signal terminal RST (n-1)/RST (n) and the emission signal terminal EM (n-1)/EM (n) are high-level signals, and the signals of the scan signal terminal Gate (n-1)/Gate (n) are low-level signals. The signals of the reset signal terminal RST (n-1)/RST (n) and the luminescence signal terminal EM (n-1)/EM (n) are high level signals, so that the first transistor T1, the seventh transistor T7, the fifth transistor T5 and the sixth transistor T6 of the pixel driving circuit in the n-1 th column and the n-th column are all cut off; the second transistor T2 and the fourth transistor T4 of the pixel driving circuit in the (n-1) th column and the (n) th column are turned on because the signal of the scanning signal terminal Gate (n-1)/Gate (n) is a low level signal; because the first transistor T1 is turned off, the initial signal of the initial signal terminal Vint cannot be written into the first node N1, and because the voltage across the first capacitor C1 does not suddenly change, the first node N1 maintains the low level of the previous frame, and the third warning transistor T3 is turned on.

In this stage, the signal according to the first and second multiplexed signal lines Mux (1) and Mux (2) can be divided into two sub-stages:

first sub-phase P31: the phase may be referred to as an n-1 th column pixel driving circuit data writing phase, where the signal of the first multiplexing signal line Mux (1) is a low level signal and the signal of the second multiplexing signal line Mux (2) is a high level signal. Since the signal of the first multiplexing signal line Mux (1) is a low-level signal, the first multiplexing transistor MT1 is turned on, the Data voltage of the Data output line DTh is written into the Data signal terminal Data (N-1) of the N-1 th column of pixel driving circuits through the first multiplexing transistor MT1, the Data voltage of the Data signal terminal Data (N-1) is written into the first node N1 through the turned-on fourth transistor T4, third transistor T3, and second transistor T2, and the difference between the Data voltage of the Data signal terminal Data (N-1) and the threshold voltage of the third transistor T3 is charged into the first capacitor C1, the voltage of the second terminal (first node N1) of the first capacitor C1 is Vd + Vth, vd is the Data voltage of the Data signal terminal Data (N-1), and Vth is the threshold voltage of the third transistor T3. Since the signal of the second multiplexing signal line Mux (2) is a high-level signal, the second multiplexing transistor MT2 is turned off, and the signal of the Data output line DTh cannot be written into the Data signal terminal Data (n) of the pixel drive circuit of the nth column via the second multiplexing transistor MT2.

Second sub-phase P32: the phase may be referred to as an nth column pixel driving circuit data writing phase, where the signal of the first multiplexing signal line Mux (1) is a high level signal, and the signal of the second multiplexing signal line end Mux (2) is a low level signal. Since the signal of the second multiplexing signal line Mux (2) is a low level signal, the second multiplexing transistor MT2 is turned on, the Data voltage of the Data output line DTh is written into the Data signal terminal Data (N) of the nth column of pixel driving circuits through the second multiplexing transistor MT2, the Data voltage of the Data signal terminal Data (N) is written into the first node N1 through the turned-on fourth transistor T4, the third transistor T3, and the second transistor T2, and the difference between the Data voltage of the Data signal terminal Data (N) and the threshold voltage of the third transistor T3 is charged into the first capacitor C1, the voltage Vd of the second terminal (first node N1) of the first capacitor C1 is Vd + Vth, vd is the Data voltage of the Data signal terminal Data (N), and Vth is the threshold voltage of the third transistor T3. Since the signal of the first multiplexing signal line Mux (1) is a high-level signal, the first multiplexing transistor MT1 is turned off, and the signal of the Data output line DTh cannot be written into the Data signal terminal Data (n-1) of the n-1 th column pixel driving circuit via the first multiplexing transistor MT 1.

Fourth stage P4: the signal of the reset signal terminal RST (n-1)/RST (n), the signal of the scan signal terminal Gate (n-1)/Gate (n), the signal of the first multiplexing signal line Mux (1) and the signal of the second multiplexing signal line Mux (2) are high level signals, and the signal of the emission signal terminal EM (n-1)/EM (n) is low level signals. The signal of the emission signal terminal EM (N-1)/EM (N) is a low level signal, so that the fifth transistor T5 and the sixth transistor T6 in the pixel driving circuits of the (N-1) th column and the nth column are turned on, and the voltage signal of the first power terminal VDD is written into the third node N3 (i.e., the first electrode of the third transistor) through the fifth transistor T5; the signals of the reset signal terminal RST (N-1)/RST (N), the scanning signal terminal Gate (N-1)/Gate (N), the first multiplexing signal line Mux (1) and the second multiplexing signal line Mux (2) are high level signals, the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 in the pixel driving circuits of the N-1 th column and the N-th column and the first multiplexing transistor MT1 and the second multiplexing transistor MT2 in the multiplexing circuit 20 are all turned off, the first node N1 maintains the voltage Vd + Vth of the previous frame (i.e., the control voltage of the third transistor T3), and the Vgs voltage difference = Vd + Vth-VDD between the control electrode and the first electrode of the third transistor T3, so that the third transistor T3 is turned on, and the power source outputted from the first power source terminal VDD supplies the driving voltage to the first electrode of the light emitting element through the turned on fifth transistor T5, the third transistor T3 and the sixth transistor T6, thereby driving the light emitting element.

In the working process of the pixel driving circuit, after two reset stages, the time of the effective level signal of the scanning signal end in the second reset stage is partially overlapped with the time of the effective level signal of the reset signal end, and the third node N3 of the pixel driving circuit is initialized, so that the previous row of data voltage remained by the third node N3 is prevented from being written into the first node N1 before data is written into, and the data voltage can be smoothly written into the pixel driving circuit in the data writing stage.

The pixel driving circuit in the ith row and the nth column is taken as an example for explanation: if the data voltage written by the pixel driving circuit in the previous row (i.e. the i-1 th row and the N-th column) is the high level DH, assuming that there is no second reset phase P2 in which the time of the active level signal of the scanning signal terminal Gate (N-1)/Gate (N) overlaps with the time of the active level signal of the reset signal terminal RST (N-1)/RST (N), in the data writing phase of the pixel driving circuit in the i-th row and the N-th column, the third node N3 in the pixel driving circuit in the i-th row and the N-th column maintains the previous row high level DH, and in the data writing phase of the pixel driving circuit in the N-th column, the previous row high level remaining at the third node N3 in the pixel driving circuit in the N-th column is written into the first node N1 through the third transistor T3 and the second transistor T2, the potential of the first node N1 in the pixel driving circuit in the i-th row and the N-th column is: DH + Vth, when the low level DL is written in the data writing phase in the ith row and the nth column, the potential of the third node N3 is DL, and Vgs represents the voltage difference between the control voltage (the first node N1) and the first voltage (the third node N3) of the third transistor T3, then Vgs-Vth = (DH + Vth) -DL-Vth = DH-DL, and DH > DL causes the third transistor T3 to be turned off, so the low level DL of the third node N3 cannot be written in the first node N1. In the present disclosure, the time of the effective level signal at the scanning signal end overlaps the time of the effective level signal at the reset signal end (i.e., there is the second stage P2), before the data writing stage, the third node N3 is initialized, so that the voltage of the third node N3 in the pixel driving circuits of the ith row and the nth column becomes the initial signal voltage, and the data voltage remained on the upper row of the third node N3 is cleared, and in the data writing stage of the N-1 th column, the third node N3 in the pixel driving circuits of the nth row is the initial signal voltage, so that there is no situation that the upper row of the high level DH is written into the first node N1, and the problem that the data voltage signal of the low level cannot be written can be effectively avoided.

The disclosed embodiment also provides a display device, which may include: a display panel.

The display panel is provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and are not described herein again.

In an exemplary embodiment, the Display device may be a Liquid Crystal Display (LCD) device, an Organic Light Emitting Diode (OLED) device, or a Light Emitting Diode (LED) Display device. The display device may be: the display device includes any product or component having a display function, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

According to the display panel and the display device, the time for receiving the effective level signal by the scanning signal end and the time for receiving the effective level signal by the reset signal end in the pixel driving circuit are partially overlapped, so that the data signal can be smoothly written into the pixel driving circuit, and the technical problem of abnormal data signal writing in the prior art is solved.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the purpose of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. A display panel comprising pixel cells arranged in an array, each pixel cell comprising: a light emitting element and a pixel driving circuit configured to drive the light emitting element to emit light; the pixel driving circuit includes: the device comprises a driving sub-circuit, an initial signal end, a reset signal end, a scanning signal end, a data signal end, a multiplexing signal line, a data output line, a multiplexing circuit, a reset sub-circuit, a writing sub-circuit and a compensation sub-circuit;

the multiplexing circuit is connected with the data output line, the multiplexing signal line and the data signal end and is configured to output the data signal of the data output line to the data signal end under the control of the multiplexing signal line;

the driving sub-circuit is connected with the first node, the second node and the third node;

the reset sub-circuit is connected with the initial signal end, the reset signal end and the first node and is set to write the initial signal of the initial signal end into the first node under the control of the reset signal end;

the write-in sub-circuit is connected with the scanning signal end, the data signal end and the third node, and is configured to write a signal of the data signal end into the third node under the control of the scanning signal end;

the compensation sub-circuit is connected with the scanning signal end, the first node and the second node and is arranged to provide a signal of the second node for the first node under the control of the scanning signal end;

the time when the scanning signal end receives the effective level signal is partially overlapped with the time when the reset signal end receives the effective level signal, and the time when the reset signal end receives the effective level signal is earlier than the time when the scanning signal end receives the effective level signal;

the time of the overlapping part of the time when the scanning signal end receives the effective level signal and the time when the reset signal end receives the effective level signal is earlier than the time when the multiplexing signal line receives the effective level signal;

in a time period when the scanning signal end and the reset signal end receive the effective level signal, the pixel driving circuit uses the signal of the initial signal end to initialize the third node under the control of the scanning signal end and the reset signal end.

2. The display panel according to claim 1, wherein a time length of an overlapping portion of a time when the scan signal terminal receives the active level signal and a time when the reset signal terminal receives the active level signal is greater than or equal to 1 μ sec.

3. The display panel according to claim 1, wherein the pixel driving circuit further comprises: a driving sub-circuit and a light emitting sub-circuit;

the reset sub-circuit is also connected with the first pole of the light-emitting element and is used for writing the initial signal of the initial signal end into the first pole of the light-emitting element under the control of the reset signal end;

the compensation sub-circuit is also connected with the first power supply end and is set to provide the signal of the second node to the first node under the control of the scanning signal end until the signal of the first node meets the threshold condition;

a driving sub-circuit configured to supply a driving current to the second node according to signals of the first node and the third node;

a light-emitting sub-circuit, which is respectively connected with the first power end, the second node, the third node, the light-emitting signal end and the first pole of the light-emitting element, and is configured to write the signal of the first power end into the third node and write the signal of the second power end into the first pole of the light-emitting element under the control of the light-emitting signal end;

4. The display panel according to claim 3, wherein the reset sub-circuit includes a first transistor and a seventh transistor;

5. The display panel according to claim 3, wherein the write sub-circuit includes a fourth transistor;

6. The display panel according to claim 3, wherein the compensation sub-circuit comprises a second transistor and a first capacitor;

7. The display panel according to claim 3, wherein the driving sub-circuit comprises a third transistor;

8. The display panel according to claim 3, wherein the light emitting sub-circuit comprises a fifth transistor and a sixth transistor;

9. The display panel according to claim 3, wherein the reset sub-circuit includes a first transistor and a seventh transistor; the write subcircuit includes a fourth transistor; the compensation sub-circuit comprises a second transistor and a first capacitor; the driving sub-circuit includes a third transistor; the light emitting sub-circuit comprises a fifth transistor and a sixth transistor;

10. The display panel according to claim 9, wherein the types of the first to seventh transistors are P-type transistors or N-type transistors, or wherein the types of the first to seventh transistors include P-type transistors and N-type transistors.

11. The display panel according to any one of claims 1 to 10, further comprising a scan driving circuit, a reset driving circuit, m rows of scan signal lines, m rows of reset signal lines, n columns of data signal lines; the pixel driving circuit further includes: a data signal terminal;

the ith column of data signal lines are positioned on one side of the ith column of pixel units, the data signal ends of the pixel driving circuits of the ith column of pixel units are electrically connected with the ith column of data signal lines, and i is more than or equal to 1 and less than or equal to n;

12. The display panel according to claim 11, comprising z multiplexed signal lines and k columns of data output lines, k = n/z, n and z are positive integers greater than or equal to 2, and n is an integer multiple of z;

13. The display panel according to claim 12, wherein a time at which the scan signal terminal receives an active level signal and a time at which the reset signal terminal receives an active level signal overlap each other is earlier than a time at which the z multiplexing signal lines receive an active level signal.

14. The display panel according to claim 12, wherein z has a value of 2, wherein the multiplexing signal line includes a first multiplexing signal line and a second multiplexing signal line, and wherein the multiplexing circuit includes k first multiplexing transistors and k second multiplexing transistors;

15. The display panel according to claim 3, wherein the pixel driving circuit initializes the first electrode of the light emitting element with a signal of an initialization signal terminal under control of an active level signal received by a reset signal terminal before a period in which a scan signal terminal overlaps with the active level signal received by the reset signal terminal, ensuring that the light emitting element does not emit light.

16. A display device characterized by comprising the display panel according to any one of claims 1 to 15.