CN109801594B - Display panel and display device - Google Patents
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- CN109801594B CN109801594B CN201711144711.6A CN201711144711A CN109801594B CN 109801594 B CN109801594 B CN 109801594B CN 201711144711 A CN201711144711 A CN 201711144711A CN 109801594 B CN109801594 B CN 109801594B
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Abstract
The invention discloses a display panel and a display device. The multiplexer in the display panel is used for transmitting the data signals input by the input end to the data lines electrically connected with the data signals one by one in the stage that the scanning lines output the scanning signals so as to charge the storage capacitors in the corresponding pixel circuits. The invention changes the capacitance value of the storage capacitor in the pixel circuit corresponding to the pixel which emits light when a scanning line outputs a scanning signal, so that the capacitance value of the storage capacitor in the pixel circuit which is charged first is larger than that of the storage capacitor in the pixel circuit which is charged later, the problem that the storage capacitor in the pixel circuit is charged by the voltage stored by the parasitic capacitor on the data line, so that the storage voltage on the storage capacitor in the pixel circuit corresponding to the pixel which emits light when the same scanning line outputs the scanning signal is different is solved, the uniformity of the brightness of the OLED display panel is improved, and the yield of the OLED display panel is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
An Organic Light Emitting Diode (OLED) display employs a very thin Organic material film layer and a glass substrate, and when a current flows, the Organic material emits Light. Therefore, the OLED display can save electric energy remarkably and can be made lighter and thinner.
In addition to the organic light emitting diode, a pixel circuit capable of providing a condition for the continuous lighting of the OLED is required in the OLED panel, and a capacitor is generally used in the pixel circuit to store a data voltage transmitted by the data line. When the scanning line outputs a scanning signal, the data line writes a data voltage into the storage capacitor. With the increase in screen size and the demand for high-resolution display devices, an increase in data leads and driving chips is inevitable. To reduce the number of pins, a multiplexer is usually used to solve the problem of excessive data pins.
When the display panel has a multiplexer, the multiplexer has a plurality of output terminals, and each output terminal is connected to one data line. When the scanning line is opened, the data line charges the storage capacitor, and the data line has a parasitic capacitor, so that when the output end corresponding to the data line does not provide data voltage any more, the voltage stored by the parasitic capacitor on the data line still charges the storage capacitor in the pixel circuit, which causes different charging time of the pixel circuit corresponding to different output ends of the multiplexer, and different storage voltage on the storage capacitor, resulting in different luminance for driving the OLED to emit light, and poor uniformity.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for solving the problem of inconsistent charging time of storage capacitors in different pixel circuits caused by parasitic capacitors on data lines, improving the uniformity of the brightness of an OLED display panel and improving the yield of the OLED display panel.
In a first aspect, an embodiment of the present invention provides a display panel, including:
a plurality of scanning lines extending along a first direction and arranged along a second direction; a plurality of data lines extending in the second direction and arranged in the first direction; wherein the first direction and the second direction intersect; the scanning lines and the data lines define a plurality of pixels, and each pixel comprises a pixel circuit; the pixel circuit comprises at least one storage capacitor, a first switching transistor, a driving transistor and a light-emitting element, wherein the driving transistor is used for providing driving current to drive the light-emitting element to emit light, the first switching transistor is used for writing data signal voltage on the data line corresponding to the pixel circuit into a first pole of the storage capacitor, and the storage capacitor is used for keeping the grid voltage of the driving transistor; the scanning lines are used for outputting scanning signals to the corresponding pixel circuits one by one;
the multiplexer comprises a plurality of multiplexer units, each multiplexer unit comprises an input end and n output ends, each output end is electrically connected with the corresponding pixel circuit through one data line and used for transmitting the data signals input by the input ends to the electrically connected data lines one by one in a phase that the scanning lines output scanning signals so as to charge the storage capacitors in the corresponding pixel circuits; wherein n is a positive integer greater than or equal to 2;
in a phase of any one of the scanning lines outputting a scanning signal, the capacitance value of the storage capacitor in the pixel circuit which is charged first is larger than that of the storage capacitor in the pixel circuit which is charged later.
Further, the multiplexing unit further includes:
the first poles of the n second switch transistors are electrically connected with the input end of the multi-path selection unit, the second poles of the n second switch transistors are electrically connected with the n output ends of the multi-path selection unit respectively, and the grids of the n second switch transistors are electrically connected with the first to n control signal lines respectively.
Furthermore, the capacitance values of the storage capacitors in the pixel circuits corresponding to the second switching transistors electrically connected to the same control signal line are equal.
Furthermore, in a scanning signal period, the first to nth control signal lines output pulse signals in sequence, and the first to nth second switching transistors are turned on in sequence.
Further, a first pole of the storage capacitor is electrically connected with the grid electrode of the driving transistor, and a second pole of the storage capacitor is used for inputting a fixed level signal;
the grid electrode of the second switch transistor is electrically connected with the scanning line corresponding to the pixel circuit and is used for writing the data signal voltage on the data line corresponding to the pixel circuit into the first electrode of the storage capacitor.
Further, the display panel further comprises a light emission control signal line, a first power supply voltage signal line and a second power supply voltage signal line; the pixel circuit further includes: a third switching transistor, a fourth switching transistor, and a fifth switching transistor;
a first electrode of the first switching transistor is electrically connected to the data line corresponding to the pixel circuit, a second electrode thereof is electrically connected to a first electrode of the driving transistor and a second electrode of the fifth switching transistor, and a gate electrode thereof is electrically connected to the scan line;
a second pole of the driving transistor is electrically connected with a first pole of the third switching transistor and a second pole of the fourth switching transistor, and a gate electrode is electrically connected with a first pole of the fourth switching transistor and a second pole of the storage capacitor;
a grid electrode of the fourth switching transistor is electrically connected with the scanning line;
a first electrode of the fifth switching transistor is electrically connected to the first power supply voltage signal line and a first electrode of the storage capacitor, and a gate electrode thereof is electrically connected to the emission control signal line;
a second pole of the third switching transistor is electrically connected to the first pole of the light emitting element and a gate thereof is electrically connected to the emission control signal line;
the second pole of the light emitting element is electrically connected to the second power voltage signal line.
Further, the first to fifth switching transistors and the driving transistor are P-type transistors.
Further, a parasitic capacitance exists on the data line.
Further, the capacitance values of the storage capacitors in the pixel circuits electrically connected to the same data line are equal.
Further, in a frame of display, the difference rate of the charging voltage of the storage capacitor of different pixel circuits electrically connected with the data line transmitting the data signal with the same size is less than or equal to 2%.
In a second aspect, embodiments of the present invention further provide a display device, where the display device includes the display panel provided in any embodiment of the present invention.
The invention changes the capacitance value of the storage capacitor in the pixel circuit corresponding to the pixel which emits light when a scanning line outputs a scanning signal, so that the capacitance value of the storage capacitor in the pixel circuit which is charged first is larger than that of the storage capacitor in the pixel circuit which is charged later, the problem that the storage capacitor in the pixel circuit is charged by the voltage stored by the parasitic capacitor on the data line, so that the storage voltage on the storage capacitor in the pixel circuit corresponding to the pixel which emits light when the same scanning line outputs the scanning signal is different is solved, the uniformity of the brightness of the OLED display panel is improved, and the yield of the OLED display panel is improved.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a pixel circuit according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating the charging effect of the storage capacitor in different pixel circuits in the prior art.
Fig. 4 is a schematic diagram illustrating an effect of charging a storage capacitor in different pixel circuits according to an embodiment of the present invention.
FIG. 5 is a schematic structural diagram of a multiplexer according to an embodiment of the present invention
Fig. 6 is a timing diagram of control signal lines of a multiplexer and scan lines of a pixel circuit in a display panel according to an embodiment of the present invention.
Fig. 7 is a circuit diagram of another pixel circuit of the display panel according to the embodiment of the invention.
Fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 2 is a circuit diagram of a pixel circuit according to an embodiment of the present invention, which is applicable to the display panel shown in fig. 1. The present embodiment can solve the problem of uneven light emission of the display panel, and referring to fig. 1 and 2, the display panel includes:
a plurality of scanning lines 112 extending in the first direction x and arranged in the second direction y; a plurality of data lines 111 extending in the second direction y and arranged in the first direction x; wherein the first direction x and the second direction y intersect; the plurality of scan lines 112 and the plurality of data lines 111 define a plurality of pixels, each of which includes a pixel circuit; each pixel circuit includes at least one storage capacitor Cst, a first switching transistor M1, a driving transistor Mdr for providing a driving current to drive the light emitting element E1 to emit light, and a light emitting element E1, the first switching transistor M1 for writing a data signal voltage on the data line 111 corresponding to the pixel circuit into a first pole of the storage capacitor Cst; the storage capacitor Cst is used to hold the gate voltage of the drive transistor Mdr; the plurality of scan lines 112 are used for outputting scan signals to the corresponding pixel circuits one by one. The data line corresponding to the pixel circuit is a data line electrically connected with the pixel circuit; the scanning lines corresponding to the pixel circuits are the scanning lines electrically connected with the pixel circuits. For example, each row of pixel circuits is electrically connected to a row of scan lines, and each column of pixel circuits is electrically connected to a column of data lines.
The multiplexer comprises a plurality of multiplexer units 121, each multiplexer unit 121 comprises an input terminal Vin and n output terminals, each output terminal is electrically connected with a corresponding pixel circuit through a data line 111, and the multiplexer is used for transmitting the data signals input by the input terminal Vin to the electrically connected data lines 111 one by one in the stage that the scanning lines 112 output scanning signals so as to charge the storage capacitors Cst in the corresponding pixel circuits; wherein n is a positive integer greater than or equal to 2;
in a stage where any one of the scan lines 112 outputs a scan signal, the capacitance value of the storage capacitor Cst in the pixel circuit that is charged first is greater than the capacitance value of the storage capacitor Cst in the pixel circuit that is charged later.
As shown in fig. 1, a data line D1, a data line D2, a data line D3, and a data line D4 respectively represent the first column data line 111, the second column data line 111, the third column data line 111, and the fourth column data line 111. The scan line G1, the scan line G2, the scan line G3, and the scan line G4 respectively represent the first row scan line 112, the second row scan line 112, the third row scan line 112, and the fourth row scan line 112. The plurality of scan lines 112 are used for outputting scan signals to the corresponding pixel circuits one by one, such as scan line G1 in fig. 1 outputting scan signals to the pixel circuits of the pixels 11-14, i.e. the pixel circuits corresponding to the pixels in the same row, G2 outputting scan signals to the pixel circuits of the pixels 21-24, and so on.
In the display panel, n output terminals of the multiplexing unit 121 are electrically connected to n columns of pixels in a one-to-one correspondence via n data lines 111. As shown in fig. 1, the multiplexing unit 121 has two output terminals, namely a first output terminal Vout1 and a second output terminal Vout2, the pixels (pixel 11, pixel 21, pixel 31, pixel 41, … …) electrically connected to the first output terminal Vout1 of the multiplexing unit 121 through the corresponding data line 111 are P1 type pixels, and the pixels (pixel 12, pixel 22, pixel 32, pixel 42, … …) electrically connected to the second output terminal Vout2 of the multiplexing unit 121 through the corresponding data line 111 are P2 type pixels. The pixel circuit corresponding to the P1-type pixel has the same structure as the pixel circuit corresponding to the P2-type pixel, except that the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the P1-type pixel is different from the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the P2-type pixel.
The multiplexer includes a plurality of multiplexing units 121, and a plurality of output terminals of each multiplexing unit 121 may be electrically connected to the P1-Pn pixels, as shown in fig. 1, each multiplexing unit 121 has two output terminals electrically connected to the P1-Pn pixels and the P2-Pn pixels, respectively.
As shown in fig. 1, if the P1-type pixel is charged first and the P2-type pixel is charged later, the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the P1-type pixel is larger than the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the P2-type pixel. In the present invention, charging a pixel means charging a storage capacitor Cst in a pixel circuit corresponding to the pixel. Fig. 3 is a schematic diagram illustrating an effect of charging storage capacitors in different pixel circuits in the prior art, and fig. 4 is a schematic diagram illustrating an effect of charging storage capacitors in different pixel circuits according to an embodiment of the present invention. The charging curve in fig. 3 may correspond to a case where the capacitance values of the storage capacitors Cst in the pixel circuits of the P1 and P2 pixels are equal, and the charging curve in fig. 4 corresponds to a case where the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the P1 pixel (the pixel circuit included in the P1 pixel) is greater than the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the P2 pixel. When one of the scan lines 112 in the display panel outputs a scan signal to the corresponding pixel circuit, such as the scan line G1 in fig. 1 outputting a scan signal to the corresponding pixel circuit of the pixels 11 and 12, the multiplexing unit 121 transmits the data signal at the input terminal Vin to the data lines 111 electrically connected thereto one by one, i.e., the multiplexing unit 121 sequentially transmits the data signal to the pixel circuits in the pixels 11 and 2 through the data lines D1 and D2, and the pixel circuits corresponding to the pixels 11 and 12 receive the data signal voltages on the data lines D1 and D2, respectively. The first switching transistor M1 in the pixel circuit corresponding to the pixels 11 and 12 is turned on, and then writes the data signal voltage on the corresponding data line 111 into the first electrode of the storage capacitor Cst. The storage voltage on the storage capacitor Cst causes the driving transistor Mdr to generate a driving current, which drives the light emitting element E1 to emit light. Assuming that the multiplexing unit 121 firstly transmits the data signal voltage to the pixel circuit corresponding to the pixel 11 (i.e., the P1 type pixel) through the data line D1, after a certain period of time, the path output to the data line D1 is closed, the writing of the data signal voltage to the pixel 11 is stopped, and then the data signal voltage is transmitted to the pixel circuit corresponding to the pixel 12 (i.e., the P2 type pixel) through the data line D2, and the time for the multiplexing unit 121 to transmit the data signal voltage to the electrically connected pixel circuits through each data line 111 is the same. When the multiplexing unit 121 stops writing the data signal voltage to the pixel 11 and starts writing the data signal voltage to the pixel 12, the voltage stored on the data line D1 continues to charge the storage capacitor Cst in the pixel circuit corresponding to the pixel 11 due to the influence of the parasitic capacitance on the data line D1, so that the charging time of the storage capacitor Cst in the pixel circuit corresponding to the pixel 11 is longer than the charging time of the storage capacitor Cst in the pixel circuit corresponding to the pixel 12. When the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the pixel 11 (the pixel of the P1 class) is equal to the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the pixel 12 (the pixel of the P2 class), as shown in fig. 3, the curve P1-3 is a charging curve of the pixel of the P1 class, and the curve P2-3 is a charging curve of the pixel of the P2 class. Since the capacitance values of the storage capacitors Cst in the pixel circuits corresponding to the pixel 11 (the pixel of P1 type) and the pixel 12 (the pixel of P2 type) are equal, and the charging speeds are the same, when the voltages of the data signals supplied to the data line D1 and the data line D2 are equal, the charged voltage of the storage capacitor Cst in the pixel circuit corresponding to the pixel 11 (the pixel of P1 type) will be greater than the charged voltage of the storage capacitor Cst in the pixel circuit corresponding to the pixel 12 (the pixel of P2 type). A phenomenon of display unevenness will occur. As shown in FIG. 4, the curve P1-4 is the charging curve for the pixel class P1, and the curve P2-4 is the charging curve for the pixel class P2. Although the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the pixel 11 (the P1-type pixel) is larger than the capacitance value of the storage capacitor Cst in the pixel circuit corresponding to the pixel 12 (the P2-type pixel), the parasitic capacitance on the D1 line makes the charging time of the storage capacitor Cst in the pixel circuit corresponding to the pixel 11 by the data line D1 longer, but the charging time of the storage capacitor Cst in the pixel circuit corresponding to the pixel 12 (the P2-type pixel) is faster, and when the voltages of the data signals supplied to the data line D1 and the data line D2 are equal, the charging voltages of the storage capacitors Cst in the pixel circuits corresponding to the pixel 11 (the P1-type pixel) and the pixel 12 (the P2-type pixel) are finally made equal. The problem of inconsistent charging time of storage capacitors in different pixel circuits due to parasitic capacitors on the data lines is solved, so that the display of the display panel is uniform, the uniformity of the brightness of the OLED display panel is improved, and the yield of the OLED display panel is improved.
It should be noted that the magnitude relationship between the capacitance values of the storage capacitors Cst in the pixel circuits corresponding to different types of pixels may be determined by simulation based on the charging time and the current-voltage characteristics of the driving transistors.
In the embodiment of the present invention, the light emitting element E1 can be variously selected under the condition that the present invention is satisfied, and the light emitting element E1 in the present invention is an organic light emitting diode.
According to the technical scheme, the output ends of the multi-path selection units in the multi-path selector in the display panel are electrically connected with the data lines, the capacitance value of the storage capacitor in the pixel circuit which is charged firstly is larger than that of the storage capacitor in the pixel circuit which is charged later by changing the capacitance value of the storage capacitor in the pixel circuit, the problem that due to parasitic capacitors on the data lines, the charging time of the storage capacitors in different pixel circuits is inconsistent, and further the charging voltage of the storage capacitors in different pixel circuits is inconsistent is solved, the uniformity of the brightness of the OLED display panel is improved, and the yield of the OLED display panel is improved.
In addition to the above embodiments, in one frame of display, the charging voltage difference rate of the storage capacitor Cst of different pixel circuits electrically connected to the data line 111 transmitting the data signal with the same magnitude is less than or equal to 2%.
As shown in fig. 1, among the pixels of the P1 type, there are one column corresponding to the pixel 11 and one column corresponding to the pixel 13, and the capacitance values of the storage capacitors Cst in the two pixels are equal, and since the two columns of pixels are both controlled by the control signal line CLK1, the charging time is also the same, but due to inevitable differences in the manufacturing process, the charged voltages cannot be completely equal, but can be very close to each other, and the difference rate of the charged voltages is 2% or less. Assuming that the data voltages of the data signals received by the different types of pixels are the same, for example, the pixels of the P1 type and the P2 type receive the data signals of the same magnitude, although the capacitance values of the storage capacitor Cst of the pixel circuit in the pixels of the P1 type and the P2 type are different, the same charging voltage is theoretically obtained after the charging. In the manufacturing process, due to the difference of the manufacturing process, the difference rate of the voltages of the charged different pixels is less than or equal to 2%, and the uniformity and the yield of the display panel are improved.
In the embodiment of the present invention, the capacitance values of the storage capacitors Cst in the pixel circuits electrically connected to the same data line 111 are equal.
In the display panel, the storage capacitors Cst in the pixel circuits corresponding to the pixels in the same column in the pixels arranged in the array have the same capacitance value, that is, the storage capacitors Cst in the pixel circuits corresponding to the pixels of the same type have the same capacitance value. As shown in fig. 1, the pixels 11, 21, 31, and 41, … … are electrically connected to the same data line 111, and the capacitance values of the storage capacitors in the pixel circuits of the pixels 11, 21, 31, 41, and … … are equal. The pixel 12, the pixel 22, the pixel 32, the pixel 42, and the pixel … … are electrically connected to the same data line 111, and the capacitance values of the storage capacitors in the pixel circuits of the pixel 12, the pixel 22, the pixel 32, the pixel 42, and the pixel … … are equal, so as to ensure the uniformity of the light emission of the display panel.
On the basis of the above embodiment, with continued reference to fig. 2, in the pixel circuit, the first pole of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor Mdr, and the second pole is used for inputting a fixed-level signal, for example, electrically connected to the first power voltage line ELVDD.
The gate of the first switching transistor M1 is electrically connected to the scan line 112 corresponding to the pixel circuit, and is used for writing the data signal voltage on the data line 111 corresponding to the pixel circuit into the first pole of the storage capacitor Cst, where the first pole is electrically connected to the data line 111 and the second pole is electrically connected to the first pole of the storage capacitor Cst.
The first pole of the driving transistor Mdr is electrically connected to the first power voltage line ELVDD, and the second pole is electrically connected to the anode of the light emitting element E1.
The cathode of the light emitting element E1 is electrically connected to the first secondary power voltage line ELVSS.
As shown in fig. 2, when the scan line 112 outputs a scan signal, the first switching transistor M1 of the corresponding pixel circuit is turned on, the first switching transistor M1 writes the data signal voltage on the data line 111 corresponding to the pixel circuit into the first electrode of the storage capacitor Cst, the storage voltage on the storage capacitor Cst is written into the gate of the driving transistor, and the driving transistor Mdr generates a driving current to drive the light emitting element E1 to emit light; when the scan line 112 does not output the scan signal, the first switching transistor M1 is turned off, and the driving transistor continues to generate the driving current due to the voltage stored in the storage capacitor Cst, so that the light emitting element E1 is driven to continuously emit light.
On the basis of the above technical solution, the multiplexing unit 121 further includes:
the first poles of the n second switching transistors are all electrically connected with the input end Vin of the multi-path selection unit 121, the second poles of the n second switching transistors are respectively electrically connected with the n output ends Vout of the multi-path selection unit 121, and the gates of the n second switching transistors are respectively electrically connected with the first to n control signal lines.
During the period that one scanning line outputs the scanning signal, the first to nth control signal lines output the pulse signal in sequence, and the first to nth second switching transistors are turned on in sequence.
For example, fig. 5 is a schematic structural diagram of a multiplexer according to an embodiment of the present invention, and as shown in fig. 5, the multiplexer includes 2 multiplexer units 121, and each multiplexer unit 121 includes 2 second switching transistors, which are a first second switching transistor M2-1 and a second switching transistor M2-2, respectively. The first and second switching transistors M2-1 and M2-2 have first poles electrically connected to the input terminal Vin and second poles electrically connected to the output terminal Vout, respectively, and first and second gates of the first and second switching transistors M2-1 and M2-2 are electrically connected to the control signal line CLK1 and the control signal line CLK2, respectively. In one scanning signal period, the control signal line CLK1 and the control signal line CLK2 sequentially output pulse signals to control the first second switching transistor M2-1 and the second switching transistor M2-2 to be sequentially turned on. When one second switching transistor in each of the multiplexing units 121 is turned on, the other second switching transistors are turned off.
Fig. 6 is a timing diagram of control signal lines of a multiplexer and scan lines of a pixel circuit in a display panel according to an embodiment of the present invention. Referring to fig. 5 and 6, at the stage t1, when one of the plurality of scan lines 112 outputs a scan signal to a corresponding pixel circuit, the first switching transistor M1 of the corresponding pixel circuit is turned on. Illustratively, when the scan line G1 outputs a scan signal, the control signal line CLK1 outputs an active signal prior to the control signal line CLK2 at the stage t1, and therefore, at the stage t2, the control signal line CLK1 controls the second switching transistor M2-1 and the second switching transistor M2-3 connected thereto to be turned on, the corresponding data line 111, i.e., the data line D1, writes a data signal voltage to the storage capacitor Cst in the pixel circuit corresponding to the pixel 11, and the data line D3 writes a data signal voltage to the storage capacitor Cst in the pixel circuit corresponding to the pixel 13, i.e., charges the storage capacitor Cst in the pixel circuit of the P1 type. At the stage t3, the control signal line CLK2 controls the second switching transistor M2-2 and the second switching transistor M2-4 connected thereto to be turned on, and the corresponding data line 111, i.e., the data line D2 writes the data signal voltage to the storage capacitor Cst in the pixel circuit corresponding to the pixel 12, and the data line D4 writes the data signal voltage to the storage capacitor Cst in the pixel circuit corresponding to the pixel 14, i.e., charges the storage capacitor Cst in the pixel circuit of the P2 type. At the stage t3, even though the second switching transistor M2-1 and the second switching transistor M2-3 are turned off, the data signal voltage is no longer transmitted to the data line D1 and the data line D3, and the data signal voltage stored in the data line D1 and the data line D3 continues to charge the pixels 11 and 13, that is, the pixels of the P1 class, due to the parasitic capacitance on the data line. Therefore, the charging time of the storage capacitor Cst in the pixel circuit of the P1 type is longer than that of the storage capacitor Cst in the pixel circuit of the P2 type, and as shown in fig. 3, the curve P1-3 is the charging curve of the pixel of the P1 type, and the curve P2-3 is the charging curve of the pixel of the P2 type. In the invention, the capacitance value of the storage capacitor Cst in the P1 type pixel circuit is larger than that of the storage capacitor Cst in the P2 type pixel circuit, the charging speed of the storage capacitor Cst in the P2 type pixel circuit is high, as shown by a curve P1-4 and a curve P2-4 in FIG. 4, a curve P1-4 is a charging curve of a P1 type pixel, and a curve P2-4 is a charging curve of a P2 type pixel. The slope of the curve P2-4 is large, indicating that the storage capacitor Cst in the pixel circuit of the P2 class pixel is charged fast. The charging voltage of the storage capacitor Cst is equal to the product of the charging time and the charging speed, so that the charging voltages of the storage capacitor Cst in the pixel circuits of the P1 and the P2 classes can be made the same at different times, i.e. the corresponding voltage values after charging as shown by the curve P1-4 and the curve P2-4 in fig. 4 are equal.
On the basis of the above embodiment, the capacitance values of the storage capacitors Cst in the pixel circuits corresponding to the second switch transistors electrically connected to the same control signal line are equal.
As shown in fig. 5, the multiplexer includes two multiplexer units 121, and each multiplexer unit 121 includes two second switching transistors. The two multiplexing units 121 have four second switching transistors M2-1, M2-2, M2-3 and M2-4, respectively, M2-1 and M2-3 are controlled to be turned on and off by a control signal line CLK1, and the storage capacitors Cst in the pixel circuits corresponding to the second switching transistors M2-1 and M2-3 are charged for the same time. The second switching transistors M2-2 and M2-4 are controlled to be turned on and off by the control signal line CLK2, and the storage capacitors Cst in the pixel circuits corresponding to the second switching transistors M2-2 and M2-4 are charged for the same time. The capacitance values of the storage capacitors Cst in the pixel circuits corresponding to the second switching transistors M2-1 and M2-3, M2-2 and M2-4 are respectively equal, so that it can be ensured that the charging voltages of the storage capacitors Cst in the pixel circuits corresponding to the second switching transistors M2-1 and M2-3 are equal, and the charging voltages of the storage capacitors Cst in the pixel circuits corresponding to the second switching transistors M2-2 and M2-4 are equal. The charging time of the storage capacitor Cst in the pixel circuit corresponding to different control signal lines Ctrl is different, and the charging voltage adjusts the charging speed by adjusting the capacitance value of the storage capacitor Cst, so that the final charging voltages of different pixel circuits are the same. Therefore, the charged voltages of different pixels are close to or equal to each other in the stage t1, the uniformity of the brightness of the pixels emitting light is improved, and the yield of the display panel is improved.
Fig. 7 is a circuit diagram of another pixel circuit of a display panel according to an embodiment of the present invention, where the display panel further includes a light-emitting control signal line 113 based on the above embodiments; the pixel circuit further includes third, fourth, and fifth switching transistors (M3-M5).
A first pole of the first switching transistor M1 is electrically connected to the data line 111 corresponding to the pixel circuit, a second pole is electrically connected to the first pole of the driving transistor Mdr and the second pole of the fifth switching transistor M5, and a gate is electrically connected to the scan line 112;
a second pole of the driving transistor Mdr is electrically connected to the first pole of the third switching transistor M3 and the second pole of the fourth switching transistor M4, and a gate electrode is electrically connected to the first pole of the fourth switching transistor M4 and the second pole of the storage capacitor Cst;
the gate of the fourth switching transistor M4 is electrically connected to the scan line 112;
a first pole of the fifth switching transistor M5 is electrically connected to the first power voltage signal line ELVDD and the first pole of the storage capacitor Cst, and a gate electrode is electrically connected to the light emission control signal line 113;
a second pole of the third switching transistor M3 is electrically connected to the first pole of the light emitting element E1, and a gate thereof is electrically connected to the light emission control signal line 113;
the second pole of the light emitting element E1 is electrically connected to the second power supply voltage signal line ELVSS.
The second electrode of the storage capacitor Cst is electrically connected to the first power voltage line ELVDD for inputting a fixed level signal. When the scan line 112 outputs the scan signal, the first switching transistor M1 and the fourth switching transistor M4 are turned on, and the data signal voltage on the data line 111 is written to the first pole of the driving transistor Mdr. After the light emission control signal line 113 outputs the light emission signal, the third switching transistor M3 and the fifth switching transistor M5 are turned on, the driving transistor Mdr is also turned on by the voltage change at the point N1, and the data signal voltage stored in the driving transistor Mdr continuously generates a driving current through the third switching transistor M3 and is transmitted to the light emitting element E1, so that the light emitting element E1 continuously emits light.
It should be noted that the pixel circuit in the above embodiments is only an example, and is not limited. The pixel circuit which adopts the storage capacitor for charging is within the protection scope of the invention.
On the basis of the respective embodiments described above, the first to fifth switching transistors M1 to M5 and the drive transistor Mdr may all be P-type transistors. The first to fifth switching transistors M1 to M5 and the driving transistor Mdr may be N-type transistors, and the transistors are turned on when the gates thereof receive a high level.
Fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 8, the display device 810 includes the display panel 811 according to any one of the embodiments, which has the same functions and advantages.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (11)
1. A display panel, comprising:
a plurality of scanning lines extending along a first direction and arranged along a second direction; a plurality of data lines extending in the second direction and arranged in the first direction; wherein the first direction and the second direction intersect; the scanning lines and the data lines define a plurality of pixels, and each pixel comprises a pixel circuit; the pixel circuit comprises at least one storage capacitor, a first switching transistor, a driving transistor and a light-emitting element, wherein the driving transistor is used for providing driving current to drive the light-emitting element to emit light, the first switching transistor is used for writing data signal voltage on the data line corresponding to the pixel circuit into a first pole of the storage capacitor, and the storage capacitor is used for keeping the grid voltage of the driving transistor; the scanning lines are used for outputting scanning signals to the corresponding pixel circuits one by one;
the multiplexer comprises a plurality of multiplexer units, each multiplexer unit comprises an input end and n output ends, each output end is electrically connected with the corresponding pixel circuit through one data line and used for transmitting the data signals input by the input ends to the electrically connected data lines one by one in a phase that the scanning lines output scanning signals so as to charge the storage capacitors in the corresponding pixel circuits; wherein n is a positive integer greater than or equal to 2;
in a phase of any one of the scanning lines outputting a scanning signal, the capacitance value of the storage capacitor in the pixel circuit which is charged first is larger than that of the storage capacitor in the pixel circuit which is charged later.
2. The display panel according to claim 1, wherein the multiplexing unit further comprises:
the first poles of the n second switch transistors are electrically connected with the input end of the multi-path selection unit, the second poles of the n second switch transistors are electrically connected with the n output ends of the multi-path selection unit respectively, and the grids of the n second switch transistors are electrically connected with the first to n control signal lines respectively.
3. The display panel according to claim 2, wherein the capacitance values of the storage capacitors in the pixel circuits corresponding to the second switch transistors electrically connected to the same control signal line are equal.
4. The display panel according to claim 2, wherein in one scanning signal period, the first to nth control signal lines sequentially output pulse signals, and the first to nth second switching transistors are sequentially turned on.
5. The display panel according to claim 1, wherein a first pole of the storage capacitor is electrically connected to a gate of the driving transistor, and a second pole of the storage capacitor is used for inputting a fixed level signal;
the grid electrode of the first switch transistor is electrically connected with the scanning line corresponding to the pixel circuit and is used for writing the data signal voltage on the data line corresponding to the pixel circuit into the first pole of the storage capacitor.
6. The display panel according to claim 5, wherein the display panel further comprises a light emission control signal line, a first power supply voltage signal line, and a second power supply voltage signal line; the pixel circuit further comprises a third switching transistor, a fourth switching transistor and a fifth switching transistor;
a first electrode of the first switching transistor is electrically connected to the data line corresponding to the pixel circuit, a second electrode thereof is electrically connected to a first electrode of the driving transistor and a second electrode of the fifth switching transistor, and a gate electrode thereof is electrically connected to the scan line;
a second pole of the driving transistor is electrically connected with a first pole of the third switching transistor and a second pole of the fourth switching transistor, and a gate electrode is electrically connected with a first pole of the fourth switching transistor and a second pole of the storage capacitor;
a grid electrode of the fourth switching transistor is electrically connected with the scanning line;
a first electrode of the fifth switching transistor is electrically connected to the first power supply voltage signal line and a first electrode of the storage capacitor, and a gate electrode thereof is electrically connected to the emission control signal line;
a second electrode of the third switching transistor is connected to the first electrode of the light emitting element, and a gate electrode thereof is electrically connected to the emission control signal line;
the second pole of the light emitting element is electrically connected to the second power voltage signal line.
7. The display panel according to claim 6, wherein the first to fifth switching transistors and the driving transistor are P-type transistors.
8. The display panel according to claim 1, wherein a parasitic capacitance exists on the data line.
9. The display panel according to claim 1, wherein capacitance values of storage capacitors in the pixel circuits electrically connected to the same data line are equal.
10. The display panel according to claim 1, wherein a difference rate of charging voltages of storage capacitors of different pixel circuits electrically connected to the data lines transmitting data signals of the same magnitude is 2% or less in one frame of display.
11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.
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| CN110211542A (en) * | 2019-06-10 | 2019-09-06 | 厦门天马微电子有限公司 | Liquid crystal display device and its driving method |
| CN110322827B (en) * | 2019-08-15 | 2022-05-10 | 成都辰显光电有限公司 | Digital driving method of display panel and display panel |
| CN113870771B (en) * | 2021-09-30 | 2023-01-17 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN113707081B (en) * | 2021-10-29 | 2022-01-14 | 惠科股份有限公司 | Display panel driver and display device |
| CN116868262A (en) * | 2021-11-24 | 2023-10-10 | 京东方科技集团股份有限公司 | Display substrate, driving method thereof and display device |
| CN116758865A (en) * | 2023-06-29 | 2023-09-15 | 重庆惠科金渝光电科技有限公司 | Display panel, driving method thereof and electronic equipment |
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