WO2021115458A1

WO2021115458A1 - Scan and light emission driving circuit, scan and light emission driving system, and display panel

Info

Publication number: WO2021115458A1
Application number: PCT/CN2020/135938
Authority: WO
Inventors: 郑志伟; 白维
Original assignee: 华为技术有限公司
Priority date: 2019-12-13
Filing date: 2020-12-11
Publication date: 2021-06-17
Also published as: CN113066422A; CN113066422B

Abstract

A scan and light emission driving circuit (103u), comprising a first control circuit (11), a second control circuit (12), a scan drive output circuit (14), and a light emission drive output circuit (13). The first control circuit (11) is electrically connected to the scan drive output circuit (14) and the light emission drive output circuit (13) and is used for controlling the scan drive output circuit (14) to output a scan signal in a data writing period in one scan cycle. The second control circuit (12) is electrically connected to the light emission drive output circuit (13) and is used for controlling the light emission drive output circuit (13) to output a light emission signal in a light emission period in the scan cycle. Also provided is a display panel (10) comprising the scan and light emission driving circuit (103u), satisfying design requirements for a narrow edge frame and a high screen-to-body ratio.

Description

Scanning and light-emitting drive circuit, scanning and light-emitting drive system, display panel

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office, the application number is 201911297349.5, and the application name is "scanning and light-emitting drive circuit, scanning and light-emitting drive system, display panel" on December 13, 2019, and its entire content Incorporated in this application by reference.

Technical field

This application relates to the field of image display technology, in particular to the technical field of scanning and light-emitting drive circuits, scanning and light-emitting drive systems, and display panels.

Background technique

During the image display process of the self-luminous display panel, a scanning driving circuit arranged in a non-display area is required to provide scanning signals and a light-emitting signal to cooperate with the data driving circuit to provide image data signals to drive the pixel array arranged in the image display area to perform image display. In recent years, in order to improve the integration of display panels, gate scan driving circuits, light emitting scan driving circuits, and pixel arrays have been fabricated on an array substrate, also known as gate drive array substrates (GOA, Gate on Array) and light emitting Array (EOA, Emission on Array) circuit.

Each scan driving circuit includes a plurality of scan and light-emitting driving circuits, which are usually designed in a cascaded form to sequentially output the shifted scan signals to the pixel array. Among them, each scan driving circuit includes a GOA circuit and an EOA circuit that are independent of each other. As a result, the existing scan driving circuit has more electronic components and larger volume, so that the area of the non-display area cannot be reduced, resulting in a relatively small screen occupancy of the display panel and cannot meet the requirements of a narrow frame.

Summary of the invention

In the embodiments of the present application, a scanning and light-emitting drive circuit and a scanning and light-emitting drive system with fewer electronic components and a smaller volume are provided, so that the display panel including the aforementioned light-emitting drive circuit can meet the requirements of narrow frame and high screen-to-body ratio. Design requirements.

In the first aspect, in a possible implementation manner, the scanning and light-emitting drive circuit includes a first control circuit, a second control circuit, a scan drive output circuit, and a light-emitting drive output circuit. The first control circuit is electrically connected to the scan drive output circuit and the light-emitting drive output circuit, and is used for controlling the scan drive output circuit to output a scan signal during a data writing period of a scan period. To control the pixel unit to receive image data. The second control circuit is electrically connected to the light-emitting drive output circuit, and is used for controlling the light-emitting drive output circuit to output a light-emitting signal during the light-emitting period of the scanning period, and the light-emitting signal is used to control the pixel unit The time at which the image data is displayed.

The scanning and light-emitting drive circuit cooperates with the first control circuit and the second control circuit to control the scan drive circuit to output scanning signals and control the light-emitting drive circuit to output light-emitting signals in different time periods. That is to say, the scanning and light-emitting drive circuit share the first control circuit and the second control circuit, and the same circuit is used to output the scanning signal and the light-emitting signal in time, thereby effectively reducing the amount of electronic components in the scanning and light-emitting drive circuit. The number, volume, and occupied area provide greater possibilities for reducing the area of the area where the scanning and light-emitting drive circuit is provided.

In a possible implementation manner, the first control circuit is electrically connected to the scan drive output circuit through a pull-down node; during the data writing period, the first control circuit receives a first clock signal, and Adjusting the potential of the pull-down node according to the first clock signal. The scan drive output circuit receives a pre-start scan signal and a second clock signal under the control of the potential of the pull-down node, and outputs the scan signal according to the pre-start scan signal and the second clock signal. The second control circuit is electrically connected to the light-emitting drive output circuit through the pull-up node, and during the light-emitting period, the second control circuit receives a third clock signal and responds to the third clock signal Adjust the potential of the pull-up node. In the light-emitting period, the light-emitting drive output circuit outputs a first reference voltage in the light-emitting signal under the control of the potential of the pull-up node, and the first reference voltage is used to control the display of the pixel unit The time of the image data.

Specifically, the first control circuit is also electrically connected to the light-emitting drive output circuit through a pull-up node; during the data writing time period, the first control circuit receives a first clock signal, and according to the The first clock signal adjusts the potential of the pull-up node. In the data writing period, the light-emitting drive output circuit receives a second clock signal under the control of the potential of the pull-up node, and outputs a second reference voltage in the light-emitting signal according to the second clock signal The second reference voltage is used to control the pixel unit to stop displaying the image data.

Specifically, the second control circuit is also electrically connected to the scan drive output circuit through the pull-down node; during the light-emitting time period, the second control circuit receives the third clock signal, and according to the The third clock signal adjusts the potential of the pull-down node. During the light-emitting period, the scan drive output circuit stops outputting the scan signal under the control of the potential of the pull-down node.

In the foregoing implementation manner, the first control circuit and the second control circuit control the voltages of the pull-up node and the pull-down node, so that the scan driving circuit output and the light-emitting driving circuit accurately output the scan signal light-emitting signal in different time periods.

In a possible implementation manner, when the voltage of the pull-up node is the second potential, the first control circuit controls the voltage of the pull-down node to the first potential. When the voltage of the pull-up node is at the first potential, the pull-down node is controlled to the second potential by a first inverter circuit connected between the pull-up node and the pull-down node. Through the setting of the first inverter circuit, it is possible to accurately control the pull-down node to the first potential, thereby ensuring that the pull-down node is accurately maintained at the second potential without the first control circuit during the period when the pull-up node is at the first potential. It is easier to control the first control circuit.

In a possible implementation manner, the light-emitting drive output circuit includes a light-emission pull-up output circuit and a light-emission pull-down output circuit. The control terminal of the light-emitting pull-up output circuit is electrically connected to the pull-up node, the input terminal is electrically connected to the first reference voltage terminal, and the first reference voltage terminal is used to provide the first reference voltage, The output terminal of the light-emitting pull-up output circuit is used to output the light-emitting signal. In the light-emitting period, under the control of the potential of the pull-up node, the output terminal of the light-emitting pull-up output circuit outputs the first reference voltage. The control terminal of the light-emitting pull-down output circuit is electrically connected to the pull-down node, and the input terminal is electrically connected to a second reference voltage terminal, and the second reference voltage terminal is used to provide the second reference voltage. In the data writing period, under the control of the potential of the pull-down node, the output terminal of the light-emitting pull-down output circuit outputs the second reference voltage, and the light-emitting signal includes the first reference voltage and the The second reference voltage.

In the light-emitting drive output circuit, the light-emission pull-up output circuit and the light-emission pull-down output circuit output different reference voltages in different time periods under the control of the pull-up node and the pull-down node voltage respectively, thereby being able to accurately output the light-emitting signal during the data writing period Control the voltage of the pixel unit to receive the image data, and control the voltage of the pixel unit to stop receiving the image data in the light-emitting period outputting the light-emitting signal.

In a possible implementation manner, the scan drive output circuit includes a scan pull-up output circuit and a scan pull-down output circuit. Wherein, the control terminal of the scan pull-up output circuit is electrically connected to the pull-up node, and the input terminal is electrically connected to the second reference voltage terminal. In the light-emitting period, under the control of the potential of the pull-up node, the output terminal of the scan pull-up output circuit outputs a fourth reference voltage, and the fourth reference voltage is used to control the pixel unit to stop receiving The image data. The control terminal of the scan pull-down output circuit is electrically connected to the pull-down node, the input terminal is electrically connected to the second clock terminal to receive the second clock signal, and the output terminal is electrically connected to the scan signal output terminal. In the data writing period, under the control of the potential of the pull-down node, the output terminal of the scan pull-up output circuit outputs the third reference voltage, and the third reference voltage is used to control the pixel The unit receives the image data, and the scan signal includes the third reference voltage and the fourth reference voltage.

In the scan drive output circuit, the scan pull-up output circuit and the scan pull-down output circuit output different reference voltages in different time periods under the control of the pull-up node and the pull-down node voltage, respectively, thereby being able to accurately output the scan signal during the data writing period Control the pixel unit to receive the voltage of the image data, and control the pixel unit to stop receiving the voltage of the image data in the light-emitting period outputting the scan signal.

In a possible implementation manner, the scanning and light emission drive circuit further includes a pulse width control circuit, and the pulse width control circuit is electrically connected to the light emission drive output circuit for controlling the light emission in the light emission signal. The pull-up output unit outputs the frequency of the first reference voltage and controls the light-emitting pull-down output unit to output the frequency of the second reference voltage, and the frequency of the first reference voltage and the second reference voltage output are the same. The number of times of outputting the first reference voltage in the light-emitting period is greater than one.

During the light-emitting period, the duty cycle of the light-emitting signal can be flexibly adjusted at any time, instead of continuously driving the pixel unit to display at the same voltage (duty cycle is 100%), then, during the light-emitting display period of the pixel unit , The brightness of the pixel unit can be adjusted by adjusting the output frequency of the first reference voltage that controls the pixel unit to perform image display in the light-emitting signal, thereby effectively preventing the display frequency of the pixel unit from being unable to match the current image refresh frequency and causing stroboscopic flicker phenomenon.

In a possible implementation manner, the pulse width control circuit includes a first pulse width control circuit and a second pulse width control circuit. The control terminal of the first pulse width control circuit receives the first pulse width signal with the first duty cycle, the input terminal is electrically connected to the first reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-up output circuit; The first pulse width control circuit is turned on under the control of a first pulse width signal. During the light-emitting period, when the first pulse width control circuit is turned on, the first reference voltage passes through the first pulse Wide control circuit and output from the output terminal of the light-emitting pull-up output circuit. The control terminal of the second pulse width control circuit receives a second pulse width signal with a second duty cycle, the input terminal is electrically connected to the second reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-down output circuit, the The second pulse width control circuit is turned on under the control of the second pulse width signal. During the data writing period, when the second pulse width control circuit is turned on, the second reference voltage passes through the second The pulse width control circuit is output from the output terminal of the light-emitting pull-down output circuit; the sum of the first duty cycle and the second duty cycle is 1, the first pulse width signal and the second pulse The phase of the wide signal is opposite.

During the light-emitting period, the duty cycle of the light-emitting signal can be flexibly adjusted at any time with the first pulse signal and the second pulse signal. Then, during the light-emitting display period of the pixel unit, the first pulse signal and the second pulse signal can be adjusted. The duty cycle of the pulse signal is used to accurately adjust the duty cycle of the light-emitting signal, thereby effectively preventing the stroboscopic phenomenon caused by the display frequency of the pixel unit cannot match the current image refresh frequency.

In a possible implementation manner, the first pulse width control circuit includes a first pulse transistor, the gate of the first pulse transistor receives the first pulse control signal, and the source of the first pulse transistor Is electrically connected to the first reference voltage terminal, and the drain of the first pulse transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit. The second pulse width control circuit includes a second pulse transistor, the gate of the second pulse body tube receives the second pulse control signal, and the source of the second pulse transistor is electrically connected to the second reference At the voltage terminal, the drain of the second pulse body tube is electrically connected to the output terminal of the light-emitting pull-down output circuit. The first pulse width control circuit and the second pulse width control circuit respectively use a transistor as a switching element to perform the output control of the first reference voltage and the second reference voltage, so that the structure of the pulse width control circuit is simple, and it is a scanning and light-emitting drive circuit. Simplified components and reduced volume provide more possibilities.

In a possible implementation manner, the scanning and light-emitting drive circuit further includes a reset circuit, and the reset circuit is electrically connected between the pull-up node and the pull-down node for controlling the The potential of the node is pulled up so that the light-emitting drive output circuit stops the light-emitting signal, and the potential of the pull-down node is controlled so that the scan drive output circuit stops outputting the scan signal. By resetting the pull-up node and the pull-down node during the reset period, the potentials of the pull-up node and the pull-down node are in the initial state, which can accurately be at the corresponding potential during the data writing period and the light-emitting period to prevent residue The residual charge on the pull-down node and the pull-down node affects the operation of the light-emitting drive output circuit and the scan drive output circuit.

In a possible implementation manner, the first control circuit includes a first transistor, a third transistor, and a first capacitor. The gate of the first transistor is used for receiving the first clock signal, and the drain of the first transistor is electrically connected to the pull-down node. The source of the third transistor is electrically connected to the second reference voltage terminal to receive the second reference voltage, and the drain of the third transistor is electrically connected to the pull-up node. The first capacitor is electrically connected between the first clock signal terminal and the pull-up node.

In a possible implementation manner, the second control circuit includes a double-gate transistor, wherein both gates of the double-gate transistor are electrically connected to a third clock terminal to receive the third clock signal, The source of the double-gate transistor is electrically connected to the first reference voltage terminal, and the drain of the double-gate transistor is electrically connected to the pull-up node.

The first control circuit uses two transistors as a switching element and a capacitor respectively, and the second control circuit uses a double-gate transistor as a switching element to control the voltage of the pull-up node and the pull-down node in different time periods, so that the first control The circuit structure of the circuit and the second control circuit is simple, which provides more possibilities for simplifying the components of the scanning and light-emitting drive circuit and reducing the volume.

In a possible implementation manner, the light-emitting pull-up output circuit includes a fourth transistor, and the light-emitting pull-down output circuit includes a fifth transistor and a second capacitor. The gate of the fourth transistor is electrically connected to the control terminal of the light-emitting pull-up output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit, and the fourth transistor The drain of is electrically connected to the output terminal of the light-emitting pull-up output circuit. The gate of the fifth transistor is electrically connected to the control terminal of the light-emitting pull-down output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-down output circuit, and the drain of the fifth transistor is The pole is electrically connected to the output terminal of the light-emitting pull-down output circuit. The second capacitor is electrically connected between the pull-down node and the second reference voltage terminal.

The light-emission pull-up output circuit and light-emission pull-down output circuit respectively use two transistors as switching elements and a capacitor to output two different reference voltages in the light-emission signal at different time periods, so that the circuit structure of the light-emission drive output circuit is simple, which is a scanning The simplification of components and the reduction of the volume of the light-emitting drive circuit provide more possibilities.

In a possible implementation manner, the first inverter circuit includes a sixth transistor, the gate of the sixth transistor is electrically connected to the pull-up node, and the source of the sixth transistor is electrically connected to The second reference voltage terminal and the drain of the sixth transistor are electrically connected to the pull-down node. When the sixth transistor is turned on under the control of the pull-up node, the sixth transistor controls the voltage of the pull-down node to be the same second potential as the second reference voltage. The first inverter circuit adopts one transistor to realize that the voltage of the pull-down node is different from the voltage of the pull-up node. The circuit structure is simple, which provides more possibilities for simplifying the components of the scanning and light-emitting drive circuit and reducing the size.

In a possible implementation manner, the scan pull-up output circuit includes a seventh transistor, and the scan pull-down output circuit includes an eighth transistor. The gate of the seventh transistor is the control terminal of the scan pull-up output circuit, the source of the seventh transistor is the input terminal of the scan pull-up output circuit, and the drain of the seventh transistor is the scan terminal. Pull the output terminal of the output circuit. The gate of the eighth transistor is the control terminal of the scan pull-down output circuit, the source of the eighth transistor is the input terminal of the scan pull-down output circuit, and the drain of the eighth transistor is the scan pull-down output circuit The output terminal.

The scan pull-up output circuit and the scan pull-down output circuit respectively use two transistors as switching elements and a capacitor to output two different reference voltages in the scan signal at different time periods, so that the circuit structure of the light-emitting drive output circuit is simple, which is a scan The simplification of components and the reduction of the volume of the light-emitting drive circuit provide more possibilities.

In a possible implementation manner, the reset circuit includes a tenth transistor and an eleventh transistor. The gate of the tenth transistor is electrically connected to the reset terminal to receive a reset signal, the source of the tenth transistor is electrically connected to the first reference voltage terminal, and the drain of the tenth transistor is electrically connected to The pull-up node. The gate of the eleventh transistor is electrically connected to the reset terminal to receive the reset signal, the source of the eleventh transistor is electrically connected to the second reference voltage terminal, and the eleventh transistor The drain is electrically connected to the pull-down node. The reset circuit adopts two transistors to reset the voltage of the pull-down node and the voltage of the pull-up node. The circuit structure is simple, which provides more possibilities for simplifying the components of the scanning and light-emitting drive circuit and reducing the volume.

In a second aspect, the present application provides a scanning and light-emitting driving circuit. The scanning and light-emitting driving system includes the aforementioned scanning and light-emitting driving circuit in a multi-stage cascade, wherein the scanning signal of the n-1th stage scanning and light-emitting driving circuit The output terminal is electrically connected to the first control circuit of the n-th stage scanning and light-emitting drive circuit, and the scanning signal output by the n-1th stage scanning and light-emitting drive circuit is used as the pre-start scan signal, and the n is greater than An integer of 1; the first control circuit includes a first transistor, a third transistor and a first capacitor. The gate of the first transistor is used to receive the first clock signal, and the source of the first transistor is electrically connected to the scan signal output terminal of the n-1th stage scan and light-emitting drive circuit, so The drain of the first transistor is electrically connected to the pull-down node. The gate of the third transistor is electrically connected to the scan signal output terminal of the n-1th stage scanning and light-emitting drive circuit, and the source of the third transistor is electrically connected to the second reference voltage terminal to receive the For the second reference voltage, the drain of the third transistor is electrically connected to the pull-up node. The first capacitor is electrically connected between the first clock signal terminal and the pull-up node.

In the scanning and light-emitting drive system, the scanning and light-emitting drive circuits are cascaded each other, so that part of the working time between the cascaded scanning and light-emitting drive circuits overlaps, thereby effectively improving the refresh rate of the pixel unit and meeting the requirements of high-frequency image display. demand.

In a third aspect, in a possible implementation manner, a display panel is provided, and the non-display area of the display panel includes the aforementioned scanning and light-emitting driving circuit. Since the scanning and light-emitting drive circuit uses fewer electronic components and a smaller volume, the non-display area of the display panel can be further reduced, which provides a larger design space for narrowing the frame and increasing the screen-to-body ratio.

In a fourth aspect, in a possible implementation manner, a scanning and light-emitting drive circuit is provided, including a light-emitting drive circuit and a pulse width control circuit. The light-emitting drive circuit is used to output a light-emitting signal, and the light-emitting signal is used to control The time when the pixel unit displays the image data, and the pulse width control circuit is electrically connected to the light-emitting drive circuit for controlling the frequency at which the light-emitting drive circuit outputs the light-emitting signal.

In a possible implementation manner, the light-emitting drive circuit includes a first control circuit, a second control circuit, a pull-up output circuit, and a pull-down output circuit. Wherein, the first control circuit is electrically connected to the pull-up output circuit and the pull-down output circuit through the pull-up node, and the data writing period in one scan period controls the voltage of the pull-up node according to the received first clock signal, so that all The pull-up output circuit outputs a first reference voltage, and the first reference voltage controls the pixel unit to stop displaying image data. The second control circuit is electrically connected to the pull-up output circuit through the pull-up node, the light-emitting segment in the scan period outputs a second reference voltage according to the received second clock signal, and the second reference voltage is used to control the pixel The unit displays image data, and the light-emitting signal includes the first reference voltage and the second reference voltage. The pulse width control circuit is electrically connected to the light-emitting drive circuit for controlling the frequency at which the pull-up output circuit outputs the first reference voltage and the frequency at which the pull-down output circuit outputs the second reference voltage, And the frequency of the output of the first reference voltage and the second reference voltage is the same, and the number of times the first reference voltage is output in the light-emitting period is greater than one.

Specifically, the light-emitting drive circuit includes a first pulse width control circuit and a second pulse width control circuit. The control terminal of the first pulse width control circuit receives the first pulse width signal with the first duty cycle, the input terminal is electrically connected to the first reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-up output circuit, so The first pulse width control circuit is turned on at a first frequency under the control of a first pulse width signal, and when the first pulse width control circuit is turned on during the light-emitting period, the first reference voltage passes through the first The input end of the pulse width control circuit, the output end, the output end, and the light-emitting pull-up output circuit output to the light-emitting signal output end. The control terminal of the second pulse width control circuit receives a second pulse width signal with a second duty cycle, the input terminal is electrically connected to the second reference voltage terminal, and the output terminal is electrically connected to the light-emitting signal output terminal. The second pulse width control circuit is turned on at the second frequency under the control of the second pulse width signal. When the second pulse width control circuit is turned on during the light-emitting period, the second reference voltage passes through the second pulse The input terminal and the output terminal of the wide control circuit are output to the light-emitting signal output terminal. The sum of the first duty cycle and the second duty cycle is 1, and the first pulse width signal and the second pulse width signal have opposite phases.

In a possible implementation manner, the pull-up output circuit includes a fourth transistor, the gate of the fourth transistor is electrically connected to the pull-up node, and the source of the fourth transistor is electrically connected to the In the first pulse width control circuit, the drain of the fourth transistor is electrically connected to the light-emitting signal output terminal. The pull-down output circuit includes a twelfth transistor and a third capacitor. The third capacitor is electrically connected between the pull-down node and the first reference voltage terminal. The first reference voltage terminal provides the first reference voltage terminal. A reference voltage. The gate of the twelfth transistor is electrically connected to a pull-down node, the source of the twelfth transistor is electrically connected to a first reference voltage terminal, and the second reference voltage terminal provides the second reference voltage. The drain of the twelfth transistor is electrically connected to the light-emitting signal output terminal.

In a possible implementation manner, the first pulse width control circuit includes a first pulse transistor, and the gate of the first pulse transistor is electrically connected to the first pulse signal output terminal to receive the first pulse control signal, the The source of the first pulse transistor is electrically connected to the second reference voltage terminal, and the drain of the first pulse transistor is electrically connected to the drain of the fourth transistor. The second pulse width control circuit includes a second pulse transistor, the gate of the second pulse transistor is electrically connected to the second pulse signal output terminal to receive the second pulse control signal, and the source of the second pulse transistor is electrically connected to the second pulse signal output terminal. Is electrically connected to the first reference voltage terminal, and the drain of the second pulse transistor is electrically connected to the light-emitting signal output terminal.

The first pulse width control circuit and the second pulse width control circuit respectively use a transistor as a switching element to perform the output control of the first reference voltage and the second reference voltage, so that the structure of the pulse width control circuit is simple, and it is a scanning and light-emitting drive circuit. Simplified components and reduced volume provide more possibilities.

In a fifth aspect, in a possible implementation manner, a display panel is provided, and the scanning and light-emitting driving circuit is provided in a non-display area of the display panel. Since the scanning and light-emitting drive circuit uses fewer electronic components and a smaller volume, the non-display area of the display panel can be further reduced, which provides a larger design space for narrowing the frame and increasing the screen-to-body ratio.

Description of the drawings

In order to more clearly illustrate the structural features and effects of the present application, the following will describe it in detail with reference to the accompanying drawings and specific embodiments.

FIG. 1 is a schematic diagram of a planar structure of a display panel in an embodiment of the application;

FIG. 2 is a schematic diagram of a side structure of the display panel shown in FIG. 1;

3 is a schematic diagram of a planar structure of an array substrate in the display panel shown in FIG. 2;

4 is a functional block diagram of the scanning and light-emitting driving system in an embodiment of the application;

Figure 5 is a functional block diagram of a scanning and light-emitting drive system commonly used at present;

FIG. 6 is a schematic diagram of a specific circuit structure of any scan driving unit shown in FIG. 5;

FIG. 7 is a schematic diagram of a specific circuit structure of any scan driving unit shown in FIG. 5;

FIG. 8 is a schematic diagram of the circuit structure of any pixel unit in the pixel matrix shown in FIG. 3 or FIG. 4;

FIG. 9 is a working timing diagram of the pixel unit shown in FIG. 8;

10 is a circuit block diagram of any scanning and light-emitting driving circuit shown in FIG. 4 in the first embodiment of the application;

FIG. 11 is a schematic diagram of a specific circuit structure of the scanning and light-emitting driving circuit shown in FIG. 10;

FIG. 12 is a timing diagram of the scanning and light-emitting driving circuit shown in FIG. 11 when working;

FIG. 13 is a specific circuit structure diagram of any scan and light-emitting driving circuit shown in FIG. 4 in the second embodiment of the application;

FIG. 14 is a working timing diagram of the scanning and light-emitting driving circuit shown in FIG. 13;

15 is a specific circuit structure diagram of any scan and light-emitting driving circuit shown in FIG. 4 in the third embodiment of the application;

FIG. 16 is a timing diagram of the scanning and light-emitting driving circuit shown in FIG. 15 when working;

FIG. 17 is a specific circuit structure diagram of any scan and light-emitting driving circuit described in FIG. 4 in the fourth embodiment of this application;

FIG. 18 is a timing diagram of the scanning and light-emitting driving circuit shown in FIG. 17 when operating;

FIG. 19 is a circuit block diagram of a light-emitting drive circuit in any one of the scanning and light-emitting drive circuits described in FIG. 4 in the fifth embodiment of the application;

20 is a schematic diagram of a specific circuit structure of the light-emitting drive circuit shown in FIG. 19;

FIG. 21 is a timing diagram of the light-emitting driving circuit shown in FIG. 20 during operation;

FIG. 22 is a specific circuit structure diagram of the light-emitting driving circuit in any scanning and light-emitting driving circuit described in FIG. 4 in the sixth embodiment of the application; FIG.

FIG. 23 is a timing chart of the light-emitting drive circuit shown in FIG. 22 during operation.

Detailed ways

The application will be described below with specific embodiments.

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

Please refer to FIG. 1, which is a schematic diagram of a planar structure of a display panel (DP) in an embodiment of the application. The display panel DP is applied to the display device 10 to perform image display. In this embodiment, the display device 10 can be, for example, a mobile communication terminal, a monitor, a television, etc. Of course, the display device needs to perform image display, and other components (Figure Not shown), such as power supply modules, signal processor modules, signal sensing modules, etc.

The display panel DP includes a display area AA (Active Area) and a non-display area NA (Non Active Area), where the display area AA is used to perform image display. The non-display area NA is arranged around the display area AA, and does not perform image display, but is used to set driving, control circuits, and conductive traces.

Please refer to FIG. 2, which is a schematic diagram of the side structure of the display panel DP shown in FIG. 1. As shown in FIG. 2, the display panel DP includes an array substrate 11c and a counter substrate 11d, and a display medium layer 11e sandwiched between the array substrate 11c and the counter substrate 11d. In this embodiment, the display medium in the display medium layer 11e is an organic light-emitting semiconductor material (Organic Electroluminescence Diode, OLED). In other embodiments of the present application, the display medium may also be a micro-light emitting diode (Micro-Light Emitting Diode, Micro-Light Emitting Diode). -LED) or Light Emitting Diode (LED).

Please refer to FIG. 3, which is a schematic diagram of a planar structure of the array substrate 11c in the display panel DP shown in FIG. As shown in FIG. 3, the corresponding image display area 11a in the array substrate 11c includes a plurality of m*n pixel units (Pixel) P, m data lines 120, and 2n scan drive lines arranged in a matrix. ) 130 and 2n emission lines 140, m and n are natural numbers greater than 1.

Wherein, the plurality of data lines 120 are arranged at a first predetermined distance along the X direction, and the plurality of data lines 120 are insulated from each other and arranged in parallel. Each data line 120 extends along the Y direction Y. It is worth noting that the X direction and the Y direction are perpendicular to each other.

The plurality of scan driving lines 130 are also arranged at a second predetermined distance along the Y direction, and the plurality of scan driving lines 130 are insulated from each other and arranged in parallel. Each scan driving line 130 extends in the X direction.

The light-emitting driving lines 140 are also arranged at a second predetermined distance along the Y direction, and the light-emitting driving lines 140 are insulated from each other and arranged in parallel. Each light-emitting driving line 140 extends in the X direction.

It should be noted that the plurality of scan driving lines 130, the plurality of light-emitting driving lines 140, and the plurality of data lines 120 are insulated from each other.

For ease of description, the m data lines 120 are respectively defined as D1, D2, ..., Dm-1, Dm according to the position order; the 2n scan driving lines 130 are respectively defined as G1, ..., Gn according to the position order -1, Gn, Gn+1..., G2n; the 2n light-emitting drive lines 140 are respectively defined as E1,..., En-1, En, en+1,..., E2n according to the position order. Each pixel unit P is electrically connected to a scan driving line 130 extending along the X direction, a light emitting driving line 140 extending along the X direction, and a data line 120 extending along the Y direction.

Corresponding to the non-display area NA of the display panel DP, a timing control circuit 101 for driving pixel units for image display, a data driver circuit (Data Driver) 102, and a scanning and emission driver system (Scan and Emission Driver) 103 are provided. These circuits can Set on the array substrate 11c. Wherein, the timing control circuit 101 and the data driver circuit (Data Driver) 102 can also be arranged in a position outside the non-display area NA of the display panel DP, for example, arranged on the back of the array substrate 11c, etc., wherein the array substrate 11c is provided with The surface of the pixel unit P is the front surface of the array substrate 11c.

The data driving circuit 102 is electrically connected to the plurality of data lines 120 for transmitting image data (data) to be displayed to the plurality of pixel units P through the plurality of data lines 120 in the form of voltage.

The scanning and light-emitting driving system 103 is electrically connected to the plurality of scan driving lines 130 and the plurality of light-emitting driving lines 140 respectively, and is used for outputting a scan signal Sc through the plurality of scan driving lines 130 for controlling when the pixel unit P receives an image The data and the light-emitting signal EM output through the plurality of light-emitting driving lines 140 are used to control when the pixel unit P emits light according to the received image data.

Among them, the scanning and light-emitting driving system 103 outputs scanning signals from the scanning driving lines G1,..., Gn-1, Gn, Gn+1,..., G2n in sequence according to the scanning period based on the position arrangement sequence of the plurality of scanning driving lines 130 Sc1,..., Sc n-1, Scn, Scn+1, Sc2n, and based on the sequence of the multiple light-emitting drive lines 140, the scanning and light-emitting drive system 103 sequentially emits light from the light-emitting drive lines E1 according to the scanning period. ..., En-1, En, En+1, ..., E2n output light-emitting signals E1, ..., EMn-1, EMn, EMn+1, ..., EM2n.

The timing control circuit 101 is electrically connected to the data driving circuit 102 and the scanning and lighting driving system 103, respectively, for controlling the working timing of the data driving circuit 102 and the scanning and lighting driving system 103, that is, the timing control circuit 101 outputs the corresponding timing control Signal to the data driving circuit 102 to control when the data driving circuit 102 outputs image data data; and output a corresponding timing control signal to the scanning and light-emitting driving system 103 to control when the scanning and light-emitting driving system 103 outputs the corresponding scanning signal Gn and luminous signal En.

In this embodiment, the circuit elements in the scanning and light-emitting driving system 103 and the pixel units P in the display panel 11 are manufactured in the display panel 11 in the same manufacturing process. It can be understood that the display terminal 10 also includes other auxiliary circuits for jointly displaying images, such as a graphics processing unit (Graphics Processing Unit, GPU) or a power supply circuit, which will not be described in detail in this embodiment.

Please refer to FIG. 4, which is a functional block diagram of the scanning and light-emitting driving system 103 in an embodiment of the application. As shown in FIG. 4, the scanning and light-emitting driving system 103 includes 2n scanning and light-emitting driving circuits 103u cascaded with each other. The multiple scanning and light-emitting driving circuits 103u and 2n groups of scanning lines (not labeled) are respectively cascaded. connection. When a plurality of scanning and light-emitting drive circuits 103u are cascaded with each other, the scanning signal in each scanning and light-emitting drive circuit 103u is output to the scanning line electrically connected to it, and is also output to the next stage of scanning and light-emitting drive. The circuit 103u serves as a work enable (Enable) signal of the next-stage scanning and light-emitting drive circuit 103u. Wherein, the work enable signal is used to control the startup and initialization of some electronic components in the scanning and light-emitting drive circuit 103u, and prepares for outputting scanning signals and light-emitting signals of the scanning and light-emitting drive circuit 103u.

For example, the cascade connection of the 2n scanning and light-emitting driving circuits 103u is as follows: the scanning output terminal of the n-1th stage scanning and light-emitting driving circuit is electrically connected to the n-th scanning and light emitting drive circuit. The initial enable terminal Enable of the driving circuit 103u. Among them, the scanning signal in the n-1th stage scanning and light-emitting drive circuit 103u is also output to the initial enable terminal Enable of the nth stage scanning and light-emitting drive circuit 103u at the same time, then the n-1th stage scanning and light-emitting drive circuit 103u The scanning signal in is also used as the pre-start scanning signal of the n-th stage scanning and light-emitting drive circuit 103u, that is, the work enable (Enable) signal described in this embodiment is the pre-start scanning signal.

In this embodiment, each scanning and light-emitting drive circuit 103u uses the same circuit to output the scanning signal and the light-emitting signal, that is, the circuit that outputs the scan signal and the circuit that outputs the light-emitting signal are the same, and there is no need for a separate scan signal at all. Separate circuits are provided for the output of the light-emitting signal, which effectively saves the number of electronic components and simplifies the circuit.

As shown in FIG. 4, for any three adjacent cascaded scanning and light-emitting drive circuits 103u, for example, the scanning and light-emitting drive circuits 103u of the n-1th stage, the nth stage, and the n+1th stage are as follows: :

The scanning and light-emitting drive circuit 103u of the n-1th stage outputs the scanning signal Sc through the scanning signal output terminal Scan and the light-emitting signal EM to the n-1th group of scanning lines through the light-emitting signal output terminal Eout. At the same time, the n-1th stage The scanning and light-emitting drive circuit 103u also outputs the scanning signal Sc to the initial enable terminal Enable of the n-th stage scanning and light-emitting drive circuit 103u, as a pre-start scan signal to drive the n-th stage scanning and light-emitting drive circuit 103u to start working .

The scanning and light-emitting drive circuit 103u of the nth stage outputs scanning signals and light-emitting signals to the n-th group of scanning lines. At the same time, the scanning and light-emitting drive circuit 103u of the nth stage also outputs the scanning signals to the n+1th scanning and The light-emitting driving circuit 103u starts to work by driving the scanning and light-emitting driving circuit 103u of the n+1th stage.

By analogy, the scanning and light-emitting driving circuits 103u of other stages are cascaded according to the aforementioned cascading manner, which will not be repeated in this embodiment.

Each group of scan lines includes a gate scan line Gk and a light-emitting driving line Ek, and k is any positive integer greater than 1 and less than 2n. The multiple scanning and light-emitting drive circuits 103u sequentially provide scan signals to multiple groups of scan drive lines in the pixel array, and provide light-emitting signals to multiple groups of light-emitting drive lines.

Among them, in the driving and displaying of one frame of image (1Frame), each scanning and light-emitting driving circuit 103u outputs a scanning signal and a light-emitting signal of one scanning period to a group of scanning lines connected to the scanning and light-emitting driving circuit 103u. It can be understood that for 2n groups of scan lines, the driving display time of one frame of image (1Frame) includes 2n scan periods, that is, the 2n scan and light-emitting drive circuits 103u each output a scan signal and light for one scan period. Signal to the corresponding set of scan lines.

Each scanning and light-emitting driving circuit 103u receives the clock signal CLK through the timing control circuit 101 electrically connected thereto, and at the same time receives the reset signal Reset through a reset circuit (not labeled) electrically connected thereto. In this embodiment, the reset circuit may be disposed in the non-display area NA of the array substrate 11c. Please continue to refer to FIG. 4, each pixel unit P includes a pixel drive circuit (not labeled) and a light-emitting device (not labeled). The pixel drive circuit starts to receive image data data under the control of the scan signal, and then emits light under the control of the light-emitting signal The device starts to emit light according to the image data data. When all the pixel units P in the display area AA output light according to the image data data, the image display is completed. In other words, the scan signal is used to selectively scan and turn on the pixel driving circuit in the pixel unit connected to a group of scan lines, so that the pixel driving circuit receives the image data data because it is scanned and turned on. The light-emitting signal is used to control when the driving current corresponding to the image data data is provided to the light-emitting device to perform image display, or in other words, the light-emitting signal is used to control the adjustment of the light-emitting time of the light-emitting device in the pixel unit P.

Please refer to FIG. 5, which is a functional block diagram of the scanning and light-emitting driving circuit 103 currently commonly used. As shown in FIG. 5, in this embodiment, each scanning and light-emitting driving circuit 103u includes an independent scanning driving circuit GU and a light-emitting driving circuit EU. Among them, the scan driving circuit GU is used to output scan signals, and the light-emitting drive circuit EU is used to output light-emitting signals.

Specifically, please refer to FIGS. 6-7, where FIG. 6 is a schematic diagram of a specific circuit structure of any scan driving unit GUn shown in FIG. 5, and FIG. 7 is a schematic diagram of a specific circuit structure of any scan driving unit EUn shown in FIG. .

As shown in FIG. 6, the scan driving circuit GU for outputting scan signals includes 8 transistors M1 to M8 and two capacitors C1 to C2, and as shown in FIG. 7, the light emitting drive circuit EU for outputting light emitting signals includes Twelve transistors M1 to M12 and three capacitors C1 to C3.

It can be seen from FIGS. 5-7 that the scan driving circuit GU and the light-emitting driving circuit EU do not share any electronic components. Then, each scan and light-emitting driving circuit 103u including the scan driving circuit GU and the light-emitting driving circuit EU that are independent from each other , Including at least a total of 20 transistors and 5 capacitors. It can be seen that the number of electronic components in each scanning and light-emitting driving circuit 103u is relatively large, and the area occupied is relatively large, which cannot be miniaturized, which makes it more difficult to reduce the area of the non-display area.

However, each scanning and light-emitting drive circuit 103u in this embodiment uses the same circuit to output the scanning signal and the light-emitting signal, that is to say, the scanning and light-emitting drive circuit 103u outputs the scanning signal and the light-emitting circuit that outputs the light-emitting signal. The driving circuit can be realized by sharing the same circuit, thereby effectively reducing the number of electronic components in the scanning and lighting driving circuit 103u and the scanning and lighting driving circuit 103, correspondingly reducing the volume and occupation of the scanning and lighting driving circuit 103 The area provides a greater possibility for the area of the non-display area to be reduced.

Specifically, please refer to FIG. 8, which is a schematic diagram of the circuit structure of any pixel unit P in the pixel matrix shown in FIG. 3 or FIG. 4. The pixel matrix includes a plurality of pixel units P arranged in an array and used for performing image display. As shown in FIG. 8, it is a diagram of the internal circuit structure of any pixel unit P in the pixel matrix, for example, a pixel unit P located in the nth row and jth column in the pixel matrix. The pixel unit P includes a 6T1C pixel driving circuit and a light emitting device OLED. It is worth noting that k is an integer greater than or equal to 1 and less than or equal to 2n, and the value of j is an integer greater than or equal to 1 and less than or equal to m.

Specifically, the 6T1C pixel drive circuit in the pixel unit P includes a first pixel transistor T1, a second pixel transistor T2, a third pixel transistor T3, a fourth pixel transistor T4, a fifth pixel transistor T5, a sixth pixel transistor T6, and a Drive capacitor CP1.

For the pixel unit P located in the kth row and jth column, the gate of the sixth pixel transistor T6 located in the pixel unit P is electrically connected to the scan driving line G(n-1) in the n-1th row, For receiving the scan signal Sc(n-1); the drain of the sixth pixel transistor T6 is electrically connected to the initialization terminal to receive the initialization voltage VINIT, and the source of the sixth pixel transistor T6 is electrically connected to the first pixel transistor T1的Grid.

One end of the driving capacitor CP1 is connected to the light-emitting high-voltage driving terminal ELVDD, and the other end is connected to the source of the sixth pixel transistor T6.

The gate of the fifth pixel transistor T5 is electrically connected to the light-emitting drive line E(n) in the kth row for receiving the light-emitting signal EM(n); the drain of the fifth pixel transistor T5 is electrically connected to the light-emitting high-voltage drive terminal ELVDD is used to receive the light-emitting driving voltage VDD, and the source of the fifth pixel transistor T5 is electrically connected to the source of the second pixel transistor T2.

The gate of the second pixel transistor T2 is electrically connected to the scan driving line G(n) in the k-1th row for receiving the scan signal Scan(n), and the drain of the second pixel transistor T2 is electrically connected to the jth The column data line is used to receive the book voltage VDATA of the image data data.

The drain of the first pixel transistor T1 is electrically connected to the source of the second pixel transistor T2, and the source of the first pixel transistor T1 is electrically connected to the drain of the fourth pixel transistor T4.

The gate of the third pixel transistor T3 is electrically connected to the scan driving line G(n) in the n-1th row for receiving the scan signal Sc(n), and the drain of the third pixel transistor T3 is electrically connected to the first The gate of the pixel transistor T1 and the source of the third pixel transistor T3 are electrically connected to the drain of the fourth pixel transistor T4.

The gate of the fourth pixel transistor T4 is electrically connected to the light-emitting drive line E(n) in the nth row for receiving the light-emitting signal EM(n), and the source of the fourth pixel transistor T4 is electrically connected to the light-emitting device OLED The anode terminal Anode.

The cathode of the light-emitting device OLED is electrically connected to the low-voltage driving terminal ELVSS.

For any pixel unit P in the kth row, it is necessary to perform the selection of the pixel unit by receiving gate scan signals from the scan driving lines Gn and Gn-1, and at the same time to receive the light-emitting signal through the self-luminous driving line En to execute image data The voltage VDATA of data is loaded. That is, each pixel unit P needs at least the cooperation of the light-emitting signal, the scanning signal, the image data, the clock signal, and the reset signal to be able to accurately perform the correct display of the image data.

In this embodiment, the pixel transistors T1 to T6 are all P-type thin film transistors (TFTs). Therefore, in different time periods, the light emitting signal, the scanning signal, the image data, the clock signal, and the reset signal, The pixel transistors T1 to T6 are controlled to be turned on at a low level, and the pixel transistors T1 to T6 are controlled to be turned off at a high level. Among them, the on and off states of the pixel transistors T1 to T6 under the control of the light-emitting signal, the scanning signal, the image data, the clock signal, and the reset signal in different time periods can be specifically described with reference to FIG. 9.

In other embodiments of the present application, the pixel transistors T1 to T6 may also be N-type thin film transistors (TFTs). Therefore, in different time periods, the light emitting signal, the scanning signal, the image data, the clock signal, and the reset signal The pixel transistors T1 to T6 are controlled to be turned on at a high level, and the pixel transistors T1 to T6 are controlled to be turned off at a low level.

In addition, in other embodiments of the present application, the number of pixel transistors and the number of capacitors included in the pixel drive circuit can be adjusted according to actual needs, for example, a 2T1C pixel drive circuit composed of two pixel transistors and one capacitor; 4T1C pixel driving circuit composed of 4 pixel transistors and 1 capacitor; 4T2C pixel driving circuit composed of 4 pixel transistors and 2 capacitors; 5T1C pixel driving circuit composed of 5 pixel transistors and 1 capacitor; composed of 5 2T1C pixel driving circuit composed of pixel transistors and 2 capacitors; 7T1C pixel driving circuit composed of 7 pixel transistors and 1 capacitor; or 7T2C pixel driving circuit composed of 7 pixel transistors and 2 capacitors.

In this embodiment, a scan period during the display period of one frame of image includes a reset period (Reset) Tr, a data writing period (Data) Td, and an emission period (Emission) Te arranged in chronological order, where , The three time periods are continuous and uninterrupted in time without interval. In other words, the reset period Tr, the data writing period Td, and the light emitting period Te are continuous in time, without interval, and without overlap. Wherein, one scanning period of the pixel unit P is a working period of the pixel unit P in the process of displaying one frame of image.

Please refer to FIG. 9, which is a working timing diagram of the pixel unit P shown in FIG. 8. The working process of the pixel unit P will now be described in detail with reference to FIGS. 8 and 9.

In the reset period Tr, the scan signal Sc(n-1) provided by the scan driving line Gn-1 is low level, and the initialization voltage VINIT is provided to the gate of the first pixel transistor T1. The node is initialized, and the driving capacitor CP1 is initialized to ensure that the remaining electrical signals in the pixel unit P in the previous scan period are released.

In the data writing period Td, the scan signal Sc(n) provided by the scan driving line Gn is at a low level, the first pixel transistor T1, the second pixel transistor T2, and the third pixel transistor T3 are turned on, and the voltage corresponding to the image data data VDATA is loaded to the anode terminal (Anode) of the light-emitting element OLED.

During the light-emitting period Te, the light-emitting signal EM(n) provided by the light-emitting drive line En is low, the fourth pixel transistor T4 and the fifth pixel transistor T5 begin to conduct, and the light-emitting drive voltage VDD passes through the fifth pixel transistor T5 and the second pixel transistor T5. A driving path formed by a pixel transistor T1 and a fourth pixel transistor T4 cooperates with the voltage VDATA of the image data Data to output a driving current to the light-emitting device OLED, thereby driving the light-emitting device OLED to emit light according to the image data data to perform image display.

Please refer to FIG. 10, which is a circuit block diagram of the scanning and light-emitting driving circuit 100 of any one of the scanning and light-emitting driving circuits 103 u in FIG. 4 according to the first embodiment of the application.

As shown in FIG. 8, the scanning and light-emitting drive circuit 100 includes a first control circuit 11, a second control circuit 12, a light-emitting drive output circuit 13, a scan drive output circuit 14, a first inverter circuit 15, a buffer circuit 16, and a reset circuit. 18.

Both the first control circuit 11 and the second control circuit 12 are electrically connected to the light-emitting output circuit 13 through the pull-up node B, and at the same time, the first control circuit 11 and the second control circuit 12 are both electrically connected to the scan output circuit through the pull-up node B 14. The light-emitting output circuit 13 is also electrically connected to the light-emitting signal output terminal Eout, and the scan output circuit 14 is also electrically connected to the scan signal output terminal Scan.

The first control circuit 11 is used for controlling the voltage of the pull-up node B to a second potential (the second potential is a low potential) during the data writing period Td according to the first clock signal CLK1 received from the first clock terminal CK1, and at the same time The voltage of the pull-down node C is controlled to a first potential (the first potential is a high potential).

In the data writing period Td, when the voltage of the pull-down node C is at the first potential, the light-emitting drive circuit 13 is controlled to output the second reference voltage (VSS) as the light-emitting signal EM under the control of the voltage of the pull-down node C at the first potential. To the light-emitting signal output terminal Eout, where the pixel unit P cannot be driven for image display when the light-emitting signal EM is the second reference voltage (VSS); when the voltage of the pull-down node C is the first potential, the scan output circuit 14 is controlled according to the second reference voltage (VSS). The second clock signal CLK2 received by the second clock terminal CK2 outputs the third reference voltage (high voltage) as the scan signal Sc from the scan signal output terminal Scan, and the third reference voltage in the scan signal Sc is loaded to the scan signal through the corresponding scan drive line In the pixel unit P, the pixel unit P is controlled to receive image data data.

In the data writing period Td, when the voltage of the pull-up node B is the second potential, the light-emitting drive output circuit 13 is controlled to output the first reference voltage (VDD) as the light-emitting signal EM, where the light-emitting signal EM is the first reference The voltage (VDD) can drive the pixel unit to perform image display; at the same time, the scan driving circuit 14 is controlled to stop outputting the fourth reference voltage (VSS) as the scan signal Sc, where the scan signal Sc and the fourth reference voltage (VSS) can drive the pixel unit to stop receiving Image data.

In this embodiment, the first reference voltage and the third reference voltage are both high-level voltages, and the second reference voltage and the fourth reference voltage are low-level voltages.

The second control circuit 12 is used for controlling the voltage of the pull-up node B to the first potential (high) during the light-emitting period Te according to the third clock signal CLK3 received from the third clock terminal CK3, and at the same time pulls up the first voltage of the node B. The electric potential controls the voltage of the pull-down node C to the second electric potential (low) through the first inverter circuit 15. The first inverter circuit 15 is electrically connected between the pull-up node B and the pull-down node C, and is used to control the voltage of the pull-down node C to the second potential when the pull-up node B is at the first potential.

In the light-emitting period Te, when the voltage of the pull-up node B is the first potential, the light-emitting drive output circuit 13 is controlled to output the first reference voltage (VDD), where the first reference voltage (VDD) is used to control the pixel unit P The middle pixel driving circuit loads the driving current into the light emitting device OLED to drive the light emitting device OLED to emit light and cause the pixel unit P to perform image display. When the voltage of the pull-up node B is the first potential, the scan driving circuit 14 is controlled to output the fourth reference voltage (VSS) as the scan signal Sc.

In the light emitting period Te, when the voltage of the pull-down node C is at the second potential, the light emitting drive output circuit 13 is controlled to stop outputting the second reference voltage (VSS), and the scan drive output circuit 14 is controlled to output the second reference voltage (low) as The scan signal is output from the scan signal output terminal Scan. At this time, the scan drive line Scan(n) loaded with the scan signal will not perform effective scanning, that is, the pixel circuit P of the scan drive line loaded with the scan signal Sc cannot be turned on , Then the image data data cannot be loaded into the corresponding pixel circuit P at this time.

The buffer circuit 16 is electrically connected to the pull-down node C and the second control circuit 12 for obtaining a second reference voltage (VSS) from the second control unit 12 under the control of the first potential of the pull-down node C during the data writing period Td ) And output to the light-emitting signal output terminal Eout, so as to accurately control the light-emitting signal output terminal Eout to maintain the second reference voltage (VSS).

The reset circuit 18 is electrically connected to the pull-up node B and the pull-down node C, respectively, for controlling the voltage of the pull-up node B to the first potential according to the reset signal Reset provided at the reset terminal Re during the reset period Tr, and at the same time controls the pull-down node The voltage of C is the second potential. In this embodiment, the reset terminal Re is electrically connected to the reset circuit (FIG. 4) to receive the reset signal Reset.

In this embodiment, the first control circuit 11, the second control circuit 12, the light-emitting output circuit 13, the first inverter circuit 15, the buffer circuit 16, and the reset circuit 18 cooperate to form a light-emitting drive circuit, and the first control circuit 11, the second control circuit The two control circuits 12 cooperate with the scan output circuit 14, the first inverter circuit 15, the buffer circuit 16, and the reset circuit 18 to form a scan drive circuit. That is, the light-emitting drive circuit and the scan drive circuit share the first control circuit 11, the second control circuit 12, the first inverter circuit 15, the buffer circuit 16, and the reset circuit 18, thereby effectively reducing the scanning and light-emitting drive circuit 103u The electronic components and volume increase the integration level of the scanning and light-emitting drive circuit 103u.

Please refer to FIG. 11, which is a schematic diagram of a specific circuit structure of the scanning and light-emitting driving circuit 100 shown in FIG. 10. As shown in FIG. 11, the first control circuit 11 includes a first transistor M1, a third transistor M3, and a first capacitor C1.

The gate of the first transistor M1 is electrically connected to the first clock signal terminal CK1 to receive the first clock signal CK1, and the source of the first transistor M1 is electrically connected to the scanning of the n-1th stage scanning and light-emitting drive circuit 103u For the signal output terminal Scan(n-1), the drain of the first transistor M1 is electrically connected to the pull-down node B.

The gate of the third transistor M3 is electrically connected to the scan signal output terminal Scan(n-1) of the n-1th stage scanning and light-emitting drive circuit 103u, and the source of the third transistor M3 is electrically connected to the second reference voltage terminal VSS, the drain of the third transistor M3 is electrically connected to the pull-up node B.

The first buffer capacitor C1 is electrically connected between the first clock signal terminal CK1 and the pull-up node B.

The second control circuit 12 includes a double-gate transistor M2, wherein the double-gate transistor M2 is composed of two sub-transistors in series, and the two series-connected sub-transistors may be a transistor M2a and a transistor M2b.

The gate of the transistor M2a is electrically connected to the third clock terminal CK3, the source of the transistor M2a is electrically connected to the first reference voltage terminal VDD, and the drain of the transistor M2a is electrically connected to the source of the transistor M2b.

The gate of the transistor M2b is electrically connected to the third clock terminal CK3, and the drain of the transistor M2a is electrically connected to the pull-up node B.

The light-emitting output circuit 13 further includes a light-emitting pull-up output circuit 131 and a light-emitting pull-down output circuit 132. The light-emitting pull-up output circuit 131 is electrically connected to the pull-up node B and the light-emitting signal output terminal Eout, and outputs the first reference voltage VDD when the pull-up node B is at the second potential.

The light-emitting pull-down output circuit 132 is electrically connected to the pull-down node C and the light-emitting signal output terminal Eout. When the voltage of the pull-down node C is at the second potential, it outputs a second reference voltage (VSS). The second reference voltage (VSS) constitutes the light-emitting signal, and when the light-emitting signal is the first reference voltage (VDD), the pixel unit P is driven to perform image display.

In this embodiment, the light-emitting pull-up output circuit 131 includes a fourth transistor M4, and the light-emitting pull-down output circuit 132 includes a fifth transistor M5 and a second capacitor C2.

The gate of the fourth transistor M4 is electrically connected to the pull-up node B, the source of the fourth transistor M4 is electrically connected to the first reference voltage terminal VDD, and the drain of the fourth transistor M4 is electrically connected to the light emitting signal output terminal Eout.

The gate of the fifth transistor M5 is electrically connected to the pull-down node C, the source of the fourth transistor M5 is electrically connected to the second reference voltage terminal VSS, and the drain of the fifth transistor M5 is electrically connected to the light emitting signal output terminal Eout.

The second capacitor C2 is electrically connected between the pull-down node B and the second reference voltage terminal VSS.

The first inverter circuit 15 includes a sixth transistor M6. The gate of the sixth transistor M6 is electrically connected to the pull-up node B. The source of the sixth transistor M6 is electrically connected to the second reference voltage terminal VSS. The drain is electrically connected to the pull-down node C.

When the sixth transistor M6 is turned on under the control of the pull-up node B, the voltage of the pull-down node C is controlled to be the same second potential as the second reference voltage. In other words, when the pull-up node B is at the first potential that can control the sixth transistor M6 to be turned on, the pull-down node C can be controlled to be at the second potential opposite to the pull-up node B, so that the pull-up The voltages of node B and pull-down node C are in opposite phases.

The scan output circuit 14 is electrically connected to the pull-up node B and the pull-down node C for outputting the scan signal Sc during the data writing period Td, and includes a scan pull-up output circuit 141 and a scan pull-down output circuit 142.

The scan pull-up output circuit 141 is electrically connected to the pull-up node B and the scan signal output terminal Scan. When the pull-up node B is at the first potential, the scan pull-up output circuit 141 is controlled to output the second reference voltage (VSS). The scan pull-down output circuit 142 is electrically connected to the pull-down node C and the scan signal output terminal Scan, and when the pull-down node C is at the first potential, the scan pull-up output circuit 141 is controlled to output the first reference voltage (the high potential of CLK) to the scan signal output terminal Scan, the first reference voltage is used as the scan signal Sc.

In this embodiment, the scan pull-up output circuit 141 includes a seventh transistor M7, and the scan pull-down output circuit 142 includes an eighth transistor M8.

The gate of the seventh transistor M7 is electrically connected to the pull-up node B, the source of the seventh transistor M7 is electrically connected to the second reference voltage terminal VSS, and the drain of the seventh transistor M7 is electrically connected to the scan signal output terminal Scan.

The gate of the eighth transistor M8 is electrically connected to the pull-down node C, the source of the eighth transistor M8 is electrically connected to the second clock terminal CK2 for receiving the second clock signal CLK2, and the drain of the eighth transistor M8 is electrically connected At the scan signal output terminal Scan.

The buffer circuit 16 includes a ninth transistor M9, the gate of the ninth transistor M9 is electrically connected to the pull-down node C, the source of the ninth transistor M9 is electrically connected to the double-gate diode M2, and the drain of the ninth transistor M9 is electrically connected At the luminous signal output terminal Eout.

The ninth transistor M9 applies the first reference voltage to the light-emitting signal output terminal Eout during the data writing time period Td when the pull-down node C is at the first potential to ensure that the voltage of the light-emitting signal output terminal Eout during the data writing time period Td is the first The reference voltage is used to ensure that the data signal is accurately written into the pixel unit P.

The reset circuit 18 includes a tenth transistor M10 and an eleventh transistor M11.

The gate of the tenth transistor M10 is electrically connected to the reset terminal Re for receiving a reset signal Reset, the source of the tenth transistor M10 is electrically connected to the first reference voltage terminal VDD, and the drain of the tenth transistor M10 is electrically connected to Pull up node B. In this embodiment, the reset terminal Re may be a signal terminal used by the reset circuit to output a reset signal Reset.

The gate of the eleventh transistor M11 is electrically connected to the reset terminal Re for receiving a reset signal Reset, the source of the eleventh transistor M11 is electrically connected to the second reference voltage terminal VSS, and the drain of the eleventh transistor M11 is electrically connected to the second reference voltage terminal VSS. Sexually connected to drop-down node C.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all N-type thin film transistors (TFT). Therefore, the first potential is a high potential, the second potential is a low potential, and the first reference voltage is a high voltage. The second reference voltage is a low level.

It should be noted that, since the first reference voltage VDD is a high voltage and the second reference voltage VSS is a low potential, the scan signal Sc has the second reference voltage as the scan-on voltage of the pixel unit P. Therefore, the pixel The pixel transistor receiving the scan signal Sc in the cell P should be an N-type TFT that is turned on at a high potential. When the light-emitting signal EM has the second reference voltage, it is used as the light-emission turn-on voltage of the pixel unit P, so that the pixel unit P receives the light-emitting signal The pixel transistor of Sc should be an N-type TFT with high potential conduction.

Please refer to FIG. 12, which is a timing diagram of the scanning and light-emitting driving circuit 100 shown in FIG. 11 during operation. Wherein, the marking symbol in FIG. 12 is specifically: Sc(n-1) is the voltage waveform of the scanning signal output by the scanning signal output terminal Scan of the scanning and light-emitting driving circuit 100 of the n-1th stage. CLK1 represents the voltage waveform of the first clock signal, CLK2 represents the voltage waveform of the second clock signal, CLK3 represents the voltage waveform of the third clock signal, Reset represents the voltage waveform of the reset signal output by the reset terminal Re, and VB represents the upper The voltage waveform diagram of pull-down node B, VC represents the voltage waveform diagram of pull-down node C, EM(n) represents the voltage waveform diagram of the light-emitting signal EM output from the light-emitting scan output terminal Eout of the n-th stage scanning and light-emitting drive circuit 100, Sc (n) Represents the voltage waveform diagram of the scan signal Scan output from the scan signal output terminal Scan of the nth stage scan and light-emitting drive circuit 100d.

Now, in conjunction with FIGS. 11-12, the working process of the light-emitting scanning driving circuit during 1st Frame during one frame of image scanning is described in detail.

In the reset period Tr shown in FIG. 12, the reset signal Reset output by the reset terminal Re is at a high potential, so that the tenth transistor M10 and the eleventh transistor M11 are turned on.

The first reference voltage provided by the first reference voltage terminal VDD is applied to the pull-up node B through the tenth transistor M10, so that the pull-up node B is at the first potential. The second reference voltage provided by the second reference voltage terminal VSS is applied to the pull-down node C through the eleventh transistor M11, so that the pull-down node C is at the second potential. This completes the reset operation of the pull-up node B and the pull-down node C.

The adjustment period Td1 in the data writing period Td,

The first clock terminal CK1 outputs the first clock signal CLK1, while the scan signal output terminal Scan of the n-1th stage scanning and light-emitting drive circuit 103u outputs the scan signal Sc. Therefore, the first transistor M1 in the first control circuit 11 The third transistors M3 are all turned on.

The second reference voltage provided by the second reference voltage terminal VSS is applied to the pull-up node B through the turned-on first transistor M3, so that the voltage of the pull-up node B is at the second potential. The second reference voltage in the scan signal is applied to the pull-down node C through the turned-on first transistor M1, so that the voltage of the pull-down node C is the first potential.

Since the pull-up node B is at the second potential, the third crystal M4 and the seventh transistor M7 are turned off, the pull-down node C is at the first potential, the fifth crystal M5 is turned on, and the second reference voltage provided by the second reference voltage terminal VSS is applied to The light-emitting signal output Eout; the eighth transistor M8 is turned on, but because the second clock signal terminal CK2 does not output the second clock signal at this time, the second clock signal terminal CK2 loads the first reference voltage to the scan signal output End Sc.

The writing period Td2 in the data writing period Td,

Due to the energy storage effect of the first capacitor C1, the pull-up node B further reduces the voltage on the basis of the second potential; the pull-down node C further increases the voltage on the basis of the first potential due to the energy storage of the second capacitor C2.

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 is turned on, and the second clock signal terminal CK2 loads the second clock signal CLK2 of the second potential to the scan signal output terminal Scan, so that the first scan signal is output The terminal Scan outputs the scan signal Sc of the first reference voltage.

In this embodiment, all the pixel units on the scan driving line to which the scan signal Sc of the first reference voltage is applied are turned on, so that the image data is loaded and written into the pixel unit P.

In the light-emitting period Tr, the third clock terminal outputs the third clock signal CLK3, the double-gate transistor M2 is turned on, and the first reference voltage terminal VDD loads the first reference voltage VDD to the pull-up node B, so that the voltage of the node B is pulled up When the voltage of the pull-up node B is the first potential, the sixth transistor M6 is turned on, so that the voltage of the pull-down node C is the second potential.

When the voltage of the pull-up node B is the first potential and the voltage of the pull-down node C is the second potential, the fourth transistor M4 and the seventh transistor M7 are turned on, and the fifth transistor M5 and the eighth transistor are turned off.

The first reference voltage provided by the first reference voltage terminal VDD is transmitted to the light emitting signal output terminal Eout through the fourth transistor M4, and the second reference voltage provided by the second reference voltage terminal VSS is transmitted to the scan signal output terminal Scan through the seventh transistor M7.

Since the scan signal output terminal Scan stops outputting the scan signal Sc, the pixel unit P corresponding to the scan driving line does not receive the image data data, and the light-emitting signal output terminal Eout outputs the light-emitting signal EM with the first reference voltage to control the pixel The unit P starts to emit light for the received image data data to perform image display, that is, the light-emitting signal has a first reference voltage for controlling the light-emitting time correspondence of the pixel unit P. Therefore, the light-emitting signal controls the first The duration and frequency of the reference voltage can be adjusted for the light-emitting time of the pixel unit P, and can prevent the pixel unit P from being affected by other image data during the light-emitting period Tr, and ensure that the pixel unit P performs image display correctly.

In this embodiment, the scanning and light-emitting driving circuit 100 can output light-emitting output signals and scanning signals during the scanning display period of one frame of image display, thereby effectively improving the integration of the scanning and light-emitting driving circuit 100 and reducing the number of transistors. , While reducing the cost, it can also reduce the size of the scanning and light-emitting drive circuit 100, which provides greater possibilities for the narrow bezel requirements of the display panel.

Please refer to FIG. 13, which is a specific circuit structure diagram of any scanning and light-emitting driving circuit 200 shown in FIG. 4 in the second embodiment of the application. In this embodiment, the scanning and light-emitting driving circuit 200 is similar to the one shown in FIG. The circuit structure of the scanning and lighting driving circuit 100 is basically the same, the difference is that the scanning and lighting driving circuit 200 also includes a pulse width control circuit 17.

The pulse width control circuit 17 is electrically connected to the pull-up output circuit 13, the pull-down output circuit 14, and the light-emitting signal output terminal Eout, and is used to control the pull-up output circuit 13 to output the first reference voltage and frequency and the pull-down output circuit 14 to output The frequency of the second reference voltage.

The pulse width control circuit 17 includes a first pulse width control circuit 171 and a second pulse width control circuit 172.

The first pulse width control circuit 171 and the light-emitting pull-up output circuit 131 are connected in series with the second reference voltage terminal VSS and the light-emitting signal output terminal Eout, and the first pulse width control circuit 171 is controlled by the first pulse width signal P1 according to the first frequency In the ON state.

When the pull-up output circuit 13 is in the on state under the control of the pull-up node B, the first pulse width control circuit 171 outputs the first reference voltage to the light-emitting signal output terminal Eout according to the first frequency.

The second pulse width control circuit 172 and the light-emitting pull-down output circuit 132 are connected in parallel to the second reference voltage terminal VDD and the light-emitting signal output terminal Eout. The second pulse width control circuit 172 is controlled by the second pulse width signal P2 in accordance with the second frequency. Pass state.

When the pull-down output circuit 14 is in a non-conductive state under the control of the pull-down node B, the second pulse width control circuit 172 outputs the second reference voltage to the light-emitting signal output terminal Eout according to the first frequency.

The sum of the duty ratio of the first pulse width signal P1 and the second pulse width signal P2 and the second duty ratio is 1, and the first pulse width signal and the second pulse width signal have opposite phases.

The first pulse width control circuit 171 includes a thirteenth transistor M13. The gate of the thirteenth transistor M13 is electrically connected to the first pulse signal output terminal P1 for receiving the first pulse control signal P1 from the first pulse signal output terminal P1 , The source of the thirteenth transistor M13 is electrically connected to the first reference voltage terminal VDD, and the drain of the thirteenth transistor M13 is electrically connected to the drain of the fourth transistor M4.

The second pulse width control circuit 172 includes a fourteenth transistor M14. The gate of the fourteenth transistor M15 is electrically connected to the second pulse signal output terminal P2 for receiving the second pulse control signal P2 from the second pulse signal output terminal P2 , The source of the fourteenth transistor M14 is electrically connected to the second reference voltage terminal VSS, and the drain of the fourteenth transistor M14 is electrically connected to the light-emitting scan output terminal Eout.

Please refer to FIG. 14, which is a working timing diagram of the scanning and light-emitting driving circuit 200 shown in FIG. 13. In FIG. 14, Sc(n-1) represents the voltage waveform diagram of the scan signal output by the scan signal output terminal Scan of the n-1th stage scanning and light-emitting drive circuit 200, CLK1 represents the voltage waveform diagram of the first clock signal, CLK2 Represents the voltage waveform of the second clock signal, CLK3 represents the voltage waveform of the third clock signal, Reset represents the voltage waveform of the reset signal output by the reset terminal Re, VB represents the voltage waveform of the pull-up node B, and VC represents the pull-down node The voltage waveform diagram of C, P1 represents the voltage waveform diagram of the first pulse width control signal, P2 represents the voltage waveform diagram of the second pulse width control signal, and EM(n) represents the voltage waveform of the luminescence signal output by the self-luminous scanning output terminal Eout In the figure, Sc(n) represents the scanning signal voltage waveform diagram output by the scanning signal output terminal Scan of the nth stage scanning and light-emitting driving circuit 200.

13-14, the working process of the light-emitting scanning driving circuit 200 during 1 Frame during one frame of image scanning will be described in detail.

In the reset period Tr as shown in FIG. 14, the reset signal Reset output by the reset terminal Re is at a high potential, so that the tenth transistor M10 and the eleventh transistor M11 are turned on.

The adjustment period Td1 in the data writing period Td,

The first clock terminal CK1 outputs the first clock signal CLK1, and at the same time the scan signal output terminal Scan of the n-1th stage scanning and light-emitting drive circuit outputs the scan signal. Therefore, the first transistor M1 and the third transistor in the first control circuit 11 The transistors M3 are all turned on.

Since the pull-up node B is at the second potential, the third crystal M4 and the seventh transistor M7 are turned off, the pull-down node C is at the first potential, the fifth crystal M5 is turned on, and the second reference voltage provided by the second reference voltage terminal VSS is applied to The light-emitting signal output Eout; the eighth transistor M8 is turned on, but because the second clock signal terminal CK2 does not output the second clock signal at this time, the second clock signal terminal CK2 loads the first reference voltage to the scan signal output End Scan.

The writing period Td2 in the data writing period Td,

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 is turned on, and the second clock signal terminal CK2 loads the second clock signal CLK2 of the second reference voltage to the scan signal output terminal Scan, so that the scan signal output terminal Scan outputs the scan signal Sc of the first reference voltage.

In the data writing period Td, since the voltage of the pull-down node B is maintained at the first potential, that is, the fifth crystal M5 is always in the on state, so that the light-emitting signal output terminal Eout is also maintained at the second reference voltage. Therefore, the voltage of the light-emitting signal output terminal Eout will not be affected by the pulse width control circuit 17.

The thirteenth transistor M13 outputs the first reference voltage to the light-emitting scan output terminal Eout at the first frequency under the control of the first pulse signal P1, and the fourteenth transistor M14 outputs the first reference voltage at the second frequency under the control of the second pulse signal P2. Two reference voltages to the luminous scanning output terminal Eout.

It can be seen that during the light-emitting period, the duty cycle of the light-emitting signal EM can be flexibly adjusted at any time along with the first pulse signal P1 and the second pulse signal P2. Then, during the light-emitting display period of the pixel unit P, it can be adjusted by adjusting the first pulse signal P1 and P2. The duty ratio of the pulse signal P1 and the second pulse signal P2 is used to accurately adjust the duty ratio of the light-emitting signal EM, thereby effectively preventing the stroboscopic phenomenon caused by the display frequency of the pixel unit P cannot match the current image refresh frequency.

Please refer to FIG. 15, which is a specific circuit structure diagram of any scanning and light-emitting driving circuit 300 shown in FIG. 4 in the third embodiment of the application. In this embodiment, the scanning and light-emitting driving circuit 300 is similar to that shown in FIG. The circuit structure of the scanning and light-emitting driving circuit 100 is basically the same. The only difference is that all transistors (the first transistor M1 to the eleventh transistor M11) in the scanning and light-emitting driving circuit 300 in this embodiment are all P-type thin film transistors.

In addition, in the reset circuit 18, the tenth transistor M10 and the eleventh transistor M11 are used.

The gate of the tenth transistor M10 is electrically connected to the reset terminal Re for receiving a reset signal Reset, the source of the tenth transistor M10 is electrically connected to the second reference voltage terminal VSS, and the drain of the tenth transistor M10 is electrically connected to Pull up node B.

The gate of the eleventh transistor M11 is electrically connected to the reset terminal Re for receiving a reset signal Reset, the source of the eleventh transistor M11 is electrically connected to the first reference voltage terminal VDD, and the drain of the eleventh transistor M11 is electrically connected to the first reference voltage terminal VDD. Sexually connected to drop-down node C.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all P-type thin film transistors (TFT). Therefore, the first potential is a low potential, the second potential is a high potential, and the first reference voltage is a low voltage. The second reference voltage is a high potential.

It should be noted that since the first reference voltage is a low voltage and the second reference voltage is a high potential, the scanning signal Sc has the first reference voltage as the scanning start voltage of the pixel unit P. Therefore, the pixel unit P The pixel transistor receiving the scan signal Sc should be a low-potential conduction P-type TFT. When the light-emitting signal EM has the first reference voltage, it is used as the light-emitting turn-on voltage of the pixel unit P. Therefore, the pixel unit P receives the light-emitting signal Sc The pixel transistor should be a P-type TFT that is turned on at a low potential.

Please refer to FIG. 16, which is a timing diagram of the scanning and light-emitting driving circuit 300 shown in FIG. 15 during operation. Wherein, the marking symbol in FIG. 16 is specifically: Sc(n-1) is the voltage waveform of the scanning signal output by the scanning signal output terminal Scan of the scanning and light-emitting drive circuit 100 of the n-1th stage. CLK1 represents the voltage waveform of the first clock signal, CLK2 represents the voltage waveform of the second clock signal, CLK3 represents the voltage waveform of the third clock signal, Reset represents the voltage waveform of the reset signal output by the reset terminal Re, and VB represents the upper The voltage waveform diagram of pull-down node B, VC represents the voltage waveform diagram of pull-down node C, EM(n) represents the voltage waveform diagram of the light-emitting signal EM output from the light-emitting scan output terminal Eout of the n-th stage scanning and light-emitting drive circuit 100, Sc (n) Represents the voltage waveform diagram of the scan signal Scan output from the scan signal output terminal Scan of the nth stage scan and light-emitting drive circuit 100d.

The working timing of the scanning and lighting driving circuit 300 is the same as the working timing of the scanning and lighting driving circuit 100 shown in FIG. 12, and will not be repeated in this embodiment.

Please refer to FIG. 17, which is a specific circuit structure diagram of any scanning and light-emitting driving circuit 400 shown in FIG. 4 in the fourth embodiment of the application. In this embodiment, the scanning and light-emitting driving circuit 400 is similar to that shown in FIG. The circuit structure of the scanning and lighting driving circuit 200 is basically the same, the difference is that all the transistors (the first transistor M1 to the eleventh transistor M11) in the scanning and lighting driving circuit 400 are all P-type thin film transistors.

Please refer to FIG. 18, which is a timing diagram of the scanning and light-emitting driving circuit 400 shown in FIG. 17 during operation. The working timing of the scanning and lighting driving circuit 400 is the same as the working timing of the scanning and lighting driving circuit 200 shown in FIG. 14, and will not be repeated in this embodiment.

As shown in FIG. 19, it is a circuit block diagram of the light-emitting driving circuit in any scanning and light-emitting driving circuit 500 shown in FIG. 4 in the fifth embodiment of the application. In this embodiment, the light-emitting driving circuit includes a first control circuit 11 , The second control circuit 12, the light output circuit 13, the first inverter circuit 15, the buffer circuit 16, and the pulse width control circuit 17. The light-emitting output circuit 13 includes a light-emitting pull-up output circuit 13 and a light-emitting pull-down output circuit 14, and the pulse width control circuit 171 includes a first pulse width control circuit 171 and a second pulse width control circuit 172.

The first control circuit 11 is electrically connected to the second control circuit 12 through the first node A, and is electrically connected to the pull-up output circuit 13 through the pull-up node B, and the second control circuit 12 is electrically connected to the pull-down output through the pull-down node C Circuit 14, the first inverter circuit 15 is electrically connected between the pull-up node B and the pull-down node C.

The first control circuit 11 is electrically connected to the first clock terminal CK1, the first adjustment signal terminal Vin, the second reference voltage terminal VSS, and the first node A.

The first clock signal terminal CK1 is used to output the first clock signal CLK1 according to the first preset frequency.

The first adjustment signal terminal Vin is used to output the first adjustment signal Vi.

The second reference voltage terminal VSS is used to output the second reference voltage VSS.

The first control circuit 11 receives the first clock signal CLK1 from the first clock signal terminal CK1, so that the data writing time period Td in one scanning period T turns the first potential (high) in different time periods according to the first clock signal CLK1 And the second potential (low) is transmitted to the pull-up node B. In this embodiment, the data writing time period Td in one scanning period T receives the first clock signal CLK1 in two different time periods, and thus the first potential (high) and the second potential ( Low) is transmitted to the pull-up node B.

In this embodiment, the data writing period Td includes an adjustment period Td1, a pull-up period Td2, and a pull-down period Td3 that are continuous and non-overlapping in time.

The first clock signal terminal CK1 outputs the first clock signal during the adjustment period Td1 and the pull-down period Td3, respectively. Therefore, the first control circuit 11 sets the first potential (high) during the adjustment period Td1 and the pull-down period Td3, respectively, according to the first clock signal CLK1. ) And the second potential (low) is transmitted to the pull-up node B.

When the pull-up node B is at the second potential, the first inverter circuit 15 connected between the pull-up node and the pull-down node controls the pull-down node C to the second potential.

The second control circuit 12 is electrically connected to the second clock terminal CK2 and the first reference voltage terminal VDD.

The second clock terminal CK2 is used to output the clock signal CLK2, and the first reference voltage terminal VDD is used to output the first reference voltage.

In this embodiment, the first reference voltage is higher than the second reference voltage, for example, the first reference voltage is a high reference voltage, and the second reference voltage is a low reference voltage.

The second control circuit 12 receives the second clock signal CLK2 in the pull-up period Td2 within the data writing period Td, and transmits the first potential (high) to the pull-up node B under the control of the second clock signal CLK2, and, When the pull-up node B is at the first potential, the second potential is output to the pull-down node C.

The light-emitting pull-up output circuit 131 is electrically connected to the pull-up node B and the light-emitting signal output terminal Eout. When the pull-up node B is at the second potential, the light-emitting pull-up output circuit 131 is in a conducting state, so as to output the second reference voltage. .

The light-emitting pull-down output circuit 141 is electrically connected to the pull-down node C and the light-emitting signal output terminal Eout, and when the pull-down node C is at the first potential, it outputs a first reference voltage. In this embodiment, the first reference voltage and the second reference voltage cooperate with each other to form the light-emitting signal.

The buffer circuit 16 is electrically connected between the first control circuit 11 and the first node A, and is used to control the first node A to buffer for a certain period of time to maintain the voltage conversion with the first clock signal CLK1.

The pulse width control circuit 17 is electrically connected to the light-emitting pull-up output circuit 13, the light-emitting pull-down output circuit 14, and the light-emitting signal output terminal Eout, and is used to control the pull-up output circuit 13 to output the first reference voltage and frequency and the pull-down output circuit 14 Output the frequency of the second reference voltage.

The first pulse width control circuit 171 and the pull-up output circuit 13 are connected in series with the second reference voltage terminal VSS and the light emitting signal output terminal Eout, and the first pulse width control circuit 171 is controlled by the first pulse width signal P1 at the first frequency. Conduction state.

The second pulse width control circuit 172 and the pull-down output circuit 14 are connected in parallel to the second reference voltage terminal VDD and the light emitting signal output terminal Eout. The second pulse width control circuit 172 is turned on at the second frequency under the control of the second pulse width signal P2 status.

More specifically, please refer to FIG. 20, which is a schematic diagram of a specific circuit structure of the light-emitting driving circuit shown in FIG. 19. As shown in Figure 20,

The first control circuit 11 includes a first transistor M1, a second transistor M2, and a third transistor M3.

The gate of the first transistor M1 is electrically connected to the first clock signal terminal CK1 to receive the first clock signal CK1, the source of the first transistor M1 is electrically connected to the first adjustment signal terminal Vin, and the drain of the first transistor M1 Electrically connected to the buffer circuit 16.

The gate of the second transistor M2 is electrically connected to the first clock signal terminal CK1, the source of the second transistor M2 is electrically connected to the second reference voltage VSS, and the drain of the second transistor M2 is electrically connected to the first node A.

The gate of the third transistor M3 is electrically connected to the first clock signal terminal CK1, the source of the third transistor M3 is electrically connected to the second reference voltage VSS, and the drain of the third transistor M3 is electrically connected to the pull-up node B.

The pull-up output circuit 13 includes a fourth transistor M4. The gate of the fourth transistor M4 is electrically connected to the pull-up node B. The source of the fourth transistor M4 is electrically connected to the first pulse width control circuit 171. The drain is electrically connected to the light-emitting signal output terminal Eout.

The buffer circuit 16 includes a fourth transistor M5, a sixth transistor M6, and a fourth capacitor C4.

The gate of the fifth transistor M5 is electrically connected to the drain of the first transistor M1, the source of the fifth transistor M5 is electrically connected to the first clock signal terminal CK1, and the drain of the fifth transistor M5 is electrically connected to the sixth transistor M6.

The gate of the sixth transistor M6 is electrically connected to the drain of the first transistor M1, the source of the sixth transistor M6 is electrically connected to the drain of the fifth transistor M5, and the drain of the sixth transistor M6 is electrically connected to the first transistor. Node A.

The fourth capacitor C4 is electrically connected between the gate of the fifth transistor M5 and the first reference voltage terminal VDD.

The second control circuit 12 includes a sub-pull-up control circuit 121 and a sub-pull-down control circuit 122. The sub-pull-up control circuit 121 is used to control the voltage of the pull-up node B to be at the first potential, and the sub-pull-down control circuit 122 is used to control the voltage of the pull-down node C to be at the second potential.

Specifically, the sub-pull-up control circuit 121 is electrically connected to the first node A, the second clock signal terminal CK2, the first reference voltage terminal VDD, and the pull-up node B.

When the first control circuit 12 outputs the signal of the first potential or the second potential to the pull-up node B without receiving the first clock signal CLK1, the second clock signal of the sub-pull-up control circuit 121 at the first node A and The second reference voltage terminal VDD is output to the pull-up node B under the control of the terminal CK2, and then the voltage of the pull-up node B is controlled to the first potential.

The sub pull-down control circuit 122 is electrically connected to the first node A, the second clock signal terminal CK2, the first reference voltage terminal VDD, and the pull-down node C.

When the pull-up node B cannot control the voltage of the pull-down node C because it is at the first potential, the sub pull-down control circuit 122 outputs the second potential to the pull-down node C under the control of the first node A and the second clock signal terminal CK2. , And further control the voltage of the pull-down node B to the second potential.

More specifically, the sub-pull-up control circuit 121 includes a seventh transistor M7, an eighth transistor M8, and a first capacitor C1, and the sub-pull-down control circuit 122 includes a ninth transistor M9, a tenth transistor M10, and a second capacitor C2.

The gate of the seventh transistor M7 is electrically connected to the first node A, the source of the seventh transistor M7 is electrically connected to the first reference voltage terminal VDD, and the drain of the seventh transistor M7 is electrically connected to the eighth transistor M8.

The gate of the eighth transistor M8 is electrically connected to the second clock terminal CK2 for receiving the second clock signal CLK2, the source of the eighth transistor M8 is electrically connected to the drain of the seventh transistor M7, and the drain of the eighth transistor M8 The pole is electrically connected to the pull-up node B.

The first capacitor C1 is electrically connected between CK2 of the second clock signal and the second node.

The second capacitor C2 is electrically connected between the first node A and the second node D.

The gate of the ninth transistor M9 is electrically connected to the first node A, the source of the ninth transistor M9 is electrically connected to CK2 of the second clock signal, and the drain of the seventh transistor M7 is electrically connected to the second node D.

The gate of the tenth transistor M10 is electrically connected to CK2 of the second clock signal for receiving the second clock signal CLK2, the source of the tenth transistor M10 is electrically connected to the second node D, and the drain of the tenth transistor M10 is electrically connected Sexually connected to the drop-down node C.

The first inverter circuit 15 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is electrically connected to the pull-up node B. The source of the eleventh transistor M11 is electrically connected to the first reference voltage terminal VDD. The drain of a transistor M11 is electrically connected to the pull-down node C.

The pull-down output circuit 132 includes a twelfth transistor M12 and a third capacitor C3. among them,

The third capacitor C3 is electrically connected between the pull-down node C and the first reference voltage terminal VDD.

The gate of the twelfth transistor M12 is electrically connected to the pull-down node C, the source of the twelfth transistor M12 is electrically connected to the first reference voltage terminal VDD, and the drain of the twelfth transistor M12 is electrically connected to the light-emitting signal output terminal Eout .

The first pulse width control circuit 171 includes a thirteenth transistor M13. The gate of the thirteenth transistor M13 is electrically connected to the first pulse signal output terminal P1 for receiving the first pulse control signal P1 from the first pulse signal output terminal P1 , The source of the thirteenth transistor M13 is electrically connected to the second reference voltage terminal VSS, and the drain of the thirteenth transistor M13 is electrically connected to the drain of the fourth transistor M4.

The second pulse width control circuit 172 includes a fourteenth transistor M14. The gate of the fourteenth transistor M15 is electrically connected to the second pulse signal output terminal P2 for receiving the second pulse control signal P2 from the second pulse signal output terminal P2 , The source of the fourteenth transistor M14 is electrically connected to the first reference voltage terminal VDD, and the drain of the fourteenth transistor M14 is electrically connected to the light-emitting signal output terminal Eout.

In this embodiment, the first transistor M1 to the fourteenth transistor M14 are all P-type thin film transistors (TFT). Therefore, the first potential is a high potential, the second potential is a low potential, and the first reference voltage is a high voltage. The second reference voltage is a low level. Among them, the first transistor M1 to the fourteenth transistor M14 are turned off under high voltage control, and turned on under low voltage control.

Please refer to FIG. 21, which is a timing diagram of the light-emitting driving circuit shown in FIG. 20 during operation. Wherein, the marking symbols in FIG. 21 are specifically: Vi represents the voltage waveform diagram of the first adjustment signal Vi, CLK1 represents the voltage waveform diagram of the first clock signal, CLK2 represents the voltage waveform diagram of the second clock signal, and VA represents the first node The voltage waveform of A, VB represents the voltage waveform of the pull-up node B, VC represents the voltage waveform of the pull-down node C, P1 represents the voltage waveform of the first pulse width control signal, and P2 represents the voltage of the second pulse width control signal The waveform diagram, EM(n), represents the voltage waveform diagram of the luminescence signal EM output from the luminescence scanning output terminal Eout of the scanning and luminescence driving circuit 500.

Now, in conjunction with FIGS. 20-21, the working process of the light-emitting scanning driving circuit during 1 Frame during one frame of image scanning will be described in detail.

As shown in FIG. 21, during the reset period Tr, the first clock terminal CK1 does not output the first clock signal CLK1. Therefore, the first transistor M1 to the third transistor M3 in the first control circuit 11 are all in an off state. Therefore, the first node A and the pull-up node B are both low.

Since the pull-up node B is at a low level, the fourth transistor M4 is in a conducting state, and the thirteenth transistor M13 outputs the second reference voltage to the light-emitting scan output terminal Eout at the first frequency under the control of the first pulse signal P1.

The second clock terminal CK2 outputs the second clock signal CLK2 and then stops outputting the second clock signal CLK2. The first capacitor C1 releases the residual charge through the second clock terminal CK2 to further ensure that the voltage of the pull-up node B is low. When the output stops After the second clock signal CLK2, the eighth transistor M8 and the tenth transistor M10 are turned off, and the voltage of the pull-down node C is clamped to a high potential by the first reference voltage terminal VDD through the third capacitor C3. This completes the reset operation of the pull-up node B and the pull-down node C.

Since the pull-down node C is at a low level, the twelfth transistor M12 is in the cut-off state, and the fourteenth transistor M14 is controlled by the second pulse signal P2 to output the first reference voltage at the second frequency to the light-emitting scan output terminal Eout.

The adjustment period Td1 in the data writing period Td,

The first clock terminal CK1 outputs the first clock signal CLK1, and the first adjustment signal terminal Vin outputs the first adjustment signal. Therefore, the first transistor M1 to the third transistor M3 in the first control circuit 11 are all in a conducting state, The first node A is at a low potential by the third transistor M3 being loaded with the first reference voltage, and the pull-up node B is at a high potential due to the input of the first adjustment signal.

Since the voltage of the pull-up node B is high, the fourth transistor M4 and the eleventh transistor M11 are turned off, and the pull-up node B cannot be controlled by the eleventh transistor M11 in the first inverter circuit 15 to control the voltage of the pull-down node B to be low. Potential.

The second clock terminal CK2 does not output the second clock signal CLK2, the eighth transistor M8 and the tenth transistor M10 are turned off, and the voltage of the pull-down node C is still maintained at a high potential.

During the pull-up period Td2 in the data writing period Td, the first clock terminal CK1 stops outputting the first clock signal CLK1, and the first adjustment signal terminal Vin stops outputting the first adjustment signal. As a result, the first control circuit 11 The first transistor M1 to the third transistor M3 are all in an off state.

The voltage of the first node A is maintained at a low potential due to the effect of the second capacitor C2, and thus, the ninth transistor M9 and the seventh transistor M7 are both turned on.

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 and the tenth transistor M10 are turned on,

Thus, the sub-pull-up control circuit 121 formed by the seventh transistor M7 and the eighth transistor M8 provides the first reference voltage provided by the first reference voltage terminal VDD to the pull-up node B, and controls the voltage of the pull-up node B to continue to be maintained at a high potential. .

The sub-pull-down control circuit 122 composed of the ninth transistor M9 and the tenth transistor M10 transmits the low potential in the second clock signal CLK2 to the pull-down node C, so that the voltage of the pull-down node C jumps from a high potential to a low potential.

When the voltage of the pull-down node C is at a low level, the twelfth transistor M12 is in a conducting state. Therefore, the first reference voltage terminal VDD provides the first reference voltage output to the optical scanning output terminal Eout. At this time, the optical scanning output terminal Eout is maintained at a high level and does not change with the second pulse signal P2.

During the pull-down period Td3 in the data writing period Td, the first clock terminal CK1 outputs the first clock signal CLK1, and thus, the first transistor M1 to the third transistor M3 in the first control circuit 11 are all in an off state. The first node A is at a low potential by the third transistor M3 being loaded with the first reference voltage, and the pull-up node B is at a high potential due to the input of the first adjustment signal.

When the voltage of the pull-up node B is at a low potential, the voltage of the pull-down node C is controlled to jump to a high potential through the eleventh transistor M11 turned on in the first inverter circuit 15, the twelfth transistor M12 is turned off, and the tenth transistor M11 is turned off. The four-transistor M14 outputs the first reference voltage to the light-emitting scan output terminal Eout under the control of the second pulse signal P2.

It can be seen that in the data writing period Td, the voltage of the light-emitting scan output terminal Eout is maintained at a high potential without opening the driving current path in the pixel unit P to cause the light-emitting device to emit light, thereby ensuring correct data writing.

During the light-emitting period Tr, the pull-up node B is always maintained at a low potential under the control of the first clock signal CLK1 and the second clock signal CLK2.

The thirteenth transistor M13 outputs the second reference voltage to the light-emitting scan output terminal Eout at the first frequency under the control of the first pulse signal P1, and the fourteenth transistor M14 outputs the second reference voltage at the second frequency under the control of the second pulse signal P2. A reference voltage to the luminous scanning output terminal Eout.

It can be seen that during the light-emitting period, the duty cycle of the light-emitting signal EM can be flexibly adjusted at any time along with the first pulse signal P1 and the second pulse signal P2. Then, during the light-emitting display period of the pixel unit P, it can be adjusted by adjusting the first pulse signal P1 and P2. The duty cycle of the pulse signal P1 and the second pulse signal P2 is used to accurately adjust the duty cycle of the light-emitting signal EM, that is, the time of the low potential in the two pulse signals in a pulse period is adjusted to accurately adjust the light-emitting signal EM. The low potential time effectively adjusts the time of the driving current provided to the light-emitting device in the pixel unit P, thereby effectively preventing the stroboscopic phenomenon caused by the display frequency of the pixel unit P cannot match the current image refresh frequency.

Please refer to FIG. 22, which is a specific circuit structure diagram of the light-emitting driving circuit in any scanning and light-emitting driving circuit 600 shown in FIG. 4 in the sixth embodiment of the present application. In this embodiment, the scanning and light-emitting driving circuit 600 and FIG. The circuit structure of the scanning and light-emitting drive circuit 500 shown in 20 is basically the same, except that all the transistors in the light-emitting circuit (the first transistor M1 to the fourteenth transistor M14) are all N-type thin film transistors.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all N-type thin film transistors (TFT). Therefore, the first potential is a high potential, the second potential is a low potential, and the first reference voltage is a high voltage. The second reference voltage is a low level. Among them, the first transistor M1 to the fourteenth transistor M14 are turned off under low voltage control, and turned on under high voltage control. It should be noted that since the first reference voltage is a high voltage and the second reference voltage is a low potential, the scan signal Sc has the first reference voltage as the scan-on voltage of the pixel unit P. Therefore, the pixel unit P The pixel transistor receiving the scan signal Sc should be a high-potential N-type TFT. When the light-emitting signal EM has the first reference voltage, it is used as the light-emitting turn-on voltage of the pixel unit P. Therefore, the pixel unit P receives the light-emitting signal Sc The pixel transistor should be an N-type TFT that is turned on at a high potential.

Please refer to FIG. 23, which is a timing diagram of the light-emitting driving circuit shown in FIG. 22 during operation. The working sequence of the light-emitting drive circuit is exactly the same as the working sequence of the light-emitting drive circuit shown in FIG. 21, which will not be repeated in this embodiment.

The above are the preferred embodiments of this application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of this application, several improvements and modifications can be made, and these improvements and modifications are also considered The scope of protection of this application.

Claims

A scanning and light-emitting drive circuit, characterized in that it comprises a first control circuit, a second control circuit, a scan drive output circuit and a light-emitting drive output circuit,

The first control circuit is electrically connected to the scan drive output circuit and the light-emitting drive output circuit, and is used for controlling the scan drive output circuit to output a scan signal during a data writing period of a scan period. Receiving image data in the control pixel unit;

The second control circuit is electrically connected to the light-emitting drive output circuit, and is used for controlling the light-emitting drive output circuit to output a light-emitting signal during the light-emitting period of the scanning period, and the light-emitting signal is used to control the pixel unit The time at which the image data is displayed.
The scanning and light-emitting drive circuit according to claim 1, wherein:

The first control circuit is electrically connected to the scan drive output circuit through a pull-down node; during the data writing period, the first control circuit receives a first clock signal and adjusts it according to the first clock signal The potential of the pull-down node;

The scan drive output circuit receives a pre-start scan signal and a second clock signal under the control of the potential of the pull-down node, and outputs the scan signal according to the pre-start scan signal and the second clock signal;

The second control circuit is electrically connected to the light-emitting drive output circuit through the pull-up node, and during the light-emitting period, the second control circuit receives a third clock signal and responds to the third clock signal Adjusting the potential of the pull-up node;

In the light-emitting period, the light-emitting drive output circuit outputs a first reference voltage in the light-emitting signal under the control of the potential of the pull-up node, and the first reference voltage is used to control the display of the pixel unit The time of the image data.
3. The scanning and light-emitting drive circuit of claim 2, wherein the first control circuit is also electrically connected to the light-emitting drive output circuit through a pull-up node;

During the data writing period, the first control circuit receives a first clock signal, and adjusts the potential of the pull-up node according to the first clock signal;

In the data writing period, the light-emitting drive output circuit receives a second clock signal under the control of the potential of the pull-up node, and outputs a second reference voltage in the light-emitting signal according to the second clock signal The second reference voltage is used to control the pixel unit to stop displaying the image data.
The scan and light-emitting drive circuit according to claim 2 or 3, wherein the second control circuit is also electrically connected to the scan drive output circuit through the pull-down node;

During the light-emitting period, the second control circuit receives the third clock signal, and adjusts the potential of the pull-down node according to the third clock signal;

During the light-emitting period, the scan drive output circuit stops outputting the scan signal under the control of the potential of the pull-down node.
The scanning and light-emitting drive circuit according to claim 4, wherein:

When the voltage of the pull-up node is the second potential, the first control circuit controls the voltage of the pull-down node to be the first potential;

When the voltage of the pull-up node is at the first potential, the pull-down node is controlled to the second potential by a first inverter circuit connected between the pull-up node and the pull-down node.
5. The scanning and light-emitting drive circuit according to claim 5, wherein the light-emitting drive output circuit comprises:

A light-emitting pull-up output circuit, the control terminal of the light-emitting pull-up output circuit is electrically connected to the pull-up node, the input terminal is electrically connected to the first reference voltage terminal, and the first reference voltage terminal is used to provide The first reference voltage, the output terminal of the light-emitting pull-up output circuit is used to output the light-emitting signal, and in the light-emitting period, under the control of the potential of the pull-up node, the light-emitting pull-up output circuit Output the first reference voltage at the output terminal;

A light-emitting pull-down output circuit, the control terminal of the light-emitting pull-down output circuit is electrically connected to the pull-down node, and the input terminal is electrically connected to a second reference voltage terminal, and the second reference voltage terminal is used to provide the second reference voltage In the data writing period, under the control of the potential of the pull-down node, the output terminal of the light-emitting pull-down output circuit outputs the second reference voltage, and the light-emitting signal includes the first reference voltage and The second reference voltage.
7. The scanning and light-emitting drive circuit according to claim 6, wherein the scanning drive output circuit comprises:

A scan pull-up output circuit, the control terminal of the scan pull-up output circuit is electrically connected to the pull-up node, and the input terminal is electrically connected to the second reference voltage terminal. Under the control of the potential of the pull node, the output terminal of the scan pull-up output circuit outputs a fourth reference voltage, and the fourth reference voltage is used to control the pixel unit to stop receiving the image data;

Scan pull-down output circuit, the control terminal of the scan pull-down output circuit is electrically connected to the pull-down node, the input terminal is electrically connected to the second clock terminal to receive the second clock signal, and the output terminal is electrically connected to the scan signal output In the data writing period, under the control of the potential of the pull-down node, the output terminal of the scan pull-up output circuit outputs the third reference voltage, and the third reference voltage is used to control the The pixel unit receives the image data;

The scan signal includes the third reference voltage and the fourth reference voltage.
7. The scanning and light-emitting drive circuit according to claim 6, wherein the scanning and light-emitting drive circuit further comprises a pulse width control circuit, and the pulse width control circuit is electrically connected to the light-emitting drive output circuit for The frequency at which the light-emitting pull-up output unit outputs the first reference voltage in the light-emitting signal and the frequency at which the light-emitting pull-down output unit outputs the second reference voltage are controlled, and the first reference voltage is the same as the frequency of the second reference voltage. The frequency of the second reference voltage output is the same and the number of times the first reference voltage is output in the light-emitting period is greater than one.
8. The scanning and light emitting drive circuit according to claim 8, wherein the pulse width control circuit comprises a first pulse width control circuit and a second pulse width control circuit;

The control terminal of the first pulse width control circuit receives the first pulse width signal with the first duty cycle, the input terminal is electrically connected to the first reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-up output circuit; The first pulse width control circuit is turned on under the control of a first pulse width signal. During the light-emitting period, when the first pulse width control circuit is turned on, the first reference voltage passes through the first pulse Wide control circuit and output from the output terminal of the light-emitting pull-up output circuit;

The control terminal of the second pulse width control circuit receives a second pulse width signal with a second duty cycle, the input terminal is electrically connected to the second reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-down output circuit, the The second pulse width control circuit is turned on under the control of the second pulse width signal. During the data writing period, when the second pulse width control circuit is turned on, the second reference voltage passes through the second A pulse width control circuit and output from the output terminal of the light-emitting pull-down output circuit;

The sum of the first duty cycle and the second duty cycle is 1, and the first pulse width signal and the second pulse width signal have opposite phases.
The scanning and light-emitting drive circuit according to claim 9, wherein:

The first pulse width control circuit includes a first pulse transistor, the gate of the first pulse transistor receives the first pulse control signal, and the source of the first pulse transistor is electrically connected to the first reference voltage Terminal, the drain of the first pulse transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit;

The second pulse width control circuit includes a second pulse transistor, the gate of the second pulse body tube receives the second pulse control signal, and the source of the second pulse transistor is electrically connected to the second reference At the voltage terminal, the drain of the second pulse body tube is electrically connected to the output terminal of the light-emitting pull-down output circuit.
The scanning and light-emitting drive circuit according to any one of claims 1-10, wherein the scanning and light-emitting drive circuit further comprises a reset circuit, and the reset circuit is electrically connected to the pull-up node and the Between pull-down nodes, it is used to control the potential of the pull-up node during the reset period, so that the light-emitting drive output circuit stops the light-emitting signal, and control the potential of the pull-down node to make the scan drive output The circuit stops outputting the scan signal.
The scanning and light-emitting drive circuit according to any one of claims 2 to 11, wherein:

The first control circuit includes a first transistor, a third transistor, and a first capacitor;

The gate of the first transistor is used to receive the first clock signal, and the drain of the first transistor is electrically connected to the pull-down node;

The source of the third transistor is electrically connected to a second reference voltage terminal to receive the second reference voltage, and the drain of the third transistor is electrically connected to the pull-up node;

The first capacitor is electrically connected between the first clock signal terminal and the pull-up node.
The scanning and light-emitting drive circuit of claim 12, wherein:

The second control circuit includes a double-gate transistor, wherein both gates of the double-gate transistor are electrically connected to a third clock terminal to receive the third clock signal, and the source of the double-gate transistor The pole is electrically connected to the first reference voltage terminal, and the drain of the double-gate transistor is electrically connected to the pull-up node.
The scanning and light-emitting drive circuit of claim 12, wherein:

The light-emitting pull-up output circuit includes a fourth transistor, and the light-emitting pull-down output circuit includes a fifth transistor and a second capacitor;

The gate of the fourth transistor is electrically connected to the control terminal of the light-emitting pull-up output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit, and the fourth transistor The drain of is electrically connected to the output terminal of the light-emitting pull-up output circuit;

The gate of the fifth transistor is electrically connected to the control terminal of the light-emitting pull-down output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-down output circuit, and the drain of the fifth transistor is The pole is electrically connected to the output terminal of the light-emitting pull-down output circuit;

The second capacitor is electrically connected between the pull-down node and the second reference voltage terminal.
The scanning and light-emitting drive circuit of claim 12, wherein:

The first inverter circuit includes a sixth transistor, the gate of the sixth transistor is electrically connected to the pull-up node, and the source of the sixth transistor is electrically connected to the second reference voltage terminal, The drain of the sixth transistor is electrically connected to the pull-down node;

When the sixth transistor is turned on under the control of the pull-up node, the sixth transistor controls the voltage of the pull-down node to be the same second potential as the second reference voltage.
The scanning and light-emitting drive circuit of claim 12, wherein:

The scan pull-up output circuit includes a seventh transistor, and the scan pull-down output circuit includes an eighth transistor,

The gate of the seventh transistor is the control terminal of the scan pull-up output circuit, the source of the seventh transistor is the input terminal of the scan pull-up output circuit, and the drain of the seventh transistor is the scan terminal. Pull the output terminal of the output circuit;

The gate of the eighth transistor is the control terminal of the scan pull-down output circuit, the source of the eighth transistor is the input terminal of the scan pull-down output circuit, and the drain of the eighth transistor is the scan pull-down output circuit The output terminal.
The scanning and light-emitting drive circuit of claim 12, wherein:

The reset circuit includes a tenth transistor and an eleventh transistor;

The gate of the tenth transistor is electrically connected to the reset terminal to receive a reset signal, the source of the tenth transistor is electrically connected to the first reference voltage terminal, and the drain of the tenth transistor is electrically connected to The pull-up node;

The gate of the eleventh transistor is electrically connected to the reset terminal to receive the reset signal, the source of the eleventh transistor is electrically connected to the second reference voltage terminal, and the eleventh transistor The drain is electrically connected to the pull-down node.
A scanning and light-emitting drive system, comprising a multi-stage cascaded scanning and light-emitting drive circuit according to any one of claims 1 to 17, wherein the scanning signal output terminal of the n-1th stage scanning and light-emitting drive circuit It is electrically connected to the first control circuit of the n-th stage scanning and light-emitting drive circuit, and the scanning signal output by the n-1th stage scanning and light-emitting drive circuit is used as the pre-start scanning signal, and the n is greater than 1. Integer; the first control circuit includes a first transistor, a third transistor and a first capacitor;

The gate of the first transistor is used to receive the first clock signal, and the source of the first transistor is electrically connected to the scan signal output terminal of the n-1th stage scan and light-emitting drive circuit, so The drain of the first transistor is electrically connected to the pull-down node;

The gate of the third transistor is electrically connected to the scan signal output terminal of the n-1th stage scanning and light-emitting driving circuit, and the source of the third transistor is electrically connected to the second reference voltage terminal to receive the The second reference voltage, the drain of the third transistor is electrically connected to the pull-up node;

The first capacitor is electrically connected between the first clock signal terminal and the pull-up node.
A display panel, characterized in that the non-display area of the display panel comprises the scanning and light-emitting drive circuit according to any one of claims 1-18.
A scanning and light-emitting drive circuit, its special feature is that it includes a light-emitting drive circuit and a pulse width control circuit, the light-emitting drive circuit is used to output a light-emitting signal, the light-emitting signal is used to control the pixel unit to display the image data time,

The pulse width control circuit is electrically connected to the light-emitting drive circuit for controlling the frequency at which the light-emitting drive circuit outputs the light-emitting signal.
22. The scanning and light-emitting drive circuit of claim 20, wherein the light-emitting drive circuit comprises:

The first control circuit is electrically connected to the pull-up output circuit and the pull-down output circuit through the pull-up node, and the data writing period in one scan period controls the voltage of the pull-up node according to the received first clock signal, so that the pull-up node When the output circuit is pulled, the first reference voltage is output, and the first reference voltage controls the pixel unit to stop displaying image data;

The second control circuit is electrically connected to the pull-up output circuit through the pull-up node, the light-emitting segment in the scan period outputs a second reference voltage according to the received second clock signal, and the second reference voltage is used to control the pixel The unit displays image data, and the light-emitting signal includes the first reference voltage and the second reference voltage;

The pulse width control circuit is electrically connected to the light-emitting drive circuit for controlling the frequency at which the pull-up output circuit outputs the first reference voltage and the frequency at which the pull-down output circuit outputs the second reference voltage, And the frequency of the output of the first reference voltage and the second reference voltage is the same, and the number of times the first reference voltage is output in the light-emitting period is greater than one.
22. The scanning and light-emitting drive circuit of claim 21, wherein the light-emitting drive circuit comprises a first pulse width control circuit and a second pulse width control circuit,

The control terminal of the first pulse width control circuit receives the first pulse width signal with the first duty cycle, the input terminal is electrically connected to the first reference voltage terminal, and the output terminal is electrically connected to the light-emitting pull-up output circuit, so The first pulse width control circuit is turned on at a first frequency under the control of a first pulse width signal, and when the first pulse width control circuit is turned on during the light-emitting period, the first reference voltage passes through the first The input terminal, the output terminal, the output terminal, and the light-emitting pull-up output terminal of the pulse width control circuit are output to the light-emitting signal output terminal;

The control terminal of the second pulse width control circuit receives a second pulse width signal with a second duty cycle, the input terminal is electrically connected to the second reference voltage terminal, and the output terminal is electrically connected to the light-emitting signal output terminal. The second pulse width control circuit is turned on at the second frequency under the control of the second pulse width signal. When the second pulse width control circuit is turned on during the light-emitting period, the second reference voltage passes through the second pulse The input terminal and the output terminal of the wide control circuit are output to the light-emitting signal output terminal;

The sum of the first duty cycle and the second duty cycle is 1, and the first pulse width signal and the second pulse width signal have opposite phases.
The scanning and light-emitting drive circuit according to any one of claims 20-22, wherein:

The pull-up output circuit includes a fourth transistor, the gate of the fourth transistor is electrically connected to the pull-up node, and the source of the fourth transistor is electrically connected to the first pulse width control circuit, so The drain of the fourth transistor is electrically connected to the light-emitting signal output terminal;

The pull-down output circuit includes a twelfth transistor and a third capacitor. The third capacitor is electrically connected between the pull-down node and the first reference voltage terminal. The first reference voltage terminal provides the first reference voltage terminal. A reference voltage;

The gate of the twelfth transistor is electrically connected to a pull-down node, the source of the twelfth transistor is electrically connected to a first reference voltage terminal, and the second reference voltage terminal provides the second reference voltage. The drain of the twelfth transistor is electrically connected to the light-emitting signal output terminal.
The scanning and light-emitting drive circuit of claim 23, wherein:

The first pulse width control circuit includes a first pulse transistor, the gate of the first pulse transistor is electrically connected to the first pulse signal output terminal to receive the first pulse control signal, and the source of the first pulse transistor is electrically connected to the first pulse signal output terminal. Is electrically connected to the second reference voltage terminal, and the drain of the first pulse transistor is electrically connected to the drain of the fourth transistor;

The second pulse width control circuit includes a second pulse transistor, the gate of the second pulse transistor is electrically connected to the second pulse signal output terminal to receive the second pulse control signal, and the source of the second pulse transistor is electrically connected to the second pulse signal output terminal. Is electrically connected to the first reference voltage terminal, and the drain of the second pulse transistor is electrically connected to the light-emitting signal output terminal.
A display panel, characterized in that the non-display area of the display panel comprises the scanning and light-emitting drive circuit according to any one of claims 20-24.