CN113066422B

CN113066422B - Scanning and light-emitting drive circuit, scanning and light-emitting drive system and display panel

Info

Publication number: CN113066422B
Application number: CN201911297349.5A
Authority: CN
Inventors: 郑志伟; 白维
Original assignee: Huawei Machine Co Ltd
Current assignee: Huawei Machine Co Ltd
Priority date: 2019-12-13
Filing date: 2019-12-13
Publication date: 2022-06-24
Anticipated expiration: 2039-12-13
Also published as: WO2021115458A1; CN113066422A

Abstract

The application provides a scanning and luminous drive circuit, scanning and luminous drive circuit that volume is less, the cost is lower to and the display panel who contains aforementioned scanning and luminous drive circuit that this application provided satisfies narrow frame, high screen and accounts for the design demand of comparing. The scanning and light-emitting driving circuit comprises a first control circuit, a second control circuit, a scanning driving output circuit and a light-emitting driving output circuit. The first control circuit is electrically connected with the scanning driving output circuit and the light-emitting driving output circuit and is used for controlling the scanning driving output circuit to output scanning signals in a data writing time period in a scanning period. The second control circuit is electrically connected with the light-emitting driving output circuit and is used for controlling the light-emitting driving output circuit to output light-emitting signals in the light-emitting time period in the scanning period.

Description

Scanning and light-emitting drive circuit, scanning and light-emitting drive system and display panel

Technical Field

The present application relates to the field of image display technologies, and in particular, to a scanning and light-emitting driving circuit, a scanning and light-emitting driving system, and a display panel.

Background

In the image display process of the self-luminous display panel, a scanning driving circuit arranged in a non-display area is required to provide scanning signals and light-emitting signals, and a data driving circuit is required to provide image data signals to drive a pixel array arranged in an image display area to perform image display. In recent years, in order to improve the integration of the display panel, the gate scan driving circuit, the light emitting scan driving circuit and the pixel Array are fabricated on an Array substrate, which is also called a gate driver Array (GOA) circuit and an emission Array (EOA) circuit.

Each scan driving circuit includes a plurality of scan and light emitting driving circuits, and is usually designed in a cascade manner to sequentially output shifted scan signals to the pixel array. Each scanning driving circuit comprises a GOA circuit and an EOA circuit which are independent of each other. The scanning driving circuit has more electronic components and larger volume, so that the area of a non-display area cannot be reduced, the screen occupation ratio of the display panel is smaller, and the requirement of a narrow frame cannot be met.

Disclosure of Invention

In the embodiment of the application, a scanning and light-emitting driving circuit and a scanning and light-emitting driving system with fewer electronic components and smaller volume are provided, so that a display panel comprising the light-emitting driving circuit can meet the design requirements of narrow frames and high screen occupation ratio.

In a first aspect, in a possible implementation manner, the scanning and light-emitting driving circuit includes a first control circuit, a second control circuit, a scanning driving output circuit, and a light-emitting driving output circuit. The first control circuit is electrically connected with the scanning driving output circuit and the light-emitting driving output circuit, and is used for controlling the scanning driving output circuit to output scanning signals in a data writing time period in a scanning period, and the scanning signals are used for controlling the pixel units to receive image data. The second control circuit is electrically connected to the light-emitting driving output circuit and configured to control the light-emitting driving output circuit to output a light-emitting signal in a light-emitting time period in the scanning period, where the light-emitting signal is used to control the time for the pixel unit to display the image data.

The scanning and light-emitting drive circuit is matched with the second control circuit through the first control circuit, and controls the scanning drive circuit to output scanning signals and the light-emitting drive circuit to output light-emitting signals at different time periods. That is, the scanning and light-emitting driving circuit outputs the scanning signal and the light-emitting signal in a time-sharing manner by using the same circuit through the mode of sharing the first control circuit and the second control circuit, thereby effectively reducing the number, the volume and the occupied area of the electronic elements in the scanning and light-emitting driving circuit, and providing greater possibility for reducing the area of the region provided with the scanning and light-emitting driving circuit.

In a possible implementation manner, the first control circuit is electrically connected to the scan driving output circuit through a pull-down node; in the data writing time period, the first control circuit receives a first clock signal and adjusts the potential of the pull-down node according to the first clock signal. The scan driving output circuit receives a pre-start scan signal and a second clock signal under the control of the potential of the pull-down node, and outputs the scan signal according to the pre-start scan signal and the second clock signal. The second control circuit is electrically connected with the light-emitting drive output circuit through the pull-up node, and in the light-emitting time period, the second control circuit receives a third clock signal and adjusts the potential of the pull-up node according to the third clock signal. In the light emitting time period, the light emitting driving output circuit outputs a first reference voltage in the light emitting signal under the control of the potential of the pull-up node, and the first reference voltage is used for controlling the time for displaying the image data by the pixel unit.

Specifically, the first control circuit is further electrically connected to the light-emitting driving output circuit through a pull-up node; in the data writing time period, the first control circuit receives a first clock signal and adjusts the potential of the pull-up node according to the first clock signal. In the data writing time period, the light-emitting driving output circuit receives a second clock signal under the control of the potential of the pull-up node, and outputs a second reference voltage in the light-emitting signal according to the second clock signal, wherein the second reference voltage is used for controlling the pixel unit to stop displaying the image data.

Specifically, the second control circuit is further electrically connected to the scan driving output circuit through the pull-down node; in the light emitting time period, the second control circuit receives the third clock signal and adjusts the potential of the pull-down node according to the third clock signal. In the light emitting period, the scan driving output circuit stops outputting the scan signal under control of the potential of the pull-down node.

In the foregoing implementation manner, the first control circuit and the second control circuit control the voltages of the pull-up node and the pull-down node, so that the scan driving circuit and the light emitting driving circuit accurately output the scan signal light emitting signal at different time periods.

In one possible implementation manner, when the voltage of the pull-up node is the second potential, the first control circuit controls the voltage of the pull-down node to be the first potential. When the voltage of the pull-up node is a first potential, the pull-down node is controlled to be a second potential through a first inverting circuit connected between the pull-up node and the pull-down node. Through the arrangement of the first inverter circuit, the pull-down node can be accurately controlled to be at the first potential, and then the pull-down node can be accurately maintained to be at the second potential without a first control circuit during the period that the pull-up node is at the first potential, so that the control for the first control circuit is simpler and more convenient.

In one possible implementation manner, the light-emitting driving output circuit includes a light-emitting pull-up output circuit and a light-emitting pull-down output circuit. The control end of the light-emitting pull-up output circuit is electrically connected to the pull-up node, the input end of the light-emitting pull-up output circuit is electrically connected to the first reference voltage end, the first reference voltage end is used for providing the first reference voltage, and the output end of the light-emitting pull-up output circuit is used for outputting the light-emitting signal. In the light emitting time period, the output end of the light emitting pull-up output circuit outputs the first reference voltage under the control of the potential of the pull-up node. The control end of the luminous pull-down output circuit is electrically connected with the pull-down node, the input end of the luminous pull-down output circuit is electrically connected with a second reference voltage end, and the second reference voltage end is used for providing a second reference voltage. In the data writing time period, under the control of the potential of the pull-down node, the output end of the light-emitting pull-down output circuit outputs the second reference voltage, and the light-emitting signal includes the first reference voltage and the second reference voltage.

The light-emitting pull-up output circuit and the light-emitting pull-down output circuit in the light-emitting drive output circuit respectively output different reference voltages in different time periods under the control of voltages of the pull-up node and the pull-down node, so that the voltage of the pixel unit for receiving the image data in the light-emitting signal can be accurately output in the data writing time period, and the voltage of the pixel unit for stopping receiving the image data in the light-emitting signal output in the light-emitting time period can be controlled.

In one possible implementation manner, the scan driving output circuit includes a scan pull-up output circuit and a scan pull-down output circuit. The control end of the scanning pull-up output circuit is electrically connected to the pull-up node, and the input end of the scanning pull-up output circuit is electrically connected to the second reference voltage end. In the light emitting time period, under the control of the potential of the pull-up node, the output end of the scanning pull-up output circuit outputs a fourth reference voltage, and the fourth reference voltage is used for controlling the pixel unit to stop receiving the image data. The control end of the scanning pull-down output circuit is electrically connected with the pull-down node, the input end of the scanning pull-down output circuit is electrically connected with the second clock end to receive the second clock signal, and the output end of the scanning pull-down output circuit is electrically connected with the scanning signal output end. In the data writing time period, under the control of the potential of the pull-down node, the output end of the scan pull-up output circuit outputs the third reference voltage, the third reference voltage is used for controlling the pixel unit to receive the image data, and the scan signal includes the third reference voltage and the fourth reference voltage.

The scanning pull-up output circuit and the scanning pull-down output circuit in the scanning driving output circuit respectively output different reference voltages in different time periods under the control of the voltages of the pull-up node and the pull-down node, so that the voltage of the pixel unit for receiving the image data in the scanning signals can be accurately output in the data writing time period, and the voltage of the pixel unit for stopping receiving the image data in the scanning signals output in the light emitting time period.

In one possible implementation manner, the scanning and light-emitting driving circuit further includes a pulse width control circuit, where the pulse width control circuit is electrically connected to the light-emitting driving output circuit, and is configured to control a frequency at which the light-emitting pull-up output unit outputs the first reference voltage and a frequency at which the light-emitting pull-down output unit outputs the second reference voltage in the light-emitting signal, and the frequencies of the first reference voltage and the second reference voltage are the same and the number of times of outputting the first reference voltage in the light-emitting time period is greater than 1.

In the light-emitting time period, the duty ratio of the light-emitting signal can be flexibly adjusted at any time, instead of continuously driving the pixel unit to display at the same voltage (the duty ratio is 100%), so that during the light-emitting display period of the pixel unit, the brightness of the pixel unit can be adjusted by adjusting the output frequency of the first reference voltage for controlling the pixel unit to perform image display, thereby effectively preventing the stroboscopic phenomenon caused by the fact that the display frequency of the pixel unit cannot be matched with the current image refresh frequency.

In one possible implementation manner, the pulse width control circuit includes a first pulse width control circuit and a second pulse width control circuit. The control end of the first pulse width control circuit receives a first pulse width signal with a first duty ratio, the input end of the first pulse width control circuit is electrically connected with the first reference voltage end, and the output end of the first pulse width control circuit is electrically connected with the light-emitting pull-up output circuit; the first pulse width control circuit is turned on under control of a first pulse width signal, and in the light-emitting time period, when the first pulse width control circuit is turned on, the first reference voltage is output from an output end of the light-emitting pull-up output circuit through the first pulse width control circuit. A control end of the second pulse width control circuit receives a second pulse width signal with a second duty ratio, an input end of the second pulse width control circuit is electrically connected with the second reference voltage end, an output end of the second pulse width control circuit is electrically connected with the light-emitting pull-down output circuit, the second pulse width control circuit is conducted under the control of the second pulse width signal, and in the data writing time period, when the second pulse width control circuit is conducted, the second reference voltage is output from the output end of the light-emitting pull-down output circuit through the second pulse width control circuit; the sum of the first duty ratio and the second duty ratio is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite.

In the light-emitting time period, the duty ratio of the light-emitting signal can be flexibly adjusted at any time along with the first pulse signal and the second pulse signal, so that the duty ratio of the light-emitting signal can be accurately adjusted by adjusting the duty ratios of the first pulse signal and the second pulse signal during the light-emitting display period of the pixel unit, and the stroboscopic phenomenon caused by the fact that the display frequency of the pixel unit cannot be matched with the current image refreshing frequency is effectively prevented.

In a possible implementation manner, the first pulse width control circuit includes a first pulse transistor, a gate of the first pulse transistor receives the first pulse control signal, a source of the first pulse transistor is electrically connected to the first reference voltage terminal, and a drain of the first pulse transistor is electrically connected to the input terminal of the light emission pull-up output circuit. The second pulse width control circuit comprises a second pulse transistor, the grid electrode of the second pulse transistor receives the second pulse control signal, the source electrode of the second pulse transistor is electrically connected with the second reference voltage end, and the drain electrode of the second pulse transistor is electrically connected with the output end of the light-emitting pull-down output circuit. The first pulse width control circuit and the second pulse width control circuit respectively perform output control of the first reference voltage and the second reference voltage through one transistor as a switching element, so that the pulse width control circuit has a simple structure, and provides more possibilities for element simplification and volume reduction of the scanning and light-emitting drive circuit.

In one possible implementation manner, the scanning and light-emitting driving circuit further includes a reset circuit, where the reset circuit is electrically connected between the pull-up node and the pull-down node, and is configured to control a potential of the pull-up node in a reset period, so as to enable the light-emitting driving output circuit to stop outputting the light-emitting signal, and control a potential of the pull-down node, so as to enable the scanning driving output circuit to stop outputting the scanning signal. The pull-up node and the pull-down node are reset in the reset time period, so that the potentials of the pull-up node and the pull-down node are in the initial state, the potentials can be accurately corresponding to the potentials in the data writing time period and the light emitting time period, and the influence of residual charges of the pull-up node and the pull-down node on the work of the light emitting drive output circuit and the scanning drive output circuit is prevented.

In a possible implementation manner, the first control circuit includes a first transistor, a third transistor, and a first capacitor. The grid of the first transistor is used for receiving the first clock signal, and the drain of the first transistor is electrically connected with the pull-down node. The source of the third transistor is electrically connected to a second reference voltage terminal to receive the second reference voltage, and the drain of the third transistor is electrically connected to the pull-up node. The first capacitor is electrically connected between the first clock signal end and the pull-up node.

In one possible implementation manner, the second control circuit includes a dual-gate transistor, wherein both gates of the dual-gate transistor are electrically connected to a third clock terminal to receive the third clock signal, a source of the dual-gate transistor is electrically connected to the first reference voltage terminal, and a drain of the dual-gate transistor is electrically connected to the pull-up node.

The first control circuit respectively takes two transistors as a switch element and a capacitor, the second control circuit takes a double-grid transistor as a switch element, and the pull-up node and the pull-down node are controlled by the second control circuit at different time periods, so that the circuit structures of the first control circuit and the second control circuit are simple, and more possibilities are provided for element simplification and volume reduction of the scanning and light-emitting drive circuit.

In a possible implementation manner, the light emitting pull-up output circuit includes a fourth transistor, and the light emitting pull-down output circuit includes a fifth transistor and a second capacitor. The gate of the fourth transistor is electrically connected to the control terminal of the light-emitting pull-up output circuit, the source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit, and the drain of the fourth transistor is electrically connected to the output terminal of the light-emitting pull-up output circuit. The grid electrode of the fifth transistor is electrically connected with the control end of the light-emitting pull-down output circuit, the source electrode of the fourth transistor is electrically connected with the input end of the light-emitting pull-down output circuit, and the drain electrode of the fifth transistor is electrically connected with the output end of the light-emitting pull-down output circuit. The second capacitor is electrically connected between the pull-down node and the second reference voltage terminal.

The light-emitting pull-up output circuit and the light-emitting pull-down output circuit respectively take two transistors as a switch element and a capacitor, and output two different reference voltages in light-emitting signals at different time periods, so that the circuit structure of the light-emitting driving output circuit is simple, and more possibilities are provided for element simplification and volume reduction of the scanning and light-emitting driving circuit.

In one possible implementation manner, the first inverting circuit includes a sixth transistor, a gate of the sixth transistor is electrically connected to the pull-up node, a source of the sixth transistor is electrically connected to the second reference voltage terminal, and a drain of the sixth transistor is electrically connected to the pull-down node. When the sixth transistor is turned on under the control of the pull-up node, the sixth transistor controls the voltage of the pull-down node to be a second potential which is the same as a second reference voltage. The first inverter circuit can realize that the voltage of the pull-down node is different from that of the pull-up node by adopting one transistor, has simple circuit structure and provides more possibilities for simplifying elements of the scanning and light-emitting driving circuit and reducing the volume.

In one possible implementation, the scan pull-up output circuit includes a seventh transistor, and the scan pull-down output circuit includes an eighth transistor. The gate of the seventh transistor is the control end of the scanning pull-up output circuit, the source of the seventh transistor is the input end of the scanning pull-up output circuit, and the drain of the seventh transistor is the output end of the scanning pull-up output circuit. The gate of the eighth transistor is the control end of the scanning pull-down output circuit, the source of the eighth transistor is the input end of the scanning pull-down output circuit, and the drain of the eighth transistor is the output end of the scanning pull-down output circuit.

The scanning pull-up output circuit and the scanning pull-down output circuit respectively take two transistors as a switch element and a capacitor, and output two different reference voltages in scanning signals at different time periods, so that the circuit structure of the light-emitting driving output circuit is simple, and more possibilities are provided for element simplification and volume reduction of the scanning and light-emitting driving circuit.

In one possible implementation manner, the reset circuit includes a tenth transistor and an eleventh transistor. A gate of the tenth transistor is electrically connected to the reset terminal to receive a reset signal, a source of the tenth transistor is electrically connected to the first reference voltage terminal, and a drain of the tenth transistor is electrically connected to the pull-up node. A gate of the eleventh transistor is electrically connected to the reset terminal to receive the reset signal, a source of the eleventh transistor is electrically connected to the second reference voltage terminal, and a drain of the eleventh transistor is electrically connected to the pull-down node. The reset circuit can reset the voltage of the pull-down node and the voltage of the pull-up node by adopting two transistors, has simple circuit structure and provides more possibilities for simplifying elements of the scanning and light-emitting driving circuit and reducing the volume.

In a second aspect, the present application provides a scanning and light-emitting driving system, which includes the scanning and light-emitting driving circuit in multistage cascade, wherein a scanning signal output terminal of the n-1 th scanning and light-emitting driving circuit is electrically connected to a first control circuit of the nth scanning and light-emitting driving circuit, and a scanning signal output by the n-1 th scanning and light-emitting driving circuit is used as the pre-start scanning signal, where n is an integer greater than 1; the first control circuit comprises a first transistor, a third transistor and a first capacitor. The grid electrode of the first transistor is used for receiving the first clock signal, the source electrode of the first transistor is electrically connected with the scanning signal output end of the scanning and light-emitting driving circuit of the (n-1) th level, and the drain electrode of the first transistor is electrically connected with the pull-down node. The gate of the third transistor is electrically connected to the scan signal output terminal of the n-1 th scan and light emitting driving circuit, the source of the third transistor is electrically connected to the second reference voltage terminal to receive the second reference voltage, and the drain of the third transistor is electrically connected to the pull-up node. The first capacitor is electrically connected between the first clock signal end and the pull-up node.

In the scanning and light-emitting driving system, the scanning and light-emitting driving circuits are mutually cascaded, so that part of working time between the mutually cascaded scanning and light-emitting driving circuits is overlapped, the refresh rate of a pixel unit is effectively improved, and the requirement of high-frequency image display is met.

In a third aspect, a possible implementation manner is to provide a display panel, which includes the scanning and light-emitting driving circuit in a non-display area of the display panel. Because the scanning and light-emitting driving circuit adopts fewer electronic elements and has smaller volume, the non-display area of the display panel can be further reduced, and a larger design space is provided for narrowing the frame and improving the screen occupation ratio.

In a fourth aspect, in a possible implementation manner, a scan and emission driving circuit is provided, which includes an emission driving circuit and a pulse width control circuit, where the emission driving circuit is configured to output an emission signal, the emission signal is configured to control a time for the pixel unit to display the image data, and the pulse width control circuit is electrically connected to the emission driving circuit and configured to control a frequency at which the emission driving circuit outputs the emission signal.

In the light-emitting period, the duty ratio of the light-emitting signal can be flexibly adjusted at any time, and the pixel unit is not continuously driven to display at the same voltage (the duty ratio is 100%), so that the brightness of the pixel unit can be adjusted by adjusting the output frequency of the first reference voltage for controlling the pixel unit to perform image display in the light-emitting signal during the light-emitting display period of the pixel unit, and the stroboscopic phenomenon caused by the fact that the display frequency of the pixel unit cannot be matched with the current image refreshing frequency is effectively prevented.

In one possible implementation manner, the light-emitting driving circuit includes a first control circuit, a second control circuit, a pull-up output circuit, and a pull-down output circuit. The first control circuit is electrically connected with the pull-up output circuit and the pull-down output circuit through a pull-up node, and controls the voltage of the pull-up node according to a received first clock signal in a data writing time period in a scanning period, so that a first reference voltage is output by the pull-up output circuit, and the first reference voltage controls the pixel unit to stop displaying image data. The second control circuit is electrically connected with the pull-up output circuit through a pull-up node, and outputs a second reference voltage according to a received second clock signal in the light-emitting section in the scanning period, wherein the second reference voltage is used for controlling the pixel unit to display image data, and the light-emitting signal comprises the first reference voltage and the second reference voltage. The pulse width control circuit is electrically connected to the light-emitting driving circuit, and is configured to control the frequency at which the pull-up output circuit outputs the first reference voltage and the frequency at which the pull-down output circuit outputs the second reference voltage, where the first reference voltage and the second reference voltage have the same output frequency, and the number of times of outputting the first reference voltage in the light-emitting time period is greater than 1.

Specifically, the light emitting driving circuit includes a first pulse width control circuit and a second pulse width control circuit. The control end of the first pulse width control circuit receives a first pulse width signal with a first duty ratio, the input end is electrically connected with the first reference voltage end, the output end is electrically connected with the light-emitting pull-up output circuit, the first pulse width control circuit is conducted under the control of the first pulse width signal according to a first frequency, and when the first pulse width control circuit is conducted in the light-emitting time period, the first reference voltage is output to the light-emitting signal output end through the input end of the first pulse width control circuit, the output end and the light-emitting pull-up output end circuit. The control end of the second pulse width control circuit receives a second pulse width signal with a second duty ratio, the input end of the second pulse width control circuit is electrically connected with the second reference voltage end, the output end of the second pulse width control circuit is electrically connected with the light-emitting signal output end, the second pulse width control circuit is conducted according to a second frequency under the control of the second pulse width signal, and in the light-emitting time period, when the second pulse width control circuit is conducted, the second reference voltage is output to the light-emitting signal output end through the input end and the output end of the second pulse width control circuit. The sum of the first duty ratio and the second duty ratio is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite.

In the light-emitting time period, the duty ratio of the light-emitting signal can be flexibly adjusted at any time along with the first pulse signal and the second pulse signal, so that during the light-emitting display period of the pixel unit, the duty ratio of the light-emitting signal can be accurately adjusted by adjusting the duty ratios of the first pulse signal and the second pulse signal, and the stroboscopic phenomenon caused by the fact that the display frequency of the pixel unit cannot be matched with the current image refreshing frequency is effectively prevented.

In a possible implementation manner, the pull-up output circuit includes a fourth transistor, a gate of the fourth transistor is electrically connected to the pull-up node, a source of the fourth transistor is electrically connected to the first pulse width control circuit, and a drain of the fourth transistor is electrically connected to the light-emitting signal output terminal. The pull-down output circuit comprises a twelfth transistor and a third capacitor, the third capacitor is electrically connected between the pull-down node and the first reference voltage end, and the first reference voltage end provides the first reference voltage. The gate of the twelfth transistor is electrically connected to the pull-down node, the source of the twelfth transistor is electrically connected to the first reference voltage terminal, the second reference voltage terminal provides the second reference voltage, and the drain of the twelfth transistor is electrically connected to the light-emitting signal output terminal.

The light-emitting pull-up output circuit and the light-emitting pull-down output circuit respectively serve as a switch element and a capacitor through two transistors, and two different reference voltages in light-emitting signals are output at different time periods, so that the circuit structure of the light-emitting driving output circuit is simple, and more possibilities are provided for element simplification and volume reduction of the scanning and light-emitting driving circuit.

In a possible implementation manner, the first pulse width control circuit includes a first pulse transistor, a gate of the first pulse transistor is electrically connected to the first pulse signal output end to receive the first pulse control signal, a source of the first pulse transistor is electrically connected to the second reference voltage end, and a drain of the first pulse transistor is electrically connected to a drain of the fourth transistor. The second pulse width control circuit comprises a second pulse transistor, wherein the grid electrode of the second pulse transistor is electrically connected with the second pulse signal output end to receive a second pulse control signal, the source electrode of the second pulse transistor is electrically connected with the first reference voltage end, and the drain electrode of the second pulse transistor is electrically connected with the light-emitting signal output end.

The first pulse width control circuit and the second pulse width control circuit respectively perform output control of the first reference voltage and the second reference voltage through one transistor as a switching element, so that the pulse width control circuit has a simple structure, and provides more possibilities for element simplification and volume reduction of the scanning and light-emitting drive circuit.

In a fifth aspect, in a possible implementation manner, a display panel is provided, in which the scanning and light-emitting driving circuit is disposed in a non-display area of the display panel. Because the scanning and light-emitting driving circuit adopts fewer electronic elements and has smaller volume, the non-display area of the display panel can be further reduced, and a larger design space is provided for narrowing the frame and improving the screen occupation ratio.

Drawings

To more clearly illustrate the structural features and effects of the present application, a detailed description is given below in conjunction with the accompanying drawings and specific embodiments.

Fig. 1 is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure;

FIG. 2 is a schematic side view of the display panel shown in FIG. 1;

FIG. 3 is a schematic plan view of the array substrate of the display panel shown in FIG. 2;

FIG. 4 is a functional block diagram of a scanning and light-emitting driving system according to an embodiment of the present application;

FIG. 5 is a functional block diagram of a scanning and light emission driving system commonly used at present;

FIG. 6 is a schematic diagram of a specific circuit structure of any one of the scan driving units shown in FIG. 5;

FIG. 7 is a schematic diagram of a specific circuit structure of any one of the scan driving units shown in FIG. 5;

fig. 8 is a schematic circuit diagram of a pixel unit in the pixel matrix shown in fig. 3 or fig. 4;

FIG. 9 is a timing diagram illustrating the operation of the pixel unit shown in FIG. 8;

FIG. 10 is a circuit block diagram of any one of the scan and emission driving circuits shown in FIG. 4 according to the first embodiment of the present application;

FIG. 11 is a schematic diagram of a specific circuit structure of the scan and light-emitting driving circuit shown in FIG. 10;

FIG. 12 is a timing diagram illustrating the operation of the scan and emission driving circuit shown in FIG. 11;

fig. 13 is a specific circuit structure diagram of any one of the scanning and light-emitting driving circuits shown in fig. 4 in the second embodiment of the present application;

FIG. 14 is a timing diagram illustrating the operation of the scan and emission driving circuit shown in FIG. 13;

fig. 15 is a specific circuit structure diagram of any one of the scanning and light-emitting driving circuits shown in fig. 4 in the third embodiment of the present application;

FIG. 16 is a timing diagram illustrating the operation of the scan and emission driving circuit shown in FIG. 15;

fig. 17 is a specific circuit structure diagram of any one of the scanning and light-emitting driving circuits shown in fig. 4 in the fourth embodiment of the present application;

fig. 18 is a timing chart of the operation of the scanning and light-emitting driving circuit shown in fig. 17.

Fig. 19 is a circuit block diagram of a light-emitting driving circuit in any one of the scanning and light-emitting driving circuits shown in fig. 4 according to a fifth embodiment of the present application;

fig. 20 is a schematic diagram of a specific circuit structure of the light-emitting driving circuit shown in fig. 19;

fig. 21 is a timing chart of the operation of the light emission driving circuit shown in fig. 20;

fig. 22 is a specific circuit structure diagram of a light-emitting driving circuit in any one of the scanning and light-emitting driving circuits shown in fig. 4 according to a sixth embodiment of the present application;

fig. 23 is a timing chart of the operation of the light-emission driving circuit shown in fig. 22.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Please refer to fig. 1, which is a schematic plan view illustrating a display panel dp (display panel) according to an embodiment of the present application. The display panel DP is applied to the display device 10 to perform image display, in this embodiment, the display device 10 may be, for example, a mobile communication terminal, a display, a television, and the like, and certainly, the display device needs to perform image display and needs to be provided with other components (not shown), such as a power module, a signal processor module, and a signal sensing module.

The display panel DP includes a display area AA (active area) and a non-display area na (non active area), wherein the display area AA is used for performing image display. The non-display area NA is disposed around the display area AA, does not perform image display, and is used to dispose driving, control circuits, and conductive traces.

Please refer to fig. 2, which is a schematic side view of the display panel DP shown in fig. 1. As shown in fig. 2, the display panel DP includes an array substrate 11c and an opposite substrate 11d, and a display medium layer 11e sandwiched between the array substrate 11c and the opposite substrate 11 d. In this embodiment, the display medium in the display medium layer 11e is an Organic Light Emitting semiconductor (OLED), and in other embodiments of the present application, the display medium may also be a Micro Light Emitting Diode (Micro-LED) or a Light Emitting Diode (LED).

Please refer to fig. 3, which is a schematic plan view of the array substrate 11c of the display panel DP shown in fig. 2. As shown in fig. 3, the corresponding image display area 11a of the array substrate 11c includes a plurality of m × n Pixel units (pixels) P, m Data lines (Data lines) 120, 2n Scan driving lines (Scan lines) 130, and 2n light emitting driving lines (Emission lines) 140 arranged in a matrix, where m and n are natural numbers greater than 1.

The data lines 120 are arranged at a first predetermined distance along the X direction, and the data lines 120 are insulated from each other and arranged in parallel. Each data line 120 extends in the Y direction Y. It is noted that the X-direction and the Y-direction are perpendicular to each other.

The plurality of scanning driving lines 130 are also arranged at a second predetermined distance along the Y direction, and the plurality of scanning driving lines 130 are insulated from each other and arranged in parallel. Each of the scan driving lines 130 extends in the X direction.

The plurality of light emitting driving lines 140 are also arranged at a second predetermined distance along the Y direction, and the plurality of light emitting driving lines 140 are insulated from each other and arranged in parallel. Each of the light emission driving lines 140 extends in the X direction.

It is noted that the plurality of scanning driving lines 130, the plurality of light emitting driving lines 140 and the plurality of data lines 120 are insulated from each other.

For convenience of illustration, the m data lines 120 are respectively defined as D1, D2, … …, Dm-1, Dm; the 2n scanning drive lines 130 are respectively defined as G1, … …, Gn-1, Gn +1 … … and G2n according to the position sequence; the 2n light emitting driving lines 140 are defined as E1, … …, En-1, En +1, … …, and E2n, respectively, in order of position. Each pixel unit P is electrically connected to a scan driving line 130 extending along the X direction, a light emitting driving line 140 extending along the X direction, and a data line 120 extending along the Y direction.

A timing control circuit 101 for driving the pixel units to display images, a Data Driver circuit (Data Driver)102, and a Scan and Emission Driver system (Scan and Emission Driver)103 are disposed in correspondence with the non-display area NA of the display panel DP, and these circuits may be disposed on the array substrate 11 c. The timing control circuit 101 and the Data Driver circuit (Data Driver)102 may also be disposed at a position other than the non-display area NA of the display panel DP, for example, at a back surface of the array substrate 11c, wherein a surface of the array substrate 11c on which the pixel unit P is disposed is a front surface of the array substrate 11 c.

The data driving circuit 102 is electrically connected to the data lines 120, and is configured to transmit image data (data) to be displayed to the pixel units P through the data lines 120 in the form of voltage.

The scanning and light-emitting driving system 103 is electrically connected to the plurality of scanning driving lines 130 and the plurality of light-emitting driving lines 140, respectively, and is configured to output a scanning signal Sc for controlling when the pixel unit P receives the image data through the plurality of scanning driving lines 130, and output a light-emitting signal EM for controlling when the pixel unit P emits light according to the received image data through the plurality of light-emitting driving lines 140.

The scanning and light-emitting driving system 103 sequentially outputs scanning signals Sc1, … …, Sc n-1, Scn +1 … … and Sc2n from the scanning driving lines G1, … …, Gn-1, Gn +1 … … and G2n in a scanning period based on the position arrangement order of the plurality of scanning driving lines 130, and the scanning and light-emitting driving system 103 sequentially outputs light-emitting signals E1 and … …, EMn-1, EMn +1, … … and EM2n from the scanning driving lines E1, … …, En-1, En +1 and … … and E2n in a scanning period based on the position arrangement order of the plurality of light-emitting driving lines 140.

The timing control circuit 101 is electrically connected to the data driving circuit 102 and the scanning and light emitting driving system 103, respectively, and is configured to control the working timings of the data driving circuit 102 and the scanning and light emitting driving system 103, that is, the timing control circuit 101 outputs a corresponding timing control signal to the data driving circuit 102 to control when the data driving circuit 102 outputs the image data; and outputting the corresponding timing control signal to the scanning and light-emitting driving system 103 to control when the scanning and light-emitting driving system 103 outputs the corresponding scanning signal Gn and light-emitting signal En.

In this embodiment, the circuit elements in the scanning and light-emitting driving system 103 and the pixel units P in the display panel 11 are fabricated in the display panel 11 in the same process. It can be understood that the display terminal 10 further includes other auxiliary circuits for jointly completing the display of the image, such as an image receiving Processing circuit (GPU) or a power circuit, and details thereof are not described in this embodiment.

Please refer to fig. 4, which is a functional block diagram of a scanning and light-emitting driving system 103 according to an embodiment of the present application. As shown in fig. 4, the scanning and light-emission driving system 103 includes 2n scanning and light-emission driving circuits 103u cascaded to each other, and the plurality of scanning and light-emission driving circuits 103u cascaded to each other are connected to 2n sets of scanning lines (not shown), respectively. When the plurality of scanning and light-emitting driving circuits 103u are cascaded with each other, the scanning signal in each scanning and light-emitting driving circuit 103u is output to the scanning line electrically connected thereto, and is also output to the next scanning and light-emitting driving circuit 103u as an Enable signal for the next scanning and light-emitting driving circuit 103 u. The operation enable signal is used for controlling a part of electronic components in the scanning and light-emitting driving circuit 103u to start and initialize, and is used for preparing the scanning signal and the light-emitting signal output by the scanning and light-emitting driving circuit 103 u.

Specifically, for example, the manner in which the 2n scanning and light-emitting driving circuits 103u are cascaded mutually is as follows: the scanning output end of the n-1 th scanning and light-emitting driving circuit is electrically connected to the initial Enable end Enable of the nth scanning and light-emitting driving circuit 103 u. Here, the scanning signal in the n-1 th scanning and light-emitting driving circuit 103u is also simultaneously output to the initial Enable end Enable of the n-th scanning and light-emitting driving circuit 103u, so that the scanning signal in the n-1 th scanning and light-emitting driving circuit 103u is also used as the pre-start scanning signal of the n-th scanning and light-emitting driving circuit 103u, that is, the operation Enable (Enable) signal described in this embodiment is the pre-start scanning signal.

In this embodiment, each of the scanning and light-emitting driving circuits 103u uses the same circuit to output the scanning signal and the light-emitting signal, that is, the circuit for outputting the scanning signal and the circuit for outputting the light-emitting signal are the same, and it is not necessary to separately set a circuit for outputting the scanning signal and the light-emitting signal, which effectively saves the number of electronic components and simplifies the circuits.

As shown in fig. 4, for any adjacent three cascaded scanning and light-emitting driving circuits 103u, for example, the n-1 th, nth, and n +1 th scanning and light-emitting driving circuits 103u are configured as follows:

the scanning and light-emitting driving circuit 103u of the (n-1) th stage outputs the scanning signal Sc through the scanning signal output terminal Scan and outputs the light-emitting signal EM through the light-emitting signal output terminal Eout to the (n-1) th group of scanning lines, and at the same time, the scanning and light-emitting driving circuit 103u of the (n-1) th stage also outputs the scanning signal Sc to the initial Enable terminal Enable of the scanning and light-emitting driving circuit 103u of the nth stage as a pre-start scanning signal to drive the scanning and light-emitting driving circuit 103u of the nth stage to start operating.

The nth scanning and light-emitting driving circuit 103u outputs scanning signals and light-emitting signals to the nth group of scanning lines, and meanwhile, the nth scanning and light-emitting driving circuit 103u also outputs scanning signals to the (n + 1) th scanning and light-emitting driving circuit 103u to drive the (n + 1) th scanning and light-emitting driving circuit 103u to start operating.

By analogy, the scanning and light-emitting driving circuits 103u of other stages are cascaded in the aforementioned cascade manner, and the description of this embodiment is omitted.

Each group of scanning lines includes a gate scanning line Gk and a light emission driving line Ek, k being any positive integer greater than 1 and less than 2 n. The plurality of scanning and light-emitting driving circuits 103u sequentially provide scanning signals to the plurality of groups of scanning driving lines in the pixel array and provide light-emitting signals to the plurality of groups of light-emitting driving lines.

In the driving display of one Frame image (1Frame), each scan and light-emitting driving circuit 103u outputs a scan signal and a light-emitting signal of one scan period to a group of scan lines connected to the scan and light-emitting driving circuit 103 u. It can be understood that, for 2n groups of scan lines, the display driving time of one Frame image (1Frame) includes 2n scan periods, that is, 2n scan and light emitting driving circuits 103u each output a scan signal and a light emitting signal of one scan period to a corresponding group of scan lines.

Each of the scanning and light-emission driving circuits 103u receives a clock signal CLK through a timing control circuit 101 electrically connected thereto, and simultaneously receives a Reset signal Reset through a Reset circuit (not shown) electrically connected thereto. In this embodiment, the reset circuit may be disposed in the non-display area NA of the array substrate 11 c. With reference to fig. 4, each pixel unit P includes a pixel driving circuit (not shown) and a light emitting device (not shown), the pixel driving circuit starts to receive the image data under the control of the scanning signal, and then the light emitting device starts to emit light according to the image data under the control of the light emitting signal. And the image display is completed when all the pixel units P in the display area AA output light according to the image data. That is, the scan signal is used to select and scan on the pixel driving circuit in the pixel unit connected to one group of the scan lines, so that the pixel driving circuit receives the image data because the pixel driving circuit is scan-on. The light-emitting signal is used to control when the driving current corresponding to the image data is supplied to the light-emitting device to perform image display, or the light-emitting signal is used to control the adjustment of the light-emitting time of the light-emitting device in the pixel unit P.

Please refer to fig. 5, which is a functional block diagram of a scan and light emitting driving circuit 103 commonly used at present. As shown in fig. 5, in the present embodiment, each of the scan and light-emitting driving circuits 103u includes an independent scan driving circuit GU and an independent light-emitting driving circuit EU. The scan driving circuit GU is used for outputting a scan signal, and the emission driving circuit EU is used for outputting an emission signal.

Specifically, please refer to fig. 6-7, wherein fig. 6 is a schematic circuit diagram of a specific circuit structure of any one of the scan driving units GUn shown in fig. 5, and fig. 7 is a schematic circuit structure diagram of any one of the scan driving units EUn shown in fig. 5.

As shown in fig. 6, the scan driving circuit GU for outputting the scan signal includes 8 transistors M1 to M8 and 2 capacitors C1 to C2, and as shown in fig. 7, the light emission driving circuit EU for outputting the light emission signal includes 12 transistors M1 to M12 and 3 capacitors C1 to C3.

As can be seen from fig. 5-7, the scan driving circuit GU and the emission driving circuit EU do not share any electronic components, and each of the scan and emission driving circuits 103u including the scan driving circuit GU and the emission driving circuit EU which are independent of each other at least includes 20 transistors and 5 capacitors in total. It can be seen that the number of electronic components in each scan and light emitting driving circuit 103u is large, the occupied area is large, and the miniaturization is impossible, so that the area reduction of the non-display region is more difficult.

However, in the embodiment, each of the scanning and light-emitting driving circuits 103u adopts the same circuit to output the scanning signal and the light-emitting signal, that is, the scanning driving circuit for outputting the scanning signal and the light-emitting driving circuit for outputting the light-emitting signal in the scanning and light-emitting driving circuit 103u can be implemented by using the same circuit, so that the number of electronic components in the scanning and light-emitting driving circuit 103u and the scanning and light-emitting driving circuit 103 is effectively reduced, the volume and the occupied area of the scanning and light-emitting driving circuit 103 are correspondingly reduced, and a greater possibility is provided for reducing the area of the non-display region.

Specifically, please refer to fig. 8, which is a schematic circuit diagram of a pixel unit P in the pixel matrix shown in fig. 3 or fig. 4. The pixel matrix includes a plurality of pixel units P distributed in an array and for performing image display. As shown in fig. 8, the internal circuit structure of any one pixel unit P in the pixel matrix is shown, for example, one pixel unit P located in the nth row and the jth column of the pixel matrix. The pixel unit P includes a 6T1C pixel driving circuit and a light emitting device OLED. It is to be noted that k is an integer of 1 or more and 2n or less, and j is an integer of 1 or more and m or less.

Specifically, the 6T1C pixel driving circuit within the pixel unit P includes a first pixel transistor T1, a second pixel transistor T2, a third pixel transistor T3, a fourth pixel transistor T4, a fifth pixel transistor T5, a sixth pixel transistor T6, and a driving capacitor CP 1.

For the pixel unit P in the kth row and the jth column, the gate of the sixth pixel transistor T6 in the pixel unit P is electrically connected to the scan driving line G (n-1) in the (n-1) th row for receiving the scan signal Sc (n-1); the drain of the sixth pixel transistor T6 is electrically connected to the initialization terminal for receiving the initialization voltage VINIT, and the source of the sixth pixel transistor T6 is electrically connected to the gate of the first pixel transistor T1.

The driving capacitor CP1 has one end connected to the light-emitting high-voltage driving terminal ELVDD and the other end connected to the source of the sixth pixel transistor T6.

A gate of the fifth pixel transistor T5 is electrically connected to the light-emitting driving line e (n) in the kth row, and is configured to receive a light-emitting signal em (n); the drain of the fifth pixel transistor T5 is electrically connected to the light emitting high voltage driving terminal ELVDD for receiving the light emitting driving voltage V_DDThe source of the fifth pixel transistor T5 is electrically connected to the source of the second pixel transistor T2.

A gate of the second pixel transistor T2 is electrically connected to the scan driving line g (n) in the (k-1) th row for receiving the scan signal scan (n), a drain of the second pixel transistor T2 is electrically connected to the jth column data line for receiving the book voltage V of the image data_DATA。

The drain of the first pixel transistor T1 is electrically connected to the source of the second pixel transistor T2, and the source of the first pixel transistor T1 is electrically connected to the drain of the fourth pixel transistor T4.

The gate of the third pixel transistor T3 is electrically connected to the scan driving line g (n) in the (n-1) th row for receiving the scan signal sc (n), the drain of the third pixel transistor T3 is electrically connected to the gate of the first pixel transistor T1, and the source of the third pixel transistor T3 is electrically connected to the drain of the fourth pixel transistor T4.

A gate of the fourth pixel transistor T4 is electrically connected to the light-emitting driving line e (n) in the nth row for receiving the light-emitting signal em (n), and a source of the fourth pixel transistor T4 is electrically connected to the Anode terminal Anode of the light-emitting device OLED.

And the cathode of the light-emitting device OLED is electrically connected with the low-voltage driving end ELVSS.

For any one of the pixel units P in the k-th row, it is necessary to perform selection of the pixel unit by receiving gate scanning signals from the scanning driving lines Gn and Gn-1, and to perform the voltage V of the image data by receiving light emitting signals from the light emitting driving line En_DATALoading. That is, each pixel unit P requires at least the cooperation of the light-emitting signal, the scan signal, the image data, the clock signal, and the reset signal to accurately perform the correct display of the image data.

In this embodiment, the pixel transistors T1 to T6 are all P-type Thin Film Transistors (TFTs), and thus, in different time periods, the light emission signal, the scan signal, the image data, the clock signal, and the reset signal control the pixel transistors T1 to T6 to be turned on at a low level and the pixel transistors T1 to T6 to be turned off at a high level. The states of the pixel transistors T1 to T6 turned on and off under the control of the light-emitting signal, the scanning signal, the image data, the clock signal, and the reset signal in different periods of time can be specifically described with reference to fig. 9.

In other embodiments of the present application, the pixel transistors T1 to T6 may be all N-type Thin Film Transistors (TFTs), so that the pixel transistors T1 to T6 are controlled to be turned on when the emission signal, the scan signal, the image data, the clock signal, and the reset signal are at a high level and the pixel transistors T1 to T6 are controlled to be turned off when the emission signal, the scan signal, the image data, the clock signal, and the reset signal are at a low level in different periods.

In addition, in other embodiments of the present application, the number of pixel transistors and the number of capacitors included in the pixel driving circuit may be adjusted according to actual requirements, for example, a 2T1C pixel driving circuit composed of 2 pixel transistors and 1 capacitor; a 4T1C pixel driving circuit composed of 4 pixel transistors and 1 capacitor; a 4T2C pixel driving circuit composed of 4 pixel transistors and 2 capacitors; a 5T1C pixel driving circuit composed of 5 pixel transistors and 1 capacitor; a 2T1C pixel driving circuit composed of 5 pixel transistors and 2 capacitors; a 7T1C pixel drive circuit composed of 7 pixel transistors and 1 capacitor; or a 7T2C pixel driving circuit composed of 7 pixel transistors and 2 capacitors.

In this embodiment, in one scanning period of one frame image display period, a Reset period (Reset) Tr, a Data writing period (Data) Td, and a light emitting period (Emission) Te are included in chronological order, where the three periods are continuous and uninterrupted in time and have no interval. That is, the reset period Tr, the data writing period Td, and the light emitting period Te are continuous in time without an interval and without overlap. Wherein, one scanning period of the pixel unit P is a working period of the pixel unit P in the process of displaying a frame of image.

Referring to fig. 9, which is a timing diagram illustrating the operation of the pixel unit P shown in fig. 8, the operation of the pixel unit P will now be described in detail with reference to fig. 8 and 9.

In the reset period Tr, the scan signal Sc (n-1) provided by the scan driving line Gn-1 is at a low level, the initialization voltage VINIT is provided to the gate of the first pixel transistor T1, and the initialization is performed for the node where the gate of the first pixel transistor T1 is located, and at the same time, the driving capacitor CP1 performs initialization, so that the electrical signal in the previous scan cycle remaining in the pixel unit P is ensured to be discharged completely.

In the data writing period Td, the scan signal sc (n) provided by the scan driving line Gn is at a low level, the first pixel transistor T1, the second pixel transistor T2, and the third pixel transistor T3 are turned on, and the voltage V corresponding to the image data is applied_DATATo the Anode terminal (Anode) of the light emitting element OLED.

In the emission period Te, the emission signal em (n) provided by the emission driving line En is at a low level, the fourth pixel transistor T4 and the fifth pixel transistor T5 start to be turned on, and the driving voltage V for emission_DDThe driving path constituted by the fifth pixel transistor T5, the first pixel transistor T1, and the fourth pixel transistor T4 matches the voltage V of the image Data_DATAAnd outputting the driving current to the light emitting device OLED to drive the light emitting device OLED to emit light according to the image data to perform image display.

Please refer to fig. 10, which is a circuit block diagram of a scanning and light-emitting driving circuit 100 of the scanning and light-emitting driving circuit 103u in fig. 4 according to a first embodiment of the present application.

As shown in fig. 8, the scanning and light-emission driving circuit 100 includes a first control circuit 11, a second control circuit 12, a light-emission drive output circuit 13, a scanning drive output circuit 14, a first inverter circuit 15, a buffer circuit 16, and a reset circuit 18.

The first control circuit 11 and the second control circuit 12 are both electrically connected to the light-emitting output circuit 13 through a pull-up node B, and meanwhile, the first control circuit 11 and the second control circuit 12 are both electrically connected to the Scan output circuit 14 through a pull-up node B, the light-emitting output circuit 13 is also electrically connected to the light-emitting signal output end Eout, and the Scan output circuit 14 is also electrically connected to the Scan signal output end Scan.

The first control circuit 11 is used for controlling the voltage of the pull-up node B to be the second potential (the second potential is the low potential) and simultaneously controlling the voltage of the pull-down node C to be the first potential (the first potential is the high potential) in the data writing period Td according to the first clock signal CLK1 received from the first clock terminal CK 1.

In the data writing period Td, when the voltage of the pull-down node C is the first potential, the light-emitting driving circuit 13 is controlled to output the second reference Voltage (VSS) as the light-emitting signal EM to the light-emitting signal output end Eout under the control of the voltage of the pull-down node C being the first potential, wherein the pixel unit P cannot be driven to display an image when the light-emitting signal EM is the second reference Voltage (VSS); when the voltage of the pull-down node C is at the first level, the Scan output circuit 14 is controlled to output a third reference voltage (high voltage) as a Scan signal Sc from the Scan signal output terminal Scan according to the second clock signal CLK2 received from the second clock terminal CK2, wherein the third reference voltage in the Scan signal Sc is loaded to the pixel unit P through the corresponding Scan driving line, and the pixel unit P is controlled to receive the image data.

In the data writing period Td, when the voltage of the pull-up node B is the second potential, the light emission driving output circuit 13 is controlled to output the first reference Voltage (VDD) as the light emission signal EM, wherein the light emission signal EM is the first reference Voltage (VDD) capable of driving the pixel unit to perform image display; and simultaneously controlling the scan driving circuit 14 to stop outputting the fourth reference Voltage (VSS) as the scan signal Sc, wherein the scan signal Sc is capable of driving the pixel unit to stop receiving the image data.

In this embodiment, the first reference voltage and the third reference voltage are both high-level voltages, and the second reference voltage and the fourth reference voltage are low-level voltages.

The second control circuit 12 is configured to control the voltage of the pull-up node B to be the first potential (high) according to the third clock signal CLK3 received from the third clock terminal CK3 during the light emitting period Te, while the first potential of the pull-up node B controls the voltage of the pull-down node C to be the second potential (low) through the first inverter circuit 15. The first inverter circuit 15 is electrically connected between the pull-up node B and the pull-down node C, and is configured to control the voltage of the pull-down node C to be a second potential when the pull-up node B is at a first potential.

In the light emission period Te, when the voltage of the pull-up node B is the first potential, the light emission driving output circuit 13 is controlled to output the first reference Voltage (VDD) for controlling the pixel driving circuit in the pixel unit P to load the driving current into the light emitting device OLED to drive the light emitting device OLED to emit light and cause the pixel unit P to perform image display. When the voltage of the pull-up node B is the first potential, the scan driving circuit 14 is controlled to output the fourth reference Voltage (VSS) as the scan signal Sc.

In the light-emitting period Te, when the voltage of the pull-down node C is the second potential, the light-emitting driving output circuit 13 is controlled to stop outputting the second reference Voltage (VSS), and the scanning driving output circuit 14 is controlled to output the second reference voltage (low) as the scanning signal to be output from the scanning signal output terminal Scan, at this time, the scanning driving line Scan (n) loaded with the scanning signal is not subjected to effective scanning, that is, the pixel circuits P of the scanning driving line loaded with the scanning signal Sc cannot be turned on, and at this time, the image data cannot be loaded into the corresponding pixel circuits P.

The buffer circuit 16 is electrically connected to the pull-down node C and the second control circuit 12, and configured to obtain the second reference Voltage (VSS) from the second control unit 12 and output the second reference Voltage (VSS) to the light-emitting signal output end Eout under the control of the first potential of the pull-down node C in the data writing period Td, so as to accurately control the light-emitting signal output end Eout to be maintained at the second reference Voltage (VSS).

The Reset circuit 18 is electrically connected to the pull-up node B and the pull-down node C, respectively, and is configured to control the voltage of the pull-up node B to be a first potential and control the voltage of the pull-down node C to be a second potential according to a Reset signal Reset provided at a Reset terminal Re during a Reset period Tr. In this embodiment, the Reset terminal Re is electrically connected to the Reset circuit (fig. 4) to receive the Reset signal Reset.

In this embodiment, the first control circuit 11, the second control circuit 12, the light emission output circuit 13, the first inverter circuit 15, the buffer circuit 16, and the reset circuit 18 cooperate to form a light emission driving circuit, and the first control circuit 11, the second control circuit 12, the scan output circuit 14, the first inverter circuit 15, the buffer circuit 16, and the reset circuit 18 cooperate to form a scan driving circuit. That is, the light-emitting driving circuit and the scanning driving circuit share the first control circuit 11, the second control circuit 12, the first inverter circuit 15, the buffer circuit 16 and the reset circuit 18, so that electronic components and volume of the scanning and light-emitting driving circuit 103u are effectively reduced, and integration level of the scanning and light-emitting driving circuit 103u is improved.

Referring to fig. 11, which is a schematic circuit diagram illustrating a specific circuit structure of the scan and light emitting driving circuit 100 shown in fig. 10, as shown in fig. 11, the first control circuit 11 includes a first transistor M1, a third transistor M3, and a first capacitor C1.

The gate of the first transistor M1 is electrically connected to the first clock signal terminal CK1 for receiving the first clock signal CK1, the source of the first transistor M1 is electrically connected to the Scan signal output terminal Scan (n-1) of the n-1 th Scan and light emitting driving circuit 103u, and the drain of the first transistor M1 is electrically connected to the pull-down node B.

The gate of the third transistor M3 is electrically connected to the Scan signal output terminal Scan (n-1) of the n-1 th Scan and light emitting driving circuit 103u, the source of the third transistor M3 is electrically connected to the second reference voltage terminal VSS, and the drain of the third transistor M3 is electrically connected to the pull-up node B.

The first buffer capacitor C1 is electrically connected between the first clock signal terminal CK1 and the pull-up node B.

The second control circuit 12 includes a double-gate transistor M2, wherein the double-gate transistor M2 is composed of 2 sub-transistors connected in series, and the 2 sub-transistors connected in series can be a transistor M2a and a transistor M2 b.

The gate of the transistor M2a is electrically connected to the third clock terminal CK3, the source of the transistor M2a is electrically connected to the first reference voltage terminal VDD, and the drain of the transistor M2a is electrically connected to the source of the transistor M2 b.

The gate of the transistor M2B is electrically connected to the third clock terminal CK3, and the drain of the transistor M2a is electrically connected to the pull-up node B.

The light-emitting output circuit 13 further includes a light-emitting pull-up output circuit 131 and a light-emitting pull-down output circuit 132. The light-emitting pull-up output circuit 131 is electrically connected to the pull-up node B and the light-emitting signal output end Eout, and outputs the first reference voltage VDD when the pull-up node B is at the second potential.

The light-emitting pull-down output circuit 132 is electrically connected to the pull-down node C and the light-emitting signal output end Eout, and outputs a second reference Voltage (VSS) when the voltage of the pull-down node C is a second potential, where the first reference Voltage (VDD) and the second reference Voltage (VSS) form the light-emitting signal, and the pixel unit P is driven to perform image display when the light-emitting signal is the first reference Voltage (VDD).

In this embodiment, the light emitting pull-up output circuit 131 includes a fourth transistor M4, and the light emitting pull-down output circuit 132 includes a fifth transistor M5 and a second capacitor C2.

The gate of the fourth transistor M4 is electrically connected to the pull-up node B, the source of the fourth transistor M4 is electrically connected to the first reference voltage terminal VDD, and the drain of the fourth transistor M4 is electrically connected to the light-emitting signal output terminal Eout.

The gate of the fifth transistor M5 is electrically connected to the pull-down node C, the source of the fourth transistor M5 is electrically connected to the second reference voltage terminal VSS, and the drain of the fifth transistor M5 is electrically connected to the light-emitting signal output terminal Eout.

The second capacitor C2 is electrically connected between the pull-down node B and the second reference voltage terminal VSS.

The first inverter circuit 15 includes a sixth transistor M6, a gate of the sixth transistor M6 is electrically connected to the pull-up node B, a source of the sixth transistor M6 is electrically connected to the second reference voltage terminal VSS, and a drain of the sixth transistor M6 is electrically connected to the pull-down node C.

When the sixth transistor M6 is turned on under the control of the pull-up node B, the voltage of the pull-down node C is controlled to be the same second potential as the second reference voltage. That is, when the pull-up node B is at the first potential capable of controlling the sixth transistor M6 to be in a turned-on state, the pull-down node C can be controlled to be at the second potential opposite to the pull-up node B, so that the voltages of the pull-up node B and the pull-down node C are in opposite phases.

The scan output circuit 14 is electrically connected to the pull-up node B and the pull-down node C, and is configured to output a scan signal Sc in a data writing period Td, and includes a scan pull-up output circuit 141 and a scan pull-down output circuit 142.

The Scan pull-up output circuit 141 is electrically connected to the pull-up node B and the Scan signal output terminal Scan, and controls the Scan pull-up output circuit 141 to output the second reference Voltage (VSS) when the pull-up node B is at the first potential. The Scan pull-down output circuit 142 is electrically connected to the pull-down node C and the Scan signal output terminal Scan, and controls the Scan pull-up output circuit 141 to output a first reference voltage (high potential of CLK) to the Scan signal output terminal Scan when the pull-down node C is at the first potential, where the first reference voltage is used as the Scan signal Sc.

In this embodiment, the scan pull-up output circuit 141 includes a seventh transistor M7, and the scan pull-down output circuit 142 includes an eighth transistor M8.

The gate of the seventh transistor M7 is electrically connected to the pull-up node B, the source of the seventh transistor M7 is electrically connected to the second reference voltage terminal VSS, and the drain of the seventh transistor M7 is electrically connected to the Scan signal output terminal Scan.

The gate of the eighth transistor M8 is electrically connected to the pull-down node C, the source of the eighth transistor M8 is electrically connected to the second clock terminal CK2 for receiving the second clock signal CLK2, and the drain of the eighth transistor M8 is electrically connected to the Scan signal output terminal Scan.

The buffer circuit 16 includes a ninth transistor M9, a gate of the ninth transistor M9 is electrically connected to the pull-down node C, a source of the ninth transistor M9 is electrically connected to the dual-gate diode M2, and a drain of the ninth transistor M9 is electrically connected to the light-emitting signal output end Eout.

The ninth transistor M9 applies the first reference voltage to the emission signal output end Eout during the data writing period Td when the pull-down node C is at the first potential, and ensures that the voltage of the emission signal output end Eout during the data writing period Td is the first reference voltage, so as to ensure the pixel unit P to which the data signal is accurately written.

The reset circuit 18 includes a tenth transistor M10 and an eleventh transistor M11.

The gate of the tenth transistor M10 is electrically connected to the Reset terminal Re for receiving a Reset signal Reset, the source of the tenth transistor M10 is electrically connected to the first reference voltage terminal VDD, and the drain of the tenth transistor M10 is electrically connected to the pull-up node B. In this embodiment, the Reset terminal Re may be a signal terminal of the Reset circuit for outputting the Reset signal Reset.

The gate of the eleventh transistor M11 is electrically connected to the Reset terminal Re for receiving a Reset signal Reset, the source of the eleventh transistor M11 is electrically connected to the second reference voltage terminal VSS, and the drain of the eleventh transistor M11 is electrically connected to the pull-down node C.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all N-type Thin Film Transistors (TFTs), and thus the first potential is a high potential, the second potential is a low potential, the first reference voltage is a high voltage, and the second reference voltage is a low potential.

It should be noted that, since the first reference voltage VDD is a high voltage and the second reference voltage VSS is a low voltage, the scan signal Sc is used as a scan start voltage of the pixel unit P when having the second reference voltage, so that the pixel transistor of the pixel unit P receiving the scan signal Sc should be an N-type TFT which is turned on at a high voltage, and the emission signal EM is used as an emission start voltage of the pixel unit P when having the second reference voltage, so that the pixel transistor of the pixel unit P receiving the emission signal Sc should be an N-type TFT which is turned on at a high voltage.

Please refer to fig. 12, which is a timing diagram illustrating the operation of the scan and light-emitting driving circuit 100 shown in fig. 11. Wherein, the reference symbols in fig. 12 are specifically: sc (n-1) is a voltage waveform of the scanning signal output from the scanning signal output terminal Scan of the n-1 th scanning and light-emitting drive circuit 100. CLK1 represents a voltage waveform diagram of the first clock signal, CLK2 represents a voltage waveform diagram of the second clock signal, CLK3 represents a voltage waveform diagram of the third clock signal, Reset represents a voltage waveform diagram of the Reset signal output from the Reset terminal Re, VB represents a voltage waveform diagram of the pull-up node B, VC represents a voltage waveform diagram of the pull-down node C, EM (n) represents a voltage waveform diagram of the emission signal EM output from the self-light scanning output terminal Eout of the scanning and emission driving circuit 100 of the nth stage, and sc (n) represents a voltage waveform diagram of the scanning signal Scan output from the scanning signal output terminal Scan of the scanning and emission driving circuit 100d of the nth stage.

Now, the operation of the light-emitting scanning driving circuit in the 1st Frame period of one Frame image scanning will be described in detail with reference to fig. 11 to 12.

In the Reset period Tr shown in fig. 12, the Reset signal Reset output from the Reset terminal Re is at a high potential, and thus the tenth transistor M10 and the eleventh transistor M11 are turned on.

The first reference voltage provided from the first reference voltage terminal VDD is applied to the pull-up node B through the tenth transistor M10, so that the pull-up node B is at the first potential. The second reference voltage provided from the second reference voltage terminal VSS is applied to the pull-down node C through the eleventh transistor M11, so that the pull-down node C is at the second potential. Thereby completing the reset operation of the pull-up node B and the pull-down node C.

The adjustment period Td1 in the data writing period Td,

the first clock terminal CK1 outputs the first clock signal CLK1, and the Scan signal output terminal Scan of the (n-1) th Scan and light emitting driving circuit 103u outputs the Scan signal Sc, so that the first transistor M1 and the third transistor M3 of the first control circuit 11 are both turned on.

The second reference voltage provided by the second reference voltage terminal VSS is applied to the pull-up node B through the turned-on first transistor M3, so that the voltage of the pull-up node B is at the second potential. The second reference voltage in the scan signal is applied to the pull-down node C through the turned-on first transistor M1, so that the voltage of the pull-down node C is at the first potential.

Since the pull-up node B is at the second potential, the third transistor M4 and the seventh transistor M7 are turned off, the pull-down node C is at the first potential, the fifth transistor M5 is turned on, and the second reference voltage provided by the second reference voltage terminal VSS is applied to the light emitting signal output Eout; the eighth transistor M8 is turned on, but since the second clock signal terminal CK2 does not output the second clock signal at this time, the second clock signal terminal CK2 applies the first reference voltage to the scan signal output terminal Sc.

The period Td2 is written in the data writing period Td,

the voltage of the pull-up node B is further reduced on the basis of the second potential due to the energy storage effect of the first capacitor C1; the voltage of the pull-down node C is further increased based on the first potential under the energy storage effect of the second capacitor C2.

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 is turned on, and the second clock signal terminal CK2 loads the second clock signal CLK2 with the second potential to the Scan signal output terminal Scan, so that the first Scan signal output terminal Scan outputs the Scan signal Sc with the first reference voltage.

In this embodiment, all the pixel units on the scan driving line loaded with the scan signal Sc of the first reference voltage are turned on, so that the image data is loaded and written into the pixel unit P.

In the light emitting period Tr, the third clock terminal outputs the third clock signal CLK3, the dual gate transistor M2 is turned on, the first reference voltage terminal VDD applies the first reference voltage VDD to the pull-up node B such that the voltage of the pull-up node B jumps to the first potential, and when the voltage of the pull-up node B is the first potential, the sixth transistor M6 is turned on such that the voltage of the pull-down node C is the second potential.

When the voltage at the pull-up node B is at the first level and the voltage at the pull-down node C is at the second level, the fourth transistor M4 and the seventh transistor M7 are turned on, and the fifth transistor M5 and the eighth transistor are turned off.

The first reference voltage provided from the first reference voltage terminal VDD is transmitted to the light emitting signal output terminal Eout through the fourth transistor M4, and the second reference voltage provided from the second reference voltage terminal VSS is transmitted to the Scan signal output terminal Scan through the seventh transistor M7.

The Scan signal output terminal Scan stops outputting the Scan signal Sc, so that the pixel unit P correspondingly connected to the Scan driving line does not receive the image data, the light-emitting signal output terminal Eout outputs the light-emitting signal EM with the first reference voltage, and the pixel unit P is controlled to start emitting light for performing image display with respect to the received image data, that is, the light-emitting signal has the first reference voltage for controlling the light-emitting time of the pixel unit P to correspond to each other, so that the light-emitting signal can be adjusted with respect to the light-emitting time of the pixel unit P by controlling the duration and frequency of the first reference voltage, and the pixel unit P can be prevented from being affected by other image data in the light-emitting time period Tr, thereby ensuring that the pixel unit P can correctly perform image display.

In this embodiment, the scanning and light-emitting driving circuit 100 can output the light-emitting output signal and the scanning signal in the scanning display period of the frame image display period, so that the integration level of the scanning and light-emitting driving circuit 100 is effectively improved, the number of transistors is reduced, the cost is reduced, the volume of the scanning and light-emitting driving circuit 100 can be reduced, and a higher possibility is provided for the narrow frame requirement of the display panel.

Referring to fig. 13, which is a specific circuit structure diagram of any one of the scanning and light-emitting driving circuits 200 shown in fig. 4 in the second embodiment of the present application, in the present embodiment, the scanning and light-emitting driving circuit 200 is substantially the same as the scanning and light-emitting driving circuit 100 shown in fig. 11, except that the scanning and light-emitting driving circuit 200 further includes a pulse width control circuit 17.

The pulse width control circuit 17 is electrically connected to the pull-up output circuit 13, the pull-down output circuit 14 and the light-emitting signal output end Eout, and is configured to control the frequency of the first reference voltage output by the pull-up output circuit 13 and the frequency of the second reference voltage output by the pull-down output circuit 14.

The pulse width control circuit 17 includes a first pulse width control circuit 171 and a second pulse width control circuit 172.

The first pulse width control circuit 171 and the emission pull-up output circuit 131 are connected in series to the second reference voltage terminal VSS and the emission signal output terminal Eout, and the first pulse width control circuit 171 is in a conducting state according to the first frequency under the control of the first pulse width signal P1.

When the pull-up output circuit 13 is in a conducting state under the control of the pull-up node B, the first pulse width control circuit 171 outputs the first reference voltage to the emission signal output end Eout at a first frequency.

The second pulse width control circuit 172 and the emission pull-down output circuit 132 are connected in parallel to the second reference voltage terminal VDD and the emission signal output terminal Eout, and the second pulse width control circuit 172 is in a conducting state according to the second frequency under the control of the second pulse width signal P2.

When the pull-down output circuit 14 is in a non-conducting state under the control of the pull-down node B, the second pulse width control circuit 172 outputs the second reference voltage to the light-emitting signal output end Eout according to the first frequency.

The sum of the duty ratio of the first pulse width signal P1 and the second pulse width signal P2 and the second duty ratio is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite.

The first pulse width control circuit 171 includes a thirteenth transistor M13, a gate of the thirteenth transistor M13 is electrically connected to the first pulse signal output terminal P1 for receiving the first pulse control signal P1 from the first pulse signal output terminal P1, a source of the thirteenth transistor M13 is electrically connected to the first reference voltage terminal VDD, and a drain of the thirteenth transistor M13 is electrically connected to the drain of the fourth transistor M4.

The second pulse width control circuit 172 includes a fourteenth transistor M14, a gate of the fourteenth transistor M15 is electrically connected to the second pulse signal output terminal P2 for receiving the second pulse control signal P2 from the second pulse signal output terminal P2, a source of the fourteenth transistor M14 is electrically connected to the second reference voltage terminal VSS, and a drain of the fourteenth transistor M14 is electrically connected to the light emitting scan output terminal Eout.

Please refer to fig. 14, which is a timing diagram illustrating the operation of the scan and light-emitting driving circuit 200 shown in fig. 13. In fig. 14, Sc (n-1) represents a voltage waveform diagram of a Scan signal output from the Scan signal output terminal Scan of the n-1 th Scan and light emitting driver circuit 200, CLK1 represents a voltage waveform diagram of a first clock signal, CLK2 represents a voltage waveform diagram of a second clock signal, CLK3 represents a voltage waveform diagram of a third clock signal, Reset represents a voltage waveform diagram of a Reset signal output from the Reset terminal Re, VB represents a voltage waveform diagram of the pull-up node B, VC represents a voltage waveform diagram of the pull-down node C, P1 represents a voltage waveform diagram of a first pulse width control signal, P2 represents a voltage waveform diagram of a second pulse width control signal, em (n) represents a voltage waveform diagram of a light emitting signal output from the Scan output terminal Eout, and Sc (n) represents a voltage waveform diagram of a Scan signal output from the Scan signal output terminal Scan of the n-1 th Scan and light emitting driver circuit 200.

Now, the operation of the light-emitting scanning driving circuit 200 in the 1Frame image scanning period of one Frame will be described in detail with reference to fig. 13 to 14.

In the Reset period Tr shown in fig. 14, the Reset signal Reset output from the Reset terminal Re is at a high potential, and thus the tenth transistor M10 and the eleventh transistor M11 are turned on.

In the adjustment period Td1 in the data writing period Td,

the first clock terminal CK1 outputs the first clock signal CLK1, and the Scan signal output terminal Scan of the n-1 th Scan and light emitting driving circuit outputs the Scan signal, so that the first transistor M1 and the third transistor M3 of the first control circuit 11 are both turned on.

Since the pull-up node B is at the second potential, the third transistor M4 and the seventh transistor M7 are turned off, the pull-down node C is at the first potential, the fifth transistor M5 is turned on, and the second reference voltage provided by the second reference voltage terminal VSS is applied to the light emitting signal output Eout; the eighth transistor M8 is turned on, but since the second clock signal terminal CK2 does not output the second clock signal at this time, the second clock signal terminal CK2 applies the first reference voltage to the Scan signal output terminal Scan.

The period Td2 is written in the data writing period Td,

the voltage of the pull-up node B is further reduced on the basis of the second potential due to the energy storage function of the first capacitor C1; the voltage of the pull-down node C is further increased based on the first potential under the energy storage effect of the second capacitor C2.

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 is turned on, and the second clock signal terminal CK2 loads the second clock signal CLK2 with the second reference voltage to the Scan signal output terminal Scan, so that the Scan signal output terminal Scan outputs the Scan signal Sc with the first reference voltage.

In the data writing period Td, since the voltage of the pull-down node B is maintained at the first potential, that is, the fifth transistor M5 is always in the on state, the light emitting signal output end Eout is also always maintained at the second reference voltage, and thus, the voltage of the light emitting signal output end Eout is not affected by the pulse width control circuit 17.

The thirteenth transistor M13 outputs the first reference voltage to the light-emitting scan output end Eout at the first frequency under the control of the first pulse signal P1, and the fourteenth transistor M14 outputs the second reference voltage to the light-emitting scan output end Eout at the second frequency under the control of the second pulse signal P2.

It can be seen that, in the light emitting period, the duty ratio of the light emitting signal EM can be flexibly adjusted at any time along with the first pulse signal P1 and the second pulse signal P2, so that during the light emitting display period of the pixel unit P, the duty ratio of the light emitting signal EM can be accurately adjusted by adjusting the duty ratios of the first pulse signal P1 and the second pulse signal P2, thereby effectively preventing the stroboscopic phenomenon caused by the display frequency of the pixel unit P not being matched with the current image refresh frequency.

Referring to fig. 15, which is a specific circuit structure diagram of any one of the scanning and light-emitting driving circuits 300 shown in fig. 4 in the third embodiment of the present application, in the present embodiment, the scanning and light-emitting driving circuit 300 has substantially the same circuit structure as the scanning and light-emitting driving circuit 100 shown in fig. 11, except that all transistors (the first transistor M1 through the eleventh transistor M11) in the scanning and light-emitting driving circuit 300 in the present embodiment are P-type thin film transistors.

In the reset circuit 18, the tenth transistor M10 and the eleventh transistor M11 are provided.

The gate of the tenth transistor M10 is electrically connected to the Reset terminal Re for receiving a Reset signal Reset, the source of the tenth transistor M10 is electrically connected to the second reference voltage terminal VSS, and the drain of the tenth transistor M10 is electrically connected to the pull-up node B.

The gate of the eleventh transistor M11 is electrically connected to the Reset terminal Re for receiving a Reset signal Reset, the source of the eleventh transistor M11 is electrically connected to the first reference voltage terminal VDD, and the drain of the eleventh transistor M11 is electrically connected to the pull-down node C.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all P-type Thin Film Transistors (TFTs), and thus the first potential is a low potential, the second potential is a high potential, the first reference voltage is a low voltage, and the second reference voltage is a high potential.

It should be noted that, since the first reference voltage is a low voltage and the second reference voltage is a high potential, the scan signal Sc is used as a scan start voltage of the pixel unit P when the scan signal Sc has the first reference voltage, a pixel transistor of the pixel unit P receiving the scan signal Sc should be a P-type TFT with a low potential conducting, and the emission signal EM is used as an emission start voltage of the pixel unit P when the emission signal EM has the first reference voltage, and a pixel transistor of the pixel unit P receiving the emission signal Sc should be a P-type TFT with a low potential conducting.

Please refer to fig. 16, which is a timing diagram illustrating the operation of the scan and light-emitting driving circuit 300 shown in fig. 15. Wherein, the reference symbols in fig. 16 are specifically: sc (n-1) is a voltage waveform of the scanning signal output from the scanning signal output terminal Scan of the n-1 th scanning and light-emitting drive circuit 100. CLK1 represents a voltage waveform diagram of the first clock signal, CLK2 represents a voltage waveform diagram of the second clock signal, CLK3 represents a voltage waveform diagram of the third clock signal, Reset represents a voltage waveform diagram of the Reset signal output from the Reset terminal Re, VB represents a voltage waveform diagram of the pull-up node B, VC represents a voltage waveform diagram of the pull-down node C, EM (n) represents a voltage waveform diagram of the emission signal EM output from the self-light scanning output terminal Eout of the scanning and emission driving circuit 100 of the nth stage, and sc (n) represents a voltage waveform diagram of the scanning signal Scan output from the scanning signal output terminal Scan of the scanning and emission driving circuit 100d of the nth stage.

The operation timing of the scanning and light-emitting driving circuit 300 is the same as the operation timing of the scanning and light-emitting driving circuit 100 shown in fig. 12, and the description thereof is not repeated in this embodiment.

Referring to fig. 17, which is a specific circuit structure diagram of any one of the scanning and light-emitting driving circuits 400 shown in fig. 4 in the fourth embodiment of the present application, in the present embodiment, the scanning and light-emitting driving circuit 400 has substantially the same circuit structure as the scanning and light-emitting driving circuit 200 shown in fig. 13, except that all transistors (the first transistor M1 to the eleventh transistor M11) in the scanning and light-emitting driving circuit 400 are P-type thin film transistors.

Please refer to fig. 18, which is a timing diagram illustrating the operation of the scan and light emitting driving circuit 400 shown in fig. 17. The operation timing of the scanning and light-emitting driving circuit 400 is the same as the operation timing of the scanning and light-emitting driving circuit 200 shown in fig. 14, and the description thereof is not repeated.

As shown in fig. 19, which is a circuit block diagram of the light emitting driving circuit in the scanning and light emitting driving circuit 500 shown in fig. 4 in the fifth embodiment of the present application, in this embodiment, the light emitting driving circuit includes a first control circuit 11, a second control circuit 12, a light emitting output circuit 13, a first inverter circuit 15, a buffer circuit 16, and a pulse width control circuit 17. The light emitting output circuit 13 includes a light emitting pull-up output circuit 13 and a light emitting pull-down output circuit 14, and the pulse width control circuit 171 includes a first pulse width control circuit 171 and a second pulse width control circuit 172.

The first control circuit 11 is electrically connected to the second control circuit 12 through a first node a, and is electrically connected to the pull-up output circuit 13 through a pull-up node B, the second control circuit 12 is electrically connected to the pull-down output circuit 14 through a pull-down node C, and the first inverter circuit 15 is electrically connected between the pull-up node B and the pull-down node C.

The first control circuit 11 is electrically connected to the first clock terminal CK1, the first adjustment signal terminal Vin, the second reference voltage terminal VSS and the first node a.

The first clock signal terminal CK1 is for outputting a first clock signal CLK1 at a first predetermined frequency.

The first adjustment signal terminal Vin is used for outputting a first adjustment signal Vi.

The second reference voltage terminal VSS is used for outputting a second reference voltage VSS.

The first control circuit 11 receives the first clock signal CLK1 from the first clock signal terminal CK1, thereby transmitting the first potential (high) and the second potential (low) to the pull-up node B at different time periods according to the first clock signal CLK1 during the data writing period Td within one scanning period T. In the present embodiment, the data writing period Td within one scanning period T receives the first clock signal CLK1 at two different periods, thereby transmitting the first potential (high) and the second potential (low) to the pull-up node B at different periods.

In the present embodiment, the data writing period Td includes an adjustment period Td1, a pull-up period Td2, and a pull-down period Td3 that are continuous in time and have no overlap.

The first clock signal terminal CK1 outputs the first clock signal during the adjustment period Td1 and the pull-down period Td3, respectively, so that the first control circuit 11 transmits the first potential (high) and the second potential (low) to the pull-up node B during the adjustment period Td1 and the pull-down period Td3, respectively, according to the first clock signal CLK 1.

When the pull-up node B is at the second potential, the pull-down node C is controlled to be at the second potential by the first inverter circuit 15 connected between the pull-up node and the pull-down node.

The second control circuit 12 is electrically connected to the second clock terminal CK2 and the first reference voltage terminal VDD.

The second clock terminal CK2 is for outputting the clock signal CLK2, and the first reference voltage terminal VDD is for outputting the first reference voltage.

In this embodiment, the first reference voltage is higher than the second reference voltage, for example, the first reference voltage is a high reference voltage, and the second reference voltage is a low reference voltage.

The second control circuit 12 receives the second clock signal CLK2 for a pull-up period Td2 within the data write period Td, and transmits the first potential (high) to the pull-up node B under the control of the second clock signal CLK2, and outputs the second potential to the pull-down node C when the pull-up node B is at the first potential.

The light-emitting pull-up output circuit 131 is electrically connected to the pull-up node B and the light-emitting signal output end Eout, and when the pull-up node B is at the second potential, the light-emitting pull-up output circuit 131 is in a conducting state so as to output the second reference voltage.

The light-emitting pull-down output circuit 141 is electrically connected to the pull-down node C and the light-emitting signal output end Eout, and outputs a first reference voltage when the pull-down node C is at a first potential. In this embodiment, the first reference voltage and the second reference voltage cooperate with each other to form the light emitting signal.

The buffer circuit 16 is electrically connected between the first control circuit 11 and the first node a, and is configured to control the first node a to buffer the first clock signal CLK1 for a certain period of time.

The pulse width control circuit 17 is electrically connected to the light-emitting pull-up output circuit 13, the light-emitting pull-down output circuit 14 and the light-emitting signal output end Eout, and is configured to control the frequency of the first reference voltage output by the pull-up output circuit 13 and the frequency of the second reference voltage output by the pull-down output circuit 14.

The first pulse width control circuit 171 and the pull-up output circuit 13 are connected in series to the second reference voltage terminal VSS and the light-emitting signal output terminal Eout, and the first pulse width control circuit 171 is in a conducting state according to the first frequency under the control of the first pulse width signal P1.

The second pulse width control circuit 172 and the pull-down output circuit 14 are connected in parallel to the second reference voltage terminal VDD and the light emitting signal output terminal Eout, and the second pulse width control circuit 172 is in a conducting state according to the second frequency under the control of the second pulse width signal P2.

More specifically, please refer to fig. 20, which is a schematic diagram of a specific circuit structure of the light emitting driving circuit shown in fig. 19. As shown in figure 20 of the drawings,

the first control circuit 11 includes a first transistor M1, a second transistor M2, and a third transistor M3.

The gate of the first transistor M1 is electrically connected to the first clock signal terminal CK1 for receiving the first clock signal CK1, the source of the first transistor M1 is electrically connected to the first adjustment signal terminal Vin, and the drain of the first transistor M1 is electrically connected to the buffer circuit 16.

The gate of the second transistor M2 is electrically connected to the first clock signal terminal CK1, the source of the second transistor M2 is electrically connected to the second reference voltage VSS, and the drain of the second transistor M2 is electrically connected to the first node a.

The gate of the third transistor M3 is electrically connected to the first clock signal terminal CK1, the source of the third transistor M3 is electrically connected to the second reference voltage VSS, and the drain of the third transistor M3 is electrically connected to the pull-up node B.

The pull-up output circuit 13 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the pull-up node B, a source of the fourth transistor M4 is electrically connected to the first pulse width control circuit 171, and a drain of the fourth transistor M4 is electrically connected to the light-emitting signal output end Eout.

The buffer circuit 16 includes a fourth transistor M5, a sixth transistor M6, and a fourth capacitor C4.

The gate of the fifth transistor M5 is electrically connected to the drain of the first transistor M1, the source of the fifth transistor M5 is electrically connected to the first clock signal terminal CK1, and the drain of the fifth transistor M5 is electrically connected to the sixth transistor M6.

The gate of the sixth transistor M6 is electrically connected to the drain of the first transistor M1, the source of the sixth transistor M6 is electrically connected to the drain of the fifth transistor M5, and the drain of the sixth transistor M6 is electrically connected to the first node a.

The fourth capacitor C4 is electrically connected between the gate of the fifth transistor M5 and the first reference voltage terminal VDD.

The second control circuit 12 includes a sub pull-up control circuit 121 and a sub pull-down control circuit 122. The sub-pull-up control circuit 121 is configured to control the voltage of the pull-up node B to be at a first potential, and the sub-pull-down control circuit 122 is configured to control the voltage of the pull-down node C to be at a second potential.

Specifically, the sub pull-up control circuit 121 is electrically connected to the first node a, the second clock signal terminal CK2, the first reference voltage terminal VDD, and the pull-up node B.

When the first control circuit 12 does not receive the first clock signal CLK1 and outputs the signal of the first potential or the second potential to the pull-up node B, the sub-pull-up control circuit 121 outputs the second reference voltage terminal VDD to the pull-up node B under the control of the first node a and the second clock signal terminal CK2, thereby controlling the voltage of the pull-up node B to be the first potential.

The sub pull-down control circuit 122 is electrically connected to the first node a, the second clock signal terminal CK2, the first reference voltage terminal VDD, and the pull-down node C.

When the pull-up node B cannot control the voltage of the pull-down node C due to being at the first potential, the sub-pull-down control circuit 122 outputs the second potential to the pull-down node C under the control of the first node a and the second clock signal terminal CK2, thereby controlling the voltage of the pull-down node B to be the second potential.

More specifically, the sub pull-up control circuit 121 includes a seventh transistor M7, an eighth transistor M8, and a first capacitor C1, and the sub pull-down control circuit 122 includes a ninth transistor M9, a tenth transistor M10, and a second capacitor C2.

The gate of the seventh transistor M7 is electrically connected to the first node a, the source of the seventh transistor M7 is electrically connected to the first reference voltage terminal VDD, and the drain of the seventh transistor M7 is electrically connected to the eighth transistor M8.

The gate of the eighth transistor M8 is electrically connected to the second clock terminal CK2 for receiving the second clock signal CLK2, the source of the eighth transistor M8 is electrically connected to the drain of the seventh transistor M7, and the drain of the eighth transistor M8 is electrically connected to the pull-up node B.

The first capacitor C1 is electrically connected between the CK2 of the second clock signal and the second node.

The second capacitor C2 is electrically connected between the first node a and the second node D.

The gate of the ninth transistor M9 is electrically connected to the first node a, the source of the ninth transistor M9 is electrically connected to the CK2 of the second clock signal, and the drain of the seventh transistor M7 is electrically connected to the second node D.

The gate of the tenth transistor M10 is electrically connected to the CK2 of the second clock signal for receiving the second clock signal CLK2, the source of the tenth transistor M10 is electrically connected to the second node D, and the drain of the tenth transistor M10 is electrically connected to the pull-down node C.

The first inverter circuit 15 includes an eleventh transistor M11, a gate of the eleventh transistor M11 is electrically connected to the pull-up node B, a source of the eleventh transistor M11 is electrically connected to the first reference voltage terminal VDD, and a drain of the eleventh transistor M11 is electrically connected to the pull-down node C.

The pull-down output circuit 132 includes a twelfth transistor M12 and a third capacitor C3. Wherein the content of the first and second substances,

the third capacitor C3 is electrically connected between the pull-down node C and the first reference voltage terminal VDD.

The gate of the twelfth transistor M12 is electrically connected to the pull-down node C, the source of the twelfth transistor M12 is electrically connected to the first reference voltage terminal VDD, and the drain of the twelfth transistor M12 is electrically connected to the light emitting signal output terminal Eout.

The first pulse width control circuit 171 includes a thirteenth transistor M13, a gate of the thirteenth transistor M13 is electrically connected to the first pulse signal output terminal P1 for receiving the first pulse control signal P1 from the first pulse signal output terminal P1, a source of the thirteenth transistor M13 is electrically connected to the second reference voltage terminal VSS, and a drain of the thirteenth transistor M13 is electrically connected to the drain of the fourth transistor M4.

The second pulse width control circuit 172 includes a fourteenth transistor M14, a gate of the fourteenth transistor M15 is electrically connected to the second pulse signal output terminal P2 for receiving the second pulse control signal P2 from the second pulse signal output terminal P2, a source of the fourteenth transistor M14 is electrically connected to the first reference voltage terminal VDD, and a drain of the fourteenth transistor M14 is electrically connected to the light emitting signal output terminal Eout.

In this embodiment, the first to fourteenth transistors M1 to M14 are all P-type Thin Film Transistors (TFTs), and thus the first potential is a high potential, the second potential is a low potential, the first reference voltage is a high voltage, and the second reference voltage is a low potential. Among them, the first to fourteenth transistors M1 to M14 are turned off under high voltage control and turned on under low voltage control.

Please refer to fig. 21, which is a timing diagram illustrating the operation of the light emitting driving circuit shown in fig. 20. Wherein, the notation in fig. 21 specifically includes: vi represents a voltage waveform diagram of the first adjustment signal Vi, CLK1 represents a voltage waveform diagram of the first clock signal, CLK2 represents a voltage waveform diagram of the second clock signal, VA represents a voltage waveform diagram of the first node a, VB represents a voltage waveform diagram of the pull-up node B, VC represents a voltage waveform diagram of the pull-down node C, P1 represents a voltage waveform diagram of the first pulse width control signal, P2 represents a voltage waveform diagram of the second pulse width control signal, and EM (n) represents a voltage waveform diagram of the emission signal EM output from the emission scan output Eout of the scan and emission drive circuit 500.

Now, the operation of the light-emitting scanning driving circuit in the one-Frame image scanning period 1Frame will be described in detail with reference to fig. 20 to 21.

As shown in fig. 21, the first clock terminal CK1 does not output the first clock signal CLK1 during the reset period Tr, and thus the first to third transistors M1 to M3 in the first control circuit 11 are all in the off state, and thus the first node a and the pull-up node B are both low.

Since the pull-up nodes B are all low, the fourth transistor M4 is in a turned-on state, and the thirteenth transistor M13 outputs the second reference voltage to the emission scan output Eout according to the first frequency under the control of the first pulse signal P1.

The second clock terminal CK2 outputs the second clock signal CLK2 and then stops outputting the second clock signal CLK2, the first capacitor C1 discharges the residual charge through the second clock terminal CK2, the voltage of the pull-up node B is further ensured to be at a low potential, after the output of the second clock signal CLK2 is stopped, the eighth transistor M8 and the tenth transistor M10 are turned off, and the voltage of the pull-down node C is clamped at a high potential by the first reference voltage terminal VDD through the third capacitor C3. Thereby completing the reset operation of the pull-up node B and the pull-down node C.

Since the pull-down node C is low, the twelfth transistor M12 is turned off and changed, and the fourteenth transistor M14 outputs the first reference voltage to the emission scan output end Eout according to the second frequency under the control of the second pulse signal P2.

In the adjustment period Td1 in the data writing period Td,

the first clock terminal CK1 outputs the first clock signal CLK1, and the first adjustment signal terminal Vin outputs the first adjustment signal, so that the first to third transistors M1 to M3 in the first control circuit 11 are all turned on, the first node a is at a low potential by being applied with the first reference voltage through the third transistor M3, and the pull-up node B is at a high potential by being applied with the first adjustment signal.

Since the pull-up node B is at a high level, the fourth transistor M4 and the eleventh transistor M11 are turned off, and the pull-up node B cannot control the voltage of the pull-down node B to be at a low level through the eleventh transistor M11 of the first inverter circuit 15.

The second clock terminal CK2 does not output the second clock signal CLK2, the eighth transistor M8 and the tenth transistor M10 are turned off, and the voltage of the pull-down node C is still maintained at the high level.

Since the pull-down nodes C are all low, the twelfth transistor M12 is in the off-state, and the fourteenth transistor M14 outputs the first reference voltage to the emission scan output end Eout according to the second frequency under the control of the second pulse signal P2.

In the pull-up period Td2 in the data writing period Td, the first clock terminal CK1 stops outputting the first clock signal CLK1 while the first adjustment signal terminal Vin stops outputting the first adjustment signal, and thus the first to third transistors M1 to M3 in the first control circuit 11 are all in the off state.

The voltage at the first node A is maintained at a low level by the second capacitor C2, and thus the ninth transistor M9 and the seventh transistor M7 are both turned on.

The second clock terminal CK2 outputs the second clock signal CLK2, the eighth transistor M8 and the tenth transistor M10 are turned on,

therefore, the sub-pull-up control circuit 121 formed by the seventh transistor M7 and the eighth transistor M8 provides the first reference voltage from the first reference voltage terminal VDD to the pull-up node B, and controls the voltage of the pull-up node B to be maintained at a high level.

The sub pull-down control circuit 122, which is composed of the ninth transistor M9 and the tenth transistor M10, transmits a low potential of the second clock signal CLK2 to the pull-down node C, so that the voltage of the pull-down node C jumps from a high potential to a low potential.

When the voltage at the pull-down node C is at a low level, the twelfth transistor M12 is in a conducting state, so that the first reference voltage terminal VDD provides the first reference voltage to the optical scan output terminal Eout, and the optical scan output terminal Eout is maintained at a high level and does not change with the second pulse signal P2.

In the pull-down period Td3 in the data writing period Td, the first clock terminal CK1 outputs the first clock signal CLK1, and thus, the first to third transistors M1 to M3 in the first control circuit 11 are all in the off state. The first node a is at a low potential by being loaded with the first reference voltage through the third transistor M3, and the pull-up node B is at a high potential by being inputted with the first adjustment signal.

When the voltage of the pull-up node B is at a low level, the voltage of the pull-down node C is controlled to jump to a high level by the turned-on eleventh transistor M11 of the first inverter circuit 15, the twelfth transistor M12 is turned off, and the fourteenth transistor M14 outputs the first reference voltage to the light emitting scan output end Eout under the control of the second pulse signal P2.

It can be seen that, in the data writing period Td, the voltage of the emission scan output end Eout is maintained at a high potential without turning on the path of the driving current in the pixel unit P so that the light emitting device emits light, thereby ensuring correct writing of data.

In the emission period Tr, the pull-up node B is maintained at the low level all the time under the control of the first and second clock signals CLK1 and CLK 2.

The thirteenth transistor M13 outputs the second reference voltage to the light-emitting scan output end Eout at the first frequency under the control of the first pulse signal P1, and the fourteenth transistor M14 outputs the first reference voltage to the light-emitting scan output end Eout at the second frequency under the control of the second pulse signal P2.

It can be seen that, in the light emitting period, the duty ratio of the light emitting signal EM can be flexibly adjusted at any time along with the first pulse signal P1 and the second pulse signal P2, so that, during the light emitting display period of the pixel unit P, the duty ratio of the light emitting signal EM can be accurately adjusted by adjusting the duty ratios of the first pulse signal P1 and the second pulse signal P2, that is, the low-potential time in the light emitting signal EM can be accurately adjusted by adjusting the time of the low-potential in the two pulse signals within one pulse period, so as to effectively adjust the time of the driving current provided to the light emitting device in the pixel unit P, thereby effectively preventing the stroboscopic phenomenon caused by the display frequency of the pixel unit P failing to match with the current image refresh frequency.

Referring to fig. 22, it is a specific circuit structure diagram of a light emitting driving circuit in any one of the scanning and light emitting driving circuits 600 shown in fig. 4 in the sixth embodiment of the present application, in this embodiment, the scanning and light emitting driving circuit 600 is basically the same as the scanning and light emitting driving circuit 500 shown in fig. 20, except that all transistors (the first transistor M1 to the fourteenth transistor M14) in the light emitting circuit are N-type thin film transistors.

In this embodiment, the first transistor M1 to the eleventh transistor M11 are all N-type Thin Film Transistors (TFTs), and thus the first potential is a high potential, the second potential is a low potential, the first reference voltage is a high voltage, and the second reference voltage is a low potential. Among them, the first to fourteenth transistors M1 to M14 are turned off under low voltage control and turned on under high voltage control. It should be noted that, since the first reference voltage is a high voltage and the second reference voltage is a low voltage, the scan signal Sc is used as a scan start voltage of the pixel unit P when the scan signal Sc has the first reference voltage, the pixel transistor of the pixel unit P receiving the scan signal Sc should be an N-type TFT which is turned on at a high voltage, and the emission signal EM is used as an emission start voltage of the pixel unit P when the emission signal EM has the first reference voltage, and the pixel transistor of the pixel unit P receiving the emission signal Sc should be an N-type TFT which is turned on at a high voltage.

Please refer to fig. 23, which is a timing diagram illustrating operation of the light emitting driving circuit shown in fig. 22. The working timing of the light-emitting driving circuit is completely the same as the working timing of the light-emitting driving circuit shown in fig. 21, and the description thereof is not repeated in this embodiment.

The foregoing is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.

Claims

1. A scanning and light-emitting driving circuit is characterized in that the circuit comprises a first control circuit, a second control circuit, a scanning driving output circuit and a light-emitting driving output circuit,

the first control circuit is electrically connected with the scanning driving output circuit and the light-emitting driving output circuit and is used for controlling the scanning driving output circuit to output scanning signals in a data writing time period in a scanning period, and the scanning signals are used for controlling the pixel units to receive image data;

the second control circuit is electrically connected to the light-emitting driving output circuit and is configured to control the light-emitting driving output circuit to output a light-emitting signal in a light-emitting time period in the scanning period, where the light-emitting signal is used to control the time for the pixel unit to display the image data;

the first control circuit is electrically connected with the scanning drive output circuit through a pull-down node and is also electrically connected with the light-emitting drive output circuit through a pull-up node;

in the data writing time period, the first control circuit receives a first clock signal and adjusts the potential of the pull-down node and the potential of the pull-up node according to the first clock signal, the light-emitting driving output circuit receives a second clock signal under the control of the potential of the pull-up node and outputs a second reference voltage in the light-emitting signal according to the second clock signal, and the second reference voltage is used for controlling the pixel unit to stop displaying the image data;

the second control circuit is electrically connected with the light-emitting drive output circuit through a pull-up node, the second control circuit receives a third clock signal and adjusts the potential of the pull-up node according to the third clock signal in the light-emitting time period, the light-emitting drive output circuit outputs a first reference voltage in the light-emitting signal under the control of the potential of the pull-up node, and the first reference voltage is used for controlling the time of the pixel unit for displaying the image data.

2. The scanning and light-emitting drive circuit according to claim 1,

the scan driving output circuit receives a pre-start scan signal and a second clock signal under the control of the potential of the pull-down node, and outputs the scan signal according to the pre-start scan signal and the second clock signal.

3. The scan and emission driver circuit of claim 2, wherein the second control circuit is further electrically connected to the scan driver output circuit through the pull-down node;

in the light-emitting time period, the second control circuit receives the third clock signal and adjusts the potential of the pull-down node according to the third clock signal;

in the light emitting period, the scan driving output circuit stops outputting the scan signal under control of the potential of the pull-down node.

4. The scan and emission drive circuit of claim 3,

when the voltage of the pull-up node is a second potential, the first control circuit controls the voltage of the pull-down node to be a first potential;

when the voltage of the pull-up node is a first potential, the pull-down node is controlled to be a second potential through a first inverting circuit connected between the pull-up node and the pull-down node.

5. The scan and emission drive circuit according to claim 4, wherein the emission drive output circuit comprises:

a control end of the light-emitting pull-up output circuit is electrically connected to the pull-up node, an input end of the light-emitting pull-up output circuit is electrically connected to the first reference voltage end, the first reference voltage end is used for providing the first reference voltage, an output end of the light-emitting pull-up output circuit is used for outputting the light-emitting signal, and the output end of the light-emitting pull-up output circuit outputs the first reference voltage under the control of the potential of the pull-up node in the light-emitting time period;

the control end of the light-emitting pull-down output circuit is electrically connected with the pull-down node, the input end of the light-emitting pull-down output circuit is electrically connected with a second reference voltage end, the second reference voltage end is used for providing a second reference voltage, the output end of the light-emitting pull-down output circuit outputs the second reference voltage in the data writing time period under the control of the potential of the pull-down node, and the light-emitting signal comprises the first reference voltage and the second reference voltage.

6. The scan and emission driving circuit according to claim 5, wherein the scan driving output circuit comprises:

a scan pull-up output circuit, a control end of the scan pull-up output circuit being electrically connected to the pull-up node, an input end of the scan pull-up output circuit being electrically connected to the second reference voltage end, an output end of the scan pull-up output circuit outputting a fourth reference voltage under control of a potential of the pull-up node in the light emitting period, the fourth reference voltage being used for controlling the pixel unit to stop receiving the image data;

a scan pull-down output circuit, a control end of the scan pull-down output circuit being electrically connected to the pull-down node, an input end being electrically connected to a second clock end for receiving the second clock signal, and an output end being electrically connected to the scan signal output end, wherein in the data write time period, the output end of the scan pull-up output circuit outputs a third reference voltage under the control of a potential of the pull-down node, and the third reference voltage is used for controlling the pixel unit to receive the image data;

the scan signal includes the third reference voltage and the fourth reference voltage.

7. The circuit of claim 6, further comprising a pulse width control circuit electrically connected to the light emission driving output circuit, for controlling the frequency of the light emission pull-up output unit outputting the first reference voltage and the frequency of the light emission pull-down output unit outputting the second reference voltage in the light emission signal, wherein the first reference voltage and the second reference voltage have the same output frequency and the number of times of outputting the first reference voltage in the light emission time period is greater than 1.

8. The scan and emission driver circuit of claim 7, wherein the pulse width control circuit comprises a first pulse width control circuit and a second pulse width control circuit;

the control end of the first pulse width control circuit receives a first pulse width signal with a first duty ratio, the input end of the first pulse width control circuit is electrically connected with the first reference voltage end, and the output end of the first pulse width control circuit is electrically connected with the light-emitting pull-up output circuit; the first pulse width control circuit is controlled to be conducted by a first pulse width signal, and in the light-emitting time period, when the first pulse width control circuit is conducted, the first reference voltage is output from the output end of the light-emitting pull-up output circuit through the first pulse width control circuit;

a control end of the second pulse width control circuit receives a second pulse width signal with a second duty ratio, an input end of the second pulse width control circuit is electrically connected with the second reference voltage end, an output end of the second pulse width control circuit is electrically connected with the light-emitting pull-down output circuit, the second pulse width control circuit is conducted under the control of the second pulse width signal, and in the data writing time period, when the second pulse width control circuit is conducted, the second reference voltage is output from the output end of the light-emitting pull-down output circuit through the second pulse width control circuit;

the sum of the first duty ratio and the second duty ratio is 1, and the phases of the first pulse width signal and the second pulse width signal are opposite.

9. The scan and emission drive circuit of claim 8,

the first pulse width control circuit comprises a first pulse transistor, the grid electrode of the first pulse transistor receives the first pulse control signal, the source electrode of the first pulse transistor is electrically connected with the first reference voltage end, and the drain electrode of the first pulse transistor is electrically connected with the input end of the light-emitting pull-up output circuit;

the second pulse width control circuit comprises a second pulse transistor, the grid electrode of the second pulse transistor receives the second pulse control signal, the source electrode of the second pulse transistor is electrically connected with the second reference voltage end, and the drain electrode of the second pulse transistor is electrically connected with the output end of the light-emitting pull-down output circuit.

10. The scan and light-emitting driving circuit according to claim 9, further comprising a reset circuit electrically connected between the pull-up node and the pull-down node for controlling a potential of the pull-up node during a reset period to stop the light-emitting driving output circuit from outputting the scan signal and controlling a potential of the pull-down node to stop the scan driving output circuit from outputting the scan signal.

11. The scanning and light-emitting drive circuit according to claim 9,

the first control circuit comprises a first transistor, a third transistor and a first capacitor;

the grid electrode of the first transistor is used for receiving the first clock signal, and the drain electrode of the first transistor is electrically connected with the pull-down node;

a source of the third transistor is electrically connected to a second reference voltage terminal to receive the second reference voltage, and a drain of the third transistor is electrically connected to the pull-up node;

the first capacitor is electrically connected between the first clock signal end and the pull-up node.

12. The scanning and light-emitting drive circuit according to claim 11,

the second control circuit comprises a double-gate transistor, wherein two gates of the double-gate transistor are electrically connected with a third clock terminal to receive the third clock signal, a source of the double-gate transistor is electrically connected with the first reference voltage end, and a drain of the double-gate transistor is electrically connected with the pull-up node.

13. The scanning and light-emitting drive circuit according to claim 11,

the light-emitting pull-up output circuit comprises a fourth transistor, and the light-emitting pull-down output circuit comprises a fifth transistor and a second capacitor;

a gate of the fourth transistor is electrically connected to the control terminal of the light-emitting pull-up output circuit, a source of the fourth transistor is electrically connected to the input terminal of the light-emitting pull-up output circuit, and a drain of the fourth transistor is electrically connected to the output terminal of the light-emitting pull-up output circuit;

the grid electrode of the fifth transistor is electrically connected with the control end of the light-emitting pull-down output circuit, the source electrode of the fourth transistor is electrically connected with the input end of the light-emitting pull-down output circuit, and the drain electrode of the fifth transistor is electrically connected with the output end of the light-emitting pull-down output circuit;

the second capacitor is electrically connected between the pull-down node and the second reference voltage terminal.

14. The scanning and light-emitting drive circuit according to claim 11,

the first inverter circuit comprises a sixth transistor, wherein the gate of the sixth transistor is electrically connected to the pull-up node, the source of the sixth transistor is electrically connected to the second reference voltage terminal, and the drain of the sixth transistor is electrically connected to the pull-down node;

when the sixth transistor is turned on under the control of the pull-up node, the sixth transistor controls the voltage of the pull-down node to be a second potential which is the same as a second reference voltage.

15. The scanning and light-emitting drive circuit according to claim 11,

the scan pull-up output circuit includes a seventh transistor, the scan pull-down output circuit includes an eighth transistor,

a gate of the seventh transistor is a control end of the scanning pull-up output circuit, a source of the seventh transistor is an input end of the scanning pull-up output circuit, and a drain of the seventh transistor is an output end of the scanning pull-up output circuit;

the gate of the eighth transistor is the control end of the scanning pull-down output circuit, the source of the eighth transistor is the input end of the scanning pull-down output circuit, and the drain of the eighth transistor is the output end of the scanning pull-down output circuit.

16. The scan and emission drive circuit of claim 10,

the reset circuit comprises a tenth transistor and an eleventh transistor;

a gate of the tenth transistor is electrically connected to the reset terminal to receive a reset signal, a source of the tenth transistor is electrically connected to the first reference voltage terminal, and a drain of the tenth transistor is electrically connected to the pull-up node;

a gate of the eleventh transistor is electrically connected to the reset terminal to receive the reset signal, a source of the eleventh transistor is electrically connected to the second reference voltage terminal, and a drain of the eleventh transistor is electrically connected to the pull-down node.

17. A scanning and light-emitting driving system comprising the scanning and light-emitting driving circuit according to claim 16 cascaded in multiple stages, wherein a scanning signal output terminal of the n-1 th stage of scanning and light-emitting driving circuit is electrically connected to the first control circuit of the nth stage of scanning and light-emitting driving circuit, and a scanning signal output by the n-1 th stage of scanning and light-emitting driving circuit is used as the pre-start scanning signal, wherein n is an integer greater than 1; the first control circuit comprises a first transistor, a third transistor and a first capacitor;

the grid electrode of the first transistor is used for receiving the first clock signal, the source electrode of the first transistor is electrically connected with the scanning signal output end of the scanning and light-emitting driving circuit of the (n-1) th level, and the drain electrode of the first transistor is electrically connected with the pull-down node;

a gate of the third transistor is electrically connected to the scan signal output terminal of the n-1 th scan and light emitting driving circuit, a source of the third transistor is electrically connected to a second reference voltage terminal to receive the second reference voltage, and a drain of the third transistor is electrically connected to the pull-up node;

18. A display panel comprising the scanning and light-emission driving circuit according to any one of claims 1 to 17 in a non-display region of the display panel.

19. The scanning and light-emitting drive circuit is characterized by comprising a light-emitting drive circuit and a pulse width control circuit, wherein the light-emitting drive circuit is used for outputting light-emitting signals which are used for controlling the time of pixel units for displaying image data,

the pulse width control circuit is electrically connected to the light emitting driving circuit, and is configured to control the light emitting driving circuit to output the frequency of the light emitting signal, where the light emitting driving circuit includes:

the first control circuit is electrically connected with the pull-up output circuit and the pull-down output circuit through a pull-up node, and controls the voltage of the pull-up node according to a received first clock signal in a data writing time period in a scanning period, so that a first reference voltage is output by the pull-up output circuit, and the first reference voltage controls the pixel unit to stop displaying image data;

the second control circuit is electrically connected with the pull-up output circuit through a pull-up node, and outputs a second reference voltage according to a received second clock signal in a light-emitting time period in the scanning period, wherein the second reference voltage is used for controlling the pixel unit to display image data, and the light-emitting signal comprises the first reference voltage and the second reference voltage;

the pulse width control circuit is electrically connected to the light-emitting driving circuit, and is configured to control the frequency at which the pull-up output circuit outputs the first reference voltage and the frequency at which the pull-down output circuit outputs the second reference voltage, where the first reference voltage and the second reference voltage have the same output frequency, and the number of times of outputting the first reference voltage in the light-emitting time period is greater than 1.

20. The scan and emission driver circuit of claim 19, wherein the emission driver circuit comprises a first pulse width control circuit and a second pulse width control circuit,

a control end of a first pulse width control circuit receives a first pulse width signal with a first duty ratio, an input end of the first pulse width control circuit is electrically connected with the first reference voltage end, an output end of the first pulse width control circuit is electrically connected with a light-emitting pull-up output circuit used for outputting the light-emitting signal in the light-emitting drive circuit, the first pulse width control circuit is conducted according to a first frequency under the control of the first pulse width signal, and when the first pulse width control circuit is conducted in the light-emitting time period, the first reference voltage is output to the light-emitting signal output end through the input end, the output end and the light-emitting pull-up output end circuit of the first pulse width control circuit;

the control end of the second pulse width control circuit receives a second pulse width signal with a second duty ratio, the input end of the second pulse width control circuit is electrically connected with the second reference voltage end, the output end of the second pulse width control circuit is electrically connected with the light-emitting signal output end, the second pulse width control circuit is conducted according to a second frequency under the control of the second pulse width signal, and when the second pulse width control circuit is conducted in the light-emitting time period, the second reference voltage is output to the light-emitting signal output end through the input end and the output end of the second pulse width control circuit;

21. The scanning and light-emitting driving circuit according to claim 20,

the pull-up output circuit comprises a fourth transistor, the grid electrode of the fourth transistor is electrically connected with the pull-up node, the source electrode of the fourth transistor is electrically connected with the first pulse width control circuit, and the drain electrode of the fourth transistor is electrically connected with the luminous signal output end;

the first control circuit is electrically connected with the light-emitting drive output circuit through a pull-up node, the pull-down output circuit comprises a twelfth transistor and a third capacitor, the third capacitor is electrically connected between the pull-down node and the first reference voltage end, and the first reference voltage end provides the first reference voltage;

the gate of the twelfth transistor is electrically connected to the pull-down node, the source of the twelfth transistor is electrically connected to the first reference voltage terminal, the second reference voltage terminal provides the second reference voltage, and the drain of the twelfth transistor is electrically connected to the light-emitting signal output terminal.

22. The scan and emission driver circuit according to claim 21,

the first pulse width control circuit comprises a first pulse transistor, wherein the grid electrode of the first pulse transistor is electrically connected with the first pulse signal output end so as to receive a first pulse control signal, the source electrode of the first pulse transistor is electrically connected with a second reference voltage end, and the drain electrode of the first pulse transistor is electrically connected with the drain electrode of a fourth transistor;

the second pulse width control circuit comprises a second pulse transistor, wherein the grid electrode of the second pulse transistor is electrically connected with the second pulse signal output end to receive a second pulse control signal, the source electrode of the second pulse transistor is electrically connected with the first reference voltage end, and the drain electrode of the second pulse transistor is electrically connected with the light-emitting signal output end.

23. A display panel comprising the scanning and light-emission driving circuit according to any one of claims 19 to 22 in a non-display region of the display panel.