CN108564927A - Shift register cell and its driving method, gate driving circuit, display device - Google Patents
Shift register cell and its driving method, gate driving circuit, display device Download PDFInfo
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- CN108564927A CN108564927A CN201810034479.9A CN201810034479A CN108564927A CN 108564927 A CN108564927 A CN 108564927A CN 201810034479 A CN201810034479 A CN 201810034479A CN 108564927 A CN108564927 A CN 108564927A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of shift register cell of offer of the embodiment of the present invention and its driving method, gate driving circuit, display device, it is related to display technology field, can avoid because being resetted to upper level shift register cell using next stage shift register cell, and caused by show bad problem；The shift register cell includes：First input module resets control module, reseting module；First input module is connect with signal input part；Control module is resetted to connect with signal input part, the first clock signal terminal, second clock signal end, under signal control for non-open signal and second clock signal end after exporting open signal in signal input part, the signal of the first clock signal terminal is exported to output end；Reseting module is connect with the output end of reset control module, pull-up node, signal output end, first voltage end, is used in the case where resetting the control of output end of control module, by the voltage output at first voltage end to pull-up node and signal output end.
Description
Technical field
The present invention relates to display technology fields more particularly to a kind of shift register cell and its driving method, grid to drive
Dynamic circuit, display device.
Background technology
(Thin Film Transistor Liquid Crystal Display, Thin Film Transistors-LCD are aobvious by TFT-LCD
Show device) and OLED (Active Matrix Driving OLED, active matrix-driven organic light-emitting diode) display device
Because it has the characteristics that small size, low power consumption, no radiation and cost of manufacture are relatively low, and it is applied to height more and more
In performance display field.
Above-mentioned display device is in order to realize narrow frame design, gate driving circuit generally use GOA (Gate Driver on
Array, the driving of array substrate row) circuit；The GOA circuits include multiple cascade shift register cells, it is generally the case that
The signal output end of next stage shift register cell is connected with the reset signal end of upper level shift register cell, namely
The signal output end of next stage shift register cell, it is also simultaneous while signal output end as this grade of gated sweep signal
Have as upper level shift register cell reset signal end to be resetted to upper level shift register cell, such one
Come, in the shift register cell output signal exception of certain level-one, answering for upper level shift register cell can be influenced simultaneously
Position signal causes multi-stage shift register cell operation abnormal, it is horizontal in turn result in full frame or half screen so as to cause chain reaction
Line etc. shows bad phenomenon.
Invention content
A kind of shift register cell of the embodiment of the present invention offer and its driving method, gate driving circuit, display dress
It sets, can avoid in the prior art because being answered upper level shift register cell using next stage shift register cell
Position, and caused by show bad problem.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that：
On the one hand the embodiment of the present invention provides a kind of shift register cell, including：Pull-up node and pull-down node, in institute
It states and gated sweep signal is exported by output module control signal output under the control of pull-up node, in the pull-down node
Control is lower to control the signal output end stopping output gated sweep signal by pull-down module, and the shift register cell is also
Including：First input module resets control module, reseting module；First input module is connect with signal input part, is used for
The shift register cell is opened under the control of the open signal of signal input part input；The reset control module
It is connect with the signal input part, the first clock signal terminal, second clock signal end, for being opened in signal input part output
Under the signal control for opening the non-open signal and the second clock signal end after signal, by the first clock signal terminal
Signal is exported to the output end for resetting control module；The reseting module and the output end for resetting control module, institute
Pull-up node, the signal output end, the connection of first voltage end are stated, for the control in the output end for resetting control module
Under, the voltage output at the first voltage end to the pull-up node and the signal output end is resetted.
It is further preferred that the shift register cell further includes：Pull-down module, energy-storage module, pull-down control module；
The energy-storage module and the pull-up node, store for the voltage to the pull-up node, or are saved to the pull-up
Point charges；The pull-down control module and the pull-down node, the pull-up node, first clock signal terminal, institute
The connection of first voltage end is stated, for controlling institute by the pull-up node, first clock signal terminal, the first voltage end
State the current potential of pull-down node；First input module is connect with the signal input part, the pull-up node, for described
The open signal is exported to the pull-up node under the control of the open signal of signal input part input；The pull-down module
It is connect with the signal output end, the first voltage end, the pull-down node, the pull-up node, in the drop-down
Under the control of node, by the voltage output at the first voltage end to the signal output end and the pull-up node.
It is further preferred that first input module includes the first transistor, the grid of the first transistor and
One pole is connect with the signal input part, and the second pole is connect with the pull-up node；And/or the output module includes second
Transistor, the grid of the second transistor are connect with the pull-up node, and the first pole is connect with third clock signal terminal, and second
Pole is connect with the signal output end；And/or the pull-down module includes third transistor and the 4th transistor, the third
The grid of transistor is connect with the pull-down node, and the first pole is connect with the first voltage end, and the second pole is saved with the pull-up
Point connection, the grid of the 4th transistor are connect with the pull-down node, and the first pole is connect with the first voltage end, and second
Pole is connect with the signal output end；And/or the energy-storage module includes the first capacitance, one end of first capacitance connects
The pull-up node, the other end connect the signal output end；And/or the pull-down control module include the 5th transistor and
6th transistor, the grid of the 5th transistor and the first pole connect first clock signal terminal, described in the connection of the second pole
Pull-down node；The grid of 6th transistor connects the pull-up node, and the first pole connects the pull-down node, and the second pole connects
Connect the first voltage end.
It is further preferred that the reset control module includes the 7th transistor and the 8th transistor, the 7th crystal
The grid of pipe is connect with the signal input part, and the first pole is connect with first clock signal terminal, the second pole and the described 8th
First pole of transistor connects, and the grid of the 8th transistor is connect with the second clock signal end, and the second pole is as institute
State the output end for resetting control module；The reseting module includes the 9th transistor and the tenth transistor, the 9th transistor
Grid connect with the output end for resetting control module, the first pole is connect with the pull-up node, the second pole and described the
One voltage end connects；The grid of tenth transistor with it is described reset control module output end connect, the first pole with it is described
Signal output end connects, and the second pole is connect with the first voltage end.
It is further preferred that the pull-down control module includes supplementary module, the 5th crystal in the pull-down control module
The grid of pipe is connect by the supplementary module with first clock signal terminal；The supplementary module also with first clock
Signal end, the pull-up node, first voltage end connection, for being saved by first clock signal terminal, the pull-up
Point, the first voltage end control the 5th transistor；The supplementary module includes the tenth two-transistor and the tenth
Three transistors, the grid of the tenth two-transistor and the first pole connect first clock signal terminal, described in the connection of the second pole
The grid of first pole of the grid of the 5th transistor and the 13rd transistor, the 13rd transistor connects the pull-up
Node, the second pole connect the first voltage end.
It is further preferred that the shift register cell further includes：Second input module, and/or, noise reduction module；Institute
It states the second input module to connect with first clock signal terminal, the pull-up node, signal import and export end, be same as in institute
It states the voltage output at signal import and export end to the pull-up node under the control of the first clock signal terminal；The noise reduction mould
Block is connect with first clock signal terminal, the first voltage end, the signal output end, for believing in first clock
Number end control under, by the voltage output at the first voltage end to the signal output end.
It is further preferred that second input module includes the 11st transistor, the grid of the 11st transistor
First clock signal terminal is connected, the first pole connects signal import and export end, and the second pole connects the pull-up node；It is described
Noise reduction module includes the 14th transistor, and the grid of the 14th transistor connects first clock signal terminal, the first pole
The first voltage end is connected, the second pole connects the signal output end.
On the other hand the embodiment of the present invention provides a kind of gate driving circuit, include the shifting as the aforementioned of at least two-stage cascade
Bit register unit；The signal input part of first order shift register cell is connected with initial signal end；In addition to described first
Other than grade shift register cell, signal output end and the next stage shift register cell of upper level shift register cell
Signal input part is connected.
Another further aspect of the embodiment of the present invention also provides a kind of display device, including gate driving circuit as the aforementioned.
Another further aspect of the embodiment of the present invention also provides a kind of driving method for shift register cell above-mentioned, described
Method includes：Reseting stage after signal input part exports open signal：Control module is resetted in the signal input part
Under the non-open signal of output and the control of second clock signal end, the signal of the first clock signal terminal is exported to the reset control
The output end of molding block；Reseting module is under the control of the output end for resetting control module, by the voltage at first voltage end
Output to pull-up node and signal output end is resetted.
A kind of shift register cell of offer of the embodiment of the present invention and its driving method, gate driving circuit, display device,
A kind of shift register cell includes：Pull-up node and pull-down node pass through output module control under the control of pull-up node
Signal output end processed exports gated sweep signal, and the signal output end is controlled by pull-down module under the control of pull-down node
Stop output gated sweep signal, shift register cell further includes：First input module resets control module, reseting module；
Input module is connect with signal input part, for opening shift register under the control for the open signal that signal input part inputs
Unit；It resets control module to connect with signal input part, the first clock signal terminal, second clock signal end, for defeated in signal
Enter and hold under the signal control of non-open signal and second clock signal end after exporting open signal, the first clock is believed
Number end signal export to reset control module output end；Reseting module with reset the output end of control module, pull-up node,
Signal output end, the connection of first voltage end, are used in the case where resetting the control of output end of control module, by the electricity at first voltage end
Pressure output to pull-up node and signal output end is resetted.
In conclusion resetting control module and reseting module to pull-up node and signal output end by combining in the present invention
It is resetted, connect, reset with signal input part, the first clock signal terminal, second clock signal end due to resetting control module
Module is connect with the output end of reset control module, pull-up node, signal output end, first voltage end, namely including the displacement
In the gate driving circuit of register cell, need not using the signal output end of next stage as the reset signal of upper level, and
By combining relevant voltage end that can be resetted to pull-up node and signal output end, so as to avoid in the prior art because adopting
Upper level shift register cell is resetted with next stage shift register cell, and caused by show bad problem.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram of shift LD provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another shift LD provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another shift LD provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 5 is a kind of timing control figure of associated shift deposit provided in an embodiment of the present invention.
Reference numeral：
The first input modules of 101-；102- output modules；103- pull-down modules；104- resets control module；105- resets
Module；106- memory modules；107- pull-down control modules；1071- supplementary modules；The second input modules of 108-；109- noise reduction moulds
Block；M1- the first transistors；M2- second transistors；M3- third transistor；The 4th transistors of M4-；The 5th transistors of M5-；M6-
6th transistor；The 7th transistors of M7-；The 8th transistors of M8-；The 9th transistors of M9-；The tenth transistors of M10-；M11- the tenth
One transistor；The tenth two-transistors of M12-；The 13rd transistors of M13-；The 14th transistors of M14-；PU- pull-up nodes；Under PD-
Draw node；PD_CN- auxiliary nodes；The first clock signal terminals of CLK1-；CLK2- second clock signal ends；CLK3- third clocks are believed
Number end；OUTPUT- signal output ends；INPUT- signal input parts；VSS- first voltages end.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of shift register cell, as shown in Figure 1, the shift register cell includes：On
Node PU and pull-down node PD is drawn, passes through 102 control signal output OUTPUT of output module under the control of pull-up node PU
Gated sweep signal is exported, is stopped by 103 control signal output OUTPUT of pull-down module under the control of pull-down node PD
Export gated sweep signal.
In addition, as shown in Figure 1, the shift register cell further includes：First input module 101 resets control module
104, reseting module 105.
Specifically, with reference to figure 1, the first input module 101 is connect with signal input part INPUT, in signal input part
Shift register cell is opened under the control of the open signal of INPUT inputs.
Reset control module 104 and signal input part INPUT, the first clock signal terminal CLK1, second clock signal end
CLK2 connections, for the non-open signal and second clock signal end after signal input part INPUT output open signals
Under the signal control of CLK2, the signal of the first clock signal terminal CLK1 is exported to the output end O1 for resetting control module 104.
Reseting module 105 and the output end O1 of reset control module, pull-up node PU, signal output end OUTPUT, first
Voltage end VSS connections are used in the case where resetting the control of output end O1 of control module, and the voltage output at first voltage end is supreme
Node PU and signal output end OUTPUT is drawn to be resetted.
In conclusion resetting control module and reseting module to pull-up node and signal output end by combining in the present invention
It is resetted, is connect with signal input part INPUT, the first clock signal terminal, second clock signal end due to resetting control module,
Reseting module is connect with the output end of reset control module, pull-up node, signal output end, first voltage end, namely including being somebody's turn to do
In the gate driving circuit of shift register cell, it need not believe the signal output end of next stage as the reset of upper level
Number, and pull-up node and signal output end can be resetted by combining relevant voltage end, so as to avoid the prior art
It is middle because being resetted to upper level shift register cell using next stage shift register cell, and caused by display it is undesirable
Problem.
Herein it should be noted that in the present invention, the specific facilities of above-mentioned shift register cell are not construed as limiting,
Those skilled in the art it is to be understood that generally further include other modules for actual shift register cell, for example,
Pull-down module, pull-down control module, pull-up control module, energy-storage module etc., this is not limited by the present invention, as long as can protect
Card by the way that above-mentioned reset control module 104 and reseting module 105 is arranged, need not using the signal output end of next stage as
The reset signal of upper level is resetted；Certainly, the connection of shift register cell can be selected as needed in practice
Mode and concrete structure.
Illustrated below, it includes preferably above-mentioned first input module 101, output module 102, reset control to provide a kind of
The complete shift register cell of module 104 and reseting module 105, the shift register cell is including above-mentioned first input mould
Block 101, resets other than control module 104 and reseting module 105 output module 102, as shown in Figure 1, further including：Pull-down module
103, energy-storage module 106, pull-down control module 107.
Specifically, energy-storage module 106 and pull-up node PU, stores or right for the voltage to pull-up node PU
Pull-up node PU charges.
Pull-down control module 107 and pull-down node PD, pull-up node PU, the first clock signal terminal CLK1, first voltage end
VSS connections, the electricity for controlling pull-down node PD by pull-up node PU, the first clock signal terminal CLK1, first voltage end VSS
Position.
First input module 101 is connect with signal input part INPUT, pull-up node PU, in signal input part INPUT
Open signal is exported to pull-up node PU under the control of the open signal of input.
Pull-down module 103 and signal output end OUTPUT, first voltage end VSS, pull-down node PD, pull-up node PU connect
It connects, is used under the control of pull-down node PD, by the voltage output of first voltage end VSS to signal output end OUTPUT and pull-up
Node PU.
With reference to figure 2, the specific facilities of each module in above-mentioned shift register cell are described further below.
Specifically, the first input module 101 includes the first transistor M1, the grid of the first transistor M1 and the first pole and letter
Number input terminal INPUT connections, the second pole is connect with pull-up node PU.
Output module 102 includes second transistor M2, and the grid of second transistor M2 is connect with pull-up node PU, the first pole
It is connect with third clock signal terminal CLK3, the second pole connect OUTPUT with signal output end.
Pull-down module 103 includes third transistor M3 and the 4th transistor M4, and grid and the drop-down of third transistor M3 save
Point PD connections, the first pole are connect with first voltage end VSS, and the second pole is connect with pull-up node PU, the grid of the 4th transistor M4
It is connect with pull-down node PD, the first pole is connect with first voltage end VSS, and the second pole is connect with signal output end OUTPUT.
Energy-storage module 106 includes that one end of the first capacitance C1, the first capacitance C1 connects pull-up node PU, other end connection letter
Number output end OUTPUT.
Pull-down control module 107 includes the 5th transistor M5 and the 6th transistor M6, the grid of the 5th transistor M5 and the
One pole connects the first clock signal terminal CLK1, and the second pole connects pull-down node PD；The grid connection pull-up section of 6th transistor M6
Point PU, the first pole connect pull-down node PD, and the second pole connects first voltage end VSS.
It includes the 7th transistor M7 and the 8th transistor M8, the grid and letter of the 7th transistor M7 to reset control module 104
Number input terminal INPUT connections, the first pole are connect with the first clock signal terminal CLK1, the first pole of the second pole and the 8th transistor M8
Connection, the grid of the 8th transistor M8 are connect with second clock signal end CLK2, and the second pole is as the output for resetting control module
Hold O1.
Reseting module 105 includes the 9th transistor M9 and the tenth transistor M10, and grid and the reset of the 9th transistor M9 are controlled
The output end (namely second pole of the 8th transistor M8) of molding block 104 connects, and the first pole is connect with pull-up node PU, the second pole
It is connect with first voltage end VSS；(namely the 8th is brilliant with the output end O1 that resets control module 104 for the grid of tenth transistor M10
The second pole of body pipe M8) it connects, the first pole is connect with signal output end OUTPUT, and the second pole is connect with first voltage end VSS.
It should here be understood that arrive, it is defeated by signal input part INPUT for the first input module 101 with reference to figure 2
The open signal entered is so that the first transistor M1 conductings, are opened to realize shift register cell；And it is controlled for resetting
For molding block 104, non-open signal after signal input part INPUT output open signal opens the 7th transistor M7,
To realize the control of Electric potentials of the output end O1 to resetting control module.
Due to the open signal of signal input part INPUT input and opposite (namely the open signal of the polarity of non-open signal
It is opposite with non-open signal current potential), it is based on this, then is necessarily required to the unlatching electricity of setting the first transistor M1 and the 7th transistor M7
Press polarity opposite (it is opposite to open current potential), for example, when the first transistor M1 is N-type transistor, then the 7th transistor M7 is that p-type is brilliant
Body pipe, certainly in the case, signal input part INPUT output open signal is high level, and non-after open signal opens
It is low level to open signal, and to ensure that the first transistor M1 is opened under the control of open signal, and the 7th transistor M7 is non-
It is opened under the control of open signal；In another example when the first transistor M1 is P-type transistor, then the 7th transistor M7 is N-type crystal
Pipe, certainly in the case, signal input part INPUT output open signals are low level, and the non-unlatching after open signal
Signal is high level, and to ensure that the first transistor M1 is opened under the control of open signal, and the 7th transistor M7 is opened non-
It opens and is opened under the control of signal；Certainly it is N-type transistor generally to mostly use the first transistor M1 in practice, and the 7th transistor M7 is
P-type transistor.
Herein it should be noted that above-mentioned said by taking the specific setting structure of each module shown in Figure 2 as an example
Bright, the other structures of setting can be selected according to the actual needs in the block one or more of each mould in practice, also
Other control modules can be set, and this is not limited by the present invention.
On the basis of shifting deposit unit shown in figure 2, in order to ensure that pull-down control module 107 can be controlled effectively
The current potential of pull-down node PD processed, for example, when pull-up node is high potential, it is effective to ensure that pull-down node is low potential；Upper
It is effective to ensure that pull-down node is high potential when drawing node is low potential；It is currently preferred, as shown in figure 3, drop-down control mould
Block 107 includes supplementary module 1071, and the grid of the 5th transistor M5 passes through supplementary module 1071 and the in pull-down control module 107
One clock signal terminal CLK1 connections；The supplementary module 1071 also with the first clock signal terminal CLK1, pull-up node PU, first voltage
VSS connections are held, for passing through the first clock signal terminal CLK1, pull-up node PU, VSS pairs of first voltage end the 5th transistor M5
The current potential of grid is controlled (namely on or off of the 5th transistor M5 of control), to realize the current potential to pull-down node PD
Control ensures that pull-down node PD has stable current potential in each stage.
Specifically, as shown in figure 3, the supplementary module 1071 include the tenth two-transistor M12 and the 13rd transistor M13,
The grid of tenth two-transistor M12 and the first pole connect the first clock signal terminal CLK1, and the second pole connects the 5th transistor M5's
The grid of first pole of grid and the 13rd transistor M13, the 13rd transistor M13 connects pull-up node PU, the connection of the second pole
First voltage end VSS.
In addition, causing the unlatching of the shift register by shadow in order to avoid breaking down in the first input module 101
It rings, it is currently preferred, as shown in figure 3, the shift register cell further includes：Second input module 108, the second input mould
Block 108 is connect with the first clock signal terminal CLK1, pull-up node PU, signal import and export end INPUT, is same as in the first clock signal
It holds the voltage output of signal import and export end INPUT under the control of CLK1 to pull-up node PU, so, even if the first input
Module 101 breaks down, and can equally ensure the normally-open of shift register by second input module 108.
Specifically, with reference to figure 3, which includes the 11st transistor M11, the 11st transistor M11's
Grid the first clock signal terminal of connection CLK1, the first pole connection signal import and export end INPUT, the second pole connects pull-up node PU.
Further, in order to effectively reduce the noise that the signal output end OUTPUT of shift register is generated, this hair
It is bright preferred, as shown in figure 3, the shift register cell further includes noise reduction module 109；The noise reduction module and the first clock signal
CLK1, first voltage end VSS, signal output end OUTPUT connections are held, is used under the control of the first clock signal terminal CLK1, it will
The voltage output of first voltage end VSS carries out noise reduction to signal output end OUTPUT, to reach to signal output end OUTPUT
Purpose.
Specifically, as shown in figure 3, the noise reduction module 109 includes the 14th transistor M14, the grid of the 14th transistor M14
Pole connects the first clock signal terminal CLK1, and the first pole connects first voltage end VSS, the second pole connection signal output end OUTPUT.
The embodiment of the present invention also provides a kind of gate driving circuit (GOA circuits), as shown in figure 4, including at least two-stage grade
Connection such as aforementioned shift register unit, the signal input part of first order shift register cell is connected with initial signal end STV
It connects；Other than first order shift register cell, signal output end and the next stage of upper level shift register cell shift
The signal input part of register cell is connected；With structure identical with the shift register cell that previous embodiment provides and
Advantageous effect.Since previous embodiment is described in detail the structure of shift register cell and advantageous effect,
Details are not described herein again.
The embodiment of the present invention also provides a kind of display device, including gate driving circuit above-mentioned, equally includes above-mentioned
Shift register cell has structure identical with the shift register cell that previous embodiment provides and advantageous effect.Due to
Previous embodiment is described in detail the structure of shift register cell and advantageous effect, and details are not described herein again.
It should be noted that in embodiments of the present invention, display device at least may include specifically liquid crystal display panel and
Organic LED display panel, for example, the display panel can be applied to liquid crystal display, LCD TV, Digital Frame,
In any product or component with display function such as mobile phone or tablet computer.
The embodiment of the present invention also provides a kind of driving method of driving aforementioned shift register unit, the driving method packet
It includes：
Reseting stage after signal input part INPUT output open signals：
Reset the non-open signal and second clock signal end CLK2 that control module 104 is exported in signal input part INPUT
Control under, the signal of the first clock signal terminal CLK1 is exported to the output end O1 of the reset control module 104.
Reseting module 105 is in the case where resetting the control of output end O1 of control module 104, by the voltage of first voltage end VSS
It exports to pull-up node PU and signal output end OUTPUT and is resetted.
Specifically, each module in the timing control figure and shift register cell shown in Fig. 2 of combination Fig. 5 illustrated below
In each transistor on off operating mode, each stage of the driving method in actual displayed frame is described in detail.It needs
Illustrate, is the explanation carried out by taking the VSS input low levels of first voltage end as an example in the embodiment of the present invention, the present invention is implemented
The switching process of transistor is so that except the 7th transistor M7 resetted in control module 104 is P-type transistor, remaining is brilliant in example
Body pipe is that (but the present invention is not restricted to this, can also select opposite types in practice for the explanation that carries out for N-type transistor
Transistor, for example, the 7th transistor M7 be N-type, remaining transistor is P-type transistor, certainly control signal also select phase
The signal of reversed polarity).
In a picture frame, above-mentioned driving method includes：
First stage S1：
Under the control of input signal end INPUT, the open signal that the first input module 101 exports input signal end is defeated
Go out to pull-up node PU, and the open signal that input signal end exports is stored into energy-storage module 106.
Specifically, the high level that input signal end INPUT is exported at this stage, the first transistor M1 is opened, certainly, for
In gate driving circuit for first order shift register cell RS1, inputted at this stage to signal by initial signal end STV
End INPUT input high levels are exported the high potential to pull-up node PU, and store to storage with opening the first input module 101
In the first capacitance C1 in energy module 106.
Herein it should be noted that with reference to figure 2, for pull-down control module 107, need that the 6th transistor M6 is arranged
Channel width-over-length ratio to be more than the channel width-over-length ratio of the 5th transistor M5 to ensure in this stage be high electricity in pull-up node PU
Position, and in the case of the first clock signal terminal CLK1 output high level so that pass through the first voltage end VSS of the 6th transistor M6
Low level the high potential signal by the 5th the first clock signal terminals of transistor M5 CLK1 " can be neutralized ", and ensure in the rank
Section pull-down node PD maintains low potential.
Second stage S2：
The voltage output that memory module 106 stores S1 in the first stage to pull-up node PU, output module 102 is opened,
And by the voltage output of third clock signal terminal CLK3 to signal output end OUTPUT.
Specifically, the first capacitance C1 in memory module 106 discharges to pull-up node PU, pull-up node PU is at itself
Boot strap under, current potential further increases (with reference to figure 5), second transistor M2 is opened, and by third clock signal terminal CLK3
Output high potential exports to signal output end OUTPUT, signal output end Output and exports high level in this stage at this stage.
Phase III S3：
Pull-down control module 107 is under the control of the first clock signal terminal CLK1, by the electricity of the first clock signal terminal CLK1
Pressure output is to pull-down node PD, and under the control of pull-down node PD, pull-down module 103 is opened, and by the electricity of first voltage end VSS
Pressure is exported to signal output end OUTPUT and pull-up node PU.
Under the non-open signal of signal input part INPUT outputs and the control of second clock signal end CLK2, control is resetted
Molding block 104 exports the signal of the first clock signal terminal CLK1 to the output end O1 of the reset control module 104；It is controlled resetting
Under the control of the output end O1 of molding block 104, reseting module 105 is by the voltage output of first voltage end VSS to pull-up node PU
It is resetted with signal output end OUTPUT.
Specifically, in this stage, the first clock signal terminal CLK1 exports high level, and the 5th transistor M5 is opened, and by the
The high level output of one clock signal terminal CLK1 is to pull-down node PD, under the control of pull-down node PD high potentials, pull-down module
Third transistor M3 and the 4th transistor M4 in 103 are opened, and by by signal output end OUTPUT's and pull-up node PU
Current potential is pulled down to the low potential of first voltage end VSS.
Meanwhile in this stage, signal input part INPUT exports low level, and the 7th transistor M7 (p-type) is opened, and second
The first half stage is high level (with reference to figure 5) to clock signal terminal CLK2 in this stage, to open the 8th transistor M8 so that the
For the high level output of one clock signal terminal CLK1 to reseting module 105, the 9th transistor M9 and the tenth in reseting module 105 is brilliant
Body pipe M10 is opened under the control of the high level of the first clock signal terminal CLK1, and the low potential of first voltage end VSS is exported
To signal output end OUTPUT and pull-up node PU, to be resetted to signal output end OUTPUT and pull-up node PU.
It should here be understood that arriving, third transistor M3 and the 4th transistor M4 are opened in pull-down module 103 in S3 at this stage
It opens, the current potential of signal output end OUTPUT and pull-up node PU is pulled down to the low potential of first voltage end VSS；Meanwhile it resetting
The 9th transistor M9 and the tenth transistor M10 are opened in the first half stage of (S3) at this stage of module 105, pass through first voltage end
The low potential of VSS resets signal output end OUTPUT and pull-up node PU.
It further should be understood that arriving, before arriving next display frame after phase III S3, in the first clock signal terminal
CLK1 and second clock signal CLK2 is under the control of high level, with reference to grey square frame position in figure 5, reseting module 105 simultaneously
In the 9th transistor M9 and the tenth transistor M10 opened in the form of period distances, to which property performance period exports signal
End OUTPUT and pull-up node PU is resetted, and then effectively ensures that signal output end OUTPUT and pull-up node PU remain low
Current potential.
In addition, it is necessary to explanation but, it is defeated in shift register cell shown in Fig. 3 second below in conjunction with Fig. 5
Enter module 108, the supplementary module 1071 that pull-down control module 107 includes, in noise reduction module 109 unlatching of transistor carry out letter
Single explanation, the unlatching and closing of remaining module can refer to aforementioned to showing the unlatching of transistor and pass in each module in Fig. 2
It closes, details are not described herein again.
S1 in the first stage, under the first clock signal terminal CLK1 output high level control, the in the second input module 108
11 transistor M11 are opened, and the first clock signal terminal CLK1 is exported high level output to pull-up node PU, to avoid
First input module 101 breaks down and the unlatching of the shift register is caused to be affected.
The channel width-over-length ratio that the 13rd transistor M13 is set is needed to be more than the tenth two-transistor M12 in supplementary module 1071
Channel width-over-length ratio, to ensure in first stage S1, pull-up node PU is high potential, and the first clock signal terminal CLK1 is defeated
In the case of going out high level, with reference to figure 3 so that by auxiliary node PD_CN be low potential, to ensure S1 the in the first stage
Five transistor M5 cut-offs, and then effectively ensure that pull-down node maintains low potential at this stage.
Certainly, it is low potential, the 13rd transistor M13 cut-offs, the first clock signal in phase III S3, pull-up node PU
CLK1 is held to export high level, the tenth two-transistor M12 is opened, and the high level output of the first clock signal terminal CLK1 is extremely assisted
Node PD_CN, and the 5th transistor M5 is opened, and then ensure that pull-down node PD maintains high potential at this stage.
In addition, in phase III S3, the 14th transistor M14 in noise reduction module 109 is in the first clock signal terminal CLK1
The lower unlatching of high level control is exported, and by the low level output of first voltage end VSS to signal output end OUTPUT, with to signal
Output end OUTPUT carries out noise reduction.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of shift register cell, including：Pull-up node and pull-down node, by defeated under the control of the pull-up node
Go out module control signal output end output gated sweep signal, institute is controlled by pull-down module under the control of the pull-down node
It states signal output end and stops output gated sweep signal, which is characterized in that
The shift register cell further includes：First input module resets control module, reseting module；
First input module is connect with signal input part, the control of the open signal for being inputted in the signal input part
It is lower to open the shift register cell；
The reset control module is connect with the signal input part, the first clock signal terminal, second clock signal end, is used for
The signal control of non-open signal and the second clock signal end after the signal input part output open signal
Under, the signal of the first clock signal terminal is exported to the output end for resetting control module；
The reseting module and the output end for resetting control module, the pull-up node, the signal output end, the first electricity
Press bond is used under the control of the output end for resetting control module, extremely by the voltage output at the first voltage end
The pull-up node and the signal output end are resetted.
2. shift register cell according to claim 1, which is characterized in that the shift register cell further includes：
Pull-down module, energy-storage module, pull-down control module；
The energy-storage module and the pull-up node, store for the voltage to the pull-up node, or on described
Node is drawn to charge；
The pull-down control module and the pull-down node, the pull-up node, first clock signal terminal, first electricity
Press bond, for controlling the drop-down by the pull-up node, first clock signal terminal, the first voltage end and saving
The current potential of point；
First input module is connect with the signal input part, the pull-up node, for defeated in the signal input part
The open signal is exported to the pull-up node under the control of the open signal entered；
The pull-down module connects with the signal output end, the first voltage end, the pull-down node, the pull-up node
It connects, is used under the control of the pull-down node, by the voltage output at the first voltage end to the signal output end and institute
State pull-up node.
3. shift register cell according to claim 2, which is characterized in that
First input module includes the first transistor, and the grid of the first transistor and the first pole are inputted with the signal
End connection, the second pole is connect with the pull-up node；
And/or the output module includes second transistor, the grid of the second transistor is connect with the pull-up node,
First pole is connect with third clock signal terminal, and the second pole is connect with the signal output end；
And/or the pull-down module includes third transistor and the 4th transistor, the grid of the third transistor with it is described under
Node connection, the first pole is drawn to be connect with the first voltage end, the second pole is connect with the pull-up node, the 4th transistor
Grid connect with the pull-down node, the first pole is connect with the first voltage end, and the second pole and the signal output end connect
It connects；
And/or the energy-storage module includes the first capacitance, one end of first capacitance connects the pull-up node, the other end
Connect the signal output end；
And/or the pull-down control module includes the 5th transistor and the 6th transistor, the grid of the 5th transistor and the
One pole connects first clock signal terminal, and the second pole connects the pull-down node；The grid of 6th transistor connects institute
Pull-up node is stated, the first pole connects the pull-down node, and the second pole connects the first voltage end.
4. according to claim 1-3 any one of them shift register cells, which is characterized in that
The reset control module includes the 7th transistor and the 8th transistor, grid and the signal of the 7th transistor
Input terminal connects, and the first pole is connect with first clock signal terminal, and the second pole is connect with the first pole of the 8th transistor,
The grid of 8th transistor is connect with the second clock signal end, and the second pole is as the output for resetting control module
End；
The reseting module includes the 9th transistor and the tenth transistor, and grid and the reset of the 9th transistor control
The output end of module connects, and the first pole is connect with the pull-up node, and the second pole is connect with the first voltage end；Described tenth
The grid of transistor is connect with the output end for resetting control module, and the first pole is connect with the signal output end, the second pole
It is connect with the first voltage end.
5. shift register cell according to claim 3, which is characterized in that the pull-down control module includes auxiliary mould
Block, the grid of the 5th transistor passes through the supplementary module and connects with first clock signal terminal in the pull-down control module
It connects；
The supplementary module is also connect with first clock signal terminal, the pull-up node, the first voltage end, for leading to
Cross first clock signal terminal, the pull-up node, the first voltage end control the 5th transistor；
The supplementary module includes the tenth two-transistor and the 13rd transistor, the grid of the tenth two-transistor and the first pole
Connect first clock signal terminal, the second pole connect the 5th transistor grid and the 13rd transistor first
The grid of pole, the 13rd transistor connects the pull-up node, and the second pole connects the first voltage end.
6. shift register cell according to claim 2, which is characterized in that the shift register cell further includes：
Second input module, and/or, noise reduction module；
Second input module is connect with first clock signal terminal, the pull-up node, signal import and export end, together
By the voltage output at signal import and export end to the pull-up node under the control in first clock signal terminal；
The noise reduction module is connect with first clock signal terminal, the first voltage end, the signal output end, is used for
Under the control of first clock signal terminal, by the voltage output at the first voltage end to the signal output end.
7. shift register cell according to claim 6, which is characterized in that
Second input module includes the 11st transistor, and the grid of the 11st transistor connects the first clock letter
Number end, the first pole connect signal import and export end, and the second pole connects the pull-up node；
The noise reduction module includes the 14th transistor, and the grid of the 14th transistor connects first clock signal
End, the first pole connect the first voltage end, and the second pole connects the signal output end.
8. a kind of gate driving circuit, which is characterized in that including at least two-stage cascade such as claim 1-7 any one of them
Shift register cell；
The signal input part of first order shift register cell is connected with initial signal end；
Other than the first order shift register cell, the signal output end and next stage of upper level shift register cell
The signal input part of shift register cell is connected.
9. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 8.
10. a kind of driving method for driving such as claim 1-7 any one of them shift register cells, feature exists
In, the method includes：
Reseting stage after signal input part exports open signal：
It resets under the control of non-open signal and second clock signal end that control module is exported in the signal input part, by the
The signal of one clock signal terminal is exported to the output end of the reset control module；
Reseting module it is described reset control module output end control under, by the voltage output at first voltage end to pull up section
Point and signal output end are resetted.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020146997A1 (en) * | 2019-01-15 | 2020-07-23 | 深圳市柔宇科技有限公司 | Scan driving unit, scan driving circuit, array substrate, and display device |
| CN113066422A (en) * | 2019-12-13 | 2021-07-02 | 华为机器有限公司 | Scanning and light-emitting drive circuit, scanning and light-emitting drive system and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140098013A1 (en) * | 2012-10-09 | 2014-04-10 | Beijing Boe Optoelectronics Technology Co., Ltd. | Shift register, integrated gate line driving circuit, array substrate and display |
| CN105206235A (en) * | 2015-09-28 | 2015-12-30 | 京东方科技集团股份有限公司 | Reset device |
| CN105245089A (en) * | 2015-11-06 | 2016-01-13 | 京东方科技集团股份有限公司 | Supplementary reset module, grid driving circuit and display device |
| CN106486047A (en) * | 2017-01-03 | 2017-03-08 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driver circuit and display device |
| CN107358906A (en) * | 2017-09-14 | 2017-11-17 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN107424552A (en) * | 2017-06-13 | 2017-12-01 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
-
2018
- 2018-01-12 CN CN201810034479.9A patent/CN108564927B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140098013A1 (en) * | 2012-10-09 | 2014-04-10 | Beijing Boe Optoelectronics Technology Co., Ltd. | Shift register, integrated gate line driving circuit, array substrate and display |
| CN105206235A (en) * | 2015-09-28 | 2015-12-30 | 京东方科技集团股份有限公司 | Reset device |
| CN105245089A (en) * | 2015-11-06 | 2016-01-13 | 京东方科技集团股份有限公司 | Supplementary reset module, grid driving circuit and display device |
| CN106486047A (en) * | 2017-01-03 | 2017-03-08 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driver circuit and display device |
| CN107424552A (en) * | 2017-06-13 | 2017-12-01 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN107358906A (en) * | 2017-09-14 | 2017-11-17 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020146997A1 (en) * | 2019-01-15 | 2020-07-23 | 深圳市柔宇科技有限公司 | Scan driving unit, scan driving circuit, array substrate, and display device |
| CN113261041A (en) * | 2019-01-15 | 2021-08-13 | 深圳市柔宇科技股份有限公司 | Scanning driving unit, scanning driving circuit, array substrate and display device |
| CN113066422A (en) * | 2019-12-13 | 2021-07-02 | 华为机器有限公司 | Scanning and light-emitting drive circuit, scanning and light-emitting drive system and display panel |
| CN113066422B (en) * | 2019-12-13 | 2022-06-24 | 华为机器有限公司 | Scanning and light-emitting drive circuit, scanning and light-emitting drive system and display panel |
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