CN108564927B

CN108564927B - Shifting register unit and driving method thereof, grid driving circuit and display device

Info

Publication number: CN108564927B
Application number: CN201810034479.9A
Authority: CN
Inventors: 宋洋; 王俊伟
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2018-01-12
Filing date: 2018-01-12
Publication date: 2021-01-26
Anticipated expiration: 2038-01-12
Also published as: CN108564927A

Abstract

The embodiment of the invention provides a shift register unit and a driving method thereof, a grid driving circuit and a display device, relates to the technical field of display, and can avoid the problem of poor display caused by the fact that a next-stage shift register unit is adopted to reset a previous-stage shift register unit; the shift register unit includes: the device comprises a first input module, a reset control module and a reset module; the first input module is connected with the signal input end; the reset control module is connected with the signal input end, the first clock signal end and the second clock signal end and is used for outputting a signal of the first clock signal end to the output end under the control of a non-starting signal after the signal input end outputs a starting signal and a signal of the second clock signal end; the reset module is connected with the output end of the reset control module, the pull-up node, the signal output end and the first voltage end and is used for outputting the voltage of the first voltage end to the pull-up node and the signal output end under the control of the output end of the reset control module.

Description

Shifting register unit and driving method thereof, grid driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register unit, a driving method thereof, a grid driving circuit and a display device.

Background

TFT-LCD (Thin Film Transistor Liquid Crystal Display) and OLED (Active Matrix Driving OLED) Display devices are increasingly applied to the field of high performance Display because of their features of small size, low power consumption, no radiation, relatively low manufacturing cost, etc.

In order to realize the narrow frame design of the display device, the Gate driving circuit usually adopts a Gate Driver on Array (GOA) circuit; the GOA circuit comprises a plurality of cascaded shift register units, under the normal condition, the signal output end of the next-stage shift register unit is connected with the reset signal end of the previous-stage shift register unit, namely the signal output end of the next-stage shift register unit is used as the signal output end of the current-stage grid scanning signal, and meanwhile, the GOA circuit also has the reset signal end used as the previous-stage shift register unit to reset the previous-stage shift register unit.

Disclosure of Invention

Embodiments of the present invention provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device, which can avoid a problem of poor display caused by resetting a previous shift register unit by using a next shift register unit in the prior art.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

an embodiment of the present invention provides a shift register unit, including: pull-up node and pull-down node, through output module control signal output part output grid scanning signal under the control of pull-up node, through pull-down module control under the control of pull-down node signal output part stops output grid scanning signal, shift register unit still includes: the device comprises a first input module, a reset control module and a reset module; the first input module is connected with a signal input end and used for starting the shift register unit under the control of a starting signal input by the signal input end; the reset control module is connected with the signal input end, the first clock signal end and the second clock signal end and is used for outputting a signal of the first clock signal end to the output end of the reset control module under the control of a non-starting signal after the signal input end outputs a starting signal and a signal of the second clock signal end; the reset module is connected with the output end of the reset control module, the pull-up node, the signal output end and the first voltage end, and is used for outputting the voltage of the first voltage end to the pull-up node and the signal output end for resetting under the control of the output end of the reset control module.

Further preferably, the shift register unit further includes: the pull-down control module comprises a pull-down module, an energy storage module and a pull-down control module; the energy storage module and the pull-up node are used for storing the voltage of the pull-up node or charging the pull-up node; the pull-down control module is connected with the pull-down node, the pull-up node, the first clock signal end and the first voltage end, and is used for controlling the potential of the pull-down node through the pull-up node, the first clock signal end and the first voltage end; the first input module is connected with the signal input end and the pull-up node and is used for outputting a starting signal to the pull-up node under the control of the starting signal input by the signal input end; the pull-down module is connected with the signal output end, the first voltage end, the pull-down node and the pull-up node, and is used for outputting the voltage of the first voltage end to the signal output end and the pull-up node under the control of the pull-down node.

Further preferably, the first input module includes a first transistor, a gate and a first pole of the first transistor are connected to the signal input terminal, and a second pole of the first transistor is connected to the pull-up node; and/or the output module comprises a second transistor, the grid electrode of the second transistor is connected with the pull-up node, the first pole of the second transistor is connected with the third clock signal end, and the second pole of the second transistor is connected with the signal output end; and/or the pull-down module comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor is connected with the pull-down node, the first pole of the third transistor is connected with the first voltage end, the second pole of the third transistor is connected with the pull-up node, the grid electrode of the fourth transistor is connected with the pull-down node, the first pole of the fourth transistor is connected with the first voltage end, and the second pole of the fourth transistor is connected with the signal output end; and/or the energy storage module comprises a first capacitor, one end of the first capacitor is connected with the pull-up node, and the other end of the first capacitor is connected with the signal output end; and/or the pull-down control module comprises a fifth transistor and a sixth transistor, wherein the grid and the first pole of the fifth transistor are connected with the first clock signal end, and the second pole of the fifth transistor is connected with the pull-down node; and the grid electrode of the sixth transistor is connected with the pull-up node, the first pole of the sixth transistor is connected with the pull-down node, and the second pole of the sixth transistor is connected with the first voltage end.

Further preferably, the reset control module includes a seventh transistor and an eighth transistor, a gate of the seventh transistor is connected to the signal input terminal, a first pole of the seventh transistor is connected to the first clock signal terminal, a second pole of the seventh transistor is connected to the first pole of the eighth transistor, a gate of the eighth transistor is connected to the second clock signal terminal, and the second pole of the eighth transistor is used as the output terminal of the reset control module; the reset module comprises a ninth transistor and a tenth transistor, the grid electrode of the ninth transistor is connected with the output end of the reset control module, the first pole of the ninth transistor is connected with the pull-up node, and the second pole of the ninth transistor is connected with the first voltage end; and the grid electrode of the tenth transistor is connected with the output end of the reset control module, the first pole of the tenth transistor is connected with the signal output end, and the second pole of the tenth transistor is connected with the first voltage end.

Further preferably, the pull-down control module includes an auxiliary module, and a gate of a fifth transistor in the pull-down control module is connected to the first clock signal terminal through the auxiliary module; the auxiliary module is further connected with the first clock signal terminal, the pull-up node, and the first voltage terminal, and is configured to control the fifth transistor through the first clock signal terminal, the pull-up node, and the first voltage terminal; the auxiliary module comprises a twelfth transistor and a thirteenth transistor, wherein the grid and the first pole of the twelfth transistor are connected with the first clock signal end, the second pole of the twelfth transistor is connected with the grid of the fifth transistor and the first pole of the thirteenth transistor, the grid of the thirteenth transistor is connected with the pull-up node, and the second pole of the thirteenth transistor is connected with the first voltage end.

Further preferably, the shift register unit further includes: a second input module and/or a noise reduction module; the second input module is connected with the first clock signal end, the pull-up node and the signal input/output end, and is used for outputting the voltage of the signal input/output end to the pull-up node under the control of the first clock signal end; the noise reduction module is connected with the first clock signal end, the first voltage end and the signal output end and used for outputting the voltage of the first voltage end to the signal output end under the control of the first clock signal end.

Preferably, the second input module includes an eleventh transistor, a gate of the eleventh transistor is connected to the first clock signal terminal, a first pole of the eleventh transistor is connected to the signal input/output terminal, and a second pole of the eleventh transistor is connected to the pull-up node; the noise reduction module comprises a fourteenth transistor, wherein the grid electrode of the fourteenth transistor is connected with the first clock signal end, the first pole of the fourteenth transistor is connected with the first voltage end, and the second pole of the fourteenth transistor is connected with the signal output end.

Another aspect of the embodiments of the present invention provides a gate driving circuit, including at least two cascaded shift register units as described above; the signal input end of the first-stage shift register unit is connected with the initial signal end; and the signal output end of the nth-1 stage shift register unit is connected with the signal input end of the nth stage shift register unit, and n is a positive integer greater than or equal to 2.

In another aspect, the embodiment of the invention further provides a display device, which includes the gate driving circuit.

In another aspect, an embodiment of the present invention further provides a driving method for the shift register unit, where the method includes: in a reset phase after the signal input terminal outputs the start signal: the reset control module outputs a signal of the first clock signal end to the output end of the reset control module under the control of the non-starting signal output by the signal input end and the second clock signal end; the reset module outputs the voltage of the first voltage end to the pull-up node and the signal output end for resetting under the control of the output end of the reset control module.

The embodiment of the invention provides a shift register unit and a driving method thereof, a grid driving circuit and a display device, wherein the shift register unit comprises: pull-up node and pull-down node, through output module control signal output part output grid scanning signal under the control of pull-up node, through pull-down module control under the control of pull-down node signal output part stops output grid scanning signal, and the shift register unit still includes: the device comprises a first input module, a reset control module and a reset module; the input module is connected with the signal input end and used for starting the shift register unit under the control of a starting signal input by the signal input end; the reset control module is connected with the signal input end, the first clock signal end and the second clock signal end and is used for outputting a signal of the first clock signal end to the output end of the reset control module under the control of a non-starting signal after the signal input end outputs a starting signal and a signal of the second clock signal end; the reset module is connected with the output end of the reset control module, the pull-up node, the signal output end and the first voltage end and is used for outputting the voltage of the first voltage end to the pull-up node and the signal output end for resetting under the control of the output end of the reset control module.

In summary, in the present invention, the pull-up node and the signal output terminal are reset by combining the reset control module and the reset module, because the reset control module is connected to the signal input terminal, the first clock signal terminal, and the second clock signal terminal, and the reset module is connected to the output terminal of the reset control module, the pull-up node, the signal output terminal, and the first voltage terminal, that is, in the gate driving circuit including the shift register unit, the pull-up node and the signal output terminal can be reset by combining the corresponding voltage terminals without using the signal output terminal of the next stage as the reset signal of the previous stage, thereby avoiding the problem of poor display caused by resetting the shift register unit of the previous stage by using the shift register unit of the next stage in the prior art.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating another shift register structure according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating another shift register structure according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

FIG. 5 is a timing diagram of a shift register according to an embodiment of the present invention.

Reference numerals:

101-a first input module; 102-an output module; 103-a pull-down module; 104-a reset control module; 105-a reset module; 106-a storage module; 107-a pull-down control module; 1071 — an auxiliary module; 108-a second input module; 109-a noise reduction module; m1 — first transistor; m2 — second transistor; m3 — third transistor; m4 — fourth transistor; m5 — fifth transistor; m6 — sixth transistor; m7-seventh transistor; m8 — eighth transistor; m9 — ninth transistor; m10-tenth transistor; m11 — eleventh transistor; m12 — twelfth transistor; m13-thirteenth transistor; m14 — a fourteenth transistor; PU-pull-up node; PD-a pull-down node; PD _ CN-auxiliary node; CLK 1-first clock signal terminal; CLK 2-second clock signal terminal; CLK 3-third clock signal terminal; OUTPUT-signal OUTPUT terminal; INPUT-signal INPUT; VSS-first voltage terminal.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a shift register unit, as shown in fig. 1, the shift register unit includes: the pull-up node PU and the pull-down node PD control the signal OUTPUT terminal OUTPUT to OUTPUT the gate scan signal through the OUTPUT module 102 under the control of the pull-up node PU, and control the signal OUTPUT terminal OUTPUT to stop outputting the gate scan signal through the pull-down module 103 under the control of the pull-down node PD.

Further, as shown in fig. 1, the shift register unit further includes: a first input module 101, a reset control module 104, and a reset module 105.

Specifically, referring to fig. 1, the first INPUT module 101 is connected to the signal INPUT terminal INPUT, and is configured to turn on the shift register unit under the control of a turn-on signal INPUT by the signal INPUT terminal INPUT.

The reset control module 104 is connected to the signal INPUT terminal INPUT, the first clock signal terminal CLK1 and the second clock signal terminal CLK2, and is configured to output a signal of the first clock signal terminal CLK1 to the output terminal O1 of the reset control module 104 under the control of a non-on signal after the signal INPUT terminal INPUT outputs the on signal and the signal of the second clock signal terminal CLK 2.

The reset module 105 is connected to the OUTPUT terminal O1 of the reset control module, the pull-up node PU, the signal OUTPUT terminal OUTPUT, and the first voltage terminal VSS, and is configured to OUTPUT the voltage of the first voltage terminal to the pull-up node PU and the signal OUTPUT terminal OUTPUT for resetting under the control of the OUTPUT terminal O1 of the reset control module.

In summary, in the present invention, the pull-up node and the signal output terminal are reset by combining the reset control module and the reset module, because the reset control module is connected to the signal INPUT terminal INPUT, the first clock signal terminal, and the second clock signal terminal, and the reset module is connected to the output terminal of the reset control module, the pull-up node, the signal output terminal, and the first voltage terminal, that is, in the gate driving circuit including the shift register unit, the pull-up node and the signal output terminal can be reset by combining the corresponding voltage terminals without using the signal output terminal of the next stage as the reset signal of the previous stage, thereby avoiding the problem of poor display caused by resetting the shift register unit of the previous stage by using the shift register unit of the next stage in the prior art.

It should be noted that, in the present invention, a specific setting condition of the shift register unit is not limited, and it should be understood by those skilled in the art that an actual shift register unit generally includes other modules, for example, a pull-down module, a pull-down control module, a pull-up control module, an energy storage module, and the like, which is not limited in this respect, as long as it is ensured that a signal output end of a next stage is not required to be reset as a reset signal of a previous stage by setting the reset control module 104 and the reset module 105; of course, the connection mode and the specific structure of the shift register unit can be selected as required in practice.

As shown below, a preferred complete shift register unit including the first input module 101, the output module 102, the reset control module 104, and the reset module 105 is provided, and in addition to the first input module 101, the output module 102, the reset control module 104, and the reset module 105, as shown in fig. 1, the shift register unit further includes: a pull-down module 103, an energy storage module 106 and a pull-down control module 107.

Specifically, the energy storage module 106 and the pull-up node PU are configured to store a voltage of the pull-up node PU or charge the pull-up node PU.

The pull-down control module 107 is connected to the pull-down node PD, the pull-up node PU, the first clock signal terminal CLK1, and the first voltage terminal VSS, and is configured to control a potential of the pull-down node PD through the pull-up node PU, the first clock signal terminal CLK1, and the first voltage terminal VSS.

The first INPUT module 101 is connected to the signal INPUT terminal INPUT and the pull-up node PU, and is configured to output a start signal to the pull-up node PU under the control of a start signal INPUT by the signal INPUT terminal INPUT.

The pull-down module 103 is connected to the signal OUTPUT terminal OUTPUT, the first voltage terminal VSS, the pull-down node PD, and the pull-up node PU, and configured to OUTPUT a voltage of the first voltage terminal VSS to the signal OUTPUT terminal OUTPUT and the pull-up node PU under the control of the pull-down node PD.

Referring to fig. 2, the specific arrangement of the modules in the shift register unit is further described below.

Specifically, the first INPUT module 101 includes a first transistor M1, a gate and a first pole of the first transistor M1 are connected to the signal INPUT terminal INPUT, and a second pole is connected to the pull-up node PU.

The OUTPUT module 102 includes a second transistor M2, a gate of the second transistor M2 is connected to the pull-up node PU, a first pole is connected to the third clock signal terminal CLK3, and a second pole is connected to the signal OUTPUT terminal OUTPUT.

The pull-down module 103 includes a third transistor M3 and a fourth transistor M4, a gate of the third transistor M3 is connected to the pull-down node PD, a first pole is connected to the first voltage terminal VSS, a second pole is connected to the pull-up node PU, a gate of the fourth transistor M4 is connected to the pull-down node PD, the first pole is connected to the first voltage terminal VSS, and the second pole is connected to the signal OUTPUT terminal OUTPUT.

The energy storage module 106 includes a first capacitor C1, one end of the first capacitor C1 is connected to the pull-up node PU, and the other end is connected to the signal OUTPUT terminal OUTPUT.

The pull-down control module 107 includes a fifth transistor M5 and a sixth transistor M6, a gate and a first pole of the fifth transistor M5 are connected to the first clock signal terminal CLK1, and a second pole is connected to the pull-down node PD; the gate of the sixth transistor M6 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the first voltage terminal VSS.

The reset control module 104 includes a seventh transistor M7 and an eighth transistor M8, wherein a gate of the seventh transistor M7 is connected to the signal INPUT terminal INPUT, a first pole is connected to the first clock signal terminal CLK1, a second pole is connected to a first pole of the eighth transistor M8, a gate of the eighth transistor M8 is connected to the second clock signal terminal CLK2, and the second pole is used as the output terminal O1 of the reset control module.

The reset module 105 includes a ninth transistor M9 and a tenth transistor M10, a gate of the ninth transistor M9 is connected to an output terminal of the reset control module 104 (i.e., a second pole of the eighth transistor M8), a first pole is connected to the pull-up node PU, and a second pole is connected to the first voltage terminal VSS; the gate of the tenth transistor M10 is connected to the OUTPUT terminal O1 (i.e., the second pole of the eighth transistor M8) of the reset control module 104, the first pole is connected to the signal OUTPUT terminal OUTPUT, and the second pole is connected to the first voltage terminal VSS.

It should be understood here that, with reference to fig. 2, for the first INPUT module 101, the turning-on signal inputted through the signal INPUT terminal INPUT makes the first transistor M1 conductive, thereby realizing that the shift register unit is turned on; for the reset control module 104, the signal INPUT terminal INPUT outputs a non-on signal after the on signal to turn on the seventh transistor M7, so as to control the voltage level of the output terminal O1 of the reset control module.

Since the polarity of the on signal and the polarity of the off signal inputted by the signal INPUT terminal INPUT are opposite (i.e. the potentials of the on signal and the off signal are opposite), it is necessary to set the polarities of the on voltages of the first transistor M1 and the seventh transistor M7 (the potentials of the on signal and the off signal are opposite) based on this, for example, when the first transistor M1 is an N-type transistor, the seventh transistor M7 is a P-type transistor, in this case, the on signal outputted by the signal INPUT terminal INPUT is at a high level, and the off signal after the on signal is at a low level, so as to ensure that the first transistor M1 is turned on under the control of the on signal, and the seventh transistor M7 is turned on under the control of the off signal; for another example, when the first transistor M1 is a P-type transistor, the seventh transistor M7 is an N-type transistor, and in this case, of course, the signal INPUT terminal INPUT outputs a turn-on signal at a low level, and a non-turn-on signal after the turn-on signal is at a high level, so as to ensure that the first transistor M1 is turned on under the control of the turn-on signal, and the seventh transistor M7 is turned on under the control of the non-turn-on signal; in practice, the first transistor M1 is usually an N-type transistor, and the seventh transistor M7 is a P-type transistor.

It should be noted that the above description is only given by taking the specific arrangement structure of each module shown in fig. 2 as an example, and in practice, other structures may be selectively provided for one or more of the modules according to actual needs, and other control modules may also be provided, and the present invention is not limited to this.

On the basis of the shift register unit shown in fig. 2, in order to ensure that the pull-down control module 107 can effectively control the potential of the pull-down node PD, for example, when the pull-up node is at a high potential, the pull-down node is effectively ensured to be at a low potential; when the pull-up node is at a low potential, the pull-down node is effectively ensured to be at a high potential; preferably, as shown in fig. 3, the pull-down control module 107 includes an auxiliary module 1071, and a gate of a fifth transistor M5 in the pull-down control module 107 is connected to the first clock signal terminal CLK1 through the auxiliary module 1071; the auxiliary module 1071 is further connected to the first clock signal terminal CLK1, the pull-up node PU, and the first voltage terminal VSS, and is configured to control a potential of the gate of the fifth transistor M5 (i.e., control on or off of the fifth transistor M5) through the first clock signal terminal CLK1, the pull-up node PU, and the first voltage terminal VSS, so as to implement potential control on the pull-down node PD and ensure that the pull-down node PD has a stable potential at each stage.

Specifically, as shown in fig. 3, the auxiliary module 1071 includes a twelfth transistor M12 and a thirteenth transistor M13, a gate and a first pole of the twelfth transistor M12 are connected to the first clock signal terminal CLK1, a second pole is connected to a gate of the fifth transistor M5 and a first pole of the thirteenth transistor M13, a gate of the thirteenth transistor M13 is connected to the pull-up node PU, and a second pole is connected to the first voltage terminal VSS.

In addition, in order to avoid the influence on the start of the shift register caused by the failure of the first input module 101, it is preferable that, as shown in fig. 3, the shift register unit further includes: the second INPUT module 108, the second INPUT module 108 being connected to the first clock terminal CLK1, the pull-up node PU and the signal INPUT/output terminal INPUT, outputs the voltage of the signal INPUT/output terminal INPUT to the pull-up node PU under the control of the first clock terminal CLK1, so that the normal turning-on of the shift register can be ensured by the second INPUT module 108 even if the first INPUT module 101 fails.

Specifically, referring to fig. 3, the second INPUT module 108 includes an eleventh transistor M11, a gate of the eleventh transistor M11 is connected to the first clock signal terminal CLK1, a first pole is connected to the signal INPUT terminal INPUT, and a second pole is connected to the pull-up node PU.

Furthermore, in order to effectively reduce the noise generated at the signal OUTPUT terminal OUTPUT of the shift register, it is preferable that, as shown in fig. 3, the shift register unit further includes a noise reduction module 109; the noise reduction module is connected with the first clock signal terminal CLK1, the first voltage terminal VSS and the signal OUTPUT terminal OUTPUT, and is used for outputting the voltage of the first voltage terminal VSS to the signal OUTPUT terminal OUTPUT under the control of the first clock signal terminal CLK1, so that the purpose of reducing noise of the signal OUTPUT terminal OUTPUT is achieved.

Specifically, as shown in fig. 3, the noise reduction module 109 includes a fourteenth transistor M14, a gate of the fourteenth transistor M14 is connected to the first clock signal terminal CLK1, a first pole is connected to the first voltage terminal VSS, and a second pole is connected to the signal OUTPUT terminal OUTPUT.

An embodiment of the present invention further provides a gate driver circuit (GOA circuit), as shown in fig. 4, including at least two cascaded shift register units, where a signal input end of a first shift register unit is connected to a start signal end STV; the signal output end of the nth-1 stage shift register unit is connected with the signal input end of the nth stage shift register unit, and n is a positive integer greater than or equal to 2; has the same structure and beneficial effects as the shift register unit provided by the previous embodiment. Since the foregoing embodiments have described the structure and beneficial effects of the shift register unit in detail, no further description is provided herein.

The embodiment of the present invention further provides a display device, which includes the gate driving circuit and the shift register unit, and has the same structure and beneficial effects as the shift register unit provided in the foregoing embodiment. Since the foregoing embodiments have described the structure and beneficial effects of the shift register unit in detail, no further description is provided herein.

It should be noted that, in the embodiment of the present invention, the display device may specifically include at least a liquid crystal display panel and an organic light emitting diode display panel, for example, the display panel may be applied to any product or component with a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.

The embodiment of the present invention further provides a driving method for driving the shift register unit, where the driving method includes:

in the reset phase after the signal INPUT terminal INPUT outputs the start signal:

the reset control module 104 outputs the signal of the first clock signal terminal CLK1 to the output terminal O1 of the reset control module 104 under the control of the non-on signal output from the signal INPUT terminal INPUT and the second clock signal terminal CLK 2.

The reset module 105 OUTPUTs the voltage of the first voltage terminal VSS to the pull-up node PU and the signal OUTPUT terminal OUTPUT for resetting under the control of the OUTPUT terminal O1 of the reset control module 104.

Specifically, the following description schematically describes the driving method in detail at each stage in an actual display frame, in conjunction with the timing control diagram of fig. 5 and the on-off state of each transistor in each block in the shift register unit shown in fig. 2. It should be noted that, in the embodiment of the present invention, the first voltage terminal VSS is inputted with a low level as an example, and the on/off process of the transistors in the embodiment of the present invention is described by taking the seventh transistor M7 in the reset control module 104 as a P-type transistor and the other transistors as N-type transistors as examples (but the present invention is not limited thereto, and in practice, the opposite type of transistors may be selected, for example, the seventh transistor M7 is N-type, the other transistors are P-type transistors, and of course, the control signal may also be a signal with opposite polarity).

In an image frame, the driving method includes:

first stage S1:

under the control of the INPUT signal terminal INPUT, the first INPUT module 101 outputs the start signal output by the INPUT signal terminal to the pull-up node PU, and stores the start signal output by the INPUT signal terminal into the energy storage module 106.

Specifically, the first transistor M1 is turned on when the signal terminal INPUT outputs a high level at this stage, and certainly, for the first stage shift register unit RS1 in the gate driving circuit, a high level is INPUT to the signal terminal INPUT through the initial signal terminal STV at this stage to turn on the first INPUT module 101, and the high level is output to the pull-up node PU and stored in the first capacitor C1 in the energy storage module 106.

It should be noted that, referring to fig. 2, for the pull-down control module 107, it is necessary to set the channel width-to-length ratio of the sixth transistor M6 to be greater than the channel width-to-length ratio of the fifth transistor M5 to ensure that the low level of the first voltage terminal VSS through the sixth transistor M6 can "neutralize" the high level signal of the first clock signal terminal CLK1 through the fifth transistor M5 and ensure that the pull-down node PD maintains the low level in this stage when the pull-up node PU is at the high level and the first clock signal terminal CLK1 outputs the high level.

Second stage S2:

the memory module 106 OUTPUTs the voltage stored in the first stage S1 to the pull-up node PU, the OUTPUT module 102 is turned on, and OUTPUTs the voltage of the third clock signal terminal CLK3 to the signal OUTPUT terminal OUTPUT.

Specifically, the first capacitor C1 in the memory module 106 discharges the pull-up node PU, the voltage level of the pull-up node PU further increases under self bootstrap action (refer to fig. 5), the second transistor M2 is turned on, and the third clock signal terminal CLK3 OUTPUTs a high voltage level to the signal OUTPUT terminal OUTPUT at this stage, and the signal OUTPUT terminal OUTPUT OUTPUTs a high voltage level at this stage.

Third stage S3:

the pull-down control module 107 OUTPUTs the voltage of the first clock signal terminal CLK1 to the pull-down node PD under the control of the first clock signal terminal CLK1, and the pull-down module 103 is turned on under the control of the pull-down node PD and OUTPUTs the voltage of the first voltage terminal VSS to the signal OUTPUT terminal OUTPUT and the pull-up node PU.

Under the control of the non-on signal output from the signal INPUT terminal INPUT and the second clock signal terminal CLK2, the reset control module 104 outputs the signal of the first clock signal terminal CLK1 to the output terminal O1 of the reset control module 104; the reset module 105 OUTPUTs the voltage of the first voltage terminal VSS to the pull-up node PU and the signal OUTPUT terminal OUTPUT for resetting under the control of the OUTPUT terminal O1 of the reset control module 104.

Specifically, at this stage, the first clock signal terminal CLK1 OUTPUTs a high level, the fifth transistor M5 is turned on, and OUTPUTs the high level of the first clock signal terminal CLK1 to the pull-down node PD, and the third transistor M3 and the fourth transistor M4 in the pull-down module 103 are turned on under the control of the high level of the pull-down node PD and pull-down the potentials of the signal OUTPUT terminal OUTPUT and the pull-up node PU to the low level of the first voltage terminal VSS.

Meanwhile, in this stage, the signal INPUT terminal INPUT OUTPUTs a low level, the seventh transistor M7 (P-type) is turned on, and the second clock signal terminal CLK2 is at a high level in the first half of the stage (refer to fig. 5), so that the eighth transistor M8 is turned on, so that the high level of the first clock signal terminal CLK1 is OUTPUT to the reset module 105, and the ninth transistor M9 and the tenth transistor M10 in the reset module 105 are turned on under the control of the high level of the first clock signal terminal CLK1 and OUTPUT the low level of the first voltage terminal VSS to the signal OUTPUT terminal OUTPUT and the pull-up node PU to reset the signal OUTPUT terminal OUTPUT and the pull-up node PU.

It should be understood here that the third transistor M3 and the fourth transistor M4 in the pull-down module 103 are turned on in this stage S3, and pull down the potentials of the signal OUTPUT terminal OUTPUT and the pull-up node PU to the low potential of the first voltage terminal VSS; meanwhile, the reset module 105 turns on the ninth transistor M9 and the tenth transistor M10 in the first half of the phase (S3), and resets the signal OUTPUT terminal OUTPUT and the pull-up node PU by the low potential of the first voltage terminal VSS.

In addition, it should be further understood that, after the third stage S3 and before the next display frame, under the control that the first clock signal terminal CLK1 and the second clock signal terminal CLK2 are at the high level at the same time, referring to the gray box position in fig. 5, the ninth transistor M9 and the tenth transistor M10 in the reset module 105 are turned on at periodic intervals, so as to periodically reset the signal OUTPUT terminal OUTPUT and the pull-up node PU, thereby effectively ensuring that the signal OUTPUT terminal OUTPUT and the pull-up node PU maintain the low level.

In addition, it should be noted that, in the following, with reference to fig. 5, turning on of the transistors in the auxiliary module 1071 and the noise reduction module 109 included in the second input module 108 and the pull-down control module 107 in the shift register unit shown in fig. 3 is briefly described, and turning on and off of the remaining modules may refer to turning on and off of the transistors in each module shown in fig. 2, which is not described herein again.

In the first phase S1, the eleventh transistor M11 in the second input block 108 is turned on under the control of the first clock signal terminal CLK1 outputting a high level, and outputs the high level output from the first clock signal terminal CLK1 to the pull-up node PU, so as to prevent the turning on of the shift register from being affected due to the failure of the first input block 101.

In the auxiliary module 1071, the channel width-to-length ratio of the thirteenth transistor M13 needs to be greater than the channel width-to-length ratio of the twelfth transistor M12 to ensure that the pull-up node PU is at a high potential in the first stage S1 and the first clock signal terminal CLK1 outputs a high level, referring to fig. 3, the auxiliary node PD _ CN is at a low potential to ensure that the fifth transistor M5 is turned off in the first stage S1, thereby effectively ensuring that the pull-down node maintains a low potential in this stage.

Of course, in the third stage S3, the pull-up node PU is low, the thirteenth transistor M13 is turned off, the first clock signal terminal CLK1 outputs high, the twelfth transistor M12 is turned on, and outputs the high of the first clock signal terminal CLK1 to the auxiliary node PD _ CN and turns on the fifth transistor M5, thereby ensuring that the pull-down node PD maintains high at this stage.

In addition, in the third stage S3, the fourteenth transistor M14 in the noise reduction module 109 is turned on under the control of the first clock signal terminal CLK1 outputting a high level, and OUTPUTs a low level of the first voltage terminal VSS to the signal OUTPUT terminal OUTPUT to reduce noise at the signal OUTPUT terminal OUTPUT.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A shift register cell comprising: a pull-up node and a pull-down node, the signal output terminal is controlled by an output module to output a grid scanning signal under the control of the pull-up node, the signal output terminal is controlled by a pull-down module to stop outputting the grid scanning signal under the control of the pull-down node,

the shift register unit further includes: the device comprises a first input module, a reset control module and a reset module;

the first input module is connected with a signal input end and used for starting the shift register unit under the control of a starting signal input by the signal input end;

the reset control module is connected with the signal input end, the first clock signal end and the second clock signal end and is used for outputting a signal of the first clock signal end to the output end of the reset control module under the control of a non-starting signal after the signal input end outputs a starting signal and a signal of the second clock signal end;

the reset module is connected with the output end of the reset control module, the pull-up node, the signal output end and the first voltage end, and is used for outputting the voltage of the first voltage end to the pull-up node and the signal output end for resetting under the control of the output end of the reset control module;

the reset control module comprises a seventh transistor and an eighth transistor, wherein the grid electrode of the seventh transistor is connected with the signal input end, the first pole of the seventh transistor is connected with the first clock signal end, the second pole of the seventh transistor is connected with the first pole of the eighth transistor, the grid electrode of the eighth transistor is connected with the second clock signal end, and the second pole of the eighth transistor is used as the output end of the reset control module.

2. The shift register cell of claim 1, further comprising: the pull-down control module comprises a pull-down module, an energy storage module and a pull-down control module;

the energy storage module and the pull-up node are used for storing the voltage of the pull-up node or charging the pull-up node;

the pull-down control module is connected with the pull-down node, the pull-up node, the first clock signal end and the first voltage end, and is used for controlling the potential of the pull-down node through the pull-up node, the first clock signal end and the first voltage end;

the first input module is connected with the signal input end and the pull-up node and is used for outputting a starting signal to the pull-up node under the control of the starting signal input by the signal input end;

the pull-down module is connected with the signal output end, the first voltage end, the pull-down node and the pull-up node, and is used for outputting the voltage of the first voltage end to the signal output end and the pull-up node under the control of the pull-down node.

3. The shift register cell of claim 2,

the first input module comprises a first transistor, the grid electrode and the first pole of the first transistor are connected with the signal input end, and the second pole of the first transistor is connected with the pull-up node;

and/or the output module comprises a second transistor, the grid electrode of the second transistor is connected with the pull-up node, the first pole of the second transistor is connected with the third clock signal end, and the second pole of the second transistor is connected with the signal output end;

and/or the pull-down module comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor is connected with the pull-down node, the first pole of the third transistor is connected with the first voltage end, the second pole of the third transistor is connected with the pull-up node, the grid electrode of the fourth transistor is connected with the pull-down node, the first pole of the fourth transistor is connected with the first voltage end, and the second pole of the fourth transistor is connected with the signal output end;

and/or the energy storage module comprises a first capacitor, one end of the first capacitor is connected with the pull-up node, and the other end of the first capacitor is connected with the signal output end;

and/or the pull-down control module comprises a fifth transistor and a sixth transistor, wherein the grid and the first pole of the fifth transistor are connected with the first clock signal end, and the second pole of the fifth transistor is connected with the pull-down node; and the grid electrode of the sixth transistor is connected with the pull-up node, the first pole of the sixth transistor is connected with the pull-down node, and the second pole of the sixth transistor is connected with the first voltage end.

4. The shift register unit according to any one of claims 1 to 3, wherein the reset module includes a ninth transistor and a tenth transistor, a gate of the ninth transistor is connected to the output terminal of the reset control module, a first pole is connected to the pull-up node, and a second pole is connected to the first voltage terminal; and the grid electrode of the tenth transistor is connected with the output end of the reset control module, the first pole of the tenth transistor is connected with the signal output end, and the second pole of the tenth transistor is connected with the first voltage end.

5. The shift register unit according to claim 3, wherein the pull-down control module comprises an auxiliary module, and a gate of a fifth transistor in the pull-down control module is connected to the first clock signal terminal through the auxiliary module;

the auxiliary module is further connected with the first clock signal terminal, the pull-up node, and the first voltage terminal, and is configured to control the fifth transistor through the first clock signal terminal, the pull-up node, and the first voltage terminal;

the auxiliary module comprises a twelfth transistor and a thirteenth transistor, wherein the grid and the first pole of the twelfth transistor are connected with the first clock signal end, the second pole of the twelfth transistor is connected with the grid of the fifth transistor and the first pole of the thirteenth transistor, the grid of the thirteenth transistor is connected with the pull-up node, and the second pole of the thirteenth transistor is connected with the first voltage end.

6. The shift register cell of claim 2, further comprising: a second input module and/or a noise reduction module;

the second input module is connected to the first clock signal terminal, the pull-up node, and the signal input terminal, and is configured to output a voltage of the signal input terminal to the pull-up node under the control of the first clock signal terminal;

the noise reduction module is connected with the first clock signal end, the first voltage end and the signal output end and used for outputting the voltage of the first voltage end to the signal output end under the control of the first clock signal end.

7. The shift register cell of claim 6,

the second input module comprises an eleventh transistor, the grid electrode of the eleventh transistor is connected with the first clock signal end, the first pole of the eleventh transistor is connected with the signal input end, and the second pole of the eleventh transistor is connected with the pull-up node;

the noise reduction module comprises a fourteenth transistor, wherein the grid electrode of the fourteenth transistor is connected with the first clock signal end, the first pole of the fourteenth transistor is connected with the first voltage end, and the second pole of the fourteenth transistor is connected with the signal output end.

8. A gate drive circuit comprising at least two cascaded stages of the shift register cell of any one of claims 1-7;

the signal input end of the first-stage shift register unit is connected with the initial signal end;

and the signal output end of the nth-1 stage shift register unit is connected with the signal input end of the nth stage shift register unit, and n is a positive integer greater than or equal to 2.

9. A display device comprising the gate driver circuit according to claim 8.

10. A driving method for driving a shift register cell according to any one of claims 1 to 7, characterized in that the method comprises:

in a reset phase after the signal input terminal outputs the start signal:

the reset control module outputs a signal of the first clock signal end to the output end of the reset control module under the control of the non-starting signal output by the signal input end and the second clock signal end;

the reset module outputs the voltage of the first voltage end to the pull-up node and the signal output end for resetting under the control of the output end of the reset control module.