CN108648694B - Display device and driving method thereof - Google Patents
Display device and driving method thereof Download PDFInfo
- Publication number
- CN108648694B CN108648694B CN201810415821.XA CN201810415821A CN108648694B CN 108648694 B CN108648694 B CN 108648694B CN 201810415821 A CN201810415821 A CN 201810415821A CN 108648694 B CN108648694 B CN 108648694B
- Authority
- CN
- China
- Prior art keywords
- data
- voltage
- path selection
- data signal
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
Abstract
The invention discloses a display device and a driving method of the display device, the display device includes a plurality of pixel circuits; a plurality of data lines connected to the plurality of pixel circuits; the multi-path selection unit comprises an input end and at least two output ends, and each output end is connected with one data line; and the driving unit is used for inputting a pre-charging voltage to the input end of the multi-path selection unit in a pre-charging stage and inputting at least two data signal voltages to the input end of the multi-path selection unit in a time-sharing mode in a data writing stage, the pre-charging voltage is related to the at least two data signal voltages, and the pre-charging voltage is greater than or equal to the minimum voltage of the data signal voltages and less than or equal to the maximum voltage of the data signal voltages. The problem of incomplete charging of a pixel circuit in a display device in a data writing stage is solved, and the charging efficiency and the display effect are improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display device and a driving method of the display device.
Background
An Organic Light Emitting Diode (OLED) display employs a very thin Organic material film layer and a glass substrate, and when a current flows, the Organic material emits Light. The OLED display can thus save significant power and can be made lighter and thinner.
The OLED panel comprises an organic light emitting diode, a pixel circuit for driving the organic light emitting diode to be continuously lighted, and a data line for transmitting a data signal voltage to the pixel driving circuit. In the display process, the data lines need to be charged, that is, the data signal voltages are transmitted to the data lines, and the pixel circuits drive the organic light emitting diodes to emit light according to the data signal voltages on the connected data lines. The process of charging the data lines generally includes a precharge phase and a data write phase. In the pre-charging stage, a low potential is pre-charged to the data line, and then the data signal voltage is charged to the data line in the data writing stage, so that the voltage written into the pixel circuit on the data line is rapidly charged to an ideal potential in the data writing stage. With the increase in screen size and the demand for high-resolution display devices, an increase in data leads and driving chips is inevitable. To reduce the number of pins, a multiplexer is usually used to solve the problem of excessive data pins. In addition, the line frequency of the display panel is smaller and smaller, and in a smaller time, the data lines are not fully charged in the data writing phase.
Disclosure of Invention
The invention provides a display device and a driving method of the display device, which solve the problem that a pixel circuit in a display panel is incompletely charged in a data writing stage so as to improve the charging efficiency and the display effect.
In a first aspect, an embodiment of the present invention provides a display device, including:
a plurality of pixel circuits;
a plurality of data lines connected to the plurality of pixel circuits;
at least one multiplexing unit, said multiplexing unit includes an input end and at least two output ends, each said output end connects a said data link;
the charging process comprises a pre-charging stage and a data writing stage, wherein a pre-charging voltage is input to the input end of the multi-path selection unit in the pre-charging stage, at least two data signal voltages are input to the input end of the multi-path selection unit in a time division mode in the data writing stage, the pre-charging voltage is associated with the at least two data signal voltages, and the pre-charging voltage is greater than or equal to the minimum voltage of the data signal voltages and less than or equal to the maximum voltage of the data signal voltages.
In a second aspect, an embodiment of the present invention further provides a driving method of a display device, where the display device includes:
a plurality of pixel circuits;
a plurality of data lines connected to the plurality of pixel circuits;
at least one multiplexing unit, said multiplexing unit includes an input end and at least two output ends, each said output end connects a said data link;
the driving method includes:
a precharge stage of inputting a precharge voltage to an input terminal of the multi-path selection unit;
a data writing stage, namely inputting at least two data signal voltages to the input end of the multi-path selection unit in a time-sharing manner; the pre-charge voltage is associated with the at least two data signal voltages, and is greater than or equal to the minimum voltage of the data signal voltages and less than or equal to the maximum voltage of the data signal voltages.
According to the technical scheme provided by the embodiment of the invention, in the pre-charging stage, the driving unit inputs the pre-charging voltage associated with the voltage of the data signal to the data line through the multi-path selection unit, so that the voltage crossing of the data line in the data writing stage is reduced; in the data writing stage, the driving unit rapidly and rapidly charges the data signal voltage on the data line to the data signal voltage through the multi-path selection unit, and the charging time of the data line is greatly shortened. Therefore, when the screen size of the display panel in the display device is increased and the line frequency of the display panel is smaller and smaller, the data lines can be fully charged in the data writing stage by adjusting the pre-charging voltage, so that the charging efficiency and the display effect are improved.
Drawings
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;
FIG. 2 is a timing diagram illustrating an operation process of a display device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a multi-path selecting unit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of pulses on a scan line and pulses on a first clock signal line according to an embodiment of the present invention;
fig. 6 is a flowchart of a driving method of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The process of charging the data lines by the display panel generally includes a pre-charge phase and a data write phase. In the prior art, the display panel precharges a low potential (usually 0V or a voltage required for displaying 255 gray levels) to the data lines in the precharge stage, so that when the data writing stage is entered, the data lines can be charged from the precharged potential, so that the data lines are charged to the data signal voltage quickly. However, when the data signal voltage is very different from the precharge voltage, the data line may have a voltage jump during the data writing phase, resulting in incomplete charging of the data line. For example, when the precharge voltage is 0V or 3V, the data signal voltage is written to the black state voltage 6V in the data writing stage, and the data line has a transition from 0V or 3V to 6V. The data line has a short time in the data writing stage, so that the voltage written into the data line is not 6V of the black state, and finally the display panel is not dark in the dark state.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the invention, and as shown in fig. 1, the display device 100 includes a plurality of pixel circuits 110;
a plurality of data lines 111 connected to the plurality of pixel circuits;
at least one multiplexing unit 121, where the multiplexing unit 121 includes an input terminal and at least two output terminals, and each output terminal is connected to one data line 111;
and a driving unit 130 for charging the data lines 111 electrically connected to the multiplexing unit 121 through the multiplexing unit 121, wherein the charging process includes a pre-charging phase and a data writing phase, a pre-charging voltage is input to the input terminal Vin of the multiplexing unit 121 in the pre-charging phase, and at least two data signal voltages are input to the input terminal Vin of the multiplexing unit 121 in a time division manner in the data writing phase, the pre-charging voltage is associated with the at least two data signal voltages, and the pre-charging voltage is greater than or equal to a minimum voltage of the data signal voltages and less than or equal to a maximum voltage of the data signal voltages.
The display panel includes a plurality of multiplexing units 121, for a multiplexing unit 121, the input terminal Vin of the multiplexing unit 121 is sequentially connected to each output terminal at different times, in a time period, the input terminal Vin of the multiplexing unit 121 is connected to only one output terminal, and the voltage input by the input terminal Vin of the multiplexing unit 121 is output to the output terminal connected to the input terminal Vin, and then transmitted to the data line 111 connected to the output terminal. A pixel circuit 110 is connected to a data line 111, and the connection manner of the data line 111 and the pixel circuit 110 can be set according to the specific pixel arrangement, for example, a column of pixel circuits 110 is connected to the same data line 111. The number of outputs of the multiplexing unit may be configured according to the practical application, for example, the multiplexing unit may include 2, 3, 4 or 6 outputs. As shown in fig. 1, the data line D1, the data line D2, the data line D3 and the data line D4 respectively represent the first column data line 111, the second column data line 111, the third column data line 111 and the fourth column data line 111. The multiplexer unit in fig. 1 includes two output terminals, and specifically, the multiplexer unit 121 includes an input terminal Vin and two output terminals, which are a first output terminal Vout1 and a second output terminal Vout2, respectively, the first output terminal Vout1 and the second output terminal Vout2 of the first multiplexer unit 121 are connected to the data line D1 and the data line D2, respectively, and the first output terminal Vout1 and the second output terminal Vout2 of the second multiplexer unit 121 are connected to the data line D3 and the data line D4, respectively.
The multiplexing unit 121 further includes at least two control signal terminals for controlling whether the input terminal Vin is conducted with at least two output terminals. Generally, the number of control signal terminals is equal to the number of output terminals of the multiplexer 121. With continued reference to fig. 1, each multiplexing unit 121 includes two output terminals Vout1 and Vout2, and the multiplexing unit 121 further includes two control signal terminals, namely a first control signal terminal CTRL1 and a second control signal terminal CTRL2, for controlling whether the input terminal Vin is connected to the first output terminal Vout1 and the second output terminal Vout2, so that the first output terminal Vout1 and the second output terminal Vout2 implement the signal input by the output terminal Vin, and the signal input by the first control signal terminal CTRL1 can control the input terminal Vin to be connected to or disconnected from the first output terminal, for example, when the first control signal terminal CTRL1 inputs a low-level signal, the input terminal Vin is connected to the first output terminal, and when the first control signal terminal CTRL1 inputs a high-level signal, the input terminal Vin is disconnected from the first output terminal; or when the first control signal terminal CTRL1 inputs a high level signal, the input terminal Vin is connected to the first output terminal, and when the first control signal terminal CTRL1 inputs a low level signal, the input terminal Vin is disconnected from the first output terminal. Accordingly, the signal inputted from the second control signal terminal CTRL2 can control the input terminal Vin to be connected to or disconnected from the second output terminal Vout 2.
The driving unit 130 is electrically connected to the multiplexing unit 121, and charges the plurality of data lines 111 through the multiplexing unit 121. Fig. 2 is a timing diagram of an operation process of a display device according to an embodiment of the present invention, and fig. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present invention. As shown in fig. 3, the pixel circuit includes a first transistor T1, a second transistor T2, a driving transistor Tdr, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting element E. A gate of the first transistor T1 and a gate of the sixth transistor T6 are electrically connected to the light emitting signal line EMIT, a first pole of the first transistor T1 is electrically connected to the first voltage line PVDD, and a second pole is electrically connected to a second pole of the second transistor T2 and the first pole of the driving transistor Tdr; the gate of the second transistor T2 is electrically connected to the second SCAN line SCAN2, and the first pole is electrically connected to the data line VDATA; a gate electrode of the driving transistor Tdr is electrically connected to a second electrode of the fifth transistor T5 and a first electrode of the storage capacitor Cst, and a second electrode is electrically connected to a second electrode of the fourth transistor T4 and a first electrode of the sixth transistor T6; a gate electrode of the fourth transistor T4 is electrically connected to the second SCAN line SCAN2, and a first electrode thereof is electrically connected to the first electrode of the storage capacitor Cst; a gate of the fifth transistor T5 is electrically connected to the first SCAN line SCAN1, and a first pole is electrically connected to the reference voltage line VREF; a second pole of the sixth transistor T6 is electrically connected to the anode of the light emitting element E and a second pole of the seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to the second SCAN line SCAN2, and a first pole is electrically connected to the reference voltage line VREF; the cathode of the light emitting element E is electrically connected to a second voltage line PVEE. The operation process of the pixel circuit 110 may include an initialization phase t1, a data writing phase t2, and a light emitting display phase. Next, the operation of the display panel according to the embodiment of the invention will be described by taking the first to seventh transistors T1 to T7 as P-type transistors as an example. As shown in fig. 2, in the initialization stage T1, the first SCAN line SCAN1 inputs a low level, the fifth transistor T5 is turned on, the node N1 inputs the voltage VREF on the reference voltage line VREF, the storage capacitor Cst stores the difference between the voltage on the first voltage line PVDD and the reference voltage VREF, and the gate of the driving transistor Tdr is also the reference voltage VREF; in the data writing phase T2, the second SCAN line SCAN2 inputs a low level, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on, the storage capacitor Cst stores a voltage associated with the threshold voltage of the driving transistor Tdr, and the data signal voltage VDATA on the data line VDATA is written into the pixel circuit and transmitted to the first electrode of the sixth transistor T6 through the driving transistor Tdr; in the light emitting display period, the light emitting signal line EMIT is inputted with a low level, the sixth transistor T6 is turned on, the driving transistor Tdr outputs a driving current according to the voltage on the storage capacitor Cst, the driving current is transmitted to the anode of the light emitting element E through the sixth transistor T6, and the light emitting element E is driven to EMIT light.
In order to quickly charge the voltage on the data line VDATA to the data signal voltage required to be written into the pixel circuit in the data writing phase t2, after the initialization phase t1, the data line VDATA is written into the data voltage phase t2, and a pre-charging phase t3 is further included for the data line VDATA. As shown in fig. 1, 2 and 3, the data line VDATA of fig. 3 is the data line 111 of fig. 1, and thus, one period T of the charging process of the data line 111 may include a precharge phase T3 and data write phases T4 and T5. The output terminals Vout1 and Vout2 of the multiplexer 121 are connected to the data lines D1 and D2 for illustration. In the precharge phase t3, the signal inputted from the first control signal terminal CTRL1 of the multiplexing unit 121 is at a low level (CTRL1), the signal inputted from the second control signal terminal CTRL2 is at a low level (CTRL2), both the output terminals Vout1 and Vout2 are turned on with the input terminal Vin, and the multiplexing unit 121 outputs the precharged voltage signal pre inputted from the input terminal Vin from the output terminals Vout1 and Vout2 to the data lines D1 and D2, so as to precharge the data lines D1 and D2. Before the precharge phase t3, the driving unit 121 acquires the data signal voltages vd1 and vd2 to be written to the data lines D1 and D2, and outputs a voltage (which may include a data signal voltage equal to that on the data lines D1 and D2) between the data signal voltage vd1 and the data signal voltage vd2 as a precharge voltage through a logic operation, and precharges the data lines D1 and D2 through the multiplexing unit 121. The data writing phases include t4 phases and t5 phases, wherein the t4 phase is a data writing phase for the data line D1, and the t5 phase is a data writing phase for the data line D2. At the stage t4, the first control signal terminal CTRL1 of the multiplexing unit 121 is at a low level, the output terminal Vout1 is connected to the input terminal Vin, the second control terminal CTRL2 is at a high level, the output terminal Vout2 is disconnected from the input terminal Vin, and the data signal voltage input from the input terminal Vin is transmitted to the data line D1 through the output terminal Vout 1; at the time t5, the first control signal terminal CTRL1 of the multiplexing unit 121 is at a high level, the output terminal Vout1 is connected to the input terminal Vin, the second control terminal CTRL2 is at a low level, the output terminal Vout2 is disconnected from the input terminal Vin, and the data signal voltage input from the input terminal Vin is transmitted to the data line D2 through the output terminal Vout 2. That is, the driving unit 130 time-divisionally inputs the data signal voltages of the data lines D1 and D2 to the input terminal Vin of the multiplexing unit 121, and writes data to the pixel circuits connected to the data lines D1 and D2 through the output terminals Vout1 and Vout2 of the multiplexing unit 121. In the data writing phase, the multiplexing unit 121 generally writes data to only the data line 111 connected to one output terminal. The initial voltage of the data writing phase t2 is a precharge voltage pre, which is between the data signal voltage of the data line D1 and the data signal voltage of the data line D2, so that the data lines D1 and D2 can reduce the voltage across the data lines D1 and D2 during the data writing phase t2, and quickly charge the data signal voltages on the data lines D1 and D2 to the ideal potential, thereby greatly shortening the charging time of the data lines D1 and D2 and quickly reaching the data signal voltage. Therefore, when the screen size of the display panel in the display device 100 is increased and the line frequency of the display panel is decreased, the data lines 111 can be fully charged in the data writing stage by adjusting the pre-charge voltage, thereby improving the charging efficiency and the display effect of the display panel. After the data writing phase t2 is completed, the charging process is performed on the pixel circuits of the next row to which the data lines D1 and D2 are connected, and the above charging process is repeated. In repeating the above-described charging process, the driving unit 121 acquires the data signal voltages to be written on the data lines D1 and D2 again, at which time the data signal voltages to be charged on the data lines D1 and D2 may vary, and when the data signal voltages vd1 and vd2 to be charged on the data lines D1 and D2 vary, the precharged voltage signal pre still varies with the variation of the data signal voltages vd1 and vd2 on the data lines D1 and D2, and still has a value between the data signal voltage on the data line D1 and the data signal voltages vd1 and vd2 on the data line D2 (which may include a data signal voltage equal to that on the data lines D1 and D2), so that the precharge voltage pre-can be associated with the data signal voltages vd1 and vd1 on the data lines D1 and D1, thereby reducing the voltage across the data lines D1 and D1 in the data writing stage t1, and rapidly charging the data signal voltages on the data lines D1 and 1, thereby greatly shortening the charging time of the data lines D1 and D2.
Exemplarily, as shown in fig. 1, the display panel provided by the embodiment of the invention further includes a plurality of scan lines 112, and the scan lines G1, G2, G3 and G4 respectively represent the first row of scan lines 112, the second row of scan lines 112, the third row of scan lines 112 and the fourth row of scan lines 112. When the voltage of the data signal to be written to the pixel circuit connected to the data line D1 and the first row scanning line G1 is 6V, and the voltage of the data signal to be written to the pixel circuit connected to the data line D2 and the first row scanning line G1 is 5V, during the precharge phase t3 in the operation of the pixel circuit connected to the first row scanning line G1, the driving unit 130 obtains two voltages of the data signal to be written to the data lines D1 and D2, which are 6V and 5V, respectively, and the driving unit 130 outputs a precharge voltage signal pre equal to or greater than 5V and equal to or less than 6V to precharge the pixel circuit connected to the first row scanning line G1. In the data writing phase t2, the voltage across the pre-charge voltage signal pre to the two data signal voltages of 5V and 6V is relatively small, so that the data lines D1 and D2 can be charged to the ideal potential quickly, the charging time of the data lines D1 and D2 is greatly shortened, and the charging is complete. When the voltage of the data signal to be written to the pixel circuit connected to the data line D1 and the second row of scan lines G2 is 4V and the voltage of the data signal to be written to the pixel circuit connected to the data line D2 and the second row of scan lines G2 is 3V, after the charging process of the pixel circuit connected to the first row of scan lines G1 is completed, the precharge phase of the pixel circuit connected to the next row of scan lines G2 is entered, the driving unit 130 acquires the two voltages of the data signal to be written to the data lines D1 and D2 again, which are 4V and 3V, respectively, and the driving unit 130 outputs the precharge voltage of 3V or more and 4V or less to precharge the pixel circuit connected to the second row of scan lines G2. In the data writing phase, the voltage across the precharge voltage to the two data signal voltages of 3V and 4V is relatively small, so that the data lines D1 and D2 can be rapidly charged to the ideal potential. Therefore, the precharge voltage can be dynamically adjusted, the voltage of the data line 111 in the data writing stage is reduced, the data signal voltage on the data line 111 is quickly charged to an ideal potential, the screen size of the display panel in the display device 100 is increased, the line frequency of the display panel is smaller and smaller, and the data line 111 is completely charged in the data writing stage, so that high resolution is realized, and the charging efficiency and the display effect are improved.
In the technical scheme of the embodiment, in the pre-charging stage, the driving unit inputs pre-charging voltage related to the voltage of the data signal to the data line through the multi-path selection unit, so that the voltage across the data line in the data writing stage is reduced; in the data writing stage, the driving unit rapidly charges the voltage on the data line to the target voltage through the multi-path selection unit, and the charging time of the data line is greatly shortened. Therefore, when the screen size of a display panel in the display device is increased and the line frequency of the display panel is smaller and smaller, the data lines can be completely charged in the data writing stage by adjusting the pre-charging voltage, so that high resolution is realized, and the charging efficiency and the display effect are improved.
On the basis of the above technical solution, optionally, the precharge voltage is equal to a minimum voltage among the data signal voltages. When the minimum voltage of the data signal voltages is selected as the precharge voltage, the problem that the data signal voltage cannot be written in the pixel circuit electrically connected with the data line because the precharge voltage is greater than the data signal voltage can be avoided in the data writing stage.
Illustratively, the voltage of the data signal to be written to the pixel circuit connected to the data line D1 and the first row scanning line G1 is 6V, and the voltage of the data signal to be written to the pixel circuit connected to the data line D2 and the first row scanning line G1 is 5V, then during the operation of the pixel circuit connected to the first row scanning line G1, during the precharge phase t3, the driving unit 130 obtains two voltages of the data signal to be written to the data lines D1 and D2, which are 6V and 5V, respectively, and then the comparator in the driving unit 130 outputs 5V as the precharge voltage. When the precharge voltage is greater than 5V, the data signal voltage (5V) written by the pixel circuit connected between the data line D2 and the first row scanning line G1 is less than the precharge voltage, so that the data signal voltage 5V on the data line D2 cannot be written into the pixel circuit electrically connected to the data line D2 in the data writing phase, causing the pixel circuit electrically connected to the data line D2 to display an abnormal phenomenon.
On the basis of the above technical solution, the driving unit 130 may include a comparator that outputs a minimum voltage among the data signal voltages as a precharge voltage.
Illustratively, with continued reference to fig. 1, the driving unit 130 obtains the data signal voltages to be written on the data lines D1 and D2 connected to the multiplexing unit 121 and inputs them to the comparator, the comparator logically operates the data signal voltages to be written on the data lines D1 and D2, outputs the minimum voltage of the data signal voltages on the data lines D1 and D2 as a precharge voltage to the input terminal Vin of the multiplexing unit 121, and the two control signal terminals CTRL1 and CTRL2 of the multiplexing unit 121 control the two output terminals Vout1 and Vout2 to output the precharge voltage input from the input terminal Vin to the data lines D1 and D2 and precharge the data lines D1 and D2.
Alternatively, the precharge voltage is equal to an average value of the voltages of the respective data signals. In the data writing stage, if the difference between the voltages of the data signals is large, the problem that the difference between the pre-charge voltage and the voltages of the data signals is large, which results in large voltage across the lines can be avoided, and when the average value in the voltages of the data signals is selected as the pre-charge voltage, the difference between the pre-charge voltage and the voltages of the data signals to be charged into the data lines is not large, so that the display effect of the pixel circuit is prevented from being influenced.
Illustratively, the voltage of the data signal to be written to the pixel circuit connected between the data line D1 and the first row of scan lines G1 is 6V, and the voltage of the data signal to be written to the pixel circuit connected between the data line D2 and the first row of scan lines G1 is 3V, then during the operation of the pixel circuit connected to the first row of scan lines G1, during the precharge phase, the driving unit 130 obtains two voltages of the data signal to be written to the data lines D1 and D2, which are 6V and 3V, respectively, and if the precharge voltage is selected to be 3V, during the data write phase, there is a voltage jump from 3V to 6V when the data signal voltage 6V is written to the data line D1, resulting in the voltage written to the pixel circuit not reaching 6V. When the average value of the two data signal voltages of the data lines D1 and D2 is adopted, the precharge voltage is 4.5V, so that the difference between the precharge voltage and each data signal voltage can be reduced, the problems of large voltage across lines and voltage jump are avoided, and the pixel circuit displays the expected gray scale.
Fig. 4 is a schematic structural diagram of a multiplexing unit according to an embodiment of the present invention, and as shown in fig. 4, the multiplexing unit 121 includes at least two first transistors; the gates of the at least two first transistors are connected to the at least two first clock signal lines in a one-to-one correspondence, the first poles of the at least two first transistors are both connected to the input terminal Vin of the multiplexing unit 121, and the second poles of the at least two first transistors are respectively connected to the at least two output terminals of the multiplexing unit. The multiplexing unit 121 shown in fig. 4 includes 2 first switching transistors, i.e., a first switching transistor M1-1 and a second first switching transistor M1-2. The first and second first switching transistors M1-1 and M1-2 have first poles electrically connected to the input terminal Vin and second poles electrically connected to the output terminals Vout1 and Vout2, respectively, and the gates of the first and second first switching transistors M1-1 and M1-2 are electrically connected to the first and second first clock lines CLK1 and CLK2, respectively, through the control signal terminals of the multiplexing unit 121. Continuing to refer to fig. 2, taking the first switch transistor as a P-type transistor as an example, when the first clock signal line CLK1 is at a low level, the first switch transistor M1-1 is turned on, the output terminal Vout1 is in conductive connection with the input terminal Vin, and the first switch transistor M1-1 transmits the voltage of the input terminal Vin of the multiplexing unit 121 to the output terminal Vout 1; when the second first clock signal line CLK2 is at a low level, the second first switch transistor M1-2 is turned on, the output terminal Vout2 is connected to the input terminal Vin, and the second first switch transistor M1-2 transmits the voltage at the input terminal Vin of the multiplexer 121 to the output terminal Vout 2. It is therefore possible to control whether the two output terminals Vout1 and Vout2 of the multiplexer unit 121 are brought into conduction with the input terminal Vin by adjusting the timing of the two first clock signal lines CLK1 and CLK 2.
It should be noted that the number of the first transistors in the multiplexing unit may be greater than 2, and the number of the first transistors generally corresponds to one output terminal of the multiplexing unit. The first switch transistor may also be an N-type transistor, which is turned on when the corresponding first clock signal line is at a high level, and transmits the voltage at the input terminal Vin of the multiplexing unit 121 to the output terminal.
On the basis of the above technical solution, with continuing reference to fig. 2, as shown in fig. 1 and fig. 2, the display device 100 further includes a plurality of scan lines 112 arranged to intersect with the data lines 111; the signal on the scan line 112 and the signal on the first clock signal line each include a plurality of pulses; the pulse on the scanning line covers at least the pulse of the data writing phase on each first clock signal line.
The plurality of scan lines 112 are electrically connected to the pixel circuits of each row in a one-to-one correspondence, and are configured to output scan signals to the corresponding pixel circuits one by one. Also, taking the example that the first switch transistor in the multiplexer unit is a P-type transistor and the multiplexer unit includes two input terminals, as shown in fig. 2, the pulse on the scan line 112 (e.g., the t2 phase) covers the pulses of the data writing phases (including the t4 phase and the t5 phase) on the two first clock signal lines CLK1 and CLK 2. Namely, data is written into the pixel circuit in the process of charging the data line, so that the scanning time can be saved.
In another embodiment, which is in parallel with the above technical solution, fig. 5 is a timing chart of pulses on a scan line and pulses on a first clock signal line according to an embodiment of the present invention, as shown in fig. 1 and fig. 5, the display device 100 further includes a plurality of scan lines 112 arranged to intersect with the data lines 111; the signal on the scan line 112 and the signal on the first clock signal line each include a plurality of pulses; the pulse on the scanning signal line follows the pulse of the data writing phase on the first clock signal line. That is, data writing to the pixel circuit is performed after charging of the data line is completed.
As shown in fig. 5, also taking the case that the first switching transistor in the multiplexing unit is a P-type transistor and the multiplexing unit includes two input terminals as an example, the pulse on the scan line 112 (at the stage t 6) follows the pulses in the data writing phase (including at the stage t2 and at the stage t 3) on the two first clock signal lines CLK1 and CLK 2.
An embodiment of the present invention further provides a driving method of a display device, and fig. 6 is a flowchart of the driving method of the display device according to the embodiment of the present invention. The driving method provided by the embodiment of the present invention needs to be completed on the display device provided by the embodiment of the present invention, and the display device includes:
a plurality of pixel circuits;
a plurality of data lines connected to the plurality of pixel circuits;
and the multi-path selection unit comprises an input end and at least two output ends, and each output end is connected with one data line.
As shown in fig. 6, the driving method includes:
s610, a pre-charging stage, namely inputting a pre-charging voltage to the input end of the multi-path selection unit.
Specifically, in the precharge stage, the driving unit acquires a data signal voltage to be written to a data line electrically connected to the multiplexing unit, outputs a precharge voltage to an input terminal of the multiplexing unit through a logical operation, and at least two output terminals of the multiplexing unit output the precharge voltage to the data line, and precharges the data line, for example, the precharge voltage may be output through a comparator. Illustratively, the driving unit obtains a data signal voltage to be written on a data line connected to the multiplexing unit and inputs the data signal voltage to the comparator, the comparator performs a logic operation on the data signal voltage to be written on the data line, outputs a voltage associated with the data signal voltage on the data line as a precharge voltage to be output to an input terminal of the multiplexing unit, and the control signal terminal of the multiplexing unit controls at least two output terminals to output the precharge voltage input by the input terminal to the data line, and precharges the data line. Optionally, the comparator outputs a minimum voltage of the data signal voltages as the precharge voltage. Alternatively, the comparator outputs an average value of the voltages of the data signals as the precharge voltage.
S620, in a data writing stage, at least two data signal voltages are input to the input end of the multi-path selection unit in a time-sharing mode; the pre-charging voltage is associated with at least two data signal voltages, and is greater than or equal to the minimum voltage in each data signal voltage and less than or equal to the maximum voltage in each data signal voltage.
Specifically, in the data writing stage, the multi-path selection unit controls at least two output ends and the input end to be conducted in a time-sharing mode, and outputs data signal voltage to a data line electrically connected with the output ends in a time-sharing mode to perform data writing. In the data writing stage, only one of at least two output ends in the multi-path selection unit is conducted with the input end at the same time, and other output ends are all not conducted with the input end.
In addition, the precharge voltage in the precharge phase is related to the data signal voltage on each data line, and the precharge voltage is between the data signal voltages on each data line (which may include the data signal voltages equal to the maximum and minimum voltages on each data line), so that in the data write phase, the data lines may reduce the voltage across the data lines to charge to the data signal voltage, quickly charge the voltage on each data line to the data signal voltage, and greatly shorten the charging time of the data lines D1 and D2. Therefore, when the screen size of a display panel in the display device is increased and the line frequency of the display panel is smaller and smaller, the data lines can be completely charged in the data writing stage by adjusting the pre-charging voltage, so that high resolution is realized, and the charging efficiency and the display effect are improved.
In the technical scheme of the embodiment, in the pre-charging stage, the driving unit inputs pre-charging voltage related to the voltage of the data signal to the data line through the multi-path selection unit, so that the voltage across the data line in the data writing stage is reduced; in the data writing stage, the driving unit rapidly and rapidly charges the data signal voltage on the data line to the data signal voltage through the multi-path selection unit, and the charging time of the data line is greatly shortened. Therefore, when the screen size of a display panel in the display device is increased and the line frequency of the display panel is smaller and smaller, the data lines can be completely charged in the data writing stage by adjusting the pre-charging voltage, so that high resolution is realized, and the charging efficiency and the display effect are improved.
On the basis of the above embodiment, optionally, the precharge voltage is equal to the minimum value among the voltages of the respective data signals. When the minimum voltage of the data signal voltages is selected as the pre-charging voltage, the problem that the data signal voltage cannot be written into the pixel circuit electrically connected with the data line because the pre-charging voltage is greater than the data signal voltage can be avoided in the data writing stage.
In another alternative to the above embodiment, the precharge voltage is equal to the average of the voltages of the data signals. When the average value of the voltages of the data signals is selected as the pre-charge voltage, in the data writing stage, if the difference between the voltages of the data signals is large, the problem that the difference between the pre-charge voltage and the voltages of the data signals is large, which causes large voltage across lines can be avoided, and therefore the display effect of the pixel circuit is prevented from being influenced.
With continued reference to fig. 4, the multiplexing unit 121 includes at least two first transistors; the gates of the at least two first transistors are connected to the at least two first clock signal lines in a one-to-one correspondence, the first poles of the at least two first transistors are both connected to the input terminal Vin of the multiplexing unit 121, and the second poles of the at least two first transistors are respectively connected to the at least two output terminals of the multiplexing unit.
In the precharge stage, a clock signal is output to each first clock signal line to control each first transistor to be turned on.
In the data writing stage, clock signals are output to the first clock signal lines one by one, the first transistors are controlled to be sequentially conducted, and the driving unit outputs a data signal voltage during the conducting period of each first transistor.
When a first transistor in the multi-path selection unit is turned on, other first transistors in the multi-path selection unit are turned off.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (12)
1. A display device, comprising:
a plurality of pixel circuits;
a plurality of data lines connected to the plurality of pixel circuits;
the multi-path selection units comprise an input end and at least two output ends, and each output end is connected with one data line; the input end of the multi-path selection unit is sequentially communicated with the output ends in a time-sharing manner, and pixel circuits connected with the same row of scanning lines are charged;
the charging process comprises a pre-charging stage and a data writing stage, wherein a pre-charging voltage is input to the input end of the multi-path selection unit in the pre-charging stage, at least two data signal voltages are input to the input end of the multi-path selection unit in a time sharing mode in the data writing stage, the pre-charging voltage is associated with the at least two data signal voltages, and the pre-charging voltage is greater than or equal to the minimum voltage of the data signal voltages and less than or equal to the maximum voltage of the data signal voltages.
2. The display device according to claim 1, wherein the precharge voltage is equal to a minimum voltage among the data signal voltages.
3. The display device according to claim 2, wherein the driving unit includes a comparator that outputs a minimum voltage among the data signal voltages as the precharge voltage.
4. The display device according to claim 1, wherein the precharge voltage is equal to an average value of the voltages of the data signals.
5. The display device according to claim 1, wherein the multiplexing unit includes at least two first transistors; the grid electrodes of the at least two first transistors are connected with at least two first clock signal lines in a one-to-one correspondence mode, the first poles of the at least two first transistors are connected to the input end of the multi-path selection unit, and the second poles of the at least two first transistors are connected to the at least two output ends of the multi-path selection unit respectively.
6. The display device according to claim 5, further comprising a plurality of scan lines arranged to cross the data lines; the signal on the scan line and the signal on the first clock signal line each include a plurality of pulses;
the pulse on the scanning line covers at least the pulse of the data writing phase on each of the first clock signal lines.
7. The display device according to claim 5, further comprising a plurality of scan lines arranged to cross the data lines; the signal on the scan line and the signal on the first clock signal line each include a plurality of pulses;
the pulse on the scan line follows the pulse of the data write phase on the first clock signal line.
8. A driving method of a display device, the display device comprising:
a plurality of pixel circuits;
a plurality of data lines connected to the plurality of pixel circuits;
the multi-path selection units comprise an input end and at least two output ends, and each output end is connected with one data line; the input end of the multi-path selection unit is sequentially communicated with the output ends in a time-sharing manner, and pixel circuits connected with the same row of scanning lines are charged;
the driving method includes:
a precharge stage of inputting a precharge voltage to an input terminal of the multi-path selection unit;
a data writing stage, namely inputting at least two data signal voltages to the input end of the multi-path selection unit in a time-sharing manner; the pre-charge voltage is associated with the at least two data signal voltages, and is greater than or equal to the minimum voltage of the data signal voltages and less than or equal to the maximum voltage of the data signal voltages.
9. The driving method according to claim 8, wherein the precharge voltage is equal to a minimum value among the data signal voltages.
10. The driving method according to claim 8, wherein the precharge voltage is equal to an average value of the voltages of the data signals.
11. The driving method according to claim 8, wherein the multiplexing unit includes at least two first transistors; the grid electrodes of the at least two first transistors are respectively connected with at least two first clock signal lines, the first poles of the at least two first transistors are respectively connected to the input end of the multi-path selection unit, and the second poles of the at least two first transistors are respectively connected to at least two output ends of the multi-path selection unit;
in the pre-charging stage, outputting a clock signal to each first clock signal line to control each first transistor to be conducted;
in the data writing stage, outputting clock signals to the first clock signal line one by one, controlling the first transistors to be turned on in sequence, and outputting a data signal voltage by the driving unit during the turn-on period of each first transistor;
when one first transistor in the multi-path selection unit is turned on, the other first transistors in the multi-path selection unit are turned off.
12. The driving method according to claim 8, wherein the pixel circuit further includes a driving transistor, a storage capacitor, and a light emitting element; the driving method further comprises a light emitting phase;
in the data writing phase, a voltage associated with a threshold voltage of the driving transistor is stored by the storage capacitor;
in the light-emitting stage, the driving transistor outputs a driving current according to the voltage of the storage capacitor to drive the light-emitting element to emit light.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810415821.XA CN108648694B (en) | 2018-05-03 | 2018-05-03 | Display device and driving method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810415821.XA CN108648694B (en) | 2018-05-03 | 2018-05-03 | Display device and driving method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108648694A CN108648694A (en) | 2018-10-12 |
| CN108648694B true CN108648694B (en) | 2020-11-17 |
Family
ID=63748760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810415821.XA Active CN108648694B (en) | 2018-05-03 | 2018-05-03 | Display device and driving method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108648694B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI707335B (en) * | 2018-11-19 | 2020-10-11 | 友達光電股份有限公司 | Display device and driving method thereof |
| CN109215563B (en) * | 2018-11-26 | 2022-03-01 | 京东方科技集团股份有限公司 | Data writing control method, unit, pixel driving circuit and display device |
| CN109801585B (en) | 2019-03-25 | 2022-07-29 | 京东方科技集团股份有限公司 | Display panel driving circuit and driving method and display panel |
| TWI692747B (en) * | 2019-03-28 | 2020-05-01 | 聚積科技股份有限公司 | Display system and its shared driving circuit |
| CN110599942A (en) * | 2019-09-30 | 2019-12-20 | 京东方科技集团股份有限公司 | Display panel driving method and device and display device |
| CN110910845A (en) * | 2019-11-18 | 2020-03-24 | 福建华佳彩有限公司 | Dot display driving method |
| CN111696472B (en) * | 2020-07-13 | 2024-04-05 | 京东方科技集团股份有限公司 | Source electrode driving circuit, driving method thereof and display panel |
| CN111968581B (en) * | 2020-09-09 | 2021-11-23 | 京东方科技集团股份有限公司 | Driving method of pixel circuit |
| US11508302B2 (en) * | 2020-11-06 | 2022-11-22 | Novatek Microelectronics Corp. | Method for driving display panel and related driver circuit |
| CN112349250B (en) * | 2020-11-20 | 2022-02-25 | 武汉天马微电子有限公司 | Display panel and driving method |
| CN114613322B (en) * | 2020-12-03 | 2023-12-01 | 上海和辉光电股份有限公司 | Display driving method, display driving device and electronic equipment |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7889157B2 (en) * | 2003-12-30 | 2011-02-15 | Lg Display Co., Ltd. | Electro-luminescence display device and driving apparatus thereof |
| KR100607518B1 (en) * | 2004-02-20 | 2006-08-02 | 엘지전자 주식회사 | Electro-luminescensce dispaly panel and method for driving the same |
| CN1664910A (en) * | 2005-04-11 | 2005-09-07 | 友达光电股份有限公司 | Time division driven display and drive method thereof |
| CN105047166A (en) * | 2015-08-28 | 2015-11-11 | 深圳市华星光电技术有限公司 | Drive method for liquid crystal display panel and liquid crystal display apparatus |
| CN106297723B (en) * | 2016-11-09 | 2020-02-07 | 厦门天马微电子有限公司 | Pixel driving circuit, display panel and pixel driving method |
| CN106920524A (en) * | 2017-04-12 | 2017-07-04 | 深圳市华星光电技术有限公司 | Display panel and driving method |
| CN107195269B (en) * | 2017-05-26 | 2019-08-02 | 上海天马有机发光显示技术有限公司 | A kind of driving method of the multi-channel gating switch circuit of display panel, display device and display panel |
-
2018
- 2018-05-03 CN CN201810415821.XA patent/CN108648694B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108648694A (en) | 2018-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108648694B (en) | Display device and driving method thereof | |
| USRE48358E1 (en) | Emission control driver and organic light emitting display device having the same | |
| KR100639077B1 (en) | Display device and driving control method thereof | |
| KR101459521B1 (en) | Gate line driving method and apparatus, shifting register and display device | |
| CN108877611B (en) | Pixel driving circuit sensing method and pixel driving circuit | |
| US11862099B2 (en) | Shift register unit, gate driving circuit, display panel and driving method thereof | |
| CN106910460B (en) | Pixel-driving circuit and display panel | |
| KR20200135633A (en) | Scan driver and display device having the same | |
| CN108877662B (en) | Gate drive circuit, control method thereof and display device | |
| CN107393478B (en) | Pixel internal compensation circuit and driving method | |
| CN103578410A (en) | Organic light emitting diode display device and method for driving the same | |
| CN111243498B (en) | Pixel circuit, driving method thereof and display device | |
| CN113436583B (en) | Display panel and driving method thereof | |
| CN109801594B (en) | Display panel and display device | |
| US11127355B2 (en) | Shift register, gate driving circuit, display device and driving method | |
| JP5105699B2 (en) | Display device | |
| US20130170606A1 (en) | Shift register | |
| US20100171689A1 (en) | Shift register and organic light emitting display device using the same | |
| US20210366362A1 (en) | Pixel circuit, driving method, and display apparatus | |
| US11798482B2 (en) | Gate driver and organic light emitting display device including the same | |
| CN112785955A (en) | Light emission control drive unit and display device including the same | |
| US11741903B2 (en) | Gate driver and display device including the same | |
| CN108230998B (en) | Emission control drive circuit, emission control driver, and organic light emitting display device | |
| US20040233142A1 (en) | Display device | |
| CN110379372B (en) | Pixel driving unit, circuit, method, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211103 Address after: No.8, liufangyuan Henglu, Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: WUHAN TIANMA MICRO-ELECTRONICS Co.,Ltd. Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 200120 Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd. |
|
| TR01 | Transfer of patent right |